1/* 2 * Driver for the Conexant CX23885 PCIe bridge 3 * 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22#include <linux/init.h> 23#include <linux/module.h> 24#include <linux/pci.h> 25#include <linux/delay.h> 26#include <media/cx25840.h> 27#include <linux/firmware.h> 28#include <misc/altera.h> 29 30#include "cx23885.h" 31#include "tuner-xc2028.h" 32#include "netup-eeprom.h" 33#include "netup-init.h" 34#include "altera-ci.h" 35#include "xc4000.h" 36#include "xc5000.h" 37#include "cx23888-ir.h" 38 39static unsigned int netup_card_rev = 1; 40module_param(netup_card_rev, int, 0644); 41MODULE_PARM_DESC(netup_card_rev, 42 "NetUP Dual DVB-T/C CI card revision"); 43static unsigned int enable_885_ir; 44module_param(enable_885_ir, int, 0644); 45MODULE_PARM_DESC(enable_885_ir, 46 "Enable integrated IR controller for supported\n" 47 "\t\t CX2388[57] boards that are wired for it:\n" 48 "\t\t\tHVR-1250 (reported safe)\n" 49 "\t\t\tTeVii S470 (reported unsafe)\n" 50 "\t\t This can cause an interrupt storm with some cards.\n" 51 "\t\t Default: 0 [Disabled]"); 52 53/* ------------------------------------------------------------------ */ 54/* board config info */ 55 56struct cx23885_board cx23885_boards[] = { 57 [CX23885_BOARD_UNKNOWN] = { 58 .name = "UNKNOWN/GENERIC", 59 /* Ensure safe default for unknown boards */ 60 .clk_freq = 0, 61 .input = {{ 62 .type = CX23885_VMUX_COMPOSITE1, 63 .vmux = 0, 64 }, { 65 .type = CX23885_VMUX_COMPOSITE2, 66 .vmux = 1, 67 }, { 68 .type = CX23885_VMUX_COMPOSITE3, 69 .vmux = 2, 70 }, { 71 .type = CX23885_VMUX_COMPOSITE4, 72 .vmux = 3, 73 } }, 74 }, 75 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = { 76 .name = "Hauppauge WinTV-HVR1800lp", 77 .portc = CX23885_MPEG_DVB, 78 .input = {{ 79 .type = CX23885_VMUX_TELEVISION, 80 .vmux = 0, 81 .gpio0 = 0xff00, 82 }, { 83 .type = CX23885_VMUX_DEBUG, 84 .vmux = 0, 85 .gpio0 = 0xff01, 86 }, { 87 .type = CX23885_VMUX_COMPOSITE1, 88 .vmux = 1, 89 .gpio0 = 0xff02, 90 }, { 91 .type = CX23885_VMUX_SVIDEO, 92 .vmux = 2, 93 .gpio0 = 0xff02, 94 } }, 95 }, 96 [CX23885_BOARD_HAUPPAUGE_HVR1800] = { 97 .name = "Hauppauge WinTV-HVR1800", 98 .porta = CX23885_ANALOG_VIDEO, 99 .portb = CX23885_MPEG_ENCODER, 100 .portc = CX23885_MPEG_DVB, 101 .tuner_type = TUNER_PHILIPS_TDA8290, 102 .tuner_addr = 0x42, /* 0x84 >> 1 */ 103 .tuner_bus = 1, 104 .input = {{ 105 .type = CX23885_VMUX_TELEVISION, 106 .vmux = CX25840_VIN7_CH3 | 107 CX25840_VIN5_CH2 | 108 CX25840_VIN2_CH1, 109 .amux = CX25840_AUDIO8, 110 .gpio0 = 0, 111 }, { 112 .type = CX23885_VMUX_COMPOSITE1, 113 .vmux = CX25840_VIN7_CH3 | 114 CX25840_VIN4_CH2 | 115 CX25840_VIN6_CH1, 116 .amux = CX25840_AUDIO7, 117 .gpio0 = 0, 118 }, { 119 .type = CX23885_VMUX_SVIDEO, 120 .vmux = CX25840_VIN7_CH3 | 121 CX25840_VIN4_CH2 | 122 CX25840_VIN8_CH1 | 123 CX25840_SVIDEO_ON, 124 .amux = CX25840_AUDIO7, 125 .gpio0 = 0, 126 } }, 127 }, 128 [CX23885_BOARD_HAUPPAUGE_HVR1250] = { 129 .name = "Hauppauge WinTV-HVR1250", 130 .portc = CX23885_MPEG_DVB, 131 .input = {{ 132 .type = CX23885_VMUX_TELEVISION, 133 .vmux = 0, 134 .gpio0 = 0xff00, 135 }, { 136 .type = CX23885_VMUX_DEBUG, 137 .vmux = 0, 138 .gpio0 = 0xff01, 139 }, { 140 .type = CX23885_VMUX_COMPOSITE1, 141 .vmux = 1, 142 .gpio0 = 0xff02, 143 }, { 144 .type = CX23885_VMUX_SVIDEO, 145 .vmux = 2, 146 .gpio0 = 0xff02, 147 } }, 148 }, 149 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = { 150 .name = "DViCO FusionHDTV5 Express", 151 .portb = CX23885_MPEG_DVB, 152 }, 153 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = { 154 .name = "Hauppauge WinTV-HVR1500Q", 155 .portc = CX23885_MPEG_DVB, 156 }, 157 [CX23885_BOARD_HAUPPAUGE_HVR1500] = { 158 .name = "Hauppauge WinTV-HVR1500", 159 .porta = CX23885_ANALOG_VIDEO, 160 .portc = CX23885_MPEG_DVB, 161 .tuner_type = TUNER_XC2028, 162 .tuner_addr = 0x61, /* 0xc2 >> 1 */ 163 .input = {{ 164 .type = CX23885_VMUX_TELEVISION, 165 .vmux = CX25840_VIN7_CH3 | 166 CX25840_VIN5_CH2 | 167 CX25840_VIN2_CH1, 168 .gpio0 = 0, 169 }, { 170 .type = CX23885_VMUX_COMPOSITE1, 171 .vmux = CX25840_VIN7_CH3 | 172 CX25840_VIN4_CH2 | 173 CX25840_VIN6_CH1, 174 .gpio0 = 0, 175 }, { 176 .type = CX23885_VMUX_SVIDEO, 177 .vmux = CX25840_VIN7_CH3 | 178 CX25840_VIN4_CH2 | 179 CX25840_VIN8_CH1 | 180 CX25840_SVIDEO_ON, 181 .gpio0 = 0, 182 } }, 183 }, 184 [CX23885_BOARD_HAUPPAUGE_HVR1200] = { 185 .name = "Hauppauge WinTV-HVR1200", 186 .portc = CX23885_MPEG_DVB, 187 }, 188 [CX23885_BOARD_HAUPPAUGE_HVR1700] = { 189 .name = "Hauppauge WinTV-HVR1700", 190 .portc = CX23885_MPEG_DVB, 191 }, 192 [CX23885_BOARD_HAUPPAUGE_HVR1400] = { 193 .name = "Hauppauge WinTV-HVR1400", 194 .portc = CX23885_MPEG_DVB, 195 }, 196 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = { 197 .name = "DViCO FusionHDTV7 Dual Express", 198 .portb = CX23885_MPEG_DVB, 199 .portc = CX23885_MPEG_DVB, 200 }, 201 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = { 202 .name = "DViCO FusionHDTV DVB-T Dual Express", 203 .portb = CX23885_MPEG_DVB, 204 .portc = CX23885_MPEG_DVB, 205 }, 206 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = { 207 .name = "Leadtek Winfast PxDVR3200 H", 208 .portc = CX23885_MPEG_DVB, 209 }, 210 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = { 211 .name = "Leadtek Winfast PxDVR3200 H XC4000", 212 .porta = CX23885_ANALOG_VIDEO, 213 .portc = CX23885_MPEG_DVB, 214 .tuner_type = TUNER_XC4000, 215 .tuner_addr = 0x61, 216 .radio_type = UNSET, 217 .radio_addr = ADDR_UNSET, 218 .input = {{ 219 .type = CX23885_VMUX_TELEVISION, 220 .vmux = CX25840_VIN2_CH1 | 221 CX25840_VIN5_CH2 | 222 CX25840_NONE0_CH3, 223 }, { 224 .type = CX23885_VMUX_COMPOSITE1, 225 .vmux = CX25840_COMPOSITE1, 226 }, { 227 .type = CX23885_VMUX_SVIDEO, 228 .vmux = CX25840_SVIDEO_LUMA3 | 229 CX25840_SVIDEO_CHROMA4, 230 }, { 231 .type = CX23885_VMUX_COMPONENT, 232 .vmux = CX25840_VIN7_CH1 | 233 CX25840_VIN6_CH2 | 234 CX25840_VIN8_CH3 | 235 CX25840_COMPONENT_ON, 236 } }, 237 }, 238 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = { 239 .name = "Compro VideoMate E650F", 240 .portc = CX23885_MPEG_DVB, 241 }, 242 [CX23885_BOARD_TBS_6920] = { 243 .name = "TurboSight TBS 6920", 244 .portb = CX23885_MPEG_DVB, 245 }, 246 [CX23885_BOARD_TEVII_S470] = { 247 .name = "TeVii S470", 248 .portb = CX23885_MPEG_DVB, 249 }, 250 [CX23885_BOARD_DVBWORLD_2005] = { 251 .name = "DVBWorld DVB-S2 2005", 252 .portb = CX23885_MPEG_DVB, 253 }, 254 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = { 255 .ci_type = 1, 256 .name = "NetUP Dual DVB-S2 CI", 257 .portb = CX23885_MPEG_DVB, 258 .portc = CX23885_MPEG_DVB, 259 }, 260 [CX23885_BOARD_HAUPPAUGE_HVR1270] = { 261 .name = "Hauppauge WinTV-HVR1270", 262 .portc = CX23885_MPEG_DVB, 263 }, 264 [CX23885_BOARD_HAUPPAUGE_HVR1275] = { 265 .name = "Hauppauge WinTV-HVR1275", 266 .portc = CX23885_MPEG_DVB, 267 }, 268 [CX23885_BOARD_HAUPPAUGE_HVR1255] = { 269 .name = "Hauppauge WinTV-HVR1255", 270 .portc = CX23885_MPEG_DVB, 271 }, 272 [CX23885_BOARD_HAUPPAUGE_HVR1210] = { 273 .name = "Hauppauge WinTV-HVR1210", 274 .portc = CX23885_MPEG_DVB, 275 }, 276 [CX23885_BOARD_MYGICA_X8506] = { 277 .name = "Mygica X8506 DMB-TH", 278 .tuner_type = TUNER_XC5000, 279 .tuner_addr = 0x61, 280 .tuner_bus = 1, 281 .porta = CX23885_ANALOG_VIDEO, 282 .portb = CX23885_MPEG_DVB, 283 .input = { 284 { 285 .type = CX23885_VMUX_TELEVISION, 286 .vmux = CX25840_COMPOSITE2, 287 }, 288 { 289 .type = CX23885_VMUX_COMPOSITE1, 290 .vmux = CX25840_COMPOSITE8, 291 }, 292 { 293 .type = CX23885_VMUX_SVIDEO, 294 .vmux = CX25840_SVIDEO_LUMA3 | 295 CX25840_SVIDEO_CHROMA4, 296 }, 297 { 298 .type = CX23885_VMUX_COMPONENT, 299 .vmux = CX25840_COMPONENT_ON | 300 CX25840_VIN1_CH1 | 301 CX25840_VIN6_CH2 | 302 CX25840_VIN7_CH3, 303 }, 304 }, 305 }, 306 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = { 307 .name = "Magic-Pro ProHDTV Extreme 2", 308 .tuner_type = TUNER_XC5000, 309 .tuner_addr = 0x61, 310 .tuner_bus = 1, 311 .porta = CX23885_ANALOG_VIDEO, 312 .portb = CX23885_MPEG_DVB, 313 .input = { 314 { 315 .type = CX23885_VMUX_TELEVISION, 316 .vmux = CX25840_COMPOSITE2, 317 }, 318 { 319 .type = CX23885_VMUX_COMPOSITE1, 320 .vmux = CX25840_COMPOSITE8, 321 }, 322 { 323 .type = CX23885_VMUX_SVIDEO, 324 .vmux = CX25840_SVIDEO_LUMA3 | 325 CX25840_SVIDEO_CHROMA4, 326 }, 327 { 328 .type = CX23885_VMUX_COMPONENT, 329 .vmux = CX25840_COMPONENT_ON | 330 CX25840_VIN1_CH1 | 331 CX25840_VIN6_CH2 | 332 CX25840_VIN7_CH3, 333 }, 334 }, 335 }, 336 [CX23885_BOARD_HAUPPAUGE_HVR1850] = { 337 .name = "Hauppauge WinTV-HVR1850", 338 .porta = CX23885_ANALOG_VIDEO, 339 .portb = CX23885_MPEG_ENCODER, 340 .portc = CX23885_MPEG_DVB, 341 .tuner_type = TUNER_ABSENT, 342 .tuner_addr = 0x42, /* 0x84 >> 1 */ 343 .force_bff = 1, 344 .input = {{ 345 .type = CX23885_VMUX_TELEVISION, 346 .vmux = CX25840_VIN7_CH3 | 347 CX25840_VIN5_CH2 | 348 CX25840_VIN2_CH1 | 349 CX25840_DIF_ON, 350 .amux = CX25840_AUDIO8, 351 }, { 352 .type = CX23885_VMUX_COMPOSITE1, 353 .vmux = CX25840_VIN7_CH3 | 354 CX25840_VIN4_CH2 | 355 CX25840_VIN6_CH1, 356 .amux = CX25840_AUDIO7, 357 }, { 358 .type = CX23885_VMUX_SVIDEO, 359 .vmux = CX25840_VIN7_CH3 | 360 CX25840_VIN4_CH2 | 361 CX25840_VIN8_CH1 | 362 CX25840_SVIDEO_ON, 363 .amux = CX25840_AUDIO7, 364 } }, 365 }, 366 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = { 367 .name = "Compro VideoMate E800", 368 .portc = CX23885_MPEG_DVB, 369 }, 370 [CX23885_BOARD_HAUPPAUGE_HVR1290] = { 371 .name = "Hauppauge WinTV-HVR1290", 372 .portc = CX23885_MPEG_DVB, 373 }, 374 [CX23885_BOARD_MYGICA_X8558PRO] = { 375 .name = "Mygica X8558 PRO DMB-TH", 376 .portb = CX23885_MPEG_DVB, 377 .portc = CX23885_MPEG_DVB, 378 }, 379 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = { 380 .name = "LEADTEK WinFast PxTV1200", 381 .porta = CX23885_ANALOG_VIDEO, 382 .tuner_type = TUNER_XC2028, 383 .tuner_addr = 0x61, 384 .tuner_bus = 1, 385 .input = {{ 386 .type = CX23885_VMUX_TELEVISION, 387 .vmux = CX25840_VIN2_CH1 | 388 CX25840_VIN5_CH2 | 389 CX25840_NONE0_CH3, 390 }, { 391 .type = CX23885_VMUX_COMPOSITE1, 392 .vmux = CX25840_COMPOSITE1, 393 }, { 394 .type = CX23885_VMUX_SVIDEO, 395 .vmux = CX25840_SVIDEO_LUMA3 | 396 CX25840_SVIDEO_CHROMA4, 397 }, { 398 .type = CX23885_VMUX_COMPONENT, 399 .vmux = CX25840_VIN7_CH1 | 400 CX25840_VIN6_CH2 | 401 CX25840_VIN8_CH3 | 402 CX25840_COMPONENT_ON, 403 } }, 404 }, 405 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = { 406 .name = "GoTView X5 3D Hybrid", 407 .tuner_type = TUNER_XC5000, 408 .tuner_addr = 0x64, 409 .tuner_bus = 1, 410 .porta = CX23885_ANALOG_VIDEO, 411 .portb = CX23885_MPEG_DVB, 412 .input = {{ 413 .type = CX23885_VMUX_TELEVISION, 414 .vmux = CX25840_VIN2_CH1 | 415 CX25840_VIN5_CH2, 416 .gpio0 = 0x02, 417 }, { 418 .type = CX23885_VMUX_COMPOSITE1, 419 .vmux = CX23885_VMUX_COMPOSITE1, 420 }, { 421 .type = CX23885_VMUX_SVIDEO, 422 .vmux = CX25840_SVIDEO_LUMA3 | 423 CX25840_SVIDEO_CHROMA4, 424 } }, 425 }, 426 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = { 427 .ci_type = 2, 428 .name = "NetUP Dual DVB-T/C-CI RF", 429 .porta = CX23885_ANALOG_VIDEO, 430 .portb = CX23885_MPEG_DVB, 431 .portc = CX23885_MPEG_DVB, 432 .num_fds_portb = 2, 433 .num_fds_portc = 2, 434 .tuner_type = TUNER_XC5000, 435 .tuner_addr = 0x64, 436 .input = { { 437 .type = CX23885_VMUX_TELEVISION, 438 .vmux = CX25840_COMPOSITE1, 439 } }, 440 }, 441 [CX23885_BOARD_MPX885] = { 442 .name = "MPX-885", 443 .porta = CX23885_ANALOG_VIDEO, 444 .input = {{ 445 .type = CX23885_VMUX_COMPOSITE1, 446 .vmux = CX25840_COMPOSITE1, 447 .amux = CX25840_AUDIO6, 448 .gpio0 = 0, 449 }, { 450 .type = CX23885_VMUX_COMPOSITE2, 451 .vmux = CX25840_COMPOSITE2, 452 .amux = CX25840_AUDIO6, 453 .gpio0 = 0, 454 }, { 455 .type = CX23885_VMUX_COMPOSITE3, 456 .vmux = CX25840_COMPOSITE3, 457 .amux = CX25840_AUDIO7, 458 .gpio0 = 0, 459 }, { 460 .type = CX23885_VMUX_COMPOSITE4, 461 .vmux = CX25840_COMPOSITE4, 462 .amux = CX25840_AUDIO7, 463 .gpio0 = 0, 464 } }, 465 }, 466 [CX23885_BOARD_MYGICA_X8507] = { 467 .name = "Mygica X8507", 468 .tuner_type = TUNER_XC5000, 469 .tuner_addr = 0x61, 470 .tuner_bus = 1, 471 .porta = CX23885_ANALOG_VIDEO, 472 .input = { 473 { 474 .type = CX23885_VMUX_TELEVISION, 475 .vmux = CX25840_COMPOSITE2, 476 .amux = CX25840_AUDIO8, 477 }, 478 { 479 .type = CX23885_VMUX_COMPOSITE1, 480 .vmux = CX25840_COMPOSITE8, 481 }, 482 { 483 .type = CX23885_VMUX_SVIDEO, 484 .vmux = CX25840_SVIDEO_LUMA3 | 485 CX25840_SVIDEO_CHROMA4, 486 }, 487 { 488 .type = CX23885_VMUX_COMPONENT, 489 .vmux = CX25840_COMPONENT_ON | 490 CX25840_VIN1_CH1 | 491 CX25840_VIN6_CH2 | 492 CX25840_VIN7_CH3, 493 }, 494 }, 495 }, 496 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = { 497 .name = "TerraTec Cinergy T PCIe Dual", 498 .portb = CX23885_MPEG_DVB, 499 .portc = CX23885_MPEG_DVB, 500 } 501}; 502const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards); 503 504/* ------------------------------------------------------------------ */ 505/* PCI subsystem IDs */ 506 507struct cx23885_subid cx23885_subids[] = { 508 { 509 .subvendor = 0x0070, 510 .subdevice = 0x3400, 511 .card = CX23885_BOARD_UNKNOWN, 512 }, { 513 .subvendor = 0x0070, 514 .subdevice = 0x7600, 515 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp, 516 }, { 517 .subvendor = 0x0070, 518 .subdevice = 0x7800, 519 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 520 }, { 521 .subvendor = 0x0070, 522 .subdevice = 0x7801, 523 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 524 }, { 525 .subvendor = 0x0070, 526 .subdevice = 0x7809, 527 .card = CX23885_BOARD_HAUPPAUGE_HVR1800, 528 }, { 529 .subvendor = 0x0070, 530 .subdevice = 0x7911, 531 .card = CX23885_BOARD_HAUPPAUGE_HVR1250, 532 }, { 533 .subvendor = 0x18ac, 534 .subdevice = 0xd500, 535 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP, 536 }, { 537 .subvendor = 0x0070, 538 .subdevice = 0x7790, 539 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 540 }, { 541 .subvendor = 0x0070, 542 .subdevice = 0x7797, 543 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q, 544 }, { 545 .subvendor = 0x0070, 546 .subdevice = 0x7710, 547 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 548 }, { 549 .subvendor = 0x0070, 550 .subdevice = 0x7717, 551 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 552 }, { 553 .subvendor = 0x0070, 554 .subdevice = 0x71d1, 555 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 556 }, { 557 .subvendor = 0x0070, 558 .subdevice = 0x71d3, 559 .card = CX23885_BOARD_HAUPPAUGE_HVR1200, 560 }, { 561 .subvendor = 0x0070, 562 .subdevice = 0x8101, 563 .card = CX23885_BOARD_HAUPPAUGE_HVR1700, 564 }, { 565 .subvendor = 0x0070, 566 .subdevice = 0x8010, 567 .card = CX23885_BOARD_HAUPPAUGE_HVR1400, 568 }, { 569 .subvendor = 0x18ac, 570 .subdevice = 0xd618, 571 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP, 572 }, { 573 .subvendor = 0x18ac, 574 .subdevice = 0xdb78, 575 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP, 576 }, { 577 .subvendor = 0x107d, 578 .subdevice = 0x6681, 579 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H, 580 }, { 581 .subvendor = 0x107d, 582 .subdevice = 0x6f39, 583 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000, 584 }, { 585 .subvendor = 0x185b, 586 .subdevice = 0xe800, 587 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F, 588 }, { 589 .subvendor = 0x6920, 590 .subdevice = 0x8888, 591 .card = CX23885_BOARD_TBS_6920, 592 }, { 593 .subvendor = 0xd470, 594 .subdevice = 0x9022, 595 .card = CX23885_BOARD_TEVII_S470, 596 }, { 597 .subvendor = 0x0001, 598 .subdevice = 0x2005, 599 .card = CX23885_BOARD_DVBWORLD_2005, 600 }, { 601 .subvendor = 0x1b55, 602 .subdevice = 0x2a2c, 603 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI, 604 }, { 605 .subvendor = 0x0070, 606 .subdevice = 0x2211, 607 .card = CX23885_BOARD_HAUPPAUGE_HVR1270, 608 }, { 609 .subvendor = 0x0070, 610 .subdevice = 0x2215, 611 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 612 }, { 613 .subvendor = 0x0070, 614 .subdevice = 0x221d, 615 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 616 }, { 617 .subvendor = 0x0070, 618 .subdevice = 0x2251, 619 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 620 }, { 621 .subvendor = 0x0070, 622 .subdevice = 0x2259, 623 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 624 }, { 625 .subvendor = 0x0070, 626 .subdevice = 0x2291, 627 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 628 }, { 629 .subvendor = 0x0070, 630 .subdevice = 0x2295, 631 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 632 }, { 633 .subvendor = 0x0070, 634 .subdevice = 0x2299, 635 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 636 }, { 637 .subvendor = 0x0070, 638 .subdevice = 0x229d, 639 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 640 }, { 641 .subvendor = 0x0070, 642 .subdevice = 0x22f0, 643 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 644 }, { 645 .subvendor = 0x0070, 646 .subdevice = 0x22f1, 647 .card = CX23885_BOARD_HAUPPAUGE_HVR1255, 648 }, { 649 .subvendor = 0x0070, 650 .subdevice = 0x22f2, 651 .card = CX23885_BOARD_HAUPPAUGE_HVR1275, 652 }, { 653 .subvendor = 0x0070, 654 .subdevice = 0x22f3, 655 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 656 }, { 657 .subvendor = 0x0070, 658 .subdevice = 0x22f4, 659 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, 660 }, { 661 .subvendor = 0x0070, 662 .subdevice = 0x22f5, 663 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */ 664 }, { 665 .subvendor = 0x14f1, 666 .subdevice = 0x8651, 667 .card = CX23885_BOARD_MYGICA_X8506, 668 }, { 669 .subvendor = 0x14f1, 670 .subdevice = 0x8657, 671 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2, 672 }, { 673 .subvendor = 0x0070, 674 .subdevice = 0x8541, 675 .card = CX23885_BOARD_HAUPPAUGE_HVR1850, 676 }, { 677 .subvendor = 0x1858, 678 .subdevice = 0xe800, 679 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800, 680 }, { 681 .subvendor = 0x0070, 682 .subdevice = 0x8551, 683 .card = CX23885_BOARD_HAUPPAUGE_HVR1290, 684 }, { 685 .subvendor = 0x14f1, 686 .subdevice = 0x8578, 687 .card = CX23885_BOARD_MYGICA_X8558PRO, 688 }, { 689 .subvendor = 0x107d, 690 .subdevice = 0x6f22, 691 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200, 692 }, { 693 .subvendor = 0x5654, 694 .subdevice = 0x2390, 695 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID, 696 }, { 697 .subvendor = 0x1b55, 698 .subdevice = 0xe2e4, 699 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF, 700 }, { 701 .subvendor = 0x14f1, 702 .subdevice = 0x8502, 703 .card = CX23885_BOARD_MYGICA_X8507, 704 }, { 705 .subvendor = 0x153b, 706 .subdevice = 0x117e, 707 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL, 708 }, 709}; 710const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids); 711 712void cx23885_card_list(struct cx23885_dev *dev) 713{ 714 int i; 715 716 if (0 == dev->pci->subsystem_vendor && 717 0 == dev->pci->subsystem_device) { 718 printk(KERN_INFO 719 "%s: Board has no valid PCIe Subsystem ID and can't\n" 720 "%s: be autodetected. Pass card=<n> insmod option\n" 721 "%s: to workaround that. Redirect complaints to the\n" 722 "%s: vendor of the TV card. Best regards,\n" 723 "%s: -- tux\n", 724 dev->name, dev->name, dev->name, dev->name, dev->name); 725 } else { 726 printk(KERN_INFO 727 "%s: Your board isn't known (yet) to the driver.\n" 728 "%s: Try to pick one of the existing card configs via\n" 729 "%s: card=<n> insmod option. Updating to the latest\n" 730 "%s: version might help as well.\n", 731 dev->name, dev->name, dev->name, dev->name); 732 } 733 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n", 734 dev->name); 735 for (i = 0; i < cx23885_bcount; i++) 736 printk(KERN_INFO "%s: card=%d -> %s\n", 737 dev->name, i, cx23885_boards[i].name); 738} 739 740static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) 741{ 742 struct tveeprom tv; 743 744 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv, 745 eeprom_data); 746 747 /* Make sure we support the board model */ 748 switch (tv.model) { 749 case 22001: 750 /* WinTV-HVR1270 (PCIe, Retail, half height) 751 * ATSC/QAM and basic analog, IR Blast */ 752 case 22009: 753 /* WinTV-HVR1210 (PCIe, Retail, half height) 754 * DVB-T and basic analog, IR Blast */ 755 case 22011: 756 /* WinTV-HVR1270 (PCIe, Retail, half height) 757 * ATSC/QAM and basic analog, IR Recv */ 758 case 22019: 759 /* WinTV-HVR1210 (PCIe, Retail, half height) 760 * DVB-T and basic analog, IR Recv */ 761 case 22021: 762 /* WinTV-HVR1275 (PCIe, Retail, half height) 763 * ATSC/QAM and basic analog, IR Recv */ 764 case 22029: 765 /* WinTV-HVR1210 (PCIe, Retail, half height) 766 * DVB-T and basic analog, IR Recv */ 767 case 22101: 768 /* WinTV-HVR1270 (PCIe, Retail, full height) 769 * ATSC/QAM and basic analog, IR Blast */ 770 case 22109: 771 /* WinTV-HVR1210 (PCIe, Retail, full height) 772 * DVB-T and basic analog, IR Blast */ 773 case 22111: 774 /* WinTV-HVR1270 (PCIe, Retail, full height) 775 * ATSC/QAM and basic analog, IR Recv */ 776 case 22119: 777 /* WinTV-HVR1210 (PCIe, Retail, full height) 778 * DVB-T and basic analog, IR Recv */ 779 case 22121: 780 /* WinTV-HVR1275 (PCIe, Retail, full height) 781 * ATSC/QAM and basic analog, IR Recv */ 782 case 22129: 783 /* WinTV-HVR1210 (PCIe, Retail, full height) 784 * DVB-T and basic analog, IR Recv */ 785 case 71009: 786 /* WinTV-HVR1200 (PCIe, Retail, full height) 787 * DVB-T and basic analog */ 788 case 71359: 789 /* WinTV-HVR1200 (PCIe, OEM, half height) 790 * DVB-T and basic analog */ 791 case 71439: 792 /* WinTV-HVR1200 (PCIe, OEM, half height) 793 * DVB-T and basic analog */ 794 case 71449: 795 /* WinTV-HVR1200 (PCIe, OEM, full height) 796 * DVB-T and basic analog */ 797 case 71939: 798 /* WinTV-HVR1200 (PCIe, OEM, half height) 799 * DVB-T and basic analog */ 800 case 71949: 801 /* WinTV-HVR1200 (PCIe, OEM, full height) 802 * DVB-T and basic analog */ 803 case 71959: 804 /* WinTV-HVR1200 (PCIe, OEM, full height) 805 * DVB-T and basic analog */ 806 case 71979: 807 /* WinTV-HVR1200 (PCIe, OEM, half height) 808 * DVB-T and basic analog */ 809 case 71999: 810 /* WinTV-HVR1200 (PCIe, OEM, full height) 811 * DVB-T and basic analog */ 812 case 76601: 813 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual 814 channel ATSC and MPEG2 HW Encoder */ 815 case 77001: 816 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC 817 and Basic analog */ 818 case 77011: 819 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC 820 and Basic analog */ 821 case 77041: 822 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM 823 and Basic analog */ 824 case 77051: 825 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM 826 and Basic analog */ 827 case 78011: 828 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM, 829 Dual channel ATSC and MPEG2 HW Encoder */ 830 case 78501: 831 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 832 Dual channel ATSC and MPEG2 HW Encoder */ 833 case 78521: 834 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM, 835 Dual channel ATSC and MPEG2 HW Encoder */ 836 case 78531: 837 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM, 838 Dual channel ATSC and MPEG2 HW Encoder */ 839 case 78631: 840 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM, 841 Dual channel ATSC and MPEG2 HW Encoder */ 842 case 79001: 843 /* WinTV-HVR1250 (PCIe, Retail, IR, full height, 844 ATSC and Basic analog */ 845 case 79101: 846 /* WinTV-HVR1250 (PCIe, Retail, IR, half height, 847 ATSC and Basic analog */ 848 case 79501: 849 /* WinTV-HVR1250 (PCIe, No IR, half height, 850 ATSC [at least] and Basic analog) */ 851 case 79561: 852 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 853 ATSC and Basic analog */ 854 case 79571: 855 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height, 856 ATSC and Basic analog */ 857 case 79671: 858 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, 859 ATSC and Basic analog */ 860 case 80019: 861 /* WinTV-HVR1400 (Express Card, Retail, IR, 862 * DVB-T and Basic analog */ 863 case 81509: 864 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height) 865 * DVB-T and MPEG2 HW Encoder */ 866 case 81519: 867 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height) 868 * DVB-T and MPEG2 HW Encoder */ 869 break; 870 case 85021: 871 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM, 872 Dual channel ATSC and MPEG2 HW Encoder */ 873 break; 874 case 85721: 875 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR, 876 Dual channel ATSC and Basic analog */ 877 break; 878 default: 879 printk(KERN_WARNING "%s: warning: " 880 "unknown hauppauge model #%d\n", 881 dev->name, tv.model); 882 break; 883 } 884 885 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n", 886 dev->name, tv.model); 887} 888 889int cx23885_tuner_callback(void *priv, int component, int command, int arg) 890{ 891 struct cx23885_tsport *port = priv; 892 struct cx23885_dev *dev = port->dev; 893 u32 bitmask = 0; 894 895 if (command == XC2028_RESET_CLK) 896 return 0; 897 898 if (command != 0) { 899 printk(KERN_ERR "%s(): Unknown command 0x%x.\n", 900 __func__, command); 901 return -EINVAL; 902 } 903 904 switch (dev->board) { 905 case CX23885_BOARD_HAUPPAUGE_HVR1400: 906 case CX23885_BOARD_HAUPPAUGE_HVR1500: 907 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 908 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 909 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 910 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 911 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 912 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 913 /* Tuner Reset Command */ 914 bitmask = 0x04; 915 break; 916 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 917 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 918 /* Two identical tuners on two different i2c buses, 919 * we need to reset the correct gpio. */ 920 if (port->nr == 1) 921 bitmask = 0x01; 922 else if (port->nr == 2) 923 bitmask = 0x04; 924 break; 925 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 926 /* Tuner Reset Command */ 927 bitmask = 0x02; 928 break; 929 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 930 altera_ci_tuner_reset(dev, port->nr); 931 break; 932 } 933 934 if (bitmask) { 935 /* Drive the tuner into reset and back out */ 936 cx_clear(GP0_IO, bitmask); 937 mdelay(200); 938 cx_set(GP0_IO, bitmask); 939 } 940 941 return 0; 942} 943 944void cx23885_gpio_setup(struct cx23885_dev *dev) 945{ 946 switch (dev->board) { 947 case CX23885_BOARD_HAUPPAUGE_HVR1250: 948 /* GPIO-0 cx24227 demodulator reset */ 949 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 950 break; 951 case CX23885_BOARD_HAUPPAUGE_HVR1500: 952 /* GPIO-0 cx24227 demodulator */ 953 /* GPIO-2 xc3028 tuner */ 954 955 /* Put the parts into reset */ 956 cx_set(GP0_IO, 0x00050000); 957 cx_clear(GP0_IO, 0x00000005); 958 msleep(5); 959 960 /* Bring the parts out of reset */ 961 cx_set(GP0_IO, 0x00050005); 962 break; 963 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 964 /* GPIO-0 cx24227 demodulator reset */ 965 /* GPIO-2 xc5000 tuner reset */ 966 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */ 967 break; 968 case CX23885_BOARD_HAUPPAUGE_HVR1800: 969 /* GPIO-0 656_CLK */ 970 /* GPIO-1 656_D0 */ 971 /* GPIO-2 8295A Reset */ 972 /* GPIO-3-10 cx23417 data0-7 */ 973 /* GPIO-11-14 cx23417 addr0-3 */ 974 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 975 /* GPIO-19 IR_RX */ 976 977 /* CX23417 GPIO's */ 978 /* EIO15 Zilog Reset */ 979 /* EIO14 S5H1409/CX24227 Reset */ 980 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1); 981 982 /* Put the demod into reset and protect the eeprom */ 983 mc417_gpio_clear(dev, GPIO_15 | GPIO_14); 984 mdelay(100); 985 986 /* Bring the demod and blaster out of reset */ 987 mc417_gpio_set(dev, GPIO_15 | GPIO_14); 988 mdelay(100); 989 990 /* Force the TDA8295A into reset and back */ 991 cx23885_gpio_enable(dev, GPIO_2, 1); 992 cx23885_gpio_set(dev, GPIO_2); 993 mdelay(20); 994 cx23885_gpio_clear(dev, GPIO_2); 995 mdelay(20); 996 cx23885_gpio_set(dev, GPIO_2); 997 mdelay(20); 998 break; 999 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1000 /* GPIO-0 tda10048 demodulator reset */ 1001 /* GPIO-2 tda18271 tuner reset */ 1002 1003 /* Put the parts into reset and back */ 1004 cx_set(GP0_IO, 0x00050000); 1005 mdelay(20); 1006 cx_clear(GP0_IO, 0x00000005); 1007 mdelay(20); 1008 cx_set(GP0_IO, 0x00050005); 1009 break; 1010 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1011 /* GPIO-0 TDA10048 demodulator reset */ 1012 /* GPIO-2 TDA8295A Reset */ 1013 /* GPIO-3-10 cx23417 data0-7 */ 1014 /* GPIO-11-14 cx23417 addr0-3 */ 1015 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1016 1017 /* The following GPIO's are on the interna AVCore (cx25840) */ 1018 /* GPIO-19 IR_RX */ 1019 /* GPIO-20 IR_TX 416/DVBT Select */ 1020 /* GPIO-21 IIS DAT */ 1021 /* GPIO-22 IIS WCLK */ 1022 /* GPIO-23 IIS BCLK */ 1023 1024 /* Put the parts into reset and back */ 1025 cx_set(GP0_IO, 0x00050000); 1026 mdelay(20); 1027 cx_clear(GP0_IO, 0x00000005); 1028 mdelay(20); 1029 cx_set(GP0_IO, 0x00050005); 1030 break; 1031 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1032 /* GPIO-0 Dibcom7000p demodulator reset */ 1033 /* GPIO-2 xc3028L tuner reset */ 1034 /* GPIO-13 LED */ 1035 1036 /* Put the parts into reset and back */ 1037 cx_set(GP0_IO, 0x00050000); 1038 mdelay(20); 1039 cx_clear(GP0_IO, 0x00000005); 1040 mdelay(20); 1041 cx_set(GP0_IO, 0x00050005); 1042 break; 1043 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1044 /* GPIO-0 xc5000 tuner reset i2c bus 0 */ 1045 /* GPIO-1 s5h1409 demod reset i2c bus 0 */ 1046 /* GPIO-2 xc5000 tuner reset i2c bus 1 */ 1047 /* GPIO-3 s5h1409 demod reset i2c bus 0 */ 1048 1049 /* Put the parts into reset and back */ 1050 cx_set(GP0_IO, 0x000f0000); 1051 mdelay(20); 1052 cx_clear(GP0_IO, 0x0000000f); 1053 mdelay(20); 1054 cx_set(GP0_IO, 0x000f000f); 1055 break; 1056 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1057 /* GPIO-0 portb xc3028 reset */ 1058 /* GPIO-1 portb zl10353 reset */ 1059 /* GPIO-2 portc xc3028 reset */ 1060 /* GPIO-3 portc zl10353 reset */ 1061 1062 /* Put the parts into reset and back */ 1063 cx_set(GP0_IO, 0x000f0000); 1064 mdelay(20); 1065 cx_clear(GP0_IO, 0x0000000f); 1066 mdelay(20); 1067 cx_set(GP0_IO, 0x000f000f); 1068 break; 1069 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1070 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1071 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1072 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1073 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1074 /* GPIO-2 xc3028 tuner reset */ 1075 1076 /* The following GPIO's are on the internal AVCore (cx25840) */ 1077 /* GPIO-? zl10353 demod reset */ 1078 1079 /* Put the parts into reset and back */ 1080 cx_set(GP0_IO, 0x00040000); 1081 mdelay(20); 1082 cx_clear(GP0_IO, 0x00000004); 1083 mdelay(20); 1084 cx_set(GP0_IO, 0x00040004); 1085 break; 1086 case CX23885_BOARD_TBS_6920: 1087 cx_write(MC417_CTL, 0x00000036); 1088 cx_write(MC417_OEN, 0x00001000); 1089 cx_set(MC417_RWD, 0x00000002); 1090 mdelay(200); 1091 cx_clear(MC417_RWD, 0x00000800); 1092 mdelay(200); 1093 cx_set(MC417_RWD, 0x00000800); 1094 mdelay(200); 1095 break; 1096 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1097 /* GPIO-0 INTA from CiMax1 1098 GPIO-1 INTB from CiMax2 1099 GPIO-2 reset chips 1100 GPIO-3 to GPIO-10 data/addr for CA 1101 GPIO-11 ~CS0 to CiMax1 1102 GPIO-12 ~CS1 to CiMax2 1103 GPIO-13 ADL0 load LSB addr 1104 GPIO-14 ADL1 load MSB addr 1105 GPIO-15 ~RDY from CiMax 1106 GPIO-17 ~RD to CiMax 1107 GPIO-18 ~WR to CiMax 1108 */ 1109 cx_set(GP0_IO, 0x00040000); /* GPIO as out */ 1110 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */ 1111 cx_clear(GP0_IO, 0x00030004); 1112 mdelay(100);/* reset delay */ 1113 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */ 1114 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */ 1115 /* GPIO-15 IN as ~ACK, rest as OUT */ 1116 cx_write(MC417_OEN, 0x00001000); 1117 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ 1118 cx_write(MC417_RWD, 0x0000c300); 1119 /* enable irq */ 1120 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1121 break; 1122 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1123 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1124 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1125 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1126 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */ 1127 /* GPIO-6 I2C Gate which can isolate the demod from the bus */ 1128 /* GPIO-9 Demod reset */ 1129 1130 /* Put the parts into reset and back */ 1131 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1); 1132 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5); 1133 cx23885_gpio_clear(dev, GPIO_9); 1134 mdelay(20); 1135 cx23885_gpio_set(dev, GPIO_9); 1136 break; 1137 case CX23885_BOARD_MYGICA_X8506: 1138 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1139 case CX23885_BOARD_MYGICA_X8507: 1140 /* GPIO-0 (0)Analog / (1)Digital TV */ 1141 /* GPIO-1 reset XC5000 */ 1142 /* GPIO-2 reset LGS8GL5 / LGS8G75 */ 1143 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1); 1144 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2); 1145 mdelay(100); 1146 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2); 1147 mdelay(100); 1148 break; 1149 case CX23885_BOARD_MYGICA_X8558PRO: 1150 /* GPIO-0 reset first ATBM8830 */ 1151 /* GPIO-1 reset second ATBM8830 */ 1152 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1); 1153 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1); 1154 mdelay(100); 1155 cx23885_gpio_set(dev, GPIO_0 | GPIO_1); 1156 mdelay(100); 1157 break; 1158 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1159 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1160 /* GPIO-0 656_CLK */ 1161 /* GPIO-1 656_D0 */ 1162 /* GPIO-2 Wake# */ 1163 /* GPIO-3-10 cx23417 data0-7 */ 1164 /* GPIO-11-14 cx23417 addr0-3 */ 1165 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 1166 /* GPIO-19 IR_RX */ 1167 /* GPIO-20 C_IR_TX */ 1168 /* GPIO-21 I2S DAT */ 1169 /* GPIO-22 I2S WCLK */ 1170 /* GPIO-23 I2S BCLK */ 1171 /* ALT GPIO: EXP GPIO LATCH */ 1172 1173 /* CX23417 GPIO's */ 1174 /* GPIO-14 S5H1411/CX24228 Reset */ 1175 /* GPIO-13 EEPROM write protect */ 1176 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1); 1177 1178 /* Put the demod into reset and protect the eeprom */ 1179 mc417_gpio_clear(dev, GPIO_14 | GPIO_13); 1180 mdelay(100); 1181 1182 /* Bring the demod out of reset */ 1183 mc417_gpio_set(dev, GPIO_14); 1184 mdelay(100); 1185 1186 /* CX24228 GPIO */ 1187 /* Connected to IF / Mux */ 1188 break; 1189 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1190 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */ 1191 break; 1192 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1193 /* GPIO-0 ~INT in 1194 GPIO-1 TMS out 1195 GPIO-2 ~reset chips out 1196 GPIO-3 to GPIO-10 data/addr for CA in/out 1197 GPIO-11 ~CS out 1198 GPIO-12 ADDR out 1199 GPIO-13 ~WR out 1200 GPIO-14 ~RD out 1201 GPIO-15 ~RDY in 1202 GPIO-16 TCK out 1203 GPIO-17 TDO in 1204 GPIO-18 TDI out 1205 */ 1206 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */ 1207 /* GPIO-0 as INT, reset & TMS low */ 1208 cx_clear(GP0_IO, 0x00010006); 1209 mdelay(100);/* reset delay */ 1210 cx_set(GP0_IO, 0x00000004); /* reset high */ 1211 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */ 1212 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */ 1213 cx_write(MC417_OEN, 0x00005000); 1214 /* ~RD, ~WR high; ADDR low; ~CS high */ 1215 cx_write(MC417_RWD, 0x00000d00); 1216 /* enable irq */ 1217 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ 1218 break; 1219 } 1220} 1221 1222int cx23885_ir_init(struct cx23885_dev *dev) 1223{ 1224 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = { 1225 { 1226 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1227 .pin = CX23885_PIN_IR_RX_GPIO19, 1228 .function = CX23885_PAD_IR_RX, 1229 .value = 0, 1230 .strength = CX25840_PIN_DRIVE_MEDIUM, 1231 }, { 1232 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT, 1233 .pin = CX23885_PIN_IR_TX_GPIO20, 1234 .function = CX23885_PAD_IR_TX, 1235 .value = 0, 1236 .strength = CX25840_PIN_DRIVE_MEDIUM, 1237 } 1238 }; 1239 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg); 1240 1241 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = { 1242 { 1243 .flags = V4L2_SUBDEV_IO_PIN_INPUT, 1244 .pin = CX23885_PIN_IR_RX_GPIO19, 1245 .function = CX23885_PAD_IR_RX, 1246 .value = 0, 1247 .strength = CX25840_PIN_DRIVE_MEDIUM, 1248 } 1249 }; 1250 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg); 1251 1252 struct v4l2_subdev_ir_parameters params; 1253 int ret = 0; 1254 switch (dev->board) { 1255 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1256 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1257 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1258 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1259 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1260 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1261 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1262 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1263 /* FIXME: Implement me */ 1264 break; 1265 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1266 ret = cx23888_ir_probe(dev); 1267 if (ret) 1268 break; 1269 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1270 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1271 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1272 break; 1273 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1274 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1275 ret = cx23888_ir_probe(dev); 1276 if (ret) 1277 break; 1278 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR); 1279 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1280 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1281 /* 1282 * For these boards we need to invert the Tx output via the 1283 * IR controller to have the LED off while idle 1284 */ 1285 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, ¶ms); 1286 params.enable = false; 1287 params.shutdown = false; 1288 params.invert_level = true; 1289 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1290 params.shutdown = true; 1291 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, ¶ms); 1292 break; 1293 case CX23885_BOARD_TEVII_S470: 1294 if (!enable_885_ir) 1295 break; 1296 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1297 if (dev->sd_ir == NULL) { 1298 ret = -ENODEV; 1299 break; 1300 } 1301 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1302 ir_rx_pin_cfg_count, ir_rx_pin_cfg); 1303 break; 1304 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1305 if (!enable_885_ir) 1306 break; 1307 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); 1308 if (dev->sd_ir == NULL) { 1309 ret = -ENODEV; 1310 break; 1311 } 1312 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, 1313 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg); 1314 break; 1315 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1316 request_module("ir-kbd-i2c"); 1317 break; 1318 } 1319 1320 return ret; 1321} 1322 1323void cx23885_ir_fini(struct cx23885_dev *dev) 1324{ 1325 switch (dev->board) { 1326 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1327 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1328 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1329 cx23885_irq_remove(dev, PCI_MSK_IR); 1330 cx23888_ir_remove(dev); 1331 dev->sd_ir = NULL; 1332 break; 1333 case CX23885_BOARD_TEVII_S470: 1334 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1335 cx23885_irq_remove(dev, PCI_MSK_AV_CORE); 1336 /* sd_ir is a duplicate pointer to the AV Core, just clear it */ 1337 dev->sd_ir = NULL; 1338 break; 1339 } 1340} 1341 1342int netup_jtag_io(void *device, int tms, int tdi, int read_tdo) 1343{ 1344 int data; 1345 int tdo = 0; 1346 struct cx23885_dev *dev = (struct cx23885_dev *)device; 1347 /*TMS*/ 1348 data = ((cx_read(GP0_IO)) & (~0x00000002)); 1349 data |= (tms ? 0x00020002 : 0x00020000); 1350 cx_write(GP0_IO, data); 1351 1352 /*TDI*/ 1353 data = ((cx_read(MC417_RWD)) & (~0x0000a000)); 1354 data |= (tdi ? 0x00008000 : 0); 1355 cx_write(MC417_RWD, data); 1356 if (read_tdo) 1357 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/ 1358 1359 cx_write(MC417_RWD, data | 0x00002000); 1360 udelay(1); 1361 /*TCK*/ 1362 cx_write(MC417_RWD, data); 1363 1364 return tdo; 1365} 1366 1367void cx23885_ir_pci_int_enable(struct cx23885_dev *dev) 1368{ 1369 switch (dev->board) { 1370 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1371 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1372 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1373 if (dev->sd_ir) 1374 cx23885_irq_add_enable(dev, PCI_MSK_IR); 1375 break; 1376 case CX23885_BOARD_TEVII_S470: 1377 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1378 if (dev->sd_ir) 1379 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE); 1380 break; 1381 } 1382} 1383 1384void cx23885_card_setup(struct cx23885_dev *dev) 1385{ 1386 struct cx23885_tsport *ts1 = &dev->ts1; 1387 struct cx23885_tsport *ts2 = &dev->ts2; 1388 1389 static u8 eeprom[256]; 1390 1391 if (dev->i2c_bus[0].i2c_rc == 0) { 1392 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; 1393 tveeprom_read(&dev->i2c_bus[0].i2c_client, 1394 eeprom, sizeof(eeprom)); 1395 } 1396 1397 switch (dev->board) { 1398 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1399 if (dev->i2c_bus[0].i2c_rc == 0) { 1400 if (eeprom[0x80] != 0x84) 1401 hauppauge_eeprom(dev, eeprom+0xc0); 1402 else 1403 hauppauge_eeprom(dev, eeprom+0x80); 1404 } 1405 break; 1406 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1407 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1408 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1409 if (dev->i2c_bus[0].i2c_rc == 0) 1410 hauppauge_eeprom(dev, eeprom+0x80); 1411 break; 1412 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1413 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1414 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1415 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1416 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1417 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1418 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1419 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1420 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1421 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1422 if (dev->i2c_bus[0].i2c_rc == 0) 1423 hauppauge_eeprom(dev, eeprom+0xc0); 1424 break; 1425 } 1426 1427 switch (dev->board) { 1428 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: 1429 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: 1430 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1431 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1432 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1433 /* break omitted intentionally */ 1434 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: 1435 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1436 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1437 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1438 break; 1439 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1440 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1441 /* Defaults for VID B - Analog encoder */ 1442 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */ 1443 ts1->gen_ctrl_val = 0x10e; 1444 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1445 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1446 1447 /* APB_TSVALERR_POL (active low)*/ 1448 ts1->vld_misc_val = 0x2000; 1449 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc); 1450 cx_write(0x130184, 0xc); 1451 1452 /* Defaults for VID C */ 1453 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1454 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1455 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1456 break; 1457 case CX23885_BOARD_TBS_6920: 1458 ts1->gen_ctrl_val = 0x4; /* Parallel */ 1459 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1460 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1461 break; 1462 case CX23885_BOARD_TEVII_S470: 1463 case CX23885_BOARD_DVBWORLD_2005: 1464 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1465 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1466 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1467 break; 1468 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1469 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1470 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1471 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1472 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1473 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1474 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1475 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1476 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1477 break; 1478 case CX23885_BOARD_MYGICA_X8506: 1479 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1480 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1481 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1482 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1483 break; 1484 case CX23885_BOARD_MYGICA_X8558PRO: 1485 ts1->gen_ctrl_val = 0x5; /* Parallel */ 1486 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1487 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1488 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1489 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1490 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1491 break; 1492 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1493 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1494 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 1495 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1496 case CX23885_BOARD_HAUPPAUGE_HVR1200: 1497 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1498 case CX23885_BOARD_HAUPPAUGE_HVR1400: 1499 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1500 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1501 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1502 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1503 case CX23885_BOARD_HAUPPAUGE_HVR1275: 1504 case CX23885_BOARD_HAUPPAUGE_HVR1255: 1505 case CX23885_BOARD_HAUPPAUGE_HVR1210: 1506 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1507 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1508 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1509 default: 1510 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 1511 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 1512 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 1513 } 1514 1515 /* Certain boards support analog, or require the avcore to be 1516 * loaded, ensure this happens. 1517 */ 1518 switch (dev->board) { 1519 case CX23885_BOARD_TEVII_S470: 1520 case CX23885_BOARD_HAUPPAUGE_HVR1250: 1521 /* Currently only enabled for the integrated IR controller */ 1522 if (!enable_885_ir) 1523 break; 1524 case CX23885_BOARD_HAUPPAUGE_HVR1800: 1525 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 1526 case CX23885_BOARD_HAUPPAUGE_HVR1700: 1527 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: 1528 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: 1529 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: 1530 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1531 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: 1532 case CX23885_BOARD_COMPRO_VIDEOMATE_E800: 1533 case CX23885_BOARD_HAUPPAUGE_HVR1270: 1534 case CX23885_BOARD_HAUPPAUGE_HVR1850: 1535 case CX23885_BOARD_MYGICA_X8506: 1536 case CX23885_BOARD_MAGICPRO_PROHDTVE2: 1537 case CX23885_BOARD_HAUPPAUGE_HVR1290: 1538 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200: 1539 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID: 1540 case CX23885_BOARD_HAUPPAUGE_HVR1500: 1541 case CX23885_BOARD_MPX885: 1542 case CX23885_BOARD_MYGICA_X8507: 1543 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: 1544 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, 1545 &dev->i2c_bus[2].i2c_adap, 1546 "cx25840", 0x88 >> 1, NULL); 1547 if (dev->sd_cx25840) { 1548 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE; 1549 v4l2_subdev_call(dev->sd_cx25840, core, load_fw); 1550 } 1551 break; 1552 } 1553 1554 /* AUX-PLL 27MHz CLK */ 1555 switch (dev->board) { 1556 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: 1557 netup_initialize(dev); 1558 break; 1559 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { 1560 int ret; 1561 const struct firmware *fw; 1562 const char *filename = "dvb-netup-altera-01.fw"; 1563 char *action = "configure"; 1564 static struct netup_card_info cinfo; 1565 struct altera_config netup_config = { 1566 .dev = dev, 1567 .action = action, 1568 .jtag_io = netup_jtag_io, 1569 }; 1570 1571 netup_initialize(dev); 1572 1573 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); 1574 if (netup_card_rev) 1575 cinfo.rev = netup_card_rev; 1576 1577 switch (cinfo.rev) { 1578 case 0x4: 1579 filename = "dvb-netup-altera-04.fw"; 1580 break; 1581 default: 1582 filename = "dvb-netup-altera-01.fw"; 1583 break; 1584 } 1585 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n", 1586 cinfo.rev, filename); 1587 1588 ret = request_firmware(&fw, filename, &dev->pci->dev); 1589 if (ret != 0) 1590 printk(KERN_ERR "did not find the firmware file. (%s) " 1591 "Please see linux/Documentation/dvb/ for more details " 1592 "on firmware-problems.", filename); 1593 else 1594 altera_init(&netup_config, fw); 1595 1596 release_firmware(fw); 1597 break; 1598 } 1599 } 1600} 1601 1602/* ------------------------------------------------------------------ */ 1603