1/** 2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com 5 * Author: Keshava Munegowda <keshava_mgowda@ti.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 of 9 * the License as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19#include <linux/kernel.h> 20#include <linux/module.h> 21#include <linux/types.h> 22#include <linux/slab.h> 23#include <linux/delay.h> 24#include <linux/platform_device.h> 25#include <linux/clk.h> 26#include <linux/dma-mapping.h> 27#include <linux/spinlock.h> 28#include <plat/cpu.h> 29#include <plat/usb.h> 30#include <linux/pm_runtime.h> 31 32#define USBHS_DRIVER_NAME "usbhs_omap" 33#define OMAP_EHCI_DEVICE "ehci-omap" 34#define OMAP_OHCI_DEVICE "ohci-omap3" 35 36/* OMAP USBHOST Register addresses */ 37 38/* TLL Register Set */ 39#define OMAP_USBTLL_REVISION (0x00) 40#define OMAP_USBTLL_SYSCONFIG (0x10) 41#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) 42#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) 43#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) 44#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) 45#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0) 46 47#define OMAP_USBTLL_SYSSTATUS (0x14) 48#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) 49 50#define OMAP_USBTLL_IRQSTATUS (0x18) 51#define OMAP_USBTLL_IRQENABLE (0x1C) 52 53#define OMAP_TLL_SHARED_CONF (0x30) 54#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6) 55#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5) 56#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2) 57#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1) 58#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0) 59 60#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num) 61#define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24 62#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) 63#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10) 64#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9) 65#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8) 66#define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1) 67#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0) 68 69#define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0 70#define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1 71#define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2 72#define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3 73#define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4 74#define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5 75#define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6 76#define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7 77#define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA 78#define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB 79 80#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num) 81#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num) 82#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num) 83#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num) 84#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num) 85#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num) 86#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num) 87#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num) 88#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num) 89 90#define OMAP_TLL_CHANNEL_COUNT 3 91#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0) 92#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1) 93#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2) 94 95/* UHH Register Set */ 96#define OMAP_UHH_REVISION (0x00) 97#define OMAP_UHH_SYSCONFIG (0x10) 98#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) 99#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) 100#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) 101#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) 102#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) 103#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0) 104 105#define OMAP_UHH_SYSSTATUS (0x14) 106#define OMAP_UHH_HOSTCONFIG (0x40) 107#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0) 108#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0) 109#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) 110#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) 111#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) 112#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) 113#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) 114#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) 115#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8) 116#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9) 117#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10) 118#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31) 119 120/* OMAP4-specific defines */ 121#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2) 122#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2) 123#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4) 124#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4) 125#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0) 126 127#define OMAP4_P1_MODE_CLEAR (3 << 16) 128#define OMAP4_P1_MODE_TLL (1 << 16) 129#define OMAP4_P1_MODE_HSIC (3 << 16) 130#define OMAP4_P2_MODE_CLEAR (3 << 18) 131#define OMAP4_P2_MODE_TLL (1 << 18) 132#define OMAP4_P2_MODE_HSIC (3 << 18) 133 134#define OMAP_REV2_TLL_CHANNEL_COUNT 2 135 136#define OMAP_UHH_DEBUG_CSR (0x44) 137 138/* Values of UHH_REVISION - Note: these are not given in the TRM */ 139#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */ 140#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */ 141 142#define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1) 143#define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2) 144 145#define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY) 146#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL) 147#define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC) 148 149 150struct usbhs_hcd_omap { 151 struct clk *xclk60mhsp1_ck; 152 struct clk *xclk60mhsp2_ck; 153 struct clk *utmi_p1_fck; 154 struct clk *usbhost_p1_fck; 155 struct clk *usbtll_p1_fck; 156 struct clk *utmi_p2_fck; 157 struct clk *usbhost_p2_fck; 158 struct clk *usbtll_p2_fck; 159 struct clk *init_60m_fclk; 160 struct clk *ehci_logic_fck; 161 162 void __iomem *uhh_base; 163 void __iomem *tll_base; 164 165 struct usbhs_omap_platform_data platdata; 166 167 u32 usbhs_rev; 168 spinlock_t lock; 169}; 170/*-------------------------------------------------------------------------*/ 171 172const char usbhs_driver_name[] = USBHS_DRIVER_NAME; 173static u64 usbhs_dmamask = DMA_BIT_MASK(32); 174 175/*-------------------------------------------------------------------------*/ 176 177static inline void usbhs_write(void __iomem *base, u32 reg, u32 val) 178{ 179 __raw_writel(val, base + reg); 180} 181 182static inline u32 usbhs_read(void __iomem *base, u32 reg) 183{ 184 return __raw_readl(base + reg); 185} 186 187static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val) 188{ 189 __raw_writeb(val, base + reg); 190} 191 192static inline u8 usbhs_readb(void __iomem *base, u8 reg) 193{ 194 return __raw_readb(base + reg); 195} 196 197/*-------------------------------------------------------------------------*/ 198 199static struct platform_device *omap_usbhs_alloc_child(const char *name, 200 struct resource *res, int num_resources, void *pdata, 201 size_t pdata_size, struct device *dev) 202{ 203 struct platform_device *child; 204 int ret; 205 206 child = platform_device_alloc(name, 0); 207 208 if (!child) { 209 dev_err(dev, "platform_device_alloc %s failed\n", name); 210 goto err_end; 211 } 212 213 ret = platform_device_add_resources(child, res, num_resources); 214 if (ret) { 215 dev_err(dev, "platform_device_add_resources failed\n"); 216 goto err_alloc; 217 } 218 219 ret = platform_device_add_data(child, pdata, pdata_size); 220 if (ret) { 221 dev_err(dev, "platform_device_add_data failed\n"); 222 goto err_alloc; 223 } 224 225 child->dev.dma_mask = &usbhs_dmamask; 226 dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32)); 227 child->dev.parent = dev; 228 229 ret = platform_device_add(child); 230 if (ret) { 231 dev_err(dev, "platform_device_add failed\n"); 232 goto err_alloc; 233 } 234 235 return child; 236 237err_alloc: 238 platform_device_put(child); 239 240err_end: 241 return NULL; 242} 243 244static int omap_usbhs_alloc_children(struct platform_device *pdev) 245{ 246 struct device *dev = &pdev->dev; 247 struct usbhs_hcd_omap *omap; 248 struct ehci_hcd_omap_platform_data *ehci_data; 249 struct ohci_hcd_omap_platform_data *ohci_data; 250 struct platform_device *ehci; 251 struct platform_device *ohci; 252 struct resource *res; 253 struct resource resources[2]; 254 int ret; 255 256 omap = platform_get_drvdata(pdev); 257 ehci_data = omap->platdata.ehci_data; 258 ohci_data = omap->platdata.ohci_data; 259 260 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci"); 261 if (!res) { 262 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n"); 263 ret = -ENODEV; 264 goto err_end; 265 } 266 resources[0] = *res; 267 268 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq"); 269 if (!res) { 270 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n"); 271 ret = -ENODEV; 272 goto err_end; 273 } 274 resources[1] = *res; 275 276 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data, 277 sizeof(*ehci_data), dev); 278 279 if (!ehci) { 280 dev_err(dev, "omap_usbhs_alloc_child failed\n"); 281 ret = -ENOMEM; 282 goto err_end; 283 } 284 285 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci"); 286 if (!res) { 287 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n"); 288 ret = -ENODEV; 289 goto err_ehci; 290 } 291 resources[0] = *res; 292 293 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq"); 294 if (!res) { 295 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n"); 296 ret = -ENODEV; 297 goto err_ehci; 298 } 299 resources[1] = *res; 300 301 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data, 302 sizeof(*ohci_data), dev); 303 if (!ohci) { 304 dev_err(dev, "omap_usbhs_alloc_child failed\n"); 305 ret = -ENOMEM; 306 goto err_ehci; 307 } 308 309 return 0; 310 311err_ehci: 312 platform_device_unregister(ehci); 313 314err_end: 315 return ret; 316} 317 318static bool is_ohci_port(enum usbhs_omap_port_mode pmode) 319{ 320 switch (pmode) { 321 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: 322 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: 323 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: 324 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: 325 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: 326 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: 327 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: 328 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: 329 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: 330 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: 331 return true; 332 333 default: 334 return false; 335 } 336} 337 338/* 339 * convert the port-mode enum to a value we can use in the FSLSMODE 340 * field of USBTLL_CHANNEL_CONF 341 */ 342static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode) 343{ 344 switch (mode) { 345 case OMAP_USBHS_PORT_MODE_UNUSED: 346 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: 347 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0; 348 349 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: 350 return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM; 351 352 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: 353 return OMAP_TLL_FSLSMODE_3PIN_PHY; 354 355 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: 356 return OMAP_TLL_FSLSMODE_4PIN_PHY; 357 358 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: 359 return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0; 360 361 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: 362 return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM; 363 364 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: 365 return OMAP_TLL_FSLSMODE_3PIN_TLL; 366 367 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: 368 return OMAP_TLL_FSLSMODE_4PIN_TLL; 369 370 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: 371 return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0; 372 373 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: 374 return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM; 375 default: 376 pr_warning("Invalid port mode, using default\n"); 377 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0; 378 } 379} 380 381static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count) 382{ 383 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); 384 struct usbhs_omap_platform_data *pdata = dev->platform_data; 385 unsigned reg; 386 int i; 387 388 /* Program Common TLL register */ 389 reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF); 390 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON 391 | OMAP_TLL_SHARED_CONF_USB_DIVRATION); 392 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; 393 reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN; 394 395 usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg); 396 397 /* Enable channels now */ 398 for (i = 0; i < tll_channel_count; i++) { 399 reg = usbhs_read(omap->tll_base, 400 OMAP_TLL_CHANNEL_CONF(i)); 401 402 if (is_ohci_port(pdata->port_mode[i])) { 403 reg |= ohci_omap3_fslsmode(pdata->port_mode[i]) 404 << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT; 405 reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS; 406 } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) { 407 408 /* Disable AutoIdle, BitStuffing and use SDR Mode */ 409 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE 410 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF 411 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE); 412 413 } else 414 continue; 415 416 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; 417 usbhs_write(omap->tll_base, 418 OMAP_TLL_CHANNEL_CONF(i), reg); 419 420 usbhs_writeb(omap->tll_base, 421 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe); 422 } 423} 424 425static int usbhs_runtime_resume(struct device *dev) 426{ 427 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); 428 struct usbhs_omap_platform_data *pdata = &omap->platdata; 429 unsigned long flags; 430 431 dev_dbg(dev, "usbhs_runtime_resume\n"); 432 433 if (!pdata) { 434 dev_dbg(dev, "missing platform_data\n"); 435 return -ENODEV; 436 } 437 438 spin_lock_irqsave(&omap->lock, flags); 439 440 if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck)) 441 clk_enable(omap->ehci_logic_fck); 442 443 if (is_ehci_tll_mode(pdata->port_mode[0])) { 444 clk_enable(omap->usbhost_p1_fck); 445 clk_enable(omap->usbtll_p1_fck); 446 } 447 if (is_ehci_tll_mode(pdata->port_mode[1])) { 448 clk_enable(omap->usbhost_p2_fck); 449 clk_enable(omap->usbtll_p2_fck); 450 } 451 clk_enable(omap->utmi_p1_fck); 452 clk_enable(omap->utmi_p2_fck); 453 454 spin_unlock_irqrestore(&omap->lock, flags); 455 456 return 0; 457} 458 459static int usbhs_runtime_suspend(struct device *dev) 460{ 461 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); 462 struct usbhs_omap_platform_data *pdata = &omap->platdata; 463 unsigned long flags; 464 465 dev_dbg(dev, "usbhs_runtime_suspend\n"); 466 467 if (!pdata) { 468 dev_dbg(dev, "missing platform_data\n"); 469 return -ENODEV; 470 } 471 472 spin_lock_irqsave(&omap->lock, flags); 473 474 if (is_ehci_tll_mode(pdata->port_mode[0])) { 475 clk_disable(omap->usbhost_p1_fck); 476 clk_disable(omap->usbtll_p1_fck); 477 } 478 if (is_ehci_tll_mode(pdata->port_mode[1])) { 479 clk_disable(omap->usbhost_p2_fck); 480 clk_disable(omap->usbtll_p2_fck); 481 } 482 clk_disable(omap->utmi_p2_fck); 483 clk_disable(omap->utmi_p1_fck); 484 485 if (omap->ehci_logic_fck && !IS_ERR(omap->ehci_logic_fck)) 486 clk_disable(omap->ehci_logic_fck); 487 488 spin_unlock_irqrestore(&omap->lock, flags); 489 490 return 0; 491} 492 493static void omap_usbhs_init(struct device *dev) 494{ 495 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); 496 struct usbhs_omap_platform_data *pdata = &omap->platdata; 497 unsigned long flags; 498 unsigned reg; 499 500 dev_dbg(dev, "starting TI HSUSB Controller\n"); 501 502 pm_runtime_get_sync(dev); 503 spin_lock_irqsave(&omap->lock, flags); 504 505 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); 506 dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); 507 508 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG); 509 /* setup ULPI bypass and burst configurations */ 510 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN 511 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN 512 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); 513 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK; 514 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; 515 516 if (is_omap_usbhs_rev1(omap)) { 517 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) 518 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; 519 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) 520 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; 521 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) 522 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; 523 524 /* Bypass the TLL module for PHY mode operation */ 525 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { 526 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n"); 527 if (is_ehci_phy_mode(pdata->port_mode[0]) || 528 is_ehci_phy_mode(pdata->port_mode[1]) || 529 is_ehci_phy_mode(pdata->port_mode[2])) 530 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; 531 else 532 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; 533 } else { 534 dev_dbg(dev, "OMAP3 ES version > ES2.1\n"); 535 if (is_ehci_phy_mode(pdata->port_mode[0])) 536 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; 537 else 538 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; 539 if (is_ehci_phy_mode(pdata->port_mode[1])) 540 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; 541 else 542 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; 543 if (is_ehci_phy_mode(pdata->port_mode[2])) 544 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; 545 else 546 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; 547 } 548 } else if (is_omap_usbhs_rev2(omap)) { 549 /* Clear port mode fields for PHY mode*/ 550 reg &= ~OMAP4_P1_MODE_CLEAR; 551 reg &= ~OMAP4_P2_MODE_CLEAR; 552 553 if (is_ehci_tll_mode(pdata->port_mode[0]) || 554 (is_ohci_port(pdata->port_mode[0]))) 555 reg |= OMAP4_P1_MODE_TLL; 556 else if (is_ehci_hsic_mode(pdata->port_mode[0])) 557 reg |= OMAP4_P1_MODE_HSIC; 558 559 if (is_ehci_tll_mode(pdata->port_mode[1]) || 560 (is_ohci_port(pdata->port_mode[1]))) 561 reg |= OMAP4_P2_MODE_TLL; 562 else if (is_ehci_hsic_mode(pdata->port_mode[1])) 563 reg |= OMAP4_P2_MODE_HSIC; 564 } 565 566 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); 567 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); 568 569 if (is_ehci_tll_mode(pdata->port_mode[0]) || 570 is_ehci_tll_mode(pdata->port_mode[1]) || 571 is_ehci_tll_mode(pdata->port_mode[2]) || 572 (is_ohci_port(pdata->port_mode[0])) || 573 (is_ohci_port(pdata->port_mode[1])) || 574 (is_ohci_port(pdata->port_mode[2]))) { 575 576 /* Enable UTMI mode for required TLL channels */ 577 if (is_omap_usbhs_rev2(omap)) 578 usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT); 579 else 580 usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT); 581 } 582 583 spin_unlock_irqrestore(&omap->lock, flags); 584 pm_runtime_put_sync(dev); 585} 586 587 588/** 589 * usbhs_omap_probe - initialize TI-based HCDs 590 * 591 * Allocates basic resources for this USB host controller. 592 */ 593static int __devinit usbhs_omap_probe(struct platform_device *pdev) 594{ 595 struct device *dev = &pdev->dev; 596 struct usbhs_omap_platform_data *pdata = dev->platform_data; 597 struct usbhs_hcd_omap *omap; 598 struct resource *res; 599 int ret = 0; 600 int i; 601 602 if (!pdata) { 603 dev_err(dev, "Missing platform data\n"); 604 ret = -ENOMEM; 605 goto end_probe; 606 } 607 608 omap = kzalloc(sizeof(*omap), GFP_KERNEL); 609 if (!omap) { 610 dev_err(dev, "Memory allocation failed\n"); 611 ret = -ENOMEM; 612 goto end_probe; 613 } 614 615 spin_lock_init(&omap->lock); 616 617 for (i = 0; i < OMAP3_HS_USB_PORTS; i++) 618 omap->platdata.port_mode[i] = pdata->port_mode[i]; 619 620 omap->platdata.ehci_data = pdata->ehci_data; 621 omap->platdata.ohci_data = pdata->ohci_data; 622 623 pm_runtime_enable(dev); 624 625 626 for (i = 0; i < OMAP3_HS_USB_PORTS; i++) 627 if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) || 628 is_ehci_hsic_mode(i)) { 629 omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck"); 630 if (IS_ERR(omap->ehci_logic_fck)) { 631 ret = PTR_ERR(omap->ehci_logic_fck); 632 dev_warn(dev, "ehci_logic_fck failed:%d\n", 633 ret); 634 } 635 break; 636 } 637 638 omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk"); 639 if (IS_ERR(omap->utmi_p1_fck)) { 640 ret = PTR_ERR(omap->utmi_p1_fck); 641 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret); 642 goto err_end; 643 } 644 645 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck"); 646 if (IS_ERR(omap->xclk60mhsp1_ck)) { 647 ret = PTR_ERR(omap->xclk60mhsp1_ck); 648 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret); 649 goto err_utmi_p1_fck; 650 } 651 652 omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk"); 653 if (IS_ERR(omap->utmi_p2_fck)) { 654 ret = PTR_ERR(omap->utmi_p2_fck); 655 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret); 656 goto err_xclk60mhsp1_ck; 657 } 658 659 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck"); 660 if (IS_ERR(omap->xclk60mhsp2_ck)) { 661 ret = PTR_ERR(omap->xclk60mhsp2_ck); 662 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret); 663 goto err_utmi_p2_fck; 664 } 665 666 omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk"); 667 if (IS_ERR(omap->usbhost_p1_fck)) { 668 ret = PTR_ERR(omap->usbhost_p1_fck); 669 dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret); 670 goto err_xclk60mhsp2_ck; 671 } 672 673 omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk"); 674 if (IS_ERR(omap->usbtll_p1_fck)) { 675 ret = PTR_ERR(omap->usbtll_p1_fck); 676 dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret); 677 goto err_usbhost_p1_fck; 678 } 679 680 omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk"); 681 if (IS_ERR(omap->usbhost_p2_fck)) { 682 ret = PTR_ERR(omap->usbhost_p2_fck); 683 dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret); 684 goto err_usbtll_p1_fck; 685 } 686 687 omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk"); 688 if (IS_ERR(omap->usbtll_p2_fck)) { 689 ret = PTR_ERR(omap->usbtll_p2_fck); 690 dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret); 691 goto err_usbhost_p2_fck; 692 } 693 694 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk"); 695 if (IS_ERR(omap->init_60m_fclk)) { 696 ret = PTR_ERR(omap->init_60m_fclk); 697 dev_err(dev, "init_60m_fclk failed error:%d\n", ret); 698 goto err_usbtll_p2_fck; 699 } 700 701 if (is_ehci_phy_mode(pdata->port_mode[0])) { 702 /* for OMAP3 , the clk set paretn fails */ 703 ret = clk_set_parent(omap->utmi_p1_fck, 704 omap->xclk60mhsp1_ck); 705 if (ret != 0) 706 dev_err(dev, "xclk60mhsp1_ck set parent" 707 "failed error:%d\n", ret); 708 } else if (is_ehci_tll_mode(pdata->port_mode[0])) { 709 ret = clk_set_parent(omap->utmi_p1_fck, 710 omap->init_60m_fclk); 711 if (ret != 0) 712 dev_err(dev, "init_60m_fclk set parent" 713 "failed error:%d\n", ret); 714 } 715 716 if (is_ehci_phy_mode(pdata->port_mode[1])) { 717 ret = clk_set_parent(omap->utmi_p2_fck, 718 omap->xclk60mhsp2_ck); 719 if (ret != 0) 720 dev_err(dev, "xclk60mhsp2_ck set parent" 721 "failed error:%d\n", ret); 722 } else if (is_ehci_tll_mode(pdata->port_mode[1])) { 723 ret = clk_set_parent(omap->utmi_p2_fck, 724 omap->init_60m_fclk); 725 if (ret != 0) 726 dev_err(dev, "init_60m_fclk set parent" 727 "failed error:%d\n", ret); 728 } 729 730 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh"); 731 if (!res) { 732 dev_err(dev, "UHH EHCI get resource failed\n"); 733 ret = -ENODEV; 734 goto err_init_60m_fclk; 735 } 736 737 omap->uhh_base = ioremap(res->start, resource_size(res)); 738 if (!omap->uhh_base) { 739 dev_err(dev, "UHH ioremap failed\n"); 740 ret = -ENOMEM; 741 goto err_init_60m_fclk; 742 } 743 744 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll"); 745 if (!res) { 746 dev_err(dev, "UHH EHCI get resource failed\n"); 747 ret = -ENODEV; 748 goto err_tll; 749 } 750 751 omap->tll_base = ioremap(res->start, resource_size(res)); 752 if (!omap->tll_base) { 753 dev_err(dev, "TLL ioremap failed\n"); 754 ret = -ENOMEM; 755 goto err_tll; 756 } 757 758 platform_set_drvdata(pdev, omap); 759 760 omap_usbhs_init(dev); 761 ret = omap_usbhs_alloc_children(pdev); 762 if (ret) { 763 dev_err(dev, "omap_usbhs_alloc_children failed\n"); 764 goto err_alloc; 765 } 766 767 goto end_probe; 768 769err_alloc: 770 iounmap(omap->tll_base); 771 772err_tll: 773 iounmap(omap->uhh_base); 774 775err_init_60m_fclk: 776 clk_put(omap->init_60m_fclk); 777 778err_usbtll_p2_fck: 779 clk_put(omap->usbtll_p2_fck); 780 781err_usbhost_p2_fck: 782 clk_put(omap->usbhost_p2_fck); 783 784err_usbtll_p1_fck: 785 clk_put(omap->usbtll_p1_fck); 786 787err_usbhost_p1_fck: 788 clk_put(omap->usbhost_p1_fck); 789 790err_xclk60mhsp2_ck: 791 clk_put(omap->xclk60mhsp2_ck); 792 793err_utmi_p2_fck: 794 clk_put(omap->utmi_p2_fck); 795 796err_xclk60mhsp1_ck: 797 clk_put(omap->xclk60mhsp1_ck); 798 799err_utmi_p1_fck: 800 clk_put(omap->utmi_p1_fck); 801 802err_end: 803 clk_put(omap->ehci_logic_fck); 804 pm_runtime_disable(dev); 805 kfree(omap); 806 807end_probe: 808 return ret; 809} 810 811/** 812 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs 813 * @pdev: USB Host Controller being removed 814 * 815 * Reverses the effect of usbhs_omap_probe(). 816 */ 817static int __devexit usbhs_omap_remove(struct platform_device *pdev) 818{ 819 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev); 820 821 iounmap(omap->tll_base); 822 iounmap(omap->uhh_base); 823 clk_put(omap->init_60m_fclk); 824 clk_put(omap->usbtll_p2_fck); 825 clk_put(omap->usbhost_p2_fck); 826 clk_put(omap->usbtll_p1_fck); 827 clk_put(omap->usbhost_p1_fck); 828 clk_put(omap->xclk60mhsp2_ck); 829 clk_put(omap->utmi_p2_fck); 830 clk_put(omap->xclk60mhsp1_ck); 831 clk_put(omap->utmi_p1_fck); 832 clk_put(omap->ehci_logic_fck); 833 pm_runtime_disable(&pdev->dev); 834 kfree(omap); 835 836 return 0; 837} 838 839static const struct dev_pm_ops usbhsomap_dev_pm_ops = { 840 .runtime_suspend = usbhs_runtime_suspend, 841 .runtime_resume = usbhs_runtime_resume, 842}; 843 844static struct platform_driver usbhs_omap_driver = { 845 .driver = { 846 .name = (char *)usbhs_driver_name, 847 .owner = THIS_MODULE, 848 .pm = &usbhsomap_dev_pm_ops, 849 }, 850 .remove = __exit_p(usbhs_omap_remove), 851}; 852 853MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>"); 854MODULE_ALIAS("platform:" USBHS_DRIVER_NAME); 855MODULE_LICENSE("GPL v2"); 856MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI"); 857 858static int __init omap_usbhs_drvinit(void) 859{ 860 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe); 861} 862 863/* 864 * init before ehci and ohci drivers; 865 * The usbhs core driver should be initialized much before 866 * the omap ehci and ohci probe functions are called. 867 */ 868fs_initcall(omap_usbhs_drvinit); 869 870static void __exit omap_usbhs_drvexit(void) 871{ 872 platform_driver_unregister(&usbhs_omap_driver); 873} 874module_exit(omap_usbhs_drvexit); 875