1/* 2 * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver 3 * 4 * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved 5 * 6 * Copyright (C) 2006 Malcolm Noyes 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13/* 14 This is the AT91 MCI driver that has been tested with both MMC cards 15 and SD-cards. Boards that support write protect are now supported. 16 The CCAT91SBC001 board does not support SD cards. 17 18 The three entry points are at91_mci_request, at91_mci_set_ios 19 and at91_mci_get_ro. 20 21 SET IOS 22 This configures the device to put it into the correct mode and clock speed 23 required. 24 25 MCI REQUEST 26 MCI request processes the commands sent in the mmc_request structure. This 27 can consist of a processing command and a stop command in the case of 28 multiple block transfers. 29 30 There are three main types of request, commands, reads and writes. 31 32 Commands are straight forward. The command is submitted to the controller and 33 the request function returns. When the controller generates an interrupt to indicate 34 the command is finished, the response to the command are read and the mmc_request_done 35 function called to end the request. 36 37 Reads and writes work in a similar manner to normal commands but involve the PDC (DMA) 38 controller to manage the transfers. 39 40 A read is done from the controller directly to the scatterlist passed in from the request. 41 Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte 42 swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug. 43 44 The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY 45 46 A write is slightly different in that the bytes to write are read from the scatterlist 47 into a dma memory buffer (this is in case the source buffer should be read only). The 48 entire write buffer is then done from this single dma memory buffer. 49 50 The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY 51 52 GET RO 53 Gets the status of the write protect pin, if available. 54*/ 55 56#include <linux/module.h> 57#include <linux/moduleparam.h> 58#include <linux/init.h> 59#include <linux/ioport.h> 60#include <linux/platform_device.h> 61#include <linux/interrupt.h> 62#include <linux/blkdev.h> 63#include <linux/delay.h> 64#include <linux/err.h> 65#include <linux/dma-mapping.h> 66#include <linux/clk.h> 67#include <linux/atmel_pdc.h> 68#include <linux/gfp.h> 69#include <linux/highmem.h> 70 71#include <linux/mmc/host.h> 72#include <linux/mmc/sdio.h> 73 74#include <asm/io.h> 75#include <asm/irq.h> 76#include <asm/gpio.h> 77 78#include <mach/board.h> 79#include <mach/cpu.h> 80 81#include "at91_mci.h" 82 83#define DRIVER_NAME "at91_mci" 84 85static inline int at91mci_is_mci1rev2xx(void) 86{ 87 return ( cpu_is_at91sam9260() 88 || cpu_is_at91sam9263() 89 || cpu_is_at91sam9rl() 90 || cpu_is_at91sam9g10() 91 || cpu_is_at91sam9g20() 92 ); 93} 94 95#define FL_SENT_COMMAND (1 << 0) 96#define FL_SENT_STOP (1 << 1) 97 98#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ 99 | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ 100 | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) 101 102#define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg)) 103#define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg)) 104 105#define MCI_BLKSIZE 512 106#define MCI_MAXBLKSIZE 4095 107#define MCI_BLKATONCE 256 108#define MCI_BUFSIZE (MCI_BLKSIZE * MCI_BLKATONCE) 109 110/* 111 * Low level type for this driver 112 */ 113struct at91mci_host 114{ 115 struct mmc_host *mmc; 116 struct mmc_command *cmd; 117 struct mmc_request *request; 118 119 void __iomem *baseaddr; 120 int irq; 121 122 struct at91_mmc_data *board; 123 int present; 124 125 struct clk *mci_clk; 126 127 /* 128 * Flag indicating when the command has been sent. This is used to 129 * work out whether or not to send the stop 130 */ 131 unsigned int flags; 132 /* flag for current bus settings */ 133 u32 bus_mode; 134 135 /* DMA buffer used for transmitting */ 136 unsigned int* buffer; 137 dma_addr_t physical_address; 138 unsigned int total_length; 139 140 /* Latest in the scatterlist that has been enabled for transfer, but not freed */ 141 int in_use_index; 142 143 /* Latest in the scatterlist that has been enabled for transfer */ 144 int transfer_index; 145 146 /* Timer for timeouts */ 147 struct timer_list timer; 148}; 149 150/* 151 * Reset the controller and restore most of the state 152 */ 153static void at91_reset_host(struct at91mci_host *host) 154{ 155 unsigned long flags; 156 u32 mr; 157 u32 sdcr; 158 u32 dtor; 159 u32 imr; 160 161 local_irq_save(flags); 162 imr = at91_mci_read(host, AT91_MCI_IMR); 163 164 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); 165 166 /* save current state */ 167 mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; 168 sdcr = at91_mci_read(host, AT91_MCI_SDCR); 169 dtor = at91_mci_read(host, AT91_MCI_DTOR); 170 171 /* reset the controller */ 172 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); 173 174 /* restore state */ 175 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); 176 at91_mci_write(host, AT91_MCI_MR, mr); 177 at91_mci_write(host, AT91_MCI_SDCR, sdcr); 178 at91_mci_write(host, AT91_MCI_DTOR, dtor); 179 at91_mci_write(host, AT91_MCI_IER, imr); 180 181 /* make sure sdio interrupts will fire */ 182 at91_mci_read(host, AT91_MCI_SR); 183 184 local_irq_restore(flags); 185} 186 187static void at91_timeout_timer(unsigned long data) 188{ 189 struct at91mci_host *host; 190 191 host = (struct at91mci_host *)data; 192 193 if (host->request) { 194 dev_err(host->mmc->parent, "Timeout waiting end of packet\n"); 195 196 if (host->cmd && host->cmd->data) { 197 host->cmd->data->error = -ETIMEDOUT; 198 } else { 199 if (host->cmd) 200 host->cmd->error = -ETIMEDOUT; 201 else 202 host->request->cmd->error = -ETIMEDOUT; 203 } 204 205 at91_reset_host(host); 206 mmc_request_done(host->mmc, host->request); 207 } 208} 209 210/* 211 * Copy from sg to a dma block - used for transfers 212 */ 213static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data) 214{ 215 unsigned int len, i, size; 216 unsigned *dmabuf = host->buffer; 217 218 size = data->blksz * data->blocks; 219 len = data->sg_len; 220 221 /* MCI1 rev2xx Data Write Operation and number of bytes erratum */ 222 if (at91mci_is_mci1rev2xx()) 223 if (host->total_length == 12) 224 memset(dmabuf, 0, 12); 225 226 /* 227 * Just loop through all entries. Size might not 228 * be the entire list though so make sure that 229 * we do not transfer too much. 230 */ 231 for (i = 0; i < len; i++) { 232 struct scatterlist *sg; 233 int amount; 234 unsigned int *sgbuffer; 235 236 sg = &data->sg[i]; 237 238 sgbuffer = kmap_atomic(sg_page(sg)) + sg->offset; 239 amount = min(size, sg->length); 240 size -= amount; 241 242 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ 243 int index; 244 245 for (index = 0; index < (amount / 4); index++) 246 *dmabuf++ = swab32(sgbuffer[index]); 247 } else { 248 char *tmpv = (char *)dmabuf; 249 memcpy(tmpv, sgbuffer, amount); 250 tmpv += amount; 251 dmabuf = (unsigned *)tmpv; 252 } 253 254 kunmap_atomic(sgbuffer); 255 256 if (size == 0) 257 break; 258 } 259 260 /* 261 * Check that we didn't get a request to transfer 262 * more data than can fit into the SG list. 263 */ 264 BUG_ON(size != 0); 265} 266 267/* 268 * Handle after a dma read 269 */ 270static void at91_mci_post_dma_read(struct at91mci_host *host) 271{ 272 struct mmc_command *cmd; 273 struct mmc_data *data; 274 unsigned int len, i, size; 275 unsigned *dmabuf = host->buffer; 276 277 pr_debug("post dma read\n"); 278 279 cmd = host->cmd; 280 if (!cmd) { 281 pr_debug("no command\n"); 282 return; 283 } 284 285 data = cmd->data; 286 if (!data) { 287 pr_debug("no data\n"); 288 return; 289 } 290 291 size = data->blksz * data->blocks; 292 len = data->sg_len; 293 294 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX); 295 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF); 296 297 for (i = 0; i < len; i++) { 298 struct scatterlist *sg; 299 int amount; 300 unsigned int *sgbuffer; 301 302 sg = &data->sg[i]; 303 304 sgbuffer = kmap_atomic(sg_page(sg)) + sg->offset; 305 amount = min(size, sg->length); 306 size -= amount; 307 308 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ 309 int index; 310 for (index = 0; index < (amount / 4); index++) 311 sgbuffer[index] = swab32(*dmabuf++); 312 } else { 313 char *tmpv = (char *)dmabuf; 314 memcpy(sgbuffer, tmpv, amount); 315 tmpv += amount; 316 dmabuf = (unsigned *)tmpv; 317 } 318 319 flush_kernel_dcache_page(sg_page(sg)); 320 kunmap_atomic(sgbuffer); 321 data->bytes_xfered += amount; 322 if (size == 0) 323 break; 324 } 325 326 pr_debug("post dma read done\n"); 327} 328 329/* 330 * Handle transmitted data 331 */ 332static void at91_mci_handle_transmitted(struct at91mci_host *host) 333{ 334 struct mmc_command *cmd; 335 struct mmc_data *data; 336 337 pr_debug("Handling the transmit\n"); 338 339 /* Disable the transfer */ 340 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 341 342 /* Now wait for cmd ready */ 343 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE); 344 345 cmd = host->cmd; 346 if (!cmd) return; 347 348 data = cmd->data; 349 if (!data) return; 350 351 if (cmd->data->blocks > 1) { 352 pr_debug("multiple write : wait for BLKE...\n"); 353 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE); 354 } else 355 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); 356} 357 358/* 359 * Update bytes tranfered count during a write operation 360 */ 361static void at91_mci_update_bytes_xfered(struct at91mci_host *host) 362{ 363 struct mmc_data *data; 364 365 /* always deal with the effective request (and not the current cmd) */ 366 367 if (host->request->cmd && host->request->cmd->error != 0) 368 return; 369 370 if (host->request->data) { 371 data = host->request->data; 372 if (data->flags & MMC_DATA_WRITE) { 373 /* card is in IDLE mode now */ 374 pr_debug("-> bytes_xfered %d, total_length = %d\n", 375 data->bytes_xfered, host->total_length); 376 data->bytes_xfered = data->blksz * data->blocks; 377 } 378 } 379} 380 381 382/*Handle after command sent ready*/ 383static int at91_mci_handle_cmdrdy(struct at91mci_host *host) 384{ 385 if (!host->cmd) 386 return 1; 387 else if (!host->cmd->data) { 388 if (host->flags & FL_SENT_STOP) { 389 /*After multi block write, we must wait for NOTBUSY*/ 390 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); 391 } else return 1; 392 } else if (host->cmd->data->flags & MMC_DATA_WRITE) { 393 /*After sendding multi-block-write command, start DMA transfer*/ 394 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); 395 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 396 } 397 398 /* command not completed, have to wait */ 399 return 0; 400} 401 402 403/* 404 * Enable the controller 405 */ 406static void at91_mci_enable(struct at91mci_host *host) 407{ 408 unsigned int mr; 409 410 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); 411 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); 412 at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); 413 mr = AT91_MCI_PDCMODE | 0x34a; 414 415 if (at91mci_is_mci1rev2xx()) 416 mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; 417 418 at91_mci_write(host, AT91_MCI_MR, mr); 419 420 /* use Slot A or B (only one at same time) */ 421 at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b); 422} 423 424/* 425 * Disable the controller 426 */ 427static void at91_mci_disable(struct at91mci_host *host) 428{ 429 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); 430} 431 432/* 433 * Send a command 434 */ 435static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd) 436{ 437 unsigned int cmdr, mr; 438 unsigned int block_length; 439 struct mmc_data *data = cmd->data; 440 441 unsigned int blocks; 442 unsigned int ier = 0; 443 444 host->cmd = cmd; 445 446 /* Needed for leaving busy state before CMD1 */ 447 if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) { 448 pr_debug("Clearing timeout\n"); 449 at91_mci_write(host, AT91_MCI_ARGR, 0); 450 at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD); 451 while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) { 452 /* spin */ 453 pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR)); 454 } 455 } 456 457 cmdr = cmd->opcode; 458 459 if (mmc_resp_type(cmd) == MMC_RSP_NONE) 460 cmdr |= AT91_MCI_RSPTYP_NONE; 461 else { 462 /* if a response is expected then allow maximum response latancy */ 463 cmdr |= AT91_MCI_MAXLAT; 464 /* set 136 bit response for R2, 48 bit response otherwise */ 465 if (mmc_resp_type(cmd) == MMC_RSP_R2) 466 cmdr |= AT91_MCI_RSPTYP_136; 467 else 468 cmdr |= AT91_MCI_RSPTYP_48; 469 } 470 471 if (data) { 472 473 if (cpu_is_at91rm9200() || cpu_is_at91sam9261()) { 474 if (data->blksz & 0x3) { 475 pr_debug("Unsupported block size\n"); 476 cmd->error = -EINVAL; 477 mmc_request_done(host->mmc, host->request); 478 return; 479 } 480 if (data->flags & MMC_DATA_STREAM) { 481 pr_debug("Stream commands not supported\n"); 482 cmd->error = -EINVAL; 483 mmc_request_done(host->mmc, host->request); 484 return; 485 } 486 } 487 488 block_length = data->blksz; 489 blocks = data->blocks; 490 491 /* always set data start - also set direction flag for read */ 492 if (data->flags & MMC_DATA_READ) 493 cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); 494 else if (data->flags & MMC_DATA_WRITE) 495 cmdr |= AT91_MCI_TRCMD_START; 496 497 if (cmd->opcode == SD_IO_RW_EXTENDED) { 498 cmdr |= AT91_MCI_TRTYP_SDIO_BLOCK; 499 } else { 500 if (data->flags & MMC_DATA_STREAM) 501 cmdr |= AT91_MCI_TRTYP_STREAM; 502 if (data->blocks > 1) 503 cmdr |= AT91_MCI_TRTYP_MULTIPLE; 504 } 505 } 506 else { 507 block_length = 0; 508 blocks = 0; 509 } 510 511 if (host->flags & FL_SENT_STOP) 512 cmdr |= AT91_MCI_TRCMD_STOP; 513 514 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) 515 cmdr |= AT91_MCI_OPDCMD; 516 517 /* 518 * Set the arguments and send the command 519 */ 520 pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", 521 cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR)); 522 523 if (!data) { 524 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS); 525 at91_mci_write(host, ATMEL_PDC_RPR, 0); 526 at91_mci_write(host, ATMEL_PDC_RCR, 0); 527 at91_mci_write(host, ATMEL_PDC_RNPR, 0); 528 at91_mci_write(host, ATMEL_PDC_RNCR, 0); 529 at91_mci_write(host, ATMEL_PDC_TPR, 0); 530 at91_mci_write(host, ATMEL_PDC_TCR, 0); 531 at91_mci_write(host, ATMEL_PDC_TNPR, 0); 532 at91_mci_write(host, ATMEL_PDC_TNCR, 0); 533 ier = AT91_MCI_CMDRDY; 534 } else { 535 /* zero block length and PDC mode */ 536 mr = at91_mci_read(host, AT91_MCI_MR) & 0x5fff; 537 mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0; 538 mr |= (block_length << 16); 539 mr |= AT91_MCI_PDCMODE; 540 at91_mci_write(host, AT91_MCI_MR, mr); 541 542 if (!(cpu_is_at91rm9200() || cpu_is_at91sam9261())) 543 at91_mci_write(host, AT91_MCI_BLKR, 544 AT91_MCI_BLKR_BCNT(blocks) | 545 AT91_MCI_BLKR_BLKLEN(block_length)); 546 547 /* 548 * Disable the PDC controller 549 */ 550 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 551 552 if (cmdr & AT91_MCI_TRCMD_START) { 553 data->bytes_xfered = 0; 554 host->transfer_index = 0; 555 host->in_use_index = 0; 556 if (cmdr & AT91_MCI_TRDIR) { 557 /* 558 * Handle a read 559 */ 560 host->total_length = 0; 561 562 at91_mci_write(host, ATMEL_PDC_RPR, host->physical_address); 563 at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? 564 (blocks * block_length) : (blocks * block_length) / 4); 565 at91_mci_write(host, ATMEL_PDC_RNPR, 0); 566 at91_mci_write(host, ATMEL_PDC_RNCR, 0); 567 568 ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; 569 } 570 else { 571 /* 572 * Handle a write 573 */ 574 host->total_length = block_length * blocks; 575 /* 576 * MCI1 rev2xx Data Write Operation and 577 * number of bytes erratum 578 */ 579 if (at91mci_is_mci1rev2xx()) 580 if (host->total_length < 12) 581 host->total_length = 12; 582 583 at91_mci_sg_to_dma(host, data); 584 585 pr_debug("Transmitting %d bytes\n", host->total_length); 586 587 at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address); 588 at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ? 589 host->total_length : host->total_length / 4); 590 591 ier = AT91_MCI_CMDRDY; 592 } 593 } 594 } 595 596 /* 597 * Send the command and then enable the PDC - not the other way round as 598 * the data sheet says 599 */ 600 601 at91_mci_write(host, AT91_MCI_ARGR, cmd->arg); 602 at91_mci_write(host, AT91_MCI_CMDR, cmdr); 603 604 if (cmdr & AT91_MCI_TRCMD_START) { 605 if (cmdr & AT91_MCI_TRDIR) 606 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 607 } 608 609 /* Enable selected interrupts */ 610 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier); 611} 612 613/* 614 * Process the next step in the request 615 */ 616static void at91_mci_process_next(struct at91mci_host *host) 617{ 618 if (!(host->flags & FL_SENT_COMMAND)) { 619 host->flags |= FL_SENT_COMMAND; 620 at91_mci_send_command(host, host->request->cmd); 621 } 622 else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) { 623 host->flags |= FL_SENT_STOP; 624 at91_mci_send_command(host, host->request->stop); 625 } else { 626 del_timer(&host->timer); 627 /* the at91rm9200 mci controller hangs after some transfers, 628 * and the workaround is to reset it after each transfer. 629 */ 630 if (cpu_is_at91rm9200()) 631 at91_reset_host(host); 632 mmc_request_done(host->mmc, host->request); 633 } 634} 635 636/* 637 * Handle a command that has been completed 638 */ 639static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status) 640{ 641 struct mmc_command *cmd = host->cmd; 642 struct mmc_data *data = cmd->data; 643 644 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); 645 646 cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0)); 647 cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1)); 648 cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2)); 649 cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3)); 650 651 pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n", 652 status, at91_mci_read(host, AT91_MCI_SR), 653 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); 654 655 if (status & AT91_MCI_ERRORS) { 656 if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) { 657 cmd->error = 0; 658 } 659 else { 660 if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) { 661 if (data) { 662 if (status & AT91_MCI_DTOE) 663 data->error = -ETIMEDOUT; 664 else if (status & AT91_MCI_DCRCE) 665 data->error = -EILSEQ; 666 } 667 } else { 668 if (status & AT91_MCI_RTOE) 669 cmd->error = -ETIMEDOUT; 670 else if (status & AT91_MCI_RCRCE) 671 cmd->error = -EILSEQ; 672 else 673 cmd->error = -EIO; 674 } 675 676 pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n", 677 cmd->error, data ? data->error : 0, 678 cmd->opcode, cmd->retries); 679 } 680 } 681 else 682 cmd->error = 0; 683 684 at91_mci_process_next(host); 685} 686 687/* 688 * Handle an MMC request 689 */ 690static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) 691{ 692 struct at91mci_host *host = mmc_priv(mmc); 693 host->request = mrq; 694 host->flags = 0; 695 696 /* more than 1s timeout needed with slow SD cards */ 697 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000)); 698 699 at91_mci_process_next(host); 700} 701 702/* 703 * Set the IOS 704 */ 705static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 706{ 707 int clkdiv; 708 struct at91mci_host *host = mmc_priv(mmc); 709 unsigned long at91_master_clock = clk_get_rate(host->mci_clk); 710 711 host->bus_mode = ios->bus_mode; 712 713 if (ios->clock == 0) { 714 /* Disable the MCI controller */ 715 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS); 716 clkdiv = 0; 717 } 718 else { 719 /* Enable the MCI controller */ 720 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); 721 722 if ((at91_master_clock % (ios->clock * 2)) == 0) 723 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; 724 else 725 clkdiv = (at91_master_clock / ios->clock) / 2; 726 727 pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv, 728 at91_master_clock / (2 * (clkdiv + 1))); 729 } 730 if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) { 731 pr_debug("MMC: Setting controller bus width to 4\n"); 732 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS); 733 } 734 else { 735 pr_debug("MMC: Setting controller bus width to 1\n"); 736 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); 737 } 738 739 /* Set the clock divider */ 740 at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); 741 742 /* maybe switch power to the card */ 743 if (gpio_is_valid(host->board->vcc_pin)) { 744 switch (ios->power_mode) { 745 case MMC_POWER_OFF: 746 gpio_set_value(host->board->vcc_pin, 0); 747 break; 748 case MMC_POWER_UP: 749 gpio_set_value(host->board->vcc_pin, 1); 750 break; 751 case MMC_POWER_ON: 752 break; 753 default: 754 WARN_ON(1); 755 } 756 } 757} 758 759/* 760 * Handle an interrupt 761 */ 762static irqreturn_t at91_mci_irq(int irq, void *devid) 763{ 764 struct at91mci_host *host = devid; 765 int completed = 0; 766 unsigned int int_status, int_mask; 767 768 int_status = at91_mci_read(host, AT91_MCI_SR); 769 int_mask = at91_mci_read(host, AT91_MCI_IMR); 770 771 pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, 772 int_status & int_mask); 773 774 int_status = int_status & int_mask; 775 776 if (int_status & AT91_MCI_ERRORS) { 777 completed = 1; 778 779 if (int_status & AT91_MCI_UNRE) 780 pr_debug("MMC: Underrun error\n"); 781 if (int_status & AT91_MCI_OVRE) 782 pr_debug("MMC: Overrun error\n"); 783 if (int_status & AT91_MCI_DTOE) 784 pr_debug("MMC: Data timeout\n"); 785 if (int_status & AT91_MCI_DCRCE) 786 pr_debug("MMC: CRC error in data\n"); 787 if (int_status & AT91_MCI_RTOE) 788 pr_debug("MMC: Response timeout\n"); 789 if (int_status & AT91_MCI_RENDE) 790 pr_debug("MMC: Response end bit error\n"); 791 if (int_status & AT91_MCI_RCRCE) 792 pr_debug("MMC: Response CRC error\n"); 793 if (int_status & AT91_MCI_RDIRE) 794 pr_debug("MMC: Response direction error\n"); 795 if (int_status & AT91_MCI_RINDE) 796 pr_debug("MMC: Response index error\n"); 797 } else { 798 /* Only continue processing if no errors */ 799 800 if (int_status & AT91_MCI_TXBUFE) { 801 pr_debug("TX buffer empty\n"); 802 at91_mci_handle_transmitted(host); 803 } 804 805 if (int_status & AT91_MCI_ENDRX) { 806 pr_debug("ENDRX\n"); 807 at91_mci_post_dma_read(host); 808 } 809 810 if (int_status & AT91_MCI_RXBUFF) { 811 pr_debug("RX buffer full\n"); 812 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); 813 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); 814 completed = 1; 815 } 816 817 if (int_status & AT91_MCI_ENDTX) 818 pr_debug("Transmit has ended\n"); 819 820 if (int_status & AT91_MCI_NOTBUSY) { 821 pr_debug("Card is ready\n"); 822 at91_mci_update_bytes_xfered(host); 823 completed = 1; 824 } 825 826 if (int_status & AT91_MCI_DTIP) 827 pr_debug("Data transfer in progress\n"); 828 829 if (int_status & AT91_MCI_BLKE) { 830 pr_debug("Block transfer has ended\n"); 831 if (host->request->data && host->request->data->blocks > 1) { 832 /* multi block write : complete multi write 833 * command and send stop */ 834 completed = 1; 835 } else { 836 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); 837 } 838 } 839 840 if (int_status & AT91_MCI_SDIOIRQA) 841 mmc_signal_sdio_irq(host->mmc); 842 843 if (int_status & AT91_MCI_SDIOIRQB) 844 mmc_signal_sdio_irq(host->mmc); 845 846 if (int_status & AT91_MCI_TXRDY) 847 pr_debug("Ready to transmit\n"); 848 849 if (int_status & AT91_MCI_RXRDY) 850 pr_debug("Ready to receive\n"); 851 852 if (int_status & AT91_MCI_CMDRDY) { 853 pr_debug("Command ready\n"); 854 completed = at91_mci_handle_cmdrdy(host); 855 } 856 } 857 858 if (completed) { 859 pr_debug("Completed command\n"); 860 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); 861 at91_mci_completed_command(host, int_status); 862 } else 863 at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); 864 865 return IRQ_HANDLED; 866} 867 868static irqreturn_t at91_mmc_det_irq(int irq, void *_host) 869{ 870 struct at91mci_host *host = _host; 871 int present; 872 873 /* entering this ISR means that we have configured det_pin: 874 * we can use its value in board structure */ 875 present = !gpio_get_value(host->board->det_pin); 876 877 /* 878 * we expect this irq on both insert and remove, 879 * and use a short delay to debounce. 880 */ 881 if (present != host->present) { 882 host->present = present; 883 pr_debug("%s: card %s\n", mmc_hostname(host->mmc), 884 present ? "insert" : "remove"); 885 if (!present) { 886 pr_debug("****** Resetting SD-card bus width ******\n"); 887 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); 888 } 889 /* 0.5s needed because of early card detect switch firing */ 890 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 891 } 892 return IRQ_HANDLED; 893} 894 895static int at91_mci_get_ro(struct mmc_host *mmc) 896{ 897 struct at91mci_host *host = mmc_priv(mmc); 898 899 if (gpio_is_valid(host->board->wp_pin)) 900 return !!gpio_get_value(host->board->wp_pin); 901 /* 902 * Board doesn't support read only detection; let the mmc core 903 * decide what to do. 904 */ 905 return -ENOSYS; 906} 907 908static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable) 909{ 910 struct at91mci_host *host = mmc_priv(mmc); 911 912 pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc), 913 host->board->slot_b ? 'B':'A', enable ? "enable" : "disable"); 914 at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR, 915 host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA); 916 917} 918 919static const struct mmc_host_ops at91_mci_ops = { 920 .request = at91_mci_request, 921 .set_ios = at91_mci_set_ios, 922 .get_ro = at91_mci_get_ro, 923 .enable_sdio_irq = at91_mci_enable_sdio_irq, 924}; 925 926/* 927 * Probe for the device 928 */ 929static int __init at91_mci_probe(struct platform_device *pdev) 930{ 931 struct mmc_host *mmc; 932 struct at91mci_host *host; 933 struct resource *res; 934 int ret; 935 936 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 937 if (!res) 938 return -ENXIO; 939 940 if (!request_mem_region(res->start, resource_size(res), DRIVER_NAME)) 941 return -EBUSY; 942 943 mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); 944 if (!mmc) { 945 ret = -ENOMEM; 946 dev_dbg(&pdev->dev, "couldn't allocate mmc host\n"); 947 goto fail6; 948 } 949 950 mmc->ops = &at91_mci_ops; 951 mmc->f_min = 375000; 952 mmc->f_max = 25000000; 953 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 954 mmc->caps = 0; 955 956 mmc->max_blk_size = MCI_MAXBLKSIZE; 957 mmc->max_blk_count = MCI_BLKATONCE; 958 mmc->max_req_size = MCI_BUFSIZE; 959 mmc->max_segs = MCI_BLKATONCE; 960 mmc->max_seg_size = MCI_BUFSIZE; 961 962 host = mmc_priv(mmc); 963 host->mmc = mmc; 964 host->bus_mode = 0; 965 host->board = pdev->dev.platform_data; 966 if (host->board->wire4) { 967 if (at91mci_is_mci1rev2xx()) 968 mmc->caps |= MMC_CAP_4_BIT_DATA; 969 else 970 dev_warn(&pdev->dev, "4 wire bus mode not supported" 971 " - using 1 wire\n"); 972 } 973 974 host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE, 975 &host->physical_address, GFP_KERNEL); 976 if (!host->buffer) { 977 ret = -ENOMEM; 978 dev_err(&pdev->dev, "Can't allocate transmit buffer\n"); 979 goto fail5; 980 } 981 982 /* Add SDIO capability when available */ 983 if (at91mci_is_mci1rev2xx()) { 984 /* at91mci MCI1 rev2xx sdio interrupt erratum */ 985 if (host->board->wire4 || !host->board->slot_b) 986 mmc->caps |= MMC_CAP_SDIO_IRQ; 987 } 988 989 /* 990 * Reserve GPIOs ... board init code makes sure these pins are set 991 * up as GPIOs with the right direction (input, except for vcc) 992 */ 993 if (gpio_is_valid(host->board->det_pin)) { 994 ret = gpio_request(host->board->det_pin, "mmc_detect"); 995 if (ret < 0) { 996 dev_dbg(&pdev->dev, "couldn't claim card detect pin\n"); 997 goto fail4b; 998 } 999 } 1000 if (gpio_is_valid(host->board->wp_pin)) { 1001 ret = gpio_request(host->board->wp_pin, "mmc_wp"); 1002 if (ret < 0) { 1003 dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n"); 1004 goto fail4; 1005 } 1006 } 1007 if (gpio_is_valid(host->board->vcc_pin)) { 1008 ret = gpio_request(host->board->vcc_pin, "mmc_vcc"); 1009 if (ret < 0) { 1010 dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n"); 1011 goto fail3; 1012 } 1013 } 1014 1015 /* 1016 * Get Clock 1017 */ 1018 host->mci_clk = clk_get(&pdev->dev, "mci_clk"); 1019 if (IS_ERR(host->mci_clk)) { 1020 ret = -ENODEV; 1021 dev_dbg(&pdev->dev, "no mci_clk?\n"); 1022 goto fail2; 1023 } 1024 1025 /* 1026 * Map I/O region 1027 */ 1028 host->baseaddr = ioremap(res->start, resource_size(res)); 1029 if (!host->baseaddr) { 1030 ret = -ENOMEM; 1031 goto fail1; 1032 } 1033 1034 /* 1035 * Reset hardware 1036 */ 1037 clk_enable(host->mci_clk); /* Enable the peripheral clock */ 1038 at91_mci_disable(host); 1039 at91_mci_enable(host); 1040 1041 /* 1042 * Allocate the MCI interrupt 1043 */ 1044 host->irq = platform_get_irq(pdev, 0); 1045 ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED, 1046 mmc_hostname(mmc), host); 1047 if (ret) { 1048 dev_dbg(&pdev->dev, "request MCI interrupt failed\n"); 1049 goto fail0; 1050 } 1051 1052 setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host); 1053 1054 platform_set_drvdata(pdev, mmc); 1055 1056 /* 1057 * Add host to MMC layer 1058 */ 1059 if (gpio_is_valid(host->board->det_pin)) { 1060 host->present = !gpio_get_value(host->board->det_pin); 1061 } 1062 else 1063 host->present = -1; 1064 1065 mmc_add_host(mmc); 1066 1067 /* 1068 * monitor card insertion/removal if we can 1069 */ 1070 if (gpio_is_valid(host->board->det_pin)) { 1071 ret = request_irq(gpio_to_irq(host->board->det_pin), 1072 at91_mmc_det_irq, 0, mmc_hostname(mmc), host); 1073 if (ret) 1074 dev_warn(&pdev->dev, "request MMC detect irq failed\n"); 1075 else 1076 device_init_wakeup(&pdev->dev, 1); 1077 } 1078 1079 pr_debug("Added MCI driver\n"); 1080 1081 return 0; 1082 1083fail0: 1084 clk_disable(host->mci_clk); 1085 iounmap(host->baseaddr); 1086fail1: 1087 clk_put(host->mci_clk); 1088fail2: 1089 if (gpio_is_valid(host->board->vcc_pin)) 1090 gpio_free(host->board->vcc_pin); 1091fail3: 1092 if (gpio_is_valid(host->board->wp_pin)) 1093 gpio_free(host->board->wp_pin); 1094fail4: 1095 if (gpio_is_valid(host->board->det_pin)) 1096 gpio_free(host->board->det_pin); 1097fail4b: 1098 if (host->buffer) 1099 dma_free_coherent(&pdev->dev, MCI_BUFSIZE, 1100 host->buffer, host->physical_address); 1101fail5: 1102 mmc_free_host(mmc); 1103fail6: 1104 release_mem_region(res->start, resource_size(res)); 1105 dev_err(&pdev->dev, "probe failed, err %d\n", ret); 1106 return ret; 1107} 1108 1109/* 1110 * Remove a device 1111 */ 1112static int __exit at91_mci_remove(struct platform_device *pdev) 1113{ 1114 struct mmc_host *mmc = platform_get_drvdata(pdev); 1115 struct at91mci_host *host; 1116 struct resource *res; 1117 1118 if (!mmc) 1119 return -1; 1120 1121 host = mmc_priv(mmc); 1122 1123 if (host->buffer) 1124 dma_free_coherent(&pdev->dev, MCI_BUFSIZE, 1125 host->buffer, host->physical_address); 1126 1127 if (gpio_is_valid(host->board->det_pin)) { 1128 if (device_can_wakeup(&pdev->dev)) 1129 free_irq(gpio_to_irq(host->board->det_pin), host); 1130 device_init_wakeup(&pdev->dev, 0); 1131 gpio_free(host->board->det_pin); 1132 } 1133 1134 at91_mci_disable(host); 1135 del_timer_sync(&host->timer); 1136 mmc_remove_host(mmc); 1137 free_irq(host->irq, host); 1138 1139 clk_disable(host->mci_clk); /* Disable the peripheral clock */ 1140 clk_put(host->mci_clk); 1141 1142 if (gpio_is_valid(host->board->vcc_pin)) 1143 gpio_free(host->board->vcc_pin); 1144 if (gpio_is_valid(host->board->wp_pin)) 1145 gpio_free(host->board->wp_pin); 1146 1147 iounmap(host->baseaddr); 1148 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1149 release_mem_region(res->start, resource_size(res)); 1150 1151 mmc_free_host(mmc); 1152 platform_set_drvdata(pdev, NULL); 1153 pr_debug("MCI Removed\n"); 1154 1155 return 0; 1156} 1157 1158#ifdef CONFIG_PM 1159static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state) 1160{ 1161 struct mmc_host *mmc = platform_get_drvdata(pdev); 1162 struct at91mci_host *host = mmc_priv(mmc); 1163 int ret = 0; 1164 1165 if (gpio_is_valid(host->board->det_pin) && device_may_wakeup(&pdev->dev)) 1166 enable_irq_wake(host->board->det_pin); 1167 1168 if (mmc) 1169 ret = mmc_suspend_host(mmc); 1170 1171 return ret; 1172} 1173 1174static int at91_mci_resume(struct platform_device *pdev) 1175{ 1176 struct mmc_host *mmc = platform_get_drvdata(pdev); 1177 struct at91mci_host *host = mmc_priv(mmc); 1178 int ret = 0; 1179 1180 if (gpio_is_valid(host->board->det_pin) && device_may_wakeup(&pdev->dev)) 1181 disable_irq_wake(host->board->det_pin); 1182 1183 if (mmc) 1184 ret = mmc_resume_host(mmc); 1185 1186 return ret; 1187} 1188#else 1189#define at91_mci_suspend NULL 1190#define at91_mci_resume NULL 1191#endif 1192 1193static struct platform_driver at91_mci_driver = { 1194 .remove = __exit_p(at91_mci_remove), 1195 .suspend = at91_mci_suspend, 1196 .resume = at91_mci_resume, 1197 .driver = { 1198 .name = DRIVER_NAME, 1199 .owner = THIS_MODULE, 1200 }, 1201}; 1202 1203static int __init at91_mci_init(void) 1204{ 1205 return platform_driver_probe(&at91_mci_driver, at91_mci_probe); 1206} 1207 1208static void __exit at91_mci_exit(void) 1209{ 1210 platform_driver_unregister(&at91_mci_driver); 1211} 1212 1213module_init(at91_mci_init); 1214module_exit(at91_mci_exit); 1215 1216MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver"); 1217MODULE_AUTHOR("Nick Randell"); 1218MODULE_LICENSE("GPL"); 1219MODULE_ALIAS("platform:at91_mci"); 1220