1/* 2 * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver 3 * 4 * Copyright (C) 2007 Google Inc, 5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 6 * Copyright (C) 2009, Code Aurora Forum. All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Based on mmci.c 13 * 14 * Author: San Mehat (san@android.com) 15 * 16 */ 17 18#include <linux/module.h> 19#include <linux/moduleparam.h> 20#include <linux/init.h> 21#include <linux/ioport.h> 22#include <linux/device.h> 23#include <linux/interrupt.h> 24#include <linux/delay.h> 25#include <linux/err.h> 26#include <linux/highmem.h> 27#include <linux/log2.h> 28#include <linux/mmc/host.h> 29#include <linux/mmc/card.h> 30#include <linux/mmc/sdio.h> 31#include <linux/clk.h> 32#include <linux/scatterlist.h> 33#include <linux/platform_device.h> 34#include <linux/dma-mapping.h> 35#include <linux/debugfs.h> 36#include <linux/io.h> 37#include <linux/memory.h> 38#include <linux/gfp.h> 39#include <linux/gpio.h> 40 41#include <asm/cacheflush.h> 42#include <asm/div64.h> 43#include <asm/sizes.h> 44 45#include <mach/mmc.h> 46#include <mach/msm_iomap.h> 47#include <mach/dma.h> 48#include <mach/clk.h> 49 50#include "msm_sdcc.h" 51 52#define DRIVER_NAME "msm-sdcc" 53 54#define BUSCLK_PWRSAVE 1 55#define BUSCLK_TIMEOUT (HZ) 56static unsigned int msmsdcc_fmin = 144000; 57static unsigned int msmsdcc_fmax = 50000000; 58static unsigned int msmsdcc_4bit = 1; 59static unsigned int msmsdcc_pwrsave = 1; 60static unsigned int msmsdcc_piopoll = 1; 61static unsigned int msmsdcc_sdioirq; 62 63#define PIO_SPINMAX 30 64#define CMD_SPINMAX 20 65 66 67static inline void 68msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr) 69{ 70 WARN_ON(!host->clks_on); 71 72 BUG_ON(host->curr.mrq); 73 74 if (deferr) { 75 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT); 76 } else { 77 del_timer_sync(&host->busclk_timer); 78 /* Need to check clks_on again in case the busclk 79 * timer fired 80 */ 81 if (host->clks_on) { 82 clk_disable(host->clk); 83 clk_disable(host->pclk); 84 host->clks_on = 0; 85 } 86 } 87} 88 89static inline int 90msmsdcc_enable_clocks(struct msmsdcc_host *host) 91{ 92 int rc; 93 94 del_timer_sync(&host->busclk_timer); 95 96 if (!host->clks_on) { 97 rc = clk_enable(host->pclk); 98 if (rc) 99 return rc; 100 rc = clk_enable(host->clk); 101 if (rc) { 102 clk_disable(host->pclk); 103 return rc; 104 } 105 udelay(1 + ((3 * USEC_PER_SEC) / 106 (host->clk_rate ? host->clk_rate : msmsdcc_fmin))); 107 host->clks_on = 1; 108 } 109 return 0; 110} 111 112static inline unsigned int 113msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg) 114{ 115 return readl(host->base + reg); 116} 117 118static inline void 119msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg) 120{ 121 writel(data, host->base + reg); 122 /* 3 clk delay required! */ 123 udelay(1 + ((3 * USEC_PER_SEC) / 124 (host->clk_rate ? host->clk_rate : msmsdcc_fmin))); 125} 126 127static void 128msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, 129 u32 c); 130 131static void msmsdcc_reset_and_restore(struct msmsdcc_host *host) 132{ 133 u32 mci_clk = 0; 134 u32 mci_mask0 = 0; 135 int ret = 0; 136 137 /* Save the controller state */ 138 mci_clk = readl(host->base + MMCICLOCK); 139 mci_mask0 = readl(host->base + MMCIMASK0); 140 141 /* Reset the controller */ 142 ret = clk_reset(host->clk, CLK_RESET_ASSERT); 143 if (ret) 144 pr_err("%s: Clock assert failed at %u Hz with err %d\n", 145 mmc_hostname(host->mmc), host->clk_rate, ret); 146 147 ret = clk_reset(host->clk, CLK_RESET_DEASSERT); 148 if (ret) 149 pr_err("%s: Clock deassert failed at %u Hz with err %d\n", 150 mmc_hostname(host->mmc), host->clk_rate, ret); 151 152 pr_info("%s: Controller has been re-initialiazed\n", 153 mmc_hostname(host->mmc)); 154 155 /* Restore the contoller state */ 156 writel(host->pwr, host->base + MMCIPOWER); 157 writel(mci_clk, host->base + MMCICLOCK); 158 writel(mci_mask0, host->base + MMCIMASK0); 159 ret = clk_set_rate(host->clk, host->clk_rate); 160 if (ret) 161 pr_err("%s: Failed to set clk rate %u Hz (%d)\n", 162 mmc_hostname(host->mmc), host->clk_rate, ret); 163} 164 165static void 166msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq) 167{ 168 BUG_ON(host->curr.data); 169 170 host->curr.mrq = NULL; 171 host->curr.cmd = NULL; 172 173 if (mrq->data) 174 mrq->data->bytes_xfered = host->curr.data_xfered; 175 if (mrq->cmd->error == -ETIMEDOUT) 176 mdelay(5); 177 178#if BUSCLK_PWRSAVE 179 msmsdcc_disable_clocks(host, 1); 180#endif 181 /* 182 * Need to drop the host lock here; mmc_request_done may call 183 * back into the driver... 184 */ 185 spin_unlock(&host->lock); 186 mmc_request_done(host->mmc, mrq); 187 spin_lock(&host->lock); 188} 189 190static void 191msmsdcc_stop_data(struct msmsdcc_host *host) 192{ 193 host->curr.data = NULL; 194 host->curr.got_dataend = 0; 195} 196 197uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host) 198{ 199 return host->memres->start + MMCIFIFO; 200} 201 202static inline void 203msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) { 204 msmsdcc_writel(host, arg, MMCIARGUMENT); 205 msmsdcc_writel(host, c, MMCICOMMAND); 206} 207 208static void 209msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd) 210{ 211 struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data; 212 213 msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER); 214 msmsdcc_writel(host, (unsigned int)host->curr.xfer_size, 215 MMCIDATALENGTH); 216 msmsdcc_writel(host, (msmsdcc_readl(host, MMCIMASK0) & 217 (~MCI_IRQ_PIO)) | host->cmd_pio_irqmask, MMCIMASK0); 218 msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL); 219 220 if (host->cmd_cmd) { 221 msmsdcc_start_command_exec(host, 222 (u32) host->cmd_cmd->arg, 223 (u32) host->cmd_c); 224 } 225 host->dma.active = 1; 226} 227 228static void 229msmsdcc_dma_complete_tlet(unsigned long data) 230{ 231 struct msmsdcc_host *host = (struct msmsdcc_host *)data; 232 unsigned long flags; 233 struct mmc_request *mrq; 234 struct msm_dmov_errdata err; 235 236 spin_lock_irqsave(&host->lock, flags); 237 host->dma.active = 0; 238 239 err = host->dma.err; 240 mrq = host->curr.mrq; 241 BUG_ON(!mrq); 242 WARN_ON(!mrq->data); 243 244 if (!(host->dma.result & DMOV_RSLT_VALID)) { 245 pr_err("msmsdcc: Invalid DataMover result\n"); 246 goto out; 247 } 248 249 if (host->dma.result & DMOV_RSLT_DONE) { 250 host->curr.data_xfered = host->curr.xfer_size; 251 } else { 252 /* Error or flush */ 253 if (host->dma.result & DMOV_RSLT_ERROR) 254 pr_err("%s: DMA error (0x%.8x)\n", 255 mmc_hostname(host->mmc), host->dma.result); 256 if (host->dma.result & DMOV_RSLT_FLUSH) 257 pr_err("%s: DMA channel flushed (0x%.8x)\n", 258 mmc_hostname(host->mmc), host->dma.result); 259 260 pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n", 261 err.flush[0], err.flush[1], err.flush[2], 262 err.flush[3], err.flush[4], err.flush[5]); 263 264 msmsdcc_reset_and_restore(host); 265 if (!mrq->data->error) 266 mrq->data->error = -EIO; 267 } 268 dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents, 269 host->dma.dir); 270 271 host->dma.sg = NULL; 272 host->dma.busy = 0; 273 274 if (host->curr.got_dataend || mrq->data->error) { 275 276 /* 277 * If we've already gotten our DATAEND / DATABLKEND 278 * for this request, then complete it through here. 279 */ 280 msmsdcc_stop_data(host); 281 282 if (!mrq->data->error) 283 host->curr.data_xfered = host->curr.xfer_size; 284 if (!mrq->data->stop || mrq->cmd->error) { 285 host->curr.mrq = NULL; 286 host->curr.cmd = NULL; 287 mrq->data->bytes_xfered = host->curr.data_xfered; 288 289 spin_unlock_irqrestore(&host->lock, flags); 290#if BUSCLK_PWRSAVE 291 msmsdcc_disable_clocks(host, 1); 292#endif 293 mmc_request_done(host->mmc, mrq); 294 return; 295 } else 296 msmsdcc_start_command(host, mrq->data->stop, 0); 297 } 298 299out: 300 spin_unlock_irqrestore(&host->lock, flags); 301 return; 302} 303 304static void 305msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd, 306 unsigned int result, 307 struct msm_dmov_errdata *err) 308{ 309 struct msmsdcc_dma_data *dma_data = 310 container_of(cmd, struct msmsdcc_dma_data, hdr); 311 struct msmsdcc_host *host = dma_data->host; 312 313 dma_data->result = result; 314 if (err) 315 memcpy(&dma_data->err, err, sizeof(struct msm_dmov_errdata)); 316 317 tasklet_schedule(&host->dma_tlet); 318} 319 320static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data) 321{ 322 if (host->dma.channel == -1) 323 return -ENOENT; 324 325 if ((data->blksz * data->blocks) < MCI_FIFOSIZE) 326 return -EINVAL; 327 if ((data->blksz * data->blocks) % MCI_FIFOSIZE) 328 return -EINVAL; 329 return 0; 330} 331 332static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data) 333{ 334 struct msmsdcc_nc_dmadata *nc; 335 dmov_box *box; 336 uint32_t rows; 337 uint32_t crci; 338 unsigned int n; 339 int i, rc; 340 struct scatterlist *sg = data->sg; 341 342 rc = validate_dma(host, data); 343 if (rc) 344 return rc; 345 346 host->dma.sg = data->sg; 347 host->dma.num_ents = data->sg_len; 348 349 BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */ 350 351 nc = host->dma.nc; 352 353 switch (host->pdev_id) { 354 case 1: 355 crci = MSMSDCC_CRCI_SDC1; 356 break; 357 case 2: 358 crci = MSMSDCC_CRCI_SDC2; 359 break; 360 case 3: 361 crci = MSMSDCC_CRCI_SDC3; 362 break; 363 case 4: 364 crci = MSMSDCC_CRCI_SDC4; 365 break; 366 default: 367 host->dma.sg = NULL; 368 host->dma.num_ents = 0; 369 return -ENOENT; 370 } 371 372 if (data->flags & MMC_DATA_READ) 373 host->dma.dir = DMA_FROM_DEVICE; 374 else 375 host->dma.dir = DMA_TO_DEVICE; 376 377 host->curr.user_pages = 0; 378 379 box = &nc->cmd[0]; 380 381 /* location of command block must be 64 bit aligned */ 382 BUG_ON(host->dma.cmd_busaddr & 0x07); 383 384 nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP; 385 host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST | 386 DMOV_CMD_ADDR(host->dma.cmdptr_busaddr); 387 host->dma.hdr.complete_func = msmsdcc_dma_complete_func; 388 389 n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg, 390 host->dma.num_ents, host->dma.dir); 391 if (n == 0) { 392 pr_err("%s: Unable to map in all sg elements\n", 393 mmc_hostname(host->mmc)); 394 host->dma.sg = NULL; 395 host->dma.num_ents = 0; 396 return -ENOMEM; 397 } 398 399 for_each_sg(host->dma.sg, sg, n, i) { 400 401 box->cmd = CMD_MODE_BOX; 402 403 if (i == n - 1) 404 box->cmd |= CMD_LC; 405 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ? 406 (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 : 407 (sg_dma_len(sg) / MCI_FIFOSIZE) ; 408 409 if (data->flags & MMC_DATA_READ) { 410 box->src_row_addr = msmsdcc_fifo_addr(host); 411 box->dst_row_addr = sg_dma_address(sg); 412 413 box->src_dst_len = (MCI_FIFOSIZE << 16) | 414 (MCI_FIFOSIZE); 415 box->row_offset = MCI_FIFOSIZE; 416 417 box->num_rows = rows * ((1 << 16) + 1); 418 box->cmd |= CMD_SRC_CRCI(crci); 419 } else { 420 box->src_row_addr = sg_dma_address(sg); 421 box->dst_row_addr = msmsdcc_fifo_addr(host); 422 423 box->src_dst_len = (MCI_FIFOSIZE << 16) | 424 (MCI_FIFOSIZE); 425 box->row_offset = (MCI_FIFOSIZE << 16); 426 427 box->num_rows = rows * ((1 << 16) + 1); 428 box->cmd |= CMD_DST_CRCI(crci); 429 } 430 box++; 431 } 432 433 return 0; 434} 435 436static int 437snoop_cccr_abort(struct mmc_command *cmd) 438{ 439 if ((cmd->opcode == 52) && 440 (cmd->arg & 0x80000000) && 441 (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT)) 442 return 1; 443 return 0; 444} 445 446static void 447msmsdcc_start_command_deferred(struct msmsdcc_host *host, 448 struct mmc_command *cmd, u32 *c) 449{ 450 *c |= (cmd->opcode | MCI_CPSM_ENABLE); 451 452 if (cmd->flags & MMC_RSP_PRESENT) { 453 if (cmd->flags & MMC_RSP_136) 454 *c |= MCI_CPSM_LONGRSP; 455 *c |= MCI_CPSM_RESPONSE; 456 } 457 458 if (/*interrupt*/0) 459 *c |= MCI_CPSM_INTERRUPT; 460 461 if ((((cmd->opcode == 17) || (cmd->opcode == 18)) || 462 ((cmd->opcode == 24) || (cmd->opcode == 25))) || 463 (cmd->opcode == 53)) 464 *c |= MCI_CSPM_DATCMD; 465 466 if (host->prog_scan && (cmd->opcode == 12)) { 467 *c |= MCI_CPSM_PROGENA; 468 host->prog_enable = true; 469 } 470 471 if (cmd == cmd->mrq->stop) 472 *c |= MCI_CSPM_MCIABORT; 473 474 if (snoop_cccr_abort(cmd)) 475 *c |= MCI_CSPM_MCIABORT; 476 477 if (host->curr.cmd != NULL) { 478 pr_err("%s: Overlapping command requests\n", 479 mmc_hostname(host->mmc)); 480 } 481 host->curr.cmd = cmd; 482} 483 484static void 485msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data, 486 struct mmc_command *cmd, u32 c) 487{ 488 unsigned int datactrl, timeout; 489 unsigned long long clks; 490 unsigned int pio_irqmask = 0; 491 492 host->curr.data = data; 493 host->curr.xfer_size = data->blksz * data->blocks; 494 host->curr.xfer_remain = host->curr.xfer_size; 495 host->curr.data_xfered = 0; 496 host->curr.got_dataend = 0; 497 498 memset(&host->pio, 0, sizeof(host->pio)); 499 500 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 501 502 if (!msmsdcc_config_dma(host, data)) 503 datactrl |= MCI_DPSM_DMAENABLE; 504 else { 505 host->pio.sg = data->sg; 506 host->pio.sg_len = data->sg_len; 507 host->pio.sg_off = 0; 508 509 if (data->flags & MMC_DATA_READ) { 510 pio_irqmask = MCI_RXFIFOHALFFULLMASK; 511 if (host->curr.xfer_remain < MCI_FIFOSIZE) 512 pio_irqmask |= MCI_RXDATAAVLBLMASK; 513 } else 514 pio_irqmask = MCI_TXFIFOHALFEMPTYMASK; 515 } 516 517 if (data->flags & MMC_DATA_READ) 518 datactrl |= MCI_DPSM_DIRECTION; 519 520 clks = (unsigned long long)data->timeout_ns * host->clk_rate; 521 do_div(clks, NSEC_PER_SEC); 522 timeout = data->timeout_clks + (unsigned int)clks*2 ; 523 524 if (datactrl & MCI_DPSM_DMAENABLE) { 525 /* Save parameters for the exec function */ 526 host->cmd_timeout = timeout; 527 host->cmd_pio_irqmask = pio_irqmask; 528 host->cmd_datactrl = datactrl; 529 host->cmd_cmd = cmd; 530 531 host->dma.hdr.execute_func = msmsdcc_dma_exec_func; 532 host->dma.hdr.data = (void *)host; 533 host->dma.busy = 1; 534 535 if (cmd) { 536 msmsdcc_start_command_deferred(host, cmd, &c); 537 host->cmd_c = c; 538 } 539 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr); 540 if (data->flags & MMC_DATA_WRITE) 541 host->prog_scan = true; 542 } else { 543 msmsdcc_writel(host, timeout, MMCIDATATIMER); 544 545 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH); 546 547 msmsdcc_writel(host, (msmsdcc_readl(host, MMCIMASK0) & 548 (~MCI_IRQ_PIO)) | pio_irqmask, MMCIMASK0); 549 550 msmsdcc_writel(host, datactrl, MMCIDATACTRL); 551 552 if (cmd) { 553 /* Daisy-chain the command if requested */ 554 msmsdcc_start_command(host, cmd, c); 555 } 556 } 557} 558 559static void 560msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c) 561{ 562 if (cmd == cmd->mrq->stop) 563 c |= MCI_CSPM_MCIABORT; 564 565 host->stats.cmds++; 566 567 msmsdcc_start_command_deferred(host, cmd, &c); 568 msmsdcc_start_command_exec(host, cmd->arg, c); 569} 570 571static void 572msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data, 573 unsigned int status) 574{ 575 if (status & MCI_DATACRCFAIL) { 576 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc)); 577 pr_err("%s: opcode 0x%.8x\n", __func__, 578 data->mrq->cmd->opcode); 579 pr_err("%s: blksz %d, blocks %d\n", __func__, 580 data->blksz, data->blocks); 581 data->error = -EILSEQ; 582 } else if (status & MCI_DATATIMEOUT) { 583 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc)); 584 data->error = -ETIMEDOUT; 585 } else if (status & MCI_RXOVERRUN) { 586 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc)); 587 data->error = -EIO; 588 } else if (status & MCI_TXUNDERRUN) { 589 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc)); 590 data->error = -EIO; 591 } else { 592 pr_err("%s: Unknown error (0x%.8x)\n", 593 mmc_hostname(host->mmc), status); 594 data->error = -EIO; 595 } 596} 597 598 599static int 600msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain) 601{ 602 uint32_t *ptr = (uint32_t *) buffer; 603 int count = 0; 604 605 if (remain % 4) 606 remain = ((remain >> 2) + 1) << 2; 607 608 while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) { 609 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE)); 610 ptr++; 611 count += sizeof(uint32_t); 612 613 remain -= sizeof(uint32_t); 614 if (remain == 0) 615 break; 616 } 617 return count; 618} 619 620static int 621msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer, 622 unsigned int remain, u32 status) 623{ 624 void __iomem *base = host->base; 625 char *ptr = buffer; 626 627 do { 628 unsigned int count, maxcnt, sz; 629 630 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : 631 MCI_FIFOHALFSIZE; 632 count = min(remain, maxcnt); 633 634 sz = count % 4 ? (count >> 2) + 1 : (count >> 2); 635 writesl(base + MMCIFIFO, ptr, sz); 636 ptr += count; 637 remain -= count; 638 639 if (remain == 0) 640 break; 641 642 status = msmsdcc_readl(host, MMCISTATUS); 643 } while (status & MCI_TXFIFOHALFEMPTY); 644 645 return ptr - buffer; 646} 647 648static int 649msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin) 650{ 651 while (maxspin) { 652 if ((msmsdcc_readl(host, MMCISTATUS) & mask)) 653 return 0; 654 udelay(1); 655 --maxspin; 656 } 657 return -ETIMEDOUT; 658} 659 660static irqreturn_t 661msmsdcc_pio_irq(int irq, void *dev_id) 662{ 663 struct msmsdcc_host *host = dev_id; 664 uint32_t status; 665 u32 mci_mask0; 666 667 status = msmsdcc_readl(host, MMCISTATUS); 668 mci_mask0 = msmsdcc_readl(host, MMCIMASK0); 669 670 if (((mci_mask0 & status) & MCI_IRQ_PIO) == 0) 671 return IRQ_NONE; 672 673 do { 674 unsigned long flags; 675 unsigned int remain, len; 676 char *buffer; 677 678 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) { 679 if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll) 680 break; 681 682 if (msmsdcc_spin_on_status(host, 683 (MCI_TXFIFOHALFEMPTY | 684 MCI_RXDATAAVLBL), 685 PIO_SPINMAX)) { 686 break; 687 } 688 } 689 690 /* Map the current scatter buffer */ 691 local_irq_save(flags); 692 buffer = kmap_atomic(sg_page(host->pio.sg)) 693 + host->pio.sg->offset; 694 buffer += host->pio.sg_off; 695 remain = host->pio.sg->length - host->pio.sg_off; 696 len = 0; 697 if (status & MCI_RXACTIVE) 698 len = msmsdcc_pio_read(host, buffer, remain); 699 if (status & MCI_TXACTIVE) 700 len = msmsdcc_pio_write(host, buffer, remain, status); 701 702 /* Unmap the buffer */ 703 kunmap_atomic(buffer); 704 local_irq_restore(flags); 705 706 host->pio.sg_off += len; 707 host->curr.xfer_remain -= len; 708 host->curr.data_xfered += len; 709 remain -= len; 710 711 if (remain == 0) { 712 /* This sg page is full - do some housekeeping */ 713 if (status & MCI_RXACTIVE && host->curr.user_pages) 714 flush_dcache_page(sg_page(host->pio.sg)); 715 716 if (!--host->pio.sg_len) { 717 memset(&host->pio, 0, sizeof(host->pio)); 718 break; 719 } 720 721 /* Advance to next sg */ 722 host->pio.sg++; 723 host->pio.sg_off = 0; 724 } 725 726 status = msmsdcc_readl(host, MMCISTATUS); 727 } while (1); 728 729 if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE) 730 msmsdcc_writel(host, (mci_mask0 & (~MCI_IRQ_PIO)) | 731 MCI_RXDATAAVLBLMASK, MMCIMASK0); 732 733 if (!host->curr.xfer_remain) 734 msmsdcc_writel(host, (mci_mask0 & (~MCI_IRQ_PIO)) | 0, 735 MMCIMASK0); 736 737 return IRQ_HANDLED; 738} 739 740static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status) 741{ 742 struct mmc_command *cmd = host->curr.cmd; 743 744 host->curr.cmd = NULL; 745 cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0); 746 cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1); 747 cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2); 748 cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3); 749 750 if (status & MCI_CMDTIMEOUT) { 751 cmd->error = -ETIMEDOUT; 752 } else if (status & MCI_CMDCRCFAIL && 753 cmd->flags & MMC_RSP_CRC) { 754 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc)); 755 cmd->error = -EILSEQ; 756 } 757 758 if (!cmd->data || cmd->error) { 759 if (host->curr.data && host->dma.sg) 760 msm_dmov_stop_cmd(host->dma.channel, 761 &host->dma.hdr, 0); 762 else if (host->curr.data) { /* Non DMA */ 763 msmsdcc_reset_and_restore(host); 764 msmsdcc_stop_data(host); 765 msmsdcc_request_end(host, cmd->mrq); 766 } else { /* host->data == NULL */ 767 if (!cmd->error && host->prog_enable) { 768 if (status & MCI_PROGDONE) { 769 host->prog_scan = false; 770 host->prog_enable = false; 771 msmsdcc_request_end(host, cmd->mrq); 772 } else { 773 host->curr.cmd = cmd; 774 } 775 } else { 776 if (host->prog_enable) { 777 host->prog_scan = false; 778 host->prog_enable = false; 779 } 780 msmsdcc_request_end(host, cmd->mrq); 781 } 782 } 783 } else if (cmd->data) 784 if (!(cmd->data->flags & MMC_DATA_READ)) 785 msmsdcc_start_data(host, cmd->data, 786 NULL, 0); 787} 788 789static void 790msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status, 791 void __iomem *base) 792{ 793 struct mmc_data *data = host->curr.data; 794 795 if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL | 796 MCI_CMDTIMEOUT | MCI_PROGDONE) && host->curr.cmd) { 797 msmsdcc_do_cmdirq(host, status); 798 } 799 800 if (!data) 801 return; 802 803 /* Check for data errors */ 804 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT | 805 MCI_TXUNDERRUN | MCI_RXOVERRUN)) { 806 msmsdcc_data_err(host, data, status); 807 host->curr.data_xfered = 0; 808 if (host->dma.sg) 809 msm_dmov_stop_cmd(host->dma.channel, 810 &host->dma.hdr, 0); 811 else { 812 msmsdcc_reset_and_restore(host); 813 if (host->curr.data) 814 msmsdcc_stop_data(host); 815 if (!data->stop) 816 msmsdcc_request_end(host, data->mrq); 817 else 818 msmsdcc_start_command(host, data->stop, 0); 819 } 820 } 821 822 /* Check for data done */ 823 if (!host->curr.got_dataend && (status & MCI_DATAEND)) 824 host->curr.got_dataend = 1; 825 826 /* 827 * If DMA is still in progress, we complete via the completion handler 828 */ 829 if (host->curr.got_dataend && !host->dma.busy) { 830 /* 831 * There appears to be an issue in the controller where 832 * if you request a small block transfer (< fifo size), 833 * you may get your DATAEND/DATABLKEND irq without the 834 * PIO data irq. 835 * 836 * Check to see if there is still data to be read, 837 * and simulate a PIO irq. 838 */ 839 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL) 840 msmsdcc_pio_irq(1, host); 841 842 msmsdcc_stop_data(host); 843 if (!data->error) 844 host->curr.data_xfered = host->curr.xfer_size; 845 846 if (!data->stop) 847 msmsdcc_request_end(host, data->mrq); 848 else 849 msmsdcc_start_command(host, data->stop, 0); 850 } 851} 852 853static irqreturn_t 854msmsdcc_irq(int irq, void *dev_id) 855{ 856 struct msmsdcc_host *host = dev_id; 857 void __iomem *base = host->base; 858 u32 status; 859 int ret = 0; 860 int cardint = 0; 861 862 spin_lock(&host->lock); 863 864 do { 865 status = msmsdcc_readl(host, MMCISTATUS); 866 status &= msmsdcc_readl(host, MMCIMASK0); 867 if ((status & (~MCI_IRQ_PIO)) == 0) 868 break; 869 msmsdcc_writel(host, status, MMCICLEAR); 870 871 if (status & MCI_SDIOINTR) 872 status &= ~MCI_SDIOINTR; 873 874 if (!status) 875 break; 876 877 msmsdcc_handle_irq_data(host, status, base); 878 879 if (status & MCI_SDIOINTOPER) { 880 cardint = 1; 881 status &= ~MCI_SDIOINTOPER; 882 } 883 ret = 1; 884 } while (status); 885 886 spin_unlock(&host->lock); 887 888 /* 889 * We have to delay handling the card interrupt as it calls 890 * back into the driver. 891 */ 892 if (cardint) 893 mmc_signal_sdio_irq(host->mmc); 894 895 return IRQ_RETVAL(ret); 896} 897 898static void 899msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq) 900{ 901 struct msmsdcc_host *host = mmc_priv(mmc); 902 unsigned long flags; 903 904 WARN_ON(host->curr.mrq != NULL); 905 WARN_ON(host->pwr == 0); 906 907 spin_lock_irqsave(&host->lock, flags); 908 909 host->stats.reqs++; 910 911 if (host->eject) { 912 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) { 913 mrq->cmd->error = 0; 914 mrq->data->bytes_xfered = mrq->data->blksz * 915 mrq->data->blocks; 916 } else 917 mrq->cmd->error = -ENOMEDIUM; 918 919 spin_unlock_irqrestore(&host->lock, flags); 920 mmc_request_done(mmc, mrq); 921 return; 922 } 923 924 msmsdcc_enable_clocks(host); 925 926 host->curr.mrq = mrq; 927 928 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 929 /* Queue/read data, daisy-chain command when data starts */ 930 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0); 931 else 932 msmsdcc_start_command(host, mrq->cmd, 0); 933 934 if (host->cmdpoll && !msmsdcc_spin_on_status(host, 935 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT, 936 CMD_SPINMAX)) { 937 uint32_t status = msmsdcc_readl(host, MMCISTATUS); 938 msmsdcc_do_cmdirq(host, status); 939 msmsdcc_writel(host, 940 MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT, 941 MMCICLEAR); 942 host->stats.cmdpoll_hits++; 943 } else { 944 host->stats.cmdpoll_misses++; 945 } 946 spin_unlock_irqrestore(&host->lock, flags); 947} 948 949static void msmsdcc_setup_gpio(struct msmsdcc_host *host, bool enable) 950{ 951 struct msm_mmc_gpio_data *curr; 952 int i, rc = 0; 953 954 if (!host->plat->gpio_data || host->gpio_config_status == enable) 955 return; 956 957 curr = host->plat->gpio_data; 958 for (i = 0; i < curr->size; i++) { 959 if (enable) { 960 rc = gpio_request(curr->gpio[i].no, 961 curr->gpio[i].name); 962 if (rc) { 963 pr_err("%s: gpio_request(%d, %s) failed %d\n", 964 mmc_hostname(host->mmc), 965 curr->gpio[i].no, 966 curr->gpio[i].name, rc); 967 goto free_gpios; 968 } 969 } else { 970 gpio_free(curr->gpio[i].no); 971 } 972 } 973 host->gpio_config_status = enable; 974 return; 975 976free_gpios: 977 for (; i >= 0; i--) 978 gpio_free(curr->gpio[i].no); 979} 980 981static void 982msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 983{ 984 struct msmsdcc_host *host = mmc_priv(mmc); 985 u32 clk = 0, pwr = 0; 986 int rc; 987 unsigned long flags; 988 989 spin_lock_irqsave(&host->lock, flags); 990 991 msmsdcc_enable_clocks(host); 992 993 spin_unlock_irqrestore(&host->lock, flags); 994 995 if (ios->clock) { 996 if (ios->clock != host->clk_rate) { 997 rc = clk_set_rate(host->clk, ios->clock); 998 if (rc < 0) 999 pr_err("%s: Error setting clock rate (%d)\n", 1000 mmc_hostname(host->mmc), rc); 1001 else 1002 host->clk_rate = ios->clock; 1003 } 1004 clk |= MCI_CLK_ENABLE; 1005 } 1006 1007 if (ios->bus_width == MMC_BUS_WIDTH_4) 1008 clk |= (2 << 10); /* Set WIDEBUS */ 1009 1010 if (ios->clock > 400000 && msmsdcc_pwrsave) 1011 clk |= (1 << 9); /* PWRSAVE */ 1012 1013 clk |= (1 << 12); /* FLOW_ENA */ 1014 clk |= (1 << 15); /* feedback clock */ 1015 1016 if (host->plat->translate_vdd) 1017 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd); 1018 1019 switch (ios->power_mode) { 1020 case MMC_POWER_OFF: 1021 msmsdcc_setup_gpio(host, false); 1022 break; 1023 case MMC_POWER_UP: 1024 pwr |= MCI_PWR_UP; 1025 msmsdcc_setup_gpio(host, true); 1026 break; 1027 case MMC_POWER_ON: 1028 pwr |= MCI_PWR_ON; 1029 break; 1030 } 1031 1032 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1033 pwr |= MCI_OD; 1034 1035 msmsdcc_writel(host, clk, MMCICLOCK); 1036 1037 if (host->pwr != pwr) { 1038 host->pwr = pwr; 1039 msmsdcc_writel(host, pwr, MMCIPOWER); 1040 } 1041#if BUSCLK_PWRSAVE 1042 spin_lock_irqsave(&host->lock, flags); 1043 msmsdcc_disable_clocks(host, 1); 1044 spin_unlock_irqrestore(&host->lock, flags); 1045#endif 1046} 1047 1048static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable) 1049{ 1050 struct msmsdcc_host *host = mmc_priv(mmc); 1051 unsigned long flags; 1052 u32 status; 1053 1054 spin_lock_irqsave(&host->lock, flags); 1055 if (msmsdcc_sdioirq == 1) { 1056 status = msmsdcc_readl(host, MMCIMASK0); 1057 if (enable) 1058 status |= MCI_SDIOINTOPERMASK; 1059 else 1060 status &= ~MCI_SDIOINTOPERMASK; 1061 host->saved_irq0mask = status; 1062 msmsdcc_writel(host, status, MMCIMASK0); 1063 } 1064 spin_unlock_irqrestore(&host->lock, flags); 1065} 1066 1067static void msmsdcc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1068{ 1069 struct msmsdcc_host *host = mmc_priv(mmc); 1070 1071 if (host->plat->init_card) 1072 host->plat->init_card(card); 1073} 1074 1075static const struct mmc_host_ops msmsdcc_ops = { 1076 .request = msmsdcc_request, 1077 .set_ios = msmsdcc_set_ios, 1078 .enable_sdio_irq = msmsdcc_enable_sdio_irq, 1079 .init_card = msmsdcc_init_card, 1080}; 1081 1082static void 1083msmsdcc_check_status(unsigned long data) 1084{ 1085 struct msmsdcc_host *host = (struct msmsdcc_host *)data; 1086 unsigned int status; 1087 1088 if (!host->plat->status) { 1089 mmc_detect_change(host->mmc, 0); 1090 goto out; 1091 } 1092 1093 status = host->plat->status(mmc_dev(host->mmc)); 1094 host->eject = !status; 1095 if (status ^ host->oldstat) { 1096 pr_info("%s: Slot status change detected (%d -> %d)\n", 1097 mmc_hostname(host->mmc), host->oldstat, status); 1098 if (status) 1099 mmc_detect_change(host->mmc, (5 * HZ) / 2); 1100 else 1101 mmc_detect_change(host->mmc, 0); 1102 } 1103 1104 host->oldstat = status; 1105 1106out: 1107 if (host->timer.function) 1108 mod_timer(&host->timer, jiffies + HZ); 1109} 1110 1111static irqreturn_t 1112msmsdcc_platform_status_irq(int irq, void *dev_id) 1113{ 1114 struct msmsdcc_host *host = dev_id; 1115 1116 pr_debug("%s: %d\n", __func__, irq); 1117 msmsdcc_check_status((unsigned long) host); 1118 return IRQ_HANDLED; 1119} 1120 1121static void 1122msmsdcc_status_notify_cb(int card_present, void *dev_id) 1123{ 1124 struct msmsdcc_host *host = dev_id; 1125 1126 pr_debug("%s: card_present %d\n", mmc_hostname(host->mmc), 1127 card_present); 1128 msmsdcc_check_status((unsigned long) host); 1129} 1130 1131static void 1132msmsdcc_busclk_expired(unsigned long _data) 1133{ 1134 struct msmsdcc_host *host = (struct msmsdcc_host *) _data; 1135 1136 if (host->clks_on) 1137 msmsdcc_disable_clocks(host, 0); 1138} 1139 1140static int 1141msmsdcc_init_dma(struct msmsdcc_host *host) 1142{ 1143 memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data)); 1144 host->dma.host = host; 1145 host->dma.channel = -1; 1146 1147 if (!host->dmares) 1148 return -ENODEV; 1149 1150 host->dma.nc = dma_alloc_coherent(NULL, 1151 sizeof(struct msmsdcc_nc_dmadata), 1152 &host->dma.nc_busaddr, 1153 GFP_KERNEL); 1154 if (host->dma.nc == NULL) { 1155 pr_err("Unable to allocate DMA buffer\n"); 1156 return -ENOMEM; 1157 } 1158 memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata)); 1159 host->dma.cmd_busaddr = host->dma.nc_busaddr; 1160 host->dma.cmdptr_busaddr = host->dma.nc_busaddr + 1161 offsetof(struct msmsdcc_nc_dmadata, cmdptr); 1162 host->dma.channel = host->dmares->start; 1163 1164 return 0; 1165} 1166 1167static int 1168msmsdcc_probe(struct platform_device *pdev) 1169{ 1170 struct msm_mmc_platform_data *plat = pdev->dev.platform_data; 1171 struct msmsdcc_host *host; 1172 struct mmc_host *mmc; 1173 struct resource *cmd_irqres = NULL; 1174 struct resource *stat_irqres = NULL; 1175 struct resource *memres = NULL; 1176 struct resource *dmares = NULL; 1177 int ret; 1178 1179 /* must have platform data */ 1180 if (!plat) { 1181 pr_err("%s: Platform data not available\n", __func__); 1182 ret = -EINVAL; 1183 goto out; 1184 } 1185 1186 if (pdev->id < 1 || pdev->id > 4) 1187 return -EINVAL; 1188 1189 if (pdev->resource == NULL || pdev->num_resources < 2) { 1190 pr_err("%s: Invalid resource\n", __func__); 1191 return -ENXIO; 1192 } 1193 1194 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1195 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1196 cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 1197 "cmd_irq"); 1198 stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 1199 "status_irq"); 1200 1201 if (!cmd_irqres || !memres) { 1202 pr_err("%s: Invalid resource\n", __func__); 1203 return -ENXIO; 1204 } 1205 1206 /* 1207 * Setup our host structure 1208 */ 1209 1210 mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev); 1211 if (!mmc) { 1212 ret = -ENOMEM; 1213 goto out; 1214 } 1215 1216 host = mmc_priv(mmc); 1217 host->pdev_id = pdev->id; 1218 host->plat = plat; 1219 host->mmc = mmc; 1220 host->curr.cmd = NULL; 1221 init_timer(&host->busclk_timer); 1222 host->busclk_timer.data = (unsigned long) host; 1223 host->busclk_timer.function = msmsdcc_busclk_expired; 1224 1225 1226 host->cmdpoll = 1; 1227 1228 host->base = ioremap(memres->start, PAGE_SIZE); 1229 if (!host->base) { 1230 ret = -ENOMEM; 1231 goto host_free; 1232 } 1233 1234 host->cmd_irqres = cmd_irqres; 1235 host->memres = memres; 1236 host->dmares = dmares; 1237 spin_lock_init(&host->lock); 1238 1239 tasklet_init(&host->dma_tlet, msmsdcc_dma_complete_tlet, 1240 (unsigned long)host); 1241 1242 /* 1243 * Setup DMA 1244 */ 1245 if (host->dmares) { 1246 ret = msmsdcc_init_dma(host); 1247 if (ret) 1248 goto ioremap_free; 1249 } else { 1250 host->dma.channel = -1; 1251 } 1252 1253 /* Get our clocks */ 1254 host->pclk = clk_get(&pdev->dev, "sdc_pclk"); 1255 if (IS_ERR(host->pclk)) { 1256 ret = PTR_ERR(host->pclk); 1257 goto dma_free; 1258 } 1259 1260 host->clk = clk_get(&pdev->dev, "sdc_clk"); 1261 if (IS_ERR(host->clk)) { 1262 ret = PTR_ERR(host->clk); 1263 goto pclk_put; 1264 } 1265 1266 ret = clk_set_rate(host->clk, msmsdcc_fmin); 1267 if (ret) { 1268 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret); 1269 goto clk_put; 1270 } 1271 1272 /* Enable clocks */ 1273 ret = msmsdcc_enable_clocks(host); 1274 if (ret) 1275 goto clk_put; 1276 1277 host->pclk_rate = clk_get_rate(host->pclk); 1278 host->clk_rate = clk_get_rate(host->clk); 1279 1280 /* 1281 * Setup MMC host structure 1282 */ 1283 mmc->ops = &msmsdcc_ops; 1284 mmc->f_min = msmsdcc_fmin; 1285 mmc->f_max = msmsdcc_fmax; 1286 mmc->ocr_avail = plat->ocr_mask; 1287 1288 if (msmsdcc_4bit) 1289 mmc->caps |= MMC_CAP_4_BIT_DATA; 1290 if (msmsdcc_sdioirq) 1291 mmc->caps |= MMC_CAP_SDIO_IRQ; 1292 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED; 1293 1294 mmc->max_segs = NR_SG; 1295 mmc->max_blk_size = 4096; /* MCI_DATA_CTL BLOCKSIZE up to 4096 */ 1296 mmc->max_blk_count = 65536; 1297 1298 mmc->max_req_size = 33554432; /* MCI_DATA_LENGTH is 25 bits */ 1299 mmc->max_seg_size = mmc->max_req_size; 1300 1301 msmsdcc_writel(host, 0, MMCIMASK0); 1302 msmsdcc_writel(host, 0x5e007ff, MMCICLEAR); 1303 1304 msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0); 1305 host->saved_irq0mask = MCI_IRQENABLE; 1306 1307 /* 1308 * Setup card detect change 1309 */ 1310 1311 memset(&host->timer, 0, sizeof(host->timer)); 1312 1313 if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) { 1314 unsigned long irqflags = IRQF_SHARED | 1315 (stat_irqres->flags & IRQF_TRIGGER_MASK); 1316 1317 host->stat_irq = stat_irqres->start; 1318 ret = request_irq(host->stat_irq, 1319 msmsdcc_platform_status_irq, 1320 irqflags, 1321 DRIVER_NAME " (slot)", 1322 host); 1323 if (ret) { 1324 pr_err("%s: Unable to get slot IRQ %d (%d)\n", 1325 mmc_hostname(mmc), host->stat_irq, ret); 1326 goto clk_disable; 1327 } 1328 } else if (plat->register_status_notify) { 1329 plat->register_status_notify(msmsdcc_status_notify_cb, host); 1330 } else if (!plat->status) 1331 pr_err("%s: No card detect facilities available\n", 1332 mmc_hostname(mmc)); 1333 else { 1334 init_timer(&host->timer); 1335 host->timer.data = (unsigned long)host; 1336 host->timer.function = msmsdcc_check_status; 1337 host->timer.expires = jiffies + HZ; 1338 add_timer(&host->timer); 1339 } 1340 1341 if (plat->status) { 1342 host->oldstat = host->plat->status(mmc_dev(host->mmc)); 1343 host->eject = !host->oldstat; 1344 } 1345 1346 ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED, 1347 DRIVER_NAME " (cmd)", host); 1348 if (ret) 1349 goto stat_irq_free; 1350 1351 ret = request_irq(cmd_irqres->start, msmsdcc_pio_irq, IRQF_SHARED, 1352 DRIVER_NAME " (pio)", host); 1353 if (ret) 1354 goto cmd_irq_free; 1355 1356 mmc_set_drvdata(pdev, mmc); 1357 mmc_add_host(mmc); 1358 1359 pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n", 1360 mmc_hostname(mmc), (unsigned long long)memres->start, 1361 (unsigned int) cmd_irqres->start, 1362 (unsigned int) host->stat_irq, host->dma.channel); 1363 pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc), 1364 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled")); 1365 pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n", 1366 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate); 1367 pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject); 1368 pr_info("%s: Power save feature enable = %d\n", 1369 mmc_hostname(mmc), msmsdcc_pwrsave); 1370 1371 if (host->dma.channel != -1) { 1372 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n", 1373 mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr); 1374 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n", 1375 mmc_hostname(mmc), host->dma.cmd_busaddr, 1376 host->dma.cmdptr_busaddr); 1377 } else 1378 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc)); 1379 if (host->timer.function) 1380 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc)); 1381 1382 return 0; 1383 cmd_irq_free: 1384 free_irq(cmd_irqres->start, host); 1385 stat_irq_free: 1386 if (host->stat_irq) 1387 free_irq(host->stat_irq, host); 1388 clk_disable: 1389 msmsdcc_disable_clocks(host, 0); 1390 clk_put: 1391 clk_put(host->clk); 1392 pclk_put: 1393 clk_put(host->pclk); 1394dma_free: 1395 if (host->dmares) 1396 dma_free_coherent(NULL, sizeof(struct msmsdcc_nc_dmadata), 1397 host->dma.nc, host->dma.nc_busaddr); 1398ioremap_free: 1399 tasklet_kill(&host->dma_tlet); 1400 iounmap(host->base); 1401 host_free: 1402 mmc_free_host(mmc); 1403 out: 1404 return ret; 1405} 1406 1407#ifdef CONFIG_PM 1408#ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ 1409static void 1410do_resume_work(struct work_struct *work) 1411{ 1412 struct msmsdcc_host *host = 1413 container_of(work, struct msmsdcc_host, resume_task); 1414 struct mmc_host *mmc = host->mmc; 1415 1416 if (mmc) { 1417 mmc_resume_host(mmc); 1418 if (host->stat_irq) 1419 enable_irq(host->stat_irq); 1420 } 1421} 1422#endif 1423 1424 1425static int 1426msmsdcc_suspend(struct platform_device *dev, pm_message_t state) 1427{ 1428 struct mmc_host *mmc = mmc_get_drvdata(dev); 1429 int rc = 0; 1430 1431 if (mmc) { 1432 struct msmsdcc_host *host = mmc_priv(mmc); 1433 1434 if (host->stat_irq) 1435 disable_irq(host->stat_irq); 1436 1437 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO) 1438 rc = mmc_suspend_host(mmc); 1439 if (!rc) 1440 msmsdcc_writel(host, 0, MMCIMASK0); 1441 if (host->clks_on) 1442 msmsdcc_disable_clocks(host, 0); 1443 } 1444 return rc; 1445} 1446 1447static int 1448msmsdcc_resume(struct platform_device *dev) 1449{ 1450 struct mmc_host *mmc = mmc_get_drvdata(dev); 1451 1452 if (mmc) { 1453 struct msmsdcc_host *host = mmc_priv(mmc); 1454 1455 msmsdcc_enable_clocks(host); 1456 1457 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0); 1458 1459 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO) 1460 mmc_resume_host(mmc); 1461 if (host->stat_irq) 1462 enable_irq(host->stat_irq); 1463#if BUSCLK_PWRSAVE 1464 msmsdcc_disable_clocks(host, 1); 1465#endif 1466 } 1467 return 0; 1468} 1469#else 1470#define msmsdcc_suspend 0 1471#define msmsdcc_resume 0 1472#endif 1473 1474static struct platform_driver msmsdcc_driver = { 1475 .probe = msmsdcc_probe, 1476 .suspend = msmsdcc_suspend, 1477 .resume = msmsdcc_resume, 1478 .driver = { 1479 .name = "msm_sdcc", 1480 }, 1481}; 1482 1483module_platform_driver(msmsdcc_driver); 1484 1485MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver"); 1486MODULE_LICENSE("GPL"); 1487