1e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo/* 2e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * 5e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * Copyright 2008 Embedded Alley Solutions, Inc. 6e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * Copyright 2009-2011 Freescale Semiconductor, Inc. 7e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * 8e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * This program is free software; you can redistribute it and/or modify 9e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * it under the terms of the GNU General Public License as published by 10e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * the Free Software Foundation; either version 2 of the License, or 11e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * (at your option) any later version. 12e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * 13e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * This program is distributed in the hope that it will be useful, 14e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 15e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * GNU General Public License for more details. 17e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * 18e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * You should have received a copy of the GNU General Public License along 19e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * with this program; if not, write to the Free Software Foundation, Inc., 20e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo */ 22e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 23e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/kernel.h> 24e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/init.h> 25e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/ioport.h> 26e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/platform_device.h> 27e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/delay.h> 28e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/interrupt.h> 29e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/dma-mapping.h> 30e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/dmaengine.h> 31e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/highmem.h> 32e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/clk.h> 33e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/err.h> 34e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/completion.h> 35e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/mmc/host.h> 36e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/mmc/mmc.h> 37e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/mmc/sdio.h> 38e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/gpio.h> 39e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <linux/regulator/consumer.h> 4088b47679746b81534002bcba42da97ab82b5d12aPaul Gortmaker#include <linux/module.h> 413946860409130038ef6e0e5c50f2203053eae2b7Huang Shijie#include <linux/fsl/mxs-dma.h> 42e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 43e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <mach/mxs.h> 44e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <mach/common.h> 45e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#include <mach/mmc.h> 46e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 47e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define DRIVER_NAME "mxs-mmc" 48e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 49e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo/* card detect polling timeout */ 50e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define MXS_MMC_DETECT_TIMEOUT (HZ/2) 51e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 52e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define SSP_VERSION_LATEST 4 53e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define ssp_is_old() (host->version < SSP_VERSION_LATEST) 54e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 55e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo/* SSP registers */ 56e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_CTRL0 0x000 57e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL0_RUN (1 << 29) 58e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) 59e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26) 60e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL0_READ (1 << 25) 61e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL0_DATA_XFER (1 << 24) 62e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_CTRL0_BUS_WIDTH (22) 63e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22) 64e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) 65e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL0_LONG_RESP (1 << 19) 66e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL0_GET_RESP (1 << 17) 67e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL0_ENABLE (1 << 16) 68e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_CTRL0_XFER_COUNT (0) 69e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL0_XFER_COUNT (0xffff) 70e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_CMD0 0x010 71e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) 72e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22) 73e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21) 74e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CMD0_APPEND_8CYC (1 << 20) 75e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_CMD0_BLOCK_SIZE (16) 76e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16) 77e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_CMD0_BLOCK_COUNT (8) 78e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8) 79e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_CMD0_CMD (0) 80e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CMD0_CMD (0xff) 81e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_CMD1 0x020 82e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_XFER_SIZE 0x030 83e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_BLOCK_SIZE 0x040 84e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4) 85e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4) 86e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0) 87e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf) 88e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_TIMING (ssp_is_old() ? 0x050 : 0x070) 89e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_TIMING_TIMEOUT (16) 90e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_TIMING_TIMEOUT (0xffff << 16) 91e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_TIMING_CLOCK_DIVIDE (8) 92e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8) 93e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_TIMING_CLOCK_RATE (0) 94e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_TIMING_CLOCK_RATE (0xff) 95e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_CTRL1 (ssp_is_old() ? 0x060 : 0x080) 96e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31) 97e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30) 98e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29) 99e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) 100e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) 101e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) 102e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) 103e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) 104e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23) 105e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) 106e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) 107e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20) 108e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) 109e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) 110e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) 111e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) 112e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13) 113e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_POLARITY (1 << 9) 114e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_CTRL1_WORD_LENGTH (4) 115e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4) 116e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_CTRL1_SSP_MODE (0) 117e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_CTRL1_SSP_MODE (0xf) 118e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_SDRESP0 (ssp_is_old() ? 0x080 : 0x0a0) 119e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_SDRESP1 (ssp_is_old() ? 0x090 : 0x0b0) 120e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_SDRESP2 (ssp_is_old() ? 0x0a0 : 0x0c0) 121e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_SDRESP3 (ssp_is_old() ? 0x0b0 : 0x0d0) 122e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_STATUS (ssp_is_old() ? 0x0c0 : 0x100) 123e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_STATUS_CARD_DETECT (1 << 28) 124e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BM_SSP_STATUS_SDIO_IRQ (1 << 17) 125e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130) 126e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BP_SSP_VERSION_MAJOR (24) 127e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 128e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field) 129e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 130e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 131e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ | \ 132e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 133e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 134e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ | \ 135e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 136e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 137e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 138e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 139e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#define SSP_PIO_NUM 3 140e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 141e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostruct mxs_mmc_host { 142e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_host *mmc; 143e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_request *mrq; 144e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_command *cmd; 145e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_data *data; 146e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 147e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo void __iomem *base; 148e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo int irq; 149e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct resource *res; 150e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct resource *dma_res; 151e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct clk *clk; 152e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo unsigned int clk_rate; 153e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 154e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct dma_chan *dmach; 155e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_dma_data dma_data; 156e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo unsigned int dma_dir; 15705f5799cbe5c9e2c03f604b3de5783cf4d726227Vinod Koul enum dma_transfer_direction slave_dirn; 158e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo u32 ssp_pio_words[SSP_PIO_NUM]; 159e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 160e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo unsigned int version; 161e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo unsigned char bus_width; 162e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo spinlock_t lock; 163e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo int sdio_irq_en; 164e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo}; 165e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 166e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic int mxs_mmc_get_ro(struct mmc_host *mmc) 167e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 168e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 169e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_platform_data *pdata = 170e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc_dev(host->mmc)->platform_data; 171e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 172e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!pdata) 173e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return -EFAULT; 174e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 175e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!gpio_is_valid(pdata->wp_gpio)) 176e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return -EINVAL; 177e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 178e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return gpio_get_value(pdata->wp_gpio); 179e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 180e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 181e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic int mxs_mmc_get_cd(struct mmc_host *mmc) 182e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 183e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 184e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 185e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return !(readl(host->base + HW_SSP_STATUS) & 186e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_STATUS_CARD_DETECT); 187e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 188e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 189e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic void mxs_mmc_reset(struct mxs_mmc_host *host) 190e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 191e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo u32 ctrl0, ctrl1; 192e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 193e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mxs_reset_block(host->base); 194e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 195e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 196e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 197e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BF_SSP(0x7, CTRL1_WORD_LENGTH) | 198e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_DMA_ENABLE | 199e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_POLARITY | 200e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 201e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 202e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 203e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 204e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 205e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 206e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 207e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BF_SSP(2, TIMING_CLOCK_DIVIDE) | 208e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BF_SSP(0, TIMING_CLOCK_RATE), 209e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->base + HW_SSP_TIMING); 210e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 211e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (host->sdio_irq_en) { 212e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 213e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 214e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 215e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 216e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo writel(ctrl0, host->base + HW_SSP_CTRL0); 217e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo writel(ctrl1, host->base + HW_SSP_CTRL1); 218e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 219e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 220e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 221e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_command *cmd); 222e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 223e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic void mxs_mmc_request_done(struct mxs_mmc_host *host) 224e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 225e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_command *cmd = host->cmd; 226e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_data *data = host->data; 227e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_request *mrq = host->mrq; 228e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 229e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 230e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (mmc_resp_type(cmd) & MMC_RSP_136) { 231e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0); 232e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1); 233e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2); 234e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3); 235e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } else { 236e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0); 237e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 238e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 239e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 240e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (data) { 241e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg, 242e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo data->sg_len, host->dma_dir); 243e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo /* 244e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * If there was an error on any block, we mark all 245e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * data blocks as being in error. 246e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo */ 247e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!data->error) 248e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo data->bytes_xfered = data->blocks * data->blksz; 249e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo else 250e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo data->bytes_xfered = 0; 251e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 252e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->data = NULL; 253e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (mrq->stop) { 254e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mxs_mmc_start_cmd(host, mrq->stop); 255e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return; 256e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 257e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 258e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 259e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->mrq = NULL; 260e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc_request_done(host->mmc, mrq); 261e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 262e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 263e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic void mxs_mmc_dma_irq_callback(void *param) 264e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 265e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_host *host = param; 266e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 267e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mxs_mmc_request_done(host); 268e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 269e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 270e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 271e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 272e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_host *host = dev_id; 273e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_command *cmd = host->cmd; 274e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_data *data = host->data; 275e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo u32 stat; 276e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 277e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo spin_lock(&host->lock); 278e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 279e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo stat = readl(host->base + HW_SSP_CTRL1); 280e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo writel(stat & MXS_MMC_IRQ_BITS, 281e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR); 282e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 283e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 284e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc_signal_sdio_irq(host->mmc); 285e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 286e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo spin_unlock(&host->lock); 287e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 288e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 289e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd->error = -ETIMEDOUT; 290e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 291e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd->error = -EIO; 292e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 293e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (data) { 294e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 295e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 296e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo data->error = -ETIMEDOUT; 297e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 298e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo data->error = -EILSEQ; 299e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 300e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 301e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo data->error = -EIO; 302e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 303e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 304e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return IRQ_HANDLED; 305e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 306e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 307e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 308921de864b7c6413f15224d8f5e677541e8e1ac6dHuang Shijie struct mxs_mmc_host *host, unsigned long flags) 309e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 310e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct dma_async_tx_descriptor *desc; 311e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_data *data = host->data; 312e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct scatterlist * sgl; 313e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo unsigned int sg_len; 314e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 315e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (data) { 316e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo /* data */ 317e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dma_map_sg(mmc_dev(host->mmc), data->sg, 318e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo data->sg_len, host->dma_dir); 319e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo sgl = data->sg; 320e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo sg_len = data->sg_len; 321e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } else { 322e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo /* pio */ 323e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo sgl = (struct scatterlist *) host->ssp_pio_words; 324e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo sg_len = SSP_PIO_NUM; 325e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 326e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 32716052827d98fbc13c31ebad560af4bd53e2b4dd5Alexandre Bounine desc = dmaengine_prep_slave_sg(host->dmach, 328921de864b7c6413f15224d8f5e677541e8e1ac6dHuang Shijie sgl, sg_len, host->slave_dirn, flags); 329e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (desc) { 330e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo desc->callback = mxs_mmc_dma_irq_callback; 331e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo desc->callback_param = host; 332e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } else { 333e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (data) 334e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg, 335e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo data->sg_len, host->dma_dir); 336e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 337e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 338e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return desc; 339e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 340e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 341e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic void mxs_mmc_bc(struct mxs_mmc_host *host) 342e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 343e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_command *cmd = host->cmd; 344e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct dma_async_tx_descriptor *desc; 345e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo u32 ctrl0, cmd0, cmd1; 346e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 347e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 348e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 349e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd1 = cmd->arg; 350e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 351e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (host->sdio_irq_en) { 352e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 353e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 354e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 355e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 356e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->ssp_pio_words[0] = ctrl0; 357e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->ssp_pio_words[1] = cmd0; 358e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->ssp_pio_words[2] = cmd1; 359e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->dma_dir = DMA_NONE; 360a4e3e86d66ffc640ac54acffa29450e327a80ae2Shawn Guo host->slave_dirn = DMA_TRANS_NONE; 361921de864b7c6413f15224d8f5e677541e8e1ac6dHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 362e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!desc) 363e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo goto out; 364e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 365e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dmaengine_submit(desc); 366d04525ed0323709711277563a2c76e446a017423Shawn Guo dma_async_issue_pending(host->dmach); 367e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return; 368e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 369e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guoout: 370e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dev_warn(mmc_dev(host->mmc), 371e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo "%s: failed to prep dma\n", __func__); 372e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 373e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 374e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic void mxs_mmc_ac(struct mxs_mmc_host *host) 375e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 376e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_command *cmd = host->cmd; 377e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct dma_async_tx_descriptor *desc; 378e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo u32 ignore_crc, get_resp, long_resp; 379e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo u32 ctrl0, cmd0, cmd1; 380e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 381e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 382e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC; 383e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 384e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL0_GET_RESP : 0; 385e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 386e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL0_LONG_RESP : 0; 387e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 388e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 389e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 390e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd1 = cmd->arg; 391e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 392e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (host->sdio_irq_en) { 393e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 394e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 395e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 396e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 397e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->ssp_pio_words[0] = ctrl0; 398e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->ssp_pio_words[1] = cmd0; 399e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->ssp_pio_words[2] = cmd1; 400e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->dma_dir = DMA_NONE; 401a4e3e86d66ffc640ac54acffa29450e327a80ae2Shawn Guo host->slave_dirn = DMA_TRANS_NONE; 402921de864b7c6413f15224d8f5e677541e8e1ac6dHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 403e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!desc) 404e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo goto out; 405e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 406e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dmaengine_submit(desc); 407d04525ed0323709711277563a2c76e446a017423Shawn Guo dma_async_issue_pending(host->dmach); 408e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return; 409e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 410e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guoout: 411e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dev_warn(mmc_dev(host->mmc), 412e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo "%s: failed to prep dma\n", __func__); 413e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 414e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 415e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 416e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 417e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo const unsigned int ssp_timeout_mul = 4096; 418e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo /* 419e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * Calculate ticks in ms since ns are large numbers 420e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * and might overflow 421e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo */ 422e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo const unsigned int clock_per_ms = clock_rate / 1000; 423e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo const unsigned int ms = ns / 1000; 424e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo const unsigned int ticks = ms * clock_per_ms; 425e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 426e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 427e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo WARN_ON(ssp_ticks == 0); 428e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return ssp_ticks; 429e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 430e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 431e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic void mxs_mmc_adtc(struct mxs_mmc_host *host) 432e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 433e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_command *cmd = host->cmd; 434e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_data *data = cmd->data; 435e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct dma_async_tx_descriptor *desc; 436e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct scatterlist *sgl = data->sg, *sg; 437e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo unsigned int sg_len = data->sg_len; 438e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo int i; 439e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 440e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo unsigned short dma_data_dir, timeout; 44105f5799cbe5c9e2c03f604b3de5783cf4d726227Vinod Koul enum dma_transfer_direction slave_dirn; 442e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo unsigned int data_size = 0, log2_blksz; 443e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo unsigned int blocks = data->blocks; 444e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 445e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo u32 ignore_crc, get_resp, long_resp, read; 446e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo u32 ctrl0, cmd0, cmd1, val; 447e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 448e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 449e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC; 450e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 451e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL0_GET_RESP : 0; 452e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 453e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL0_LONG_RESP : 0; 454e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 455e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (data->flags & MMC_DATA_WRITE) { 456e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dma_data_dir = DMA_TO_DEVICE; 45705f5799cbe5c9e2c03f604b3de5783cf4d726227Vinod Koul slave_dirn = DMA_MEM_TO_DEV; 458e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo read = 0; 459e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } else { 460e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dma_data_dir = DMA_FROM_DEVICE; 46105f5799cbe5c9e2c03f604b3de5783cf4d726227Vinod Koul slave_dirn = DMA_DEV_TO_MEM; 462e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo read = BM_SSP_CTRL0_READ; 463e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 464e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 465e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 466e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ignore_crc | get_resp | long_resp | 467e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL0_DATA_XFER | read | 468e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL0_WAIT_FOR_IRQ | 469e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BM_SSP_CTRL0_ENABLE; 470e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 471e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 472e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 473e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo /* get logarithm to base 2 of block size for setting register */ 474e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo log2_blksz = ilog2(data->blksz); 475e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 476e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo /* 477e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * take special care of the case that data size from data->sg 478e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo * is not equal to blocks x blksz 479e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo */ 480e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo for_each_sg(sgl, sg, sg_len, i) 481e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo data_size += sg->length; 482e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 483e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (data_size != data->blocks * data->blksz) 484e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo blocks = 1; 485e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 486e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo /* xfer count, block size and count need to be set differently */ 487e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (ssp_is_old()) { 488e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 489e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 490e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 491e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } else { 492e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo writel(data_size, host->base + HW_SSP_XFER_SIZE); 493e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 494e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 495e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->base + HW_SSP_BLOCK_SIZE); 496e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 497e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 498e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if ((cmd->opcode == MMC_STOP_TRANSMISSION) || 499e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo (cmd->opcode == SD_IO_RW_EXTENDED)) 500e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 501e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 502e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd1 = cmd->arg; 503e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 504e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (host->sdio_irq_en) { 505e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 506e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 507e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 508e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 509e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo /* set the timeout count */ 510e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns); 511e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo val = readl(host->base + HW_SSP_TIMING); 512e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo val &= ~(BM_SSP_TIMING_TIMEOUT); 513e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo val |= BF_SSP(timeout, TIMING_TIMEOUT); 514e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo writel(val, host->base + HW_SSP_TIMING); 515e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 516e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo /* pio */ 517e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->ssp_pio_words[0] = ctrl0; 518e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->ssp_pio_words[1] = cmd0; 519e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->ssp_pio_words[2] = cmd1; 520e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->dma_dir = DMA_NONE; 521a4e3e86d66ffc640ac54acffa29450e327a80ae2Shawn Guo host->slave_dirn = DMA_TRANS_NONE; 522e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo desc = mxs_mmc_prep_dma(host, 0); 523e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!desc) 524e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo goto out; 525e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 526e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo /* append data sg */ 527e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo WARN_ON(host->data != NULL); 528e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->data = data; 529e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->dma_dir = dma_data_dir; 53005f5799cbe5c9e2c03f604b3de5783cf4d726227Vinod Koul host->slave_dirn = slave_dirn; 531921de864b7c6413f15224d8f5e677541e8e1ac6dHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 532e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!desc) 533e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo goto out; 534e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 535e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dmaengine_submit(desc); 536d04525ed0323709711277563a2c76e446a017423Shawn Guo dma_async_issue_pending(host->dmach); 537e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return; 538e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guoout: 539e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dev_warn(mmc_dev(host->mmc), 540e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo "%s: failed to prep dma\n", __func__); 541e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 542e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 543e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 544e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_command *cmd) 545e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 546e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->cmd = cmd; 547e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 548e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo switch (mmc_cmd_type(cmd)) { 549e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo case MMC_CMD_BC: 550e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mxs_mmc_bc(host); 551e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo break; 552e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo case MMC_CMD_BCR: 553e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mxs_mmc_ac(host); 554e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo break; 555e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo case MMC_CMD_AC: 556e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mxs_mmc_ac(host); 557e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo break; 558e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo case MMC_CMD_ADTC: 559e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mxs_mmc_adtc(host); 560e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo break; 561e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo default: 562e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dev_warn(mmc_dev(host->mmc), 563e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo "%s: unknown MMC command\n", __func__); 564e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo break; 565e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 566e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 567e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 568e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 569e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 570e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 571e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 572e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo WARN_ON(host->mrq != NULL); 573e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->mrq = mrq; 574e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mxs_mmc_start_cmd(host, mrq->cmd); 575e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 576e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 577e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate) 578e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 579d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel unsigned int ssp_clk, ssp_sck; 580d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel u32 clock_divide, clock_rate; 581e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo u32 val; 582e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 583d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel ssp_clk = clk_get_rate(host->clk); 584e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 585d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) { 586d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide); 587d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0; 588d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel if (clock_rate <= 255) 589e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo break; 590e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 591e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 592d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel if (clock_divide > 254) { 593e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dev_err(mmc_dev(host->mmc), 594e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo "%s: cannot set clock to %d\n", __func__, rate); 595e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return; 596e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 597e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 598d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel ssp_sck = ssp_clk / clock_divide / (1 + clock_rate); 599e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 600e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo val = readl(host->base + HW_SSP_TIMING); 601e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE); 602d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE); 603d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE); 604e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo writel(val, host->base + HW_SSP_TIMING); 605e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 606d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel host->clk_rate = ssp_sck; 607e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 608e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dev_dbg(mmc_dev(host->mmc), 609d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n", 610d982dcdc4e64eb1881df44b0035a8268bf1ab067Koen Beel __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate); 611e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 612e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 613e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 614e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 615e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 616e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 617e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (ios->bus_width == MMC_BUS_WIDTH_8) 618e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->bus_width = 2; 619e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo else if (ios->bus_width == MMC_BUS_WIDTH_4) 620e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->bus_width = 1; 621e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo else 622e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->bus_width = 0; 623e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 624e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (ios->clock) 625e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mxs_mmc_set_clk_rate(host, ios->clock); 626e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 627e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 628e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 629e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 630e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 631e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo unsigned long flags; 632e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 633e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo spin_lock_irqsave(&host->lock, flags); 634e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 635e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->sdio_irq_en = enable; 636e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 637e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (enable) { 638e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 639e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->base + HW_SSP_CTRL0 + MXS_SET_ADDR); 640e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 641e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->base + HW_SSP_CTRL1 + MXS_SET_ADDR); 642e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 643e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (readl(host->base + HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ) 644e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc_signal_sdio_irq(host->mmc); 645e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 646e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } else { 647e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 648e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->base + HW_SSP_CTRL0 + MXS_CLR_ADDR); 649e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 650e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR); 651e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 652e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 653e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo spin_unlock_irqrestore(&host->lock, flags); 654e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 655e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 656e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic const struct mmc_host_ops mxs_mmc_ops = { 657e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .request = mxs_mmc_request, 658e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .get_ro = mxs_mmc_get_ro, 659e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .get_cd = mxs_mmc_get_cd, 660e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .set_ios = mxs_mmc_set_ios, 661e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 662e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo}; 663e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 664e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param) 665e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 666e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_host *host = param; 667e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 668e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!mxs_dma_is_apbh(chan)) 669e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return false; 670e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 671e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (chan->chan_id != host->dma_res->start) 672e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return false; 673e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 674e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo chan->private = &host->dma_data; 675e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 676e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return true; 677e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 678e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 679e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic int mxs_mmc_probe(struct platform_device *pdev) 680e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 681e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_host *host; 682e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_host *mmc; 683e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct resource *iores, *dmares, *r; 684e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_platform_data *pdata; 685e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo int ret = 0, irq_err, irq_dma; 686e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dma_cap_mask_t mask; 687e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 688e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 689e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 690e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo irq_err = platform_get_irq(pdev, 0); 691e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo irq_dma = platform_get_irq(pdev, 1); 692e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!iores || !dmares || irq_err < 0 || irq_dma < 0) 693e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return -EINVAL; 694e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 695e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo r = request_mem_region(iores->start, resource_size(iores), pdev->name); 696e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!r) 697e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return -EBUSY; 698e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 699e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 700e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!mmc) { 701e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ret = -ENOMEM; 702e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo goto out_release_mem; 703e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 704e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 705e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host = mmc_priv(mmc); 706e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->base = ioremap(r->start, resource_size(r)); 707e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!host->base) { 708e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ret = -ENOMEM; 709e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo goto out_mmc_free; 710e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 711e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 712e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo /* only major verion does matter */ 713e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->version = readl(host->base + HW_SSP_VERSION) >> 714e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo BP_SSP_VERSION_MAJOR; 715e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 716e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->mmc = mmc; 717e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->res = r; 718e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->dma_res = dmares; 719e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->irq = irq_err; 720e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->sdio_irq_en = 0; 721e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 722e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->clk = clk_get(&pdev->dev, NULL); 723e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (IS_ERR(host->clk)) { 724e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ret = PTR_ERR(host->clk); 725e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo goto out_iounmap; 726e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 727efdfc52c0470fb650cb2ee44cf030ec04e97b954Shawn Guo clk_prepare_enable(host->clk); 728e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 729e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mxs_mmc_reset(host); 730e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 731e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dma_cap_zero(mask); 732e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dma_cap_set(DMA_SLAVE, mask); 733e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->dma_data.chan_irq = irq_dma; 734e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host); 735e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (!host->dmach) { 736e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dev_err(mmc_dev(host->mmc), 737e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo "%s: failed to request dma\n", __func__); 738e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo goto out_clk_put; 739e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 740e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 741e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo /* set mmc core parameters */ 742e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc->ops = &mxs_mmc_ops; 743e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 744e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; 745e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 746e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo pdata = mmc_dev(host->mmc)->platform_data; 747e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (pdata) { 748e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (pdata->flags & SLOTF_8_BIT_CAPABLE) 749e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 750e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (pdata->flags & SLOTF_4_BIT_CAPABLE) 751e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA; 752e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo } 753e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 754e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc->f_min = 400000; 755e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc->f_max = 288000000; 756e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 757e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 758e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc->max_segs = 52; 759e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc->max_blk_size = 1 << 0xf; 760e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc->max_blk_count = (ssp_is_old()) ? 0xff : 0xffffff; 761e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc->max_req_size = (ssp_is_old()) ? 0xffff : 0xffffffff; 762e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev); 763e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 764e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo platform_set_drvdata(pdev, mmc); 765e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 766e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host); 767e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (ret) 768e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo goto out_free_dma; 769e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 770e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo spin_lock_init(&host->lock); 771e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 772e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ret = mmc_add_host(mmc); 773e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (ret) 774e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo goto out_free_irq; 775e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 776e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dev_info(mmc_dev(host->mmc), "initialized\n"); 777e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 778e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return 0; 779e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 780e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guoout_free_irq: 781e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo free_irq(host->irq, host); 782e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guoout_free_dma: 783e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (host->dmach) 784e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dma_release_channel(host->dmach); 785e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guoout_clk_put: 786efdfc52c0470fb650cb2ee44cf030ec04e97b954Shawn Guo clk_disable_unprepare(host->clk); 787e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo clk_put(host->clk); 788e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guoout_iounmap: 789e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo iounmap(host->base); 790e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guoout_mmc_free: 791e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc_free_host(mmc); 792e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guoout_release_mem: 793e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo release_mem_region(iores->start, resource_size(iores)); 794e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return ret; 795e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 796e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 797e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic int mxs_mmc_remove(struct platform_device *pdev) 798e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 799e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_host *mmc = platform_get_drvdata(pdev); 800e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 801e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct resource *res = host->res; 802e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 803e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc_remove_host(mmc); 804e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 805e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo free_irq(host->irq, host); 806e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 807e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo platform_set_drvdata(pdev, NULL); 808e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 809e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo if (host->dmach) 810e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo dma_release_channel(host->dmach); 811e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 812efdfc52c0470fb650cb2ee44cf030ec04e97b954Shawn Guo clk_disable_unprepare(host->clk); 813e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo clk_put(host->clk); 814e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 815e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo iounmap(host->base); 816e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 817e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo mmc_free_host(mmc); 818e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 819e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo release_mem_region(res->start, resource_size(res)); 820e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 821e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return 0; 822e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 823e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 824e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#ifdef CONFIG_PM 825e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic int mxs_mmc_suspend(struct device *dev) 826e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 827e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_host *mmc = dev_get_drvdata(dev); 828e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 829e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo int ret = 0; 830e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 831e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ret = mmc_suspend_host(mmc); 832e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 833efdfc52c0470fb650cb2ee44cf030ec04e97b954Shawn Guo clk_disable_unprepare(host->clk); 834e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 835e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return ret; 836e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 837e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 838e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic int mxs_mmc_resume(struct device *dev) 839e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo{ 840e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mmc_host *mmc = dev_get_drvdata(dev); 841e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 842e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo int ret = 0; 843e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 844efdfc52c0470fb650cb2ee44cf030ec04e97b954Shawn Guo clk_prepare_enable(host->clk); 845e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 846e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo ret = mmc_resume_host(mmc); 847e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 848e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo return ret; 849e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo} 850e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 851e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic const struct dev_pm_ops mxs_mmc_pm_ops = { 852e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .suspend = mxs_mmc_suspend, 853e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .resume = mxs_mmc_resume, 854e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo}; 855e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#endif 856e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 857e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guostatic struct platform_driver mxs_mmc_driver = { 858e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .probe = mxs_mmc_probe, 859e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .remove = mxs_mmc_remove, 860e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .driver = { 861e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .name = DRIVER_NAME, 862e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .owner = THIS_MODULE, 863e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#ifdef CONFIG_PM 864e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo .pm = &mxs_mmc_pm_ops, 865e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo#endif 866e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo }, 867e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo}; 868e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 869d1f81a64a4250bdd776978be06ae2b8e13ec7471Axel Linmodule_platform_driver(mxs_mmc_driver); 870e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn Guo 871e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn GuoMODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 872e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn GuoMODULE_AUTHOR("Freescale Semiconductor"); 873e4243f13d10e5fbe2b84e211dcac3bc6e0792167Shawn GuoMODULE_LICENSE("GPL"); 874