mxs-mmc.c revision e4243f13d10e5fbe2b84e211dcac3bc6e0792167
1/* 2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4 * 5 * Copyright 2008 Embedded Alley Solutions, Inc. 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21 */ 22 23#include <linux/kernel.h> 24#include <linux/init.h> 25#include <linux/ioport.h> 26#include <linux/platform_device.h> 27#include <linux/delay.h> 28#include <linux/interrupt.h> 29#include <linux/dma-mapping.h> 30#include <linux/dmaengine.h> 31#include <linux/highmem.h> 32#include <linux/clk.h> 33#include <linux/err.h> 34#include <linux/completion.h> 35#include <linux/mmc/host.h> 36#include <linux/mmc/mmc.h> 37#include <linux/mmc/sdio.h> 38#include <linux/gpio.h> 39#include <linux/regulator/consumer.h> 40 41#include <mach/mxs.h> 42#include <mach/common.h> 43#include <mach/dma.h> 44#include <mach/mmc.h> 45 46#define DRIVER_NAME "mxs-mmc" 47 48/* card detect polling timeout */ 49#define MXS_MMC_DETECT_TIMEOUT (HZ/2) 50 51#define SSP_VERSION_LATEST 4 52#define ssp_is_old() (host->version < SSP_VERSION_LATEST) 53 54/* SSP registers */ 55#define HW_SSP_CTRL0 0x000 56#define BM_SSP_CTRL0_RUN (1 << 29) 57#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) 58#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26) 59#define BM_SSP_CTRL0_READ (1 << 25) 60#define BM_SSP_CTRL0_DATA_XFER (1 << 24) 61#define BP_SSP_CTRL0_BUS_WIDTH (22) 62#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22) 63#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) 64#define BM_SSP_CTRL0_LONG_RESP (1 << 19) 65#define BM_SSP_CTRL0_GET_RESP (1 << 17) 66#define BM_SSP_CTRL0_ENABLE (1 << 16) 67#define BP_SSP_CTRL0_XFER_COUNT (0) 68#define BM_SSP_CTRL0_XFER_COUNT (0xffff) 69#define HW_SSP_CMD0 0x010 70#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) 71#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22) 72#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21) 73#define BM_SSP_CMD0_APPEND_8CYC (1 << 20) 74#define BP_SSP_CMD0_BLOCK_SIZE (16) 75#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16) 76#define BP_SSP_CMD0_BLOCK_COUNT (8) 77#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8) 78#define BP_SSP_CMD0_CMD (0) 79#define BM_SSP_CMD0_CMD (0xff) 80#define HW_SSP_CMD1 0x020 81#define HW_SSP_XFER_SIZE 0x030 82#define HW_SSP_BLOCK_SIZE 0x040 83#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4) 84#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4) 85#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0) 86#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf) 87#define HW_SSP_TIMING (ssp_is_old() ? 0x050 : 0x070) 88#define BP_SSP_TIMING_TIMEOUT (16) 89#define BM_SSP_TIMING_TIMEOUT (0xffff << 16) 90#define BP_SSP_TIMING_CLOCK_DIVIDE (8) 91#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8) 92#define BP_SSP_TIMING_CLOCK_RATE (0) 93#define BM_SSP_TIMING_CLOCK_RATE (0xff) 94#define HW_SSP_CTRL1 (ssp_is_old() ? 0x060 : 0x080) 95#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31) 96#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30) 97#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29) 98#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) 99#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) 100#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) 101#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) 102#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) 103#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23) 104#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) 105#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) 106#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20) 107#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) 108#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) 109#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) 110#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) 111#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13) 112#define BM_SSP_CTRL1_POLARITY (1 << 9) 113#define BP_SSP_CTRL1_WORD_LENGTH (4) 114#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4) 115#define BP_SSP_CTRL1_SSP_MODE (0) 116#define BM_SSP_CTRL1_SSP_MODE (0xf) 117#define HW_SSP_SDRESP0 (ssp_is_old() ? 0x080 : 0x0a0) 118#define HW_SSP_SDRESP1 (ssp_is_old() ? 0x090 : 0x0b0) 119#define HW_SSP_SDRESP2 (ssp_is_old() ? 0x0a0 : 0x0c0) 120#define HW_SSP_SDRESP3 (ssp_is_old() ? 0x0b0 : 0x0d0) 121#define HW_SSP_STATUS (ssp_is_old() ? 0x0c0 : 0x100) 122#define BM_SSP_STATUS_CARD_DETECT (1 << 28) 123#define BM_SSP_STATUS_SDIO_IRQ (1 << 17) 124#define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130) 125#define BP_SSP_VERSION_MAJOR (24) 126 127#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field) 128 129#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 130 BM_SSP_CTRL1_RESP_ERR_IRQ | \ 131 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 132 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 133 BM_SSP_CTRL1_DATA_CRC_IRQ | \ 134 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 135 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 136 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 137 138#define SSP_PIO_NUM 3 139 140struct mxs_mmc_host { 141 struct mmc_host *mmc; 142 struct mmc_request *mrq; 143 struct mmc_command *cmd; 144 struct mmc_data *data; 145 146 void __iomem *base; 147 int irq; 148 struct resource *res; 149 struct resource *dma_res; 150 struct clk *clk; 151 unsigned int clk_rate; 152 153 struct dma_chan *dmach; 154 struct mxs_dma_data dma_data; 155 unsigned int dma_dir; 156 u32 ssp_pio_words[SSP_PIO_NUM]; 157 158 unsigned int version; 159 unsigned char bus_width; 160 spinlock_t lock; 161 int sdio_irq_en; 162}; 163 164static int mxs_mmc_get_ro(struct mmc_host *mmc) 165{ 166 struct mxs_mmc_host *host = mmc_priv(mmc); 167 struct mxs_mmc_platform_data *pdata = 168 mmc_dev(host->mmc)->platform_data; 169 170 if (!pdata) 171 return -EFAULT; 172 173 if (!gpio_is_valid(pdata->wp_gpio)) 174 return -EINVAL; 175 176 return gpio_get_value(pdata->wp_gpio); 177} 178 179static int mxs_mmc_get_cd(struct mmc_host *mmc) 180{ 181 struct mxs_mmc_host *host = mmc_priv(mmc); 182 183 return !(readl(host->base + HW_SSP_STATUS) & 184 BM_SSP_STATUS_CARD_DETECT); 185} 186 187static void mxs_mmc_reset(struct mxs_mmc_host *host) 188{ 189 u32 ctrl0, ctrl1; 190 191 mxs_reset_block(host->base); 192 193 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 194 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 195 BF_SSP(0x7, CTRL1_WORD_LENGTH) | 196 BM_SSP_CTRL1_DMA_ENABLE | 197 BM_SSP_CTRL1_POLARITY | 198 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 199 BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 200 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 201 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 202 BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 203 204 writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 205 BF_SSP(2, TIMING_CLOCK_DIVIDE) | 206 BF_SSP(0, TIMING_CLOCK_RATE), 207 host->base + HW_SSP_TIMING); 208 209 if (host->sdio_irq_en) { 210 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 211 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 212 } 213 214 writel(ctrl0, host->base + HW_SSP_CTRL0); 215 writel(ctrl1, host->base + HW_SSP_CTRL1); 216} 217 218static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 219 struct mmc_command *cmd); 220 221static void mxs_mmc_request_done(struct mxs_mmc_host *host) 222{ 223 struct mmc_command *cmd = host->cmd; 224 struct mmc_data *data = host->data; 225 struct mmc_request *mrq = host->mrq; 226 227 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 228 if (mmc_resp_type(cmd) & MMC_RSP_136) { 229 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0); 230 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1); 231 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2); 232 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3); 233 } else { 234 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0); 235 } 236 } 237 238 if (data) { 239 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 240 data->sg_len, host->dma_dir); 241 /* 242 * If there was an error on any block, we mark all 243 * data blocks as being in error. 244 */ 245 if (!data->error) 246 data->bytes_xfered = data->blocks * data->blksz; 247 else 248 data->bytes_xfered = 0; 249 250 host->data = NULL; 251 if (mrq->stop) { 252 mxs_mmc_start_cmd(host, mrq->stop); 253 return; 254 } 255 } 256 257 host->mrq = NULL; 258 mmc_request_done(host->mmc, mrq); 259} 260 261static void mxs_mmc_dma_irq_callback(void *param) 262{ 263 struct mxs_mmc_host *host = param; 264 265 mxs_mmc_request_done(host); 266} 267 268static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 269{ 270 struct mxs_mmc_host *host = dev_id; 271 struct mmc_command *cmd = host->cmd; 272 struct mmc_data *data = host->data; 273 u32 stat; 274 275 spin_lock(&host->lock); 276 277 stat = readl(host->base + HW_SSP_CTRL1); 278 writel(stat & MXS_MMC_IRQ_BITS, 279 host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR); 280 281 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 282 mmc_signal_sdio_irq(host->mmc); 283 284 spin_unlock(&host->lock); 285 286 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 287 cmd->error = -ETIMEDOUT; 288 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 289 cmd->error = -EIO; 290 291 if (data) { 292 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 293 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 294 data->error = -ETIMEDOUT; 295 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 296 data->error = -EILSEQ; 297 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 298 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 299 data->error = -EIO; 300 } 301 302 return IRQ_HANDLED; 303} 304 305static struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 306 struct mxs_mmc_host *host, unsigned int append) 307{ 308 struct dma_async_tx_descriptor *desc; 309 struct mmc_data *data = host->data; 310 struct scatterlist * sgl; 311 unsigned int sg_len; 312 313 if (data) { 314 /* data */ 315 dma_map_sg(mmc_dev(host->mmc), data->sg, 316 data->sg_len, host->dma_dir); 317 sgl = data->sg; 318 sg_len = data->sg_len; 319 } else { 320 /* pio */ 321 sgl = (struct scatterlist *) host->ssp_pio_words; 322 sg_len = SSP_PIO_NUM; 323 } 324 325 desc = host->dmach->device->device_prep_slave_sg(host->dmach, 326 sgl, sg_len, host->dma_dir, append); 327 if (desc) { 328 desc->callback = mxs_mmc_dma_irq_callback; 329 desc->callback_param = host; 330 } else { 331 if (data) 332 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 333 data->sg_len, host->dma_dir); 334 } 335 336 return desc; 337} 338 339static void mxs_mmc_bc(struct mxs_mmc_host *host) 340{ 341 struct mmc_command *cmd = host->cmd; 342 struct dma_async_tx_descriptor *desc; 343 u32 ctrl0, cmd0, cmd1; 344 345 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 346 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 347 cmd1 = cmd->arg; 348 349 if (host->sdio_irq_en) { 350 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 351 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 352 } 353 354 host->ssp_pio_words[0] = ctrl0; 355 host->ssp_pio_words[1] = cmd0; 356 host->ssp_pio_words[2] = cmd1; 357 host->dma_dir = DMA_NONE; 358 desc = mxs_mmc_prep_dma(host, 0); 359 if (!desc) 360 goto out; 361 362 dmaengine_submit(desc); 363 return; 364 365out: 366 dev_warn(mmc_dev(host->mmc), 367 "%s: failed to prep dma\n", __func__); 368} 369 370static void mxs_mmc_ac(struct mxs_mmc_host *host) 371{ 372 struct mmc_command *cmd = host->cmd; 373 struct dma_async_tx_descriptor *desc; 374 u32 ignore_crc, get_resp, long_resp; 375 u32 ctrl0, cmd0, cmd1; 376 377 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 378 0 : BM_SSP_CTRL0_IGNORE_CRC; 379 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 380 BM_SSP_CTRL0_GET_RESP : 0; 381 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 382 BM_SSP_CTRL0_LONG_RESP : 0; 383 384 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 385 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 386 cmd1 = cmd->arg; 387 388 if (host->sdio_irq_en) { 389 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 390 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 391 } 392 393 host->ssp_pio_words[0] = ctrl0; 394 host->ssp_pio_words[1] = cmd0; 395 host->ssp_pio_words[2] = cmd1; 396 host->dma_dir = DMA_NONE; 397 desc = mxs_mmc_prep_dma(host, 0); 398 if (!desc) 399 goto out; 400 401 dmaengine_submit(desc); 402 return; 403 404out: 405 dev_warn(mmc_dev(host->mmc), 406 "%s: failed to prep dma\n", __func__); 407} 408 409static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 410{ 411 const unsigned int ssp_timeout_mul = 4096; 412 /* 413 * Calculate ticks in ms since ns are large numbers 414 * and might overflow 415 */ 416 const unsigned int clock_per_ms = clock_rate / 1000; 417 const unsigned int ms = ns / 1000; 418 const unsigned int ticks = ms * clock_per_ms; 419 const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 420 421 WARN_ON(ssp_ticks == 0); 422 return ssp_ticks; 423} 424 425static void mxs_mmc_adtc(struct mxs_mmc_host *host) 426{ 427 struct mmc_command *cmd = host->cmd; 428 struct mmc_data *data = cmd->data; 429 struct dma_async_tx_descriptor *desc; 430 struct scatterlist *sgl = data->sg, *sg; 431 unsigned int sg_len = data->sg_len; 432 int i; 433 434 unsigned short dma_data_dir, timeout; 435 unsigned int data_size = 0, log2_blksz; 436 unsigned int blocks = data->blocks; 437 438 u32 ignore_crc, get_resp, long_resp, read; 439 u32 ctrl0, cmd0, cmd1, val; 440 441 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 442 0 : BM_SSP_CTRL0_IGNORE_CRC; 443 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 444 BM_SSP_CTRL0_GET_RESP : 0; 445 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 446 BM_SSP_CTRL0_LONG_RESP : 0; 447 448 if (data->flags & MMC_DATA_WRITE) { 449 dma_data_dir = DMA_TO_DEVICE; 450 read = 0; 451 } else { 452 dma_data_dir = DMA_FROM_DEVICE; 453 read = BM_SSP_CTRL0_READ; 454 } 455 456 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 457 ignore_crc | get_resp | long_resp | 458 BM_SSP_CTRL0_DATA_XFER | read | 459 BM_SSP_CTRL0_WAIT_FOR_IRQ | 460 BM_SSP_CTRL0_ENABLE; 461 462 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 463 464 /* get logarithm to base 2 of block size for setting register */ 465 log2_blksz = ilog2(data->blksz); 466 467 /* 468 * take special care of the case that data size from data->sg 469 * is not equal to blocks x blksz 470 */ 471 for_each_sg(sgl, sg, sg_len, i) 472 data_size += sg->length; 473 474 if (data_size != data->blocks * data->blksz) 475 blocks = 1; 476 477 /* xfer count, block size and count need to be set differently */ 478 if (ssp_is_old()) { 479 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 480 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 481 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 482 } else { 483 writel(data_size, host->base + HW_SSP_XFER_SIZE); 484 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 485 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 486 host->base + HW_SSP_BLOCK_SIZE); 487 } 488 489 if ((cmd->opcode == MMC_STOP_TRANSMISSION) || 490 (cmd->opcode == SD_IO_RW_EXTENDED)) 491 cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 492 493 cmd1 = cmd->arg; 494 495 if (host->sdio_irq_en) { 496 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 497 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 498 } 499 500 /* set the timeout count */ 501 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns); 502 val = readl(host->base + HW_SSP_TIMING); 503 val &= ~(BM_SSP_TIMING_TIMEOUT); 504 val |= BF_SSP(timeout, TIMING_TIMEOUT); 505 writel(val, host->base + HW_SSP_TIMING); 506 507 /* pio */ 508 host->ssp_pio_words[0] = ctrl0; 509 host->ssp_pio_words[1] = cmd0; 510 host->ssp_pio_words[2] = cmd1; 511 host->dma_dir = DMA_NONE; 512 desc = mxs_mmc_prep_dma(host, 0); 513 if (!desc) 514 goto out; 515 516 /* append data sg */ 517 WARN_ON(host->data != NULL); 518 host->data = data; 519 host->dma_dir = dma_data_dir; 520 desc = mxs_mmc_prep_dma(host, 1); 521 if (!desc) 522 goto out; 523 524 dmaengine_submit(desc); 525 return; 526out: 527 dev_warn(mmc_dev(host->mmc), 528 "%s: failed to prep dma\n", __func__); 529} 530 531static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 532 struct mmc_command *cmd) 533{ 534 host->cmd = cmd; 535 536 switch (mmc_cmd_type(cmd)) { 537 case MMC_CMD_BC: 538 mxs_mmc_bc(host); 539 break; 540 case MMC_CMD_BCR: 541 mxs_mmc_ac(host); 542 break; 543 case MMC_CMD_AC: 544 mxs_mmc_ac(host); 545 break; 546 case MMC_CMD_ADTC: 547 mxs_mmc_adtc(host); 548 break; 549 default: 550 dev_warn(mmc_dev(host->mmc), 551 "%s: unknown MMC command\n", __func__); 552 break; 553 } 554} 555 556static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 557{ 558 struct mxs_mmc_host *host = mmc_priv(mmc); 559 560 WARN_ON(host->mrq != NULL); 561 host->mrq = mrq; 562 mxs_mmc_start_cmd(host, mrq->cmd); 563} 564 565static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate) 566{ 567 unsigned int ssp_rate, bit_rate; 568 u32 div1, div2; 569 u32 val; 570 571 ssp_rate = clk_get_rate(host->clk); 572 573 for (div1 = 2; div1 < 254; div1 += 2) { 574 div2 = ssp_rate / rate / div1; 575 if (div2 < 0x100) 576 break; 577 } 578 579 if (div1 >= 254) { 580 dev_err(mmc_dev(host->mmc), 581 "%s: cannot set clock to %d\n", __func__, rate); 582 return; 583 } 584 585 if (div2 == 0) 586 bit_rate = ssp_rate / div1; 587 else 588 bit_rate = ssp_rate / div1 / div2; 589 590 val = readl(host->base + HW_SSP_TIMING); 591 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE); 592 val |= BF_SSP(div1, TIMING_CLOCK_DIVIDE); 593 val |= BF_SSP(div2 - 1, TIMING_CLOCK_RATE); 594 writel(val, host->base + HW_SSP_TIMING); 595 596 host->clk_rate = bit_rate; 597 598 dev_dbg(mmc_dev(host->mmc), 599 "%s: div1 %d, div2 %d, ssp %d, bit %d, rate %d\n", 600 __func__, div1, div2, ssp_rate, bit_rate, rate); 601} 602 603static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 604{ 605 struct mxs_mmc_host *host = mmc_priv(mmc); 606 607 if (ios->bus_width == MMC_BUS_WIDTH_8) 608 host->bus_width = 2; 609 else if (ios->bus_width == MMC_BUS_WIDTH_4) 610 host->bus_width = 1; 611 else 612 host->bus_width = 0; 613 614 if (ios->clock) 615 mxs_mmc_set_clk_rate(host, ios->clock); 616} 617 618static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 619{ 620 struct mxs_mmc_host *host = mmc_priv(mmc); 621 unsigned long flags; 622 623 spin_lock_irqsave(&host->lock, flags); 624 625 host->sdio_irq_en = enable; 626 627 if (enable) { 628 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 629 host->base + HW_SSP_CTRL0 + MXS_SET_ADDR); 630 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 631 host->base + HW_SSP_CTRL1 + MXS_SET_ADDR); 632 633 if (readl(host->base + HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ) 634 mmc_signal_sdio_irq(host->mmc); 635 636 } else { 637 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 638 host->base + HW_SSP_CTRL0 + MXS_CLR_ADDR); 639 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 640 host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR); 641 } 642 643 spin_unlock_irqrestore(&host->lock, flags); 644} 645 646static const struct mmc_host_ops mxs_mmc_ops = { 647 .request = mxs_mmc_request, 648 .get_ro = mxs_mmc_get_ro, 649 .get_cd = mxs_mmc_get_cd, 650 .set_ios = mxs_mmc_set_ios, 651 .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 652}; 653 654static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param) 655{ 656 struct mxs_mmc_host *host = param; 657 658 if (!mxs_dma_is_apbh(chan)) 659 return false; 660 661 if (chan->chan_id != host->dma_res->start) 662 return false; 663 664 chan->private = &host->dma_data; 665 666 return true; 667} 668 669static int mxs_mmc_probe(struct platform_device *pdev) 670{ 671 struct mxs_mmc_host *host; 672 struct mmc_host *mmc; 673 struct resource *iores, *dmares, *r; 674 struct mxs_mmc_platform_data *pdata; 675 int ret = 0, irq_err, irq_dma; 676 dma_cap_mask_t mask; 677 678 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 679 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 680 irq_err = platform_get_irq(pdev, 0); 681 irq_dma = platform_get_irq(pdev, 1); 682 if (!iores || !dmares || irq_err < 0 || irq_dma < 0) 683 return -EINVAL; 684 685 r = request_mem_region(iores->start, resource_size(iores), pdev->name); 686 if (!r) 687 return -EBUSY; 688 689 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 690 if (!mmc) { 691 ret = -ENOMEM; 692 goto out_release_mem; 693 } 694 695 host = mmc_priv(mmc); 696 host->base = ioremap(r->start, resource_size(r)); 697 if (!host->base) { 698 ret = -ENOMEM; 699 goto out_mmc_free; 700 } 701 702 /* only major verion does matter */ 703 host->version = readl(host->base + HW_SSP_VERSION) >> 704 BP_SSP_VERSION_MAJOR; 705 706 host->mmc = mmc; 707 host->res = r; 708 host->dma_res = dmares; 709 host->irq = irq_err; 710 host->sdio_irq_en = 0; 711 712 host->clk = clk_get(&pdev->dev, NULL); 713 if (IS_ERR(host->clk)) { 714 ret = PTR_ERR(host->clk); 715 goto out_iounmap; 716 } 717 clk_enable(host->clk); 718 719 mxs_mmc_reset(host); 720 721 dma_cap_zero(mask); 722 dma_cap_set(DMA_SLAVE, mask); 723 host->dma_data.chan_irq = irq_dma; 724 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host); 725 if (!host->dmach) { 726 dev_err(mmc_dev(host->mmc), 727 "%s: failed to request dma\n", __func__); 728 goto out_clk_put; 729 } 730 731 /* set mmc core parameters */ 732 mmc->ops = &mxs_mmc_ops; 733 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 734 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; 735 736 pdata = mmc_dev(host->mmc)->platform_data; 737 if (pdata) { 738 if (pdata->flags & SLOTF_8_BIT_CAPABLE) 739 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 740 if (pdata->flags & SLOTF_4_BIT_CAPABLE) 741 mmc->caps |= MMC_CAP_4_BIT_DATA; 742 } 743 744 mmc->f_min = 400000; 745 mmc->f_max = 288000000; 746 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 747 748 mmc->max_segs = 52; 749 mmc->max_blk_size = 1 << 0xf; 750 mmc->max_blk_count = (ssp_is_old()) ? 0xff : 0xffffff; 751 mmc->max_req_size = (ssp_is_old()) ? 0xffff : 0xffffffff; 752 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev); 753 754 platform_set_drvdata(pdev, mmc); 755 756 ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host); 757 if (ret) 758 goto out_free_dma; 759 760 spin_lock_init(&host->lock); 761 762 ret = mmc_add_host(mmc); 763 if (ret) 764 goto out_free_irq; 765 766 dev_info(mmc_dev(host->mmc), "initialized\n"); 767 768 return 0; 769 770out_free_irq: 771 free_irq(host->irq, host); 772out_free_dma: 773 if (host->dmach) 774 dma_release_channel(host->dmach); 775out_clk_put: 776 clk_disable(host->clk); 777 clk_put(host->clk); 778out_iounmap: 779 iounmap(host->base); 780out_mmc_free: 781 mmc_free_host(mmc); 782out_release_mem: 783 release_mem_region(iores->start, resource_size(iores)); 784 return ret; 785} 786 787static int mxs_mmc_remove(struct platform_device *pdev) 788{ 789 struct mmc_host *mmc = platform_get_drvdata(pdev); 790 struct mxs_mmc_host *host = mmc_priv(mmc); 791 struct resource *res = host->res; 792 793 mmc_remove_host(mmc); 794 795 free_irq(host->irq, host); 796 797 platform_set_drvdata(pdev, NULL); 798 799 if (host->dmach) 800 dma_release_channel(host->dmach); 801 802 clk_disable(host->clk); 803 clk_put(host->clk); 804 805 iounmap(host->base); 806 807 mmc_free_host(mmc); 808 809 release_mem_region(res->start, resource_size(res)); 810 811 return 0; 812} 813 814#ifdef CONFIG_PM 815static int mxs_mmc_suspend(struct device *dev) 816{ 817 struct mmc_host *mmc = dev_get_drvdata(dev); 818 struct mxs_mmc_host *host = mmc_priv(mmc); 819 int ret = 0; 820 821 ret = mmc_suspend_host(mmc); 822 823 clk_disable(host->clk); 824 825 return ret; 826} 827 828static int mxs_mmc_resume(struct device *dev) 829{ 830 struct mmc_host *mmc = dev_get_drvdata(dev); 831 struct mxs_mmc_host *host = mmc_priv(mmc); 832 int ret = 0; 833 834 clk_enable(host->clk); 835 836 ret = mmc_resume_host(mmc); 837 838 return ret; 839} 840 841static const struct dev_pm_ops mxs_mmc_pm_ops = { 842 .suspend = mxs_mmc_suspend, 843 .resume = mxs_mmc_resume, 844}; 845#endif 846 847static struct platform_driver mxs_mmc_driver = { 848 .probe = mxs_mmc_probe, 849 .remove = mxs_mmc_remove, 850 .driver = { 851 .name = DRIVER_NAME, 852 .owner = THIS_MODULE, 853#ifdef CONFIG_PM 854 .pm = &mxs_mmc_pm_ops, 855#endif 856 }, 857}; 858 859static int __init mxs_mmc_init(void) 860{ 861 return platform_driver_register(&mxs_mmc_driver); 862} 863 864static void __exit mxs_mmc_exit(void) 865{ 866 platform_driver_unregister(&mxs_mmc_driver); 867} 868 869module_init(mxs_mmc_init); 870module_exit(mxs_mmc_exit); 871 872MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 873MODULE_AUTHOR("Freescale Semiconductor"); 874MODULE_LICENSE("GPL"); 875