1/* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 * 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 22 */ 23 24#include <linux/module.h> 25#include <linux/kernel.h> 26#include <linux/string.h> 27#include <linux/ptrace.h> 28#include <linux/errno.h> 29#include <linux/ioport.h> 30#include <linux/slab.h> 31#include <linux/interrupt.h> 32#include <linux/pci.h> 33#include <linux/init.h> 34#include <linux/delay.h> 35#include <linux/netdevice.h> 36#include <linux/etherdevice.h> 37#include <linux/skbuff.h> 38#include <linux/spinlock.h> 39#include <linux/workqueue.h> 40#include <linux/bitops.h> 41#include <linux/io.h> 42#include <linux/irq.h> 43#include <linux/clk.h> 44#include <linux/platform_device.h> 45#include <linux/phy.h> 46#include <linux/fec.h> 47#include <linux/of.h> 48#include <linux/of_device.h> 49#include <linux/of_gpio.h> 50#include <linux/of_net.h> 51 52#include <asm/cacheflush.h> 53 54#ifndef CONFIG_ARM 55#include <asm/coldfire.h> 56#include <asm/mcfsim.h> 57#endif 58 59#include "fec.h" 60 61#if defined(CONFIG_ARM) 62#define FEC_ALIGNMENT 0xf 63#else 64#define FEC_ALIGNMENT 0x3 65#endif 66 67#define DRIVER_NAME "fec" 68 69/* Controller is ENET-MAC */ 70#define FEC_QUIRK_ENET_MAC (1 << 0) 71/* Controller needs driver to swap frame */ 72#define FEC_QUIRK_SWAP_FRAME (1 << 1) 73/* Controller uses gasket */ 74#define FEC_QUIRK_USE_GASKET (1 << 2) 75/* Controller has GBIT support */ 76#define FEC_QUIRK_HAS_GBIT (1 << 3) 77 78static struct platform_device_id fec_devtype[] = { 79 { 80 /* keep it for coldfire */ 81 .name = DRIVER_NAME, 82 .driver_data = 0, 83 }, { 84 .name = "imx25-fec", 85 .driver_data = FEC_QUIRK_USE_GASKET, 86 }, { 87 .name = "imx27-fec", 88 .driver_data = 0, 89 }, { 90 .name = "imx28-fec", 91 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, 92 }, { 93 .name = "imx6q-fec", 94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT, 95 }, { 96 /* sentinel */ 97 } 98}; 99MODULE_DEVICE_TABLE(platform, fec_devtype); 100 101enum imx_fec_type { 102 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 103 IMX27_FEC, /* runs on i.mx27/35/51 */ 104 IMX28_FEC, 105 IMX6Q_FEC, 106}; 107 108static const struct of_device_id fec_dt_ids[] = { 109 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 110 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 111 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 112 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 113 { /* sentinel */ } 114}; 115MODULE_DEVICE_TABLE(of, fec_dt_ids); 116 117static unsigned char macaddr[ETH_ALEN]; 118module_param_array(macaddr, byte, NULL, 0); 119MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 120 121#if defined(CONFIG_M5272) 122/* 123 * Some hardware gets it MAC address out of local flash memory. 124 * if this is non-zero then assume it is the address to get MAC from. 125 */ 126#if defined(CONFIG_NETtel) 127#define FEC_FLASHMAC 0xf0006006 128#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 129#define FEC_FLASHMAC 0xf0006000 130#elif defined(CONFIG_CANCam) 131#define FEC_FLASHMAC 0xf0020000 132#elif defined (CONFIG_M5272C3) 133#define FEC_FLASHMAC (0xffe04000 + 4) 134#elif defined(CONFIG_MOD5272) 135#define FEC_FLASHMAC 0xffc0406b 136#else 137#define FEC_FLASHMAC 0 138#endif 139#endif /* CONFIG_M5272 */ 140 141/* The number of Tx and Rx buffers. These are allocated from the page 142 * pool. The code may assume these are power of two, so it it best 143 * to keep them that size. 144 * We don't need to allocate pages for the transmitter. We just use 145 * the skbuffer directly. 146 */ 147#define FEC_ENET_RX_PAGES 8 148#define FEC_ENET_RX_FRSIZE 2048 149#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) 150#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) 151#define FEC_ENET_TX_FRSIZE 2048 152#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) 153#define TX_RING_SIZE 16 /* Must be power of two */ 154#define TX_RING_MOD_MASK 15 /* for this to work */ 155 156#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) 157#error "FEC: descriptor ring size constants too large" 158#endif 159 160/* Interrupt events/masks. */ 161#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 162#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 163#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 164#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 165#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ 166#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 167#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ 168#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 169#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 170#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 171 172#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) 173 174/* The FEC stores dest/src/type, data, and checksum for receive packets. 175 */ 176#define PKT_MAXBUF_SIZE 1518 177#define PKT_MINBUF_SIZE 64 178#define PKT_MAXBLR_SIZE 1520 179 180/* This device has up to three irqs on some platforms */ 181#define FEC_IRQ_NUM 3 182 183/* 184 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 185 * size bits. Other FEC hardware does not, so we need to take that into 186 * account when setting it. 187 */ 188#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 189 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) 190#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 191#else 192#define OPT_FRAME_SIZE 0 193#endif 194 195/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and 196 * tx_bd_base always point to the base of the buffer descriptors. The 197 * cur_rx and cur_tx point to the currently available buffer. 198 * The dirty_tx tracks the current buffer that is being sent by the 199 * controller. The cur_tx and dirty_tx are equal under both completely 200 * empty and completely full conditions. The empty/ready indicator in 201 * the buffer descriptor determines the actual condition. 202 */ 203struct fec_enet_private { 204 /* Hardware registers of the FEC device */ 205 void __iomem *hwp; 206 207 struct net_device *netdev; 208 209 struct clk *clk; 210 211 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 212 unsigned char *tx_bounce[TX_RING_SIZE]; 213 struct sk_buff* tx_skbuff[TX_RING_SIZE]; 214 struct sk_buff* rx_skbuff[RX_RING_SIZE]; 215 ushort skb_cur; 216 ushort skb_dirty; 217 218 /* CPM dual port RAM relative addresses */ 219 dma_addr_t bd_dma; 220 /* Address of Rx and Tx buffers */ 221 struct bufdesc *rx_bd_base; 222 struct bufdesc *tx_bd_base; 223 /* The next free ring entry */ 224 struct bufdesc *cur_rx, *cur_tx; 225 /* The ring entries to be free()ed */ 226 struct bufdesc *dirty_tx; 227 228 uint tx_full; 229 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ 230 spinlock_t hw_lock; 231 232 struct platform_device *pdev; 233 234 int opened; 235 int dev_id; 236 237 /* Phylib and MDIO interface */ 238 struct mii_bus *mii_bus; 239 struct phy_device *phy_dev; 240 int mii_timeout; 241 uint phy_speed; 242 phy_interface_t phy_interface; 243 int link; 244 int full_duplex; 245 struct completion mdio_done; 246 int irq[FEC_IRQ_NUM]; 247}; 248 249/* FEC MII MMFR bits definition */ 250#define FEC_MMFR_ST (1 << 30) 251#define FEC_MMFR_OP_READ (2 << 28) 252#define FEC_MMFR_OP_WRITE (1 << 28) 253#define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 254#define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 255#define FEC_MMFR_TA (2 << 16) 256#define FEC_MMFR_DATA(v) (v & 0xffff) 257 258#define FEC_MII_TIMEOUT 30000 /* us */ 259 260/* Transmitter timeout */ 261#define TX_TIMEOUT (2 * HZ) 262 263static int mii_cnt; 264 265static void *swap_buffer(void *bufaddr, int len) 266{ 267 int i; 268 unsigned int *buf = bufaddr; 269 270 for (i = 0; i < (len + 3) / 4; i++, buf++) 271 *buf = cpu_to_be32(*buf); 272 273 return bufaddr; 274} 275 276static netdev_tx_t 277fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 278{ 279 struct fec_enet_private *fep = netdev_priv(ndev); 280 const struct platform_device_id *id_entry = 281 platform_get_device_id(fep->pdev); 282 struct bufdesc *bdp; 283 void *bufaddr; 284 unsigned short status; 285 unsigned long flags; 286 287 if (!fep->link) { 288 /* Link is down or autonegotiation is in progress. */ 289 return NETDEV_TX_BUSY; 290 } 291 292 spin_lock_irqsave(&fep->hw_lock, flags); 293 /* Fill in a Tx ring entry */ 294 bdp = fep->cur_tx; 295 296 status = bdp->cbd_sc; 297 298 if (status & BD_ENET_TX_READY) { 299 /* Ooops. All transmit buffers are full. Bail out. 300 * This should not happen, since ndev->tbusy should be set. 301 */ 302 printk("%s: tx queue full!.\n", ndev->name); 303 spin_unlock_irqrestore(&fep->hw_lock, flags); 304 return NETDEV_TX_BUSY; 305 } 306 307 /* Clear all of the status flags */ 308 status &= ~BD_ENET_TX_STATS; 309 310 /* Set buffer length and buffer pointer */ 311 bufaddr = skb->data; 312 bdp->cbd_datlen = skb->len; 313 314 /* 315 * On some FEC implementations data must be aligned on 316 * 4-byte boundaries. Use bounce buffers to copy data 317 * and get it aligned. Ugh. 318 */ 319 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { 320 unsigned int index; 321 index = bdp - fep->tx_bd_base; 322 memcpy(fep->tx_bounce[index], skb->data, skb->len); 323 bufaddr = fep->tx_bounce[index]; 324 } 325 326 /* 327 * Some design made an incorrect assumption on endian mode of 328 * the system that it's running on. As the result, driver has to 329 * swap every frame going to and coming from the controller. 330 */ 331 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 332 swap_buffer(bufaddr, skb->len); 333 334 /* Save skb pointer */ 335 fep->tx_skbuff[fep->skb_cur] = skb; 336 337 ndev->stats.tx_bytes += skb->len; 338 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; 339 340 /* Push the data cache so the CPM does not get stale memory 341 * data. 342 */ 343 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, 344 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 345 346 /* Send it on its way. Tell FEC it's ready, interrupt when done, 347 * it's the last BD of the frame, and to put the CRC on the end. 348 */ 349 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR 350 | BD_ENET_TX_LAST | BD_ENET_TX_TC); 351 bdp->cbd_sc = status; 352 353 /* Trigger transmission start */ 354 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 355 356 /* If this was the last BD in the ring, start at the beginning again. */ 357 if (status & BD_ENET_TX_WRAP) 358 bdp = fep->tx_bd_base; 359 else 360 bdp++; 361 362 if (bdp == fep->dirty_tx) { 363 fep->tx_full = 1; 364 netif_stop_queue(ndev); 365 } 366 367 fep->cur_tx = bdp; 368 369 skb_tx_timestamp(skb); 370 371 spin_unlock_irqrestore(&fep->hw_lock, flags); 372 373 return NETDEV_TX_OK; 374} 375 376/* This function is called to start or restart the FEC during a link 377 * change. This only happens when switching between half and full 378 * duplex. 379 */ 380static void 381fec_restart(struct net_device *ndev, int duplex) 382{ 383 struct fec_enet_private *fep = netdev_priv(ndev); 384 const struct platform_device_id *id_entry = 385 platform_get_device_id(fep->pdev); 386 int i; 387 u32 temp_mac[2]; 388 u32 rcntl = OPT_FRAME_SIZE | 0x04; 389 u32 ecntl = 0x2; /* ETHEREN */ 390 391 /* Whack a reset. We should wait for this. */ 392 writel(1, fep->hwp + FEC_ECNTRL); 393 udelay(10); 394 395 /* 396 * enet-mac reset will reset mac address registers too, 397 * so need to reconfigure it. 398 */ 399 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 400 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 401 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); 402 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); 403 } 404 405 /* Clear any outstanding interrupt. */ 406 writel(0xffc00000, fep->hwp + FEC_IEVENT); 407 408 /* Reset all multicast. */ 409 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 410 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 411#ifndef CONFIG_M5272 412 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 413 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 414#endif 415 416 /* Set maximum receive buffer size. */ 417 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 418 419 /* Set receive and transmit descriptor base. */ 420 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); 421 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, 422 fep->hwp + FEC_X_DES_START); 423 424 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; 425 fep->cur_rx = fep->rx_bd_base; 426 427 /* Reset SKB transmit buffers. */ 428 fep->skb_cur = fep->skb_dirty = 0; 429 for (i = 0; i <= TX_RING_MOD_MASK; i++) { 430 if (fep->tx_skbuff[i]) { 431 dev_kfree_skb_any(fep->tx_skbuff[i]); 432 fep->tx_skbuff[i] = NULL; 433 } 434 } 435 436 /* Enable MII mode */ 437 if (duplex) { 438 /* FD enable */ 439 writel(0x04, fep->hwp + FEC_X_CNTRL); 440 } else { 441 /* No Rcv on Xmit */ 442 rcntl |= 0x02; 443 writel(0x0, fep->hwp + FEC_X_CNTRL); 444 } 445 446 fep->full_duplex = duplex; 447 448 /* Set MII speed */ 449 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 450 451 /* 452 * The phy interface and speed need to get configured 453 * differently on enet-mac. 454 */ 455 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 456 /* Enable flow control and length check */ 457 rcntl |= 0x40000000 | 0x00000020; 458 459 /* RGMII, RMII or MII */ 460 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) 461 rcntl |= (1 << 6); 462 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 463 rcntl |= (1 << 8); 464 else 465 rcntl &= ~(1 << 8); 466 467 /* 1G, 100M or 10M */ 468 if (fep->phy_dev) { 469 if (fep->phy_dev->speed == SPEED_1000) 470 ecntl |= (1 << 5); 471 else if (fep->phy_dev->speed == SPEED_100) 472 rcntl &= ~(1 << 9); 473 else 474 rcntl |= (1 << 9); 475 } 476 } else { 477#ifdef FEC_MIIGSK_ENR 478 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { 479 u32 cfgr; 480 /* disable the gasket and wait */ 481 writel(0, fep->hwp + FEC_MIIGSK_ENR); 482 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 483 udelay(1); 484 485 /* 486 * configure the gasket: 487 * RMII, 50 MHz, no loopback, no echo 488 * MII, 25 MHz, no loopback, no echo 489 */ 490 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 491 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 492 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) 493 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 494 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 495 496 /* re-enable the gasket */ 497 writel(2, fep->hwp + FEC_MIIGSK_ENR); 498 } 499#endif 500 } 501 writel(rcntl, fep->hwp + FEC_R_CNTRL); 502 503 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 504 /* enable ENET endian swap */ 505 ecntl |= (1 << 8); 506 /* enable ENET store and forward mode */ 507 writel(1 << 8, fep->hwp + FEC_X_WMRK); 508 } 509 510 /* And last, enable the transmit and receive processing */ 511 writel(ecntl, fep->hwp + FEC_ECNTRL); 512 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 513 514 /* Enable interrupts we wish to service */ 515 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 516} 517 518static void 519fec_stop(struct net_device *ndev) 520{ 521 struct fec_enet_private *fep = netdev_priv(ndev); 522 const struct platform_device_id *id_entry = 523 platform_get_device_id(fep->pdev); 524 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 525 526 /* We cannot expect a graceful transmit stop without link !!! */ 527 if (fep->link) { 528 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 529 udelay(10); 530 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 531 printk("fec_stop : Graceful transmit stop did not complete !\n"); 532 } 533 534 /* Whack a reset. We should wait for this. */ 535 writel(1, fep->hwp + FEC_ECNTRL); 536 udelay(10); 537 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 538 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 539 540 /* We have to keep ENET enabled to have MII interrupt stay working */ 541 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { 542 writel(2, fep->hwp + FEC_ECNTRL); 543 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 544 } 545} 546 547 548static void 549fec_timeout(struct net_device *ndev) 550{ 551 struct fec_enet_private *fep = netdev_priv(ndev); 552 553 ndev->stats.tx_errors++; 554 555 fec_restart(ndev, fep->full_duplex); 556 netif_wake_queue(ndev); 557} 558 559static void 560fec_enet_tx(struct net_device *ndev) 561{ 562 struct fec_enet_private *fep; 563 struct bufdesc *bdp; 564 unsigned short status; 565 struct sk_buff *skb; 566 567 fep = netdev_priv(ndev); 568 spin_lock(&fep->hw_lock); 569 bdp = fep->dirty_tx; 570 571 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 572 if (bdp == fep->cur_tx && fep->tx_full == 0) 573 break; 574 575 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 576 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 577 bdp->cbd_bufaddr = 0; 578 579 skb = fep->tx_skbuff[fep->skb_dirty]; 580 /* Check for errors. */ 581 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 582 BD_ENET_TX_RL | BD_ENET_TX_UN | 583 BD_ENET_TX_CSL)) { 584 ndev->stats.tx_errors++; 585 if (status & BD_ENET_TX_HB) /* No heartbeat */ 586 ndev->stats.tx_heartbeat_errors++; 587 if (status & BD_ENET_TX_LC) /* Late collision */ 588 ndev->stats.tx_window_errors++; 589 if (status & BD_ENET_TX_RL) /* Retrans limit */ 590 ndev->stats.tx_aborted_errors++; 591 if (status & BD_ENET_TX_UN) /* Underrun */ 592 ndev->stats.tx_fifo_errors++; 593 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 594 ndev->stats.tx_carrier_errors++; 595 } else { 596 ndev->stats.tx_packets++; 597 } 598 599 if (status & BD_ENET_TX_READY) 600 printk("HEY! Enet xmit interrupt and TX_READY.\n"); 601 602 /* Deferred means some collisions occurred during transmit, 603 * but we eventually sent the packet OK. 604 */ 605 if (status & BD_ENET_TX_DEF) 606 ndev->stats.collisions++; 607 608 /* Free the sk buffer associated with this last transmit */ 609 dev_kfree_skb_any(skb); 610 fep->tx_skbuff[fep->skb_dirty] = NULL; 611 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; 612 613 /* Update pointer to next buffer descriptor to be transmitted */ 614 if (status & BD_ENET_TX_WRAP) 615 bdp = fep->tx_bd_base; 616 else 617 bdp++; 618 619 /* Since we have freed up a buffer, the ring is no longer full 620 */ 621 if (fep->tx_full) { 622 fep->tx_full = 0; 623 if (netif_queue_stopped(ndev)) 624 netif_wake_queue(ndev); 625 } 626 } 627 fep->dirty_tx = bdp; 628 spin_unlock(&fep->hw_lock); 629} 630 631 632/* During a receive, the cur_rx points to the current incoming buffer. 633 * When we update through the ring, if the next incoming buffer has 634 * not been given to the system, we just set the empty indicator, 635 * effectively tossing the packet. 636 */ 637static void 638fec_enet_rx(struct net_device *ndev) 639{ 640 struct fec_enet_private *fep = netdev_priv(ndev); 641 const struct platform_device_id *id_entry = 642 platform_get_device_id(fep->pdev); 643 struct bufdesc *bdp; 644 unsigned short status; 645 struct sk_buff *skb; 646 ushort pkt_len; 647 __u8 *data; 648 649#ifdef CONFIG_M532x 650 flush_cache_all(); 651#endif 652 653 spin_lock(&fep->hw_lock); 654 655 /* First, grab all of the stats for the incoming packet. 656 * These get messed up if we get called due to a busy condition. 657 */ 658 bdp = fep->cur_rx; 659 660 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 661 662 /* Since we have allocated space to hold a complete frame, 663 * the last indicator should be set. 664 */ 665 if ((status & BD_ENET_RX_LAST) == 0) 666 printk("FEC ENET: rcv is not +last\n"); 667 668 if (!fep->opened) 669 goto rx_processing_done; 670 671 /* Check for errors. */ 672 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 673 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 674 ndev->stats.rx_errors++; 675 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 676 /* Frame too long or too short. */ 677 ndev->stats.rx_length_errors++; 678 } 679 if (status & BD_ENET_RX_NO) /* Frame alignment */ 680 ndev->stats.rx_frame_errors++; 681 if (status & BD_ENET_RX_CR) /* CRC Error */ 682 ndev->stats.rx_crc_errors++; 683 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 684 ndev->stats.rx_fifo_errors++; 685 } 686 687 /* Report late collisions as a frame error. 688 * On this error, the BD is closed, but we don't know what we 689 * have in the buffer. So, just drop this frame on the floor. 690 */ 691 if (status & BD_ENET_RX_CL) { 692 ndev->stats.rx_errors++; 693 ndev->stats.rx_frame_errors++; 694 goto rx_processing_done; 695 } 696 697 /* Process the incoming frame. */ 698 ndev->stats.rx_packets++; 699 pkt_len = bdp->cbd_datlen; 700 ndev->stats.rx_bytes += pkt_len; 701 data = (__u8*)__va(bdp->cbd_bufaddr); 702 703 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 704 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); 705 706 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) 707 swap_buffer(data, pkt_len); 708 709 /* This does 16 byte alignment, exactly what we need. 710 * The packet length includes FCS, but we don't want to 711 * include that when passing upstream as it messes up 712 * bridging applications. 713 */ 714 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); 715 716 if (unlikely(!skb)) { 717 printk("%s: Memory squeeze, dropping packet.\n", 718 ndev->name); 719 ndev->stats.rx_dropped++; 720 } else { 721 skb_reserve(skb, NET_IP_ALIGN); 722 skb_put(skb, pkt_len - 4); /* Make room */ 723 skb_copy_to_linear_data(skb, data, pkt_len - 4); 724 skb->protocol = eth_type_trans(skb, ndev); 725 if (!skb_defer_rx_timestamp(skb)) 726 netif_rx(skb); 727 } 728 729 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, 730 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); 731rx_processing_done: 732 /* Clear the status flags for this buffer */ 733 status &= ~BD_ENET_RX_STATS; 734 735 /* Mark the buffer empty */ 736 status |= BD_ENET_RX_EMPTY; 737 bdp->cbd_sc = status; 738 739 /* Update BD pointer to next entry */ 740 if (status & BD_ENET_RX_WRAP) 741 bdp = fep->rx_bd_base; 742 else 743 bdp++; 744 /* Doing this here will keep the FEC running while we process 745 * incoming frames. On a heavily loaded network, we should be 746 * able to keep up at the expense of system resources. 747 */ 748 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 749 } 750 fep->cur_rx = bdp; 751 752 spin_unlock(&fep->hw_lock); 753} 754 755static irqreturn_t 756fec_enet_interrupt(int irq, void *dev_id) 757{ 758 struct net_device *ndev = dev_id; 759 struct fec_enet_private *fep = netdev_priv(ndev); 760 uint int_events; 761 irqreturn_t ret = IRQ_NONE; 762 763 do { 764 int_events = readl(fep->hwp + FEC_IEVENT); 765 writel(int_events, fep->hwp + FEC_IEVENT); 766 767 if (int_events & FEC_ENET_RXF) { 768 ret = IRQ_HANDLED; 769 fec_enet_rx(ndev); 770 } 771 772 /* Transmit OK, or non-fatal error. Update the buffer 773 * descriptors. FEC handles all errors, we just discover 774 * them as part of the transmit process. 775 */ 776 if (int_events & FEC_ENET_TXF) { 777 ret = IRQ_HANDLED; 778 fec_enet_tx(ndev); 779 } 780 781 if (int_events & FEC_ENET_MII) { 782 ret = IRQ_HANDLED; 783 complete(&fep->mdio_done); 784 } 785 } while (int_events); 786 787 return ret; 788} 789 790 791 792/* ------------------------------------------------------------------------- */ 793static void __inline__ fec_get_mac(struct net_device *ndev) 794{ 795 struct fec_enet_private *fep = netdev_priv(ndev); 796 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 797 unsigned char *iap, tmpaddr[ETH_ALEN]; 798 799 /* 800 * try to get mac address in following order: 801 * 802 * 1) module parameter via kernel command line in form 803 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 804 */ 805 iap = macaddr; 806 807#ifdef CONFIG_OF 808 /* 809 * 2) from device tree data 810 */ 811 if (!is_valid_ether_addr(iap)) { 812 struct device_node *np = fep->pdev->dev.of_node; 813 if (np) { 814 const char *mac = of_get_mac_address(np); 815 if (mac) 816 iap = (unsigned char *) mac; 817 } 818 } 819#endif 820 821 /* 822 * 3) from flash or fuse (via platform data) 823 */ 824 if (!is_valid_ether_addr(iap)) { 825#ifdef CONFIG_M5272 826 if (FEC_FLASHMAC) 827 iap = (unsigned char *)FEC_FLASHMAC; 828#else 829 if (pdata) 830 iap = (unsigned char *)&pdata->mac; 831#endif 832 } 833 834 /* 835 * 4) FEC mac registers set by bootloader 836 */ 837 if (!is_valid_ether_addr(iap)) { 838 *((unsigned long *) &tmpaddr[0]) = 839 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); 840 *((unsigned short *) &tmpaddr[4]) = 841 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 842 iap = &tmpaddr[0]; 843 } 844 845 memcpy(ndev->dev_addr, iap, ETH_ALEN); 846 847 /* Adjust MAC if using macaddr */ 848 if (iap == macaddr) 849 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 850} 851 852/* ------------------------------------------------------------------------- */ 853 854/* 855 * Phy section 856 */ 857static void fec_enet_adjust_link(struct net_device *ndev) 858{ 859 struct fec_enet_private *fep = netdev_priv(ndev); 860 struct phy_device *phy_dev = fep->phy_dev; 861 unsigned long flags; 862 863 int status_change = 0; 864 865 spin_lock_irqsave(&fep->hw_lock, flags); 866 867 /* Prevent a state halted on mii error */ 868 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 869 phy_dev->state = PHY_RESUMING; 870 goto spin_unlock; 871 } 872 873 /* Duplex link change */ 874 if (phy_dev->link) { 875 if (fep->full_duplex != phy_dev->duplex) { 876 fec_restart(ndev, phy_dev->duplex); 877 /* prevent unnecessary second fec_restart() below */ 878 fep->link = phy_dev->link; 879 status_change = 1; 880 } 881 } 882 883 /* Link on or off change */ 884 if (phy_dev->link != fep->link) { 885 fep->link = phy_dev->link; 886 if (phy_dev->link) 887 fec_restart(ndev, phy_dev->duplex); 888 else 889 fec_stop(ndev); 890 status_change = 1; 891 } 892 893spin_unlock: 894 spin_unlock_irqrestore(&fep->hw_lock, flags); 895 896 if (status_change) 897 phy_print_status(phy_dev); 898} 899 900static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 901{ 902 struct fec_enet_private *fep = bus->priv; 903 unsigned long time_left; 904 905 fep->mii_timeout = 0; 906 init_completion(&fep->mdio_done); 907 908 /* start a read op */ 909 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 910 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 911 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 912 913 /* wait for end of transfer */ 914 time_left = wait_for_completion_timeout(&fep->mdio_done, 915 usecs_to_jiffies(FEC_MII_TIMEOUT)); 916 if (time_left == 0) { 917 fep->mii_timeout = 1; 918 printk(KERN_ERR "FEC: MDIO read timeout\n"); 919 return -ETIMEDOUT; 920 } 921 922 /* return value */ 923 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 924} 925 926static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 927 u16 value) 928{ 929 struct fec_enet_private *fep = bus->priv; 930 unsigned long time_left; 931 932 fep->mii_timeout = 0; 933 init_completion(&fep->mdio_done); 934 935 /* start a write op */ 936 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 937 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 938 FEC_MMFR_TA | FEC_MMFR_DATA(value), 939 fep->hwp + FEC_MII_DATA); 940 941 /* wait for end of transfer */ 942 time_left = wait_for_completion_timeout(&fep->mdio_done, 943 usecs_to_jiffies(FEC_MII_TIMEOUT)); 944 if (time_left == 0) { 945 fep->mii_timeout = 1; 946 printk(KERN_ERR "FEC: MDIO write timeout\n"); 947 return -ETIMEDOUT; 948 } 949 950 return 0; 951} 952 953static int fec_enet_mdio_reset(struct mii_bus *bus) 954{ 955 return 0; 956} 957 958static int fec_enet_mii_probe(struct net_device *ndev) 959{ 960 struct fec_enet_private *fep = netdev_priv(ndev); 961 const struct platform_device_id *id_entry = 962 platform_get_device_id(fep->pdev); 963 struct phy_device *phy_dev = NULL; 964 char mdio_bus_id[MII_BUS_ID_SIZE]; 965 char phy_name[MII_BUS_ID_SIZE + 3]; 966 int phy_id; 967 int dev_id = fep->dev_id; 968 969 fep->phy_dev = NULL; 970 971 /* check for attached phy */ 972 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 973 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 974 continue; 975 if (fep->mii_bus->phy_map[phy_id] == NULL) 976 continue; 977 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 978 continue; 979 if (dev_id--) 980 continue; 981 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 982 break; 983 } 984 985 if (phy_id >= PHY_MAX_ADDR) { 986 printk(KERN_INFO 987 "%s: no PHY, assuming direct connection to switch\n", 988 ndev->name); 989 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 990 phy_id = 0; 991 } 992 993 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); 994 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0, 995 fep->phy_interface); 996 if (IS_ERR(phy_dev)) { 997 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name); 998 return PTR_ERR(phy_dev); 999 } 1000 1001 /* mask with MAC supported features */ 1002 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) 1003 phy_dev->supported &= PHY_GBIT_FEATURES; 1004 else 1005 phy_dev->supported &= PHY_BASIC_FEATURES; 1006 1007 phy_dev->advertising = phy_dev->supported; 1008 1009 fep->phy_dev = phy_dev; 1010 fep->link = 0; 1011 fep->full_duplex = 0; 1012 1013 printk(KERN_INFO 1014 "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1015 ndev->name, 1016 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 1017 fep->phy_dev->irq); 1018 1019 return 0; 1020} 1021 1022static int fec_enet_mii_init(struct platform_device *pdev) 1023{ 1024 static struct mii_bus *fec0_mii_bus; 1025 struct net_device *ndev = platform_get_drvdata(pdev); 1026 struct fec_enet_private *fep = netdev_priv(ndev); 1027 const struct platform_device_id *id_entry = 1028 platform_get_device_id(fep->pdev); 1029 int err = -ENXIO, i; 1030 1031 /* 1032 * The dual fec interfaces are not equivalent with enet-mac. 1033 * Here are the differences: 1034 * 1035 * - fec0 supports MII & RMII modes while fec1 only supports RMII 1036 * - fec0 acts as the 1588 time master while fec1 is slave 1037 * - external phys can only be configured by fec0 1038 * 1039 * That is to say fec1 can not work independently. It only works 1040 * when fec0 is working. The reason behind this design is that the 1041 * second interface is added primarily for Switch mode. 1042 * 1043 * Because of the last point above, both phys are attached on fec0 1044 * mdio interface in board design, and need to be configured by 1045 * fec0 mii_bus. 1046 */ 1047 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { 1048 /* fec1 uses fec0 mii_bus */ 1049 if (mii_cnt && fec0_mii_bus) { 1050 fep->mii_bus = fec0_mii_bus; 1051 mii_cnt++; 1052 return 0; 1053 } 1054 return -ENOENT; 1055 } 1056 1057 fep->mii_timeout = 0; 1058 1059 /* 1060 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 1061 * 1062 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 1063 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 1064 * Reference Manual has an error on this, and gets fixed on i.MX6Q 1065 * document. 1066 */ 1067 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000); 1068 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1069 fep->phy_speed--; 1070 fep->phy_speed <<= 1; 1071 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1072 1073 fep->mii_bus = mdiobus_alloc(); 1074 if (fep->mii_bus == NULL) { 1075 err = -ENOMEM; 1076 goto err_out; 1077 } 1078 1079 fep->mii_bus->name = "fec_enet_mii_bus"; 1080 fep->mii_bus->read = fec_enet_mdio_read; 1081 fep->mii_bus->write = fec_enet_mdio_write; 1082 fep->mii_bus->reset = fec_enet_mdio_reset; 1083 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1084 pdev->name, fep->dev_id + 1); 1085 fep->mii_bus->priv = fep; 1086 fep->mii_bus->parent = &pdev->dev; 1087 1088 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 1089 if (!fep->mii_bus->irq) { 1090 err = -ENOMEM; 1091 goto err_out_free_mdiobus; 1092 } 1093 1094 for (i = 0; i < PHY_MAX_ADDR; i++) 1095 fep->mii_bus->irq[i] = PHY_POLL; 1096 1097 if (mdiobus_register(fep->mii_bus)) 1098 goto err_out_free_mdio_irq; 1099 1100 mii_cnt++; 1101 1102 /* save fec0 mii_bus */ 1103 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) 1104 fec0_mii_bus = fep->mii_bus; 1105 1106 return 0; 1107 1108err_out_free_mdio_irq: 1109 kfree(fep->mii_bus->irq); 1110err_out_free_mdiobus: 1111 mdiobus_free(fep->mii_bus); 1112err_out: 1113 return err; 1114} 1115 1116static void fec_enet_mii_remove(struct fec_enet_private *fep) 1117{ 1118 if (--mii_cnt == 0) { 1119 mdiobus_unregister(fep->mii_bus); 1120 kfree(fep->mii_bus->irq); 1121 mdiobus_free(fep->mii_bus); 1122 } 1123} 1124 1125static int fec_enet_get_settings(struct net_device *ndev, 1126 struct ethtool_cmd *cmd) 1127{ 1128 struct fec_enet_private *fep = netdev_priv(ndev); 1129 struct phy_device *phydev = fep->phy_dev; 1130 1131 if (!phydev) 1132 return -ENODEV; 1133 1134 return phy_ethtool_gset(phydev, cmd); 1135} 1136 1137static int fec_enet_set_settings(struct net_device *ndev, 1138 struct ethtool_cmd *cmd) 1139{ 1140 struct fec_enet_private *fep = netdev_priv(ndev); 1141 struct phy_device *phydev = fep->phy_dev; 1142 1143 if (!phydev) 1144 return -ENODEV; 1145 1146 return phy_ethtool_sset(phydev, cmd); 1147} 1148 1149static void fec_enet_get_drvinfo(struct net_device *ndev, 1150 struct ethtool_drvinfo *info) 1151{ 1152 struct fec_enet_private *fep = netdev_priv(ndev); 1153 1154 strcpy(info->driver, fep->pdev->dev.driver->name); 1155 strcpy(info->version, "Revision: 1.0"); 1156 strcpy(info->bus_info, dev_name(&ndev->dev)); 1157} 1158 1159static const struct ethtool_ops fec_enet_ethtool_ops = { 1160 .get_settings = fec_enet_get_settings, 1161 .set_settings = fec_enet_set_settings, 1162 .get_drvinfo = fec_enet_get_drvinfo, 1163 .get_link = ethtool_op_get_link, 1164}; 1165 1166static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 1167{ 1168 struct fec_enet_private *fep = netdev_priv(ndev); 1169 struct phy_device *phydev = fep->phy_dev; 1170 1171 if (!netif_running(ndev)) 1172 return -EINVAL; 1173 1174 if (!phydev) 1175 return -ENODEV; 1176 1177 return phy_mii_ioctl(phydev, rq, cmd); 1178} 1179 1180static void fec_enet_free_buffers(struct net_device *ndev) 1181{ 1182 struct fec_enet_private *fep = netdev_priv(ndev); 1183 int i; 1184 struct sk_buff *skb; 1185 struct bufdesc *bdp; 1186 1187 bdp = fep->rx_bd_base; 1188 for (i = 0; i < RX_RING_SIZE; i++) { 1189 skb = fep->rx_skbuff[i]; 1190 1191 if (bdp->cbd_bufaddr) 1192 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, 1193 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1194 if (skb) 1195 dev_kfree_skb(skb); 1196 bdp++; 1197 } 1198 1199 bdp = fep->tx_bd_base; 1200 for (i = 0; i < TX_RING_SIZE; i++) 1201 kfree(fep->tx_bounce[i]); 1202} 1203 1204static int fec_enet_alloc_buffers(struct net_device *ndev) 1205{ 1206 struct fec_enet_private *fep = netdev_priv(ndev); 1207 int i; 1208 struct sk_buff *skb; 1209 struct bufdesc *bdp; 1210 1211 bdp = fep->rx_bd_base; 1212 for (i = 0; i < RX_RING_SIZE; i++) { 1213 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1214 if (!skb) { 1215 fec_enet_free_buffers(ndev); 1216 return -ENOMEM; 1217 } 1218 fep->rx_skbuff[i] = skb; 1219 1220 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, 1221 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 1222 bdp->cbd_sc = BD_ENET_RX_EMPTY; 1223 bdp++; 1224 } 1225 1226 /* Set the last buffer to wrap. */ 1227 bdp--; 1228 bdp->cbd_sc |= BD_SC_WRAP; 1229 1230 bdp = fep->tx_bd_base; 1231 for (i = 0; i < TX_RING_SIZE; i++) { 1232 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 1233 1234 bdp->cbd_sc = 0; 1235 bdp->cbd_bufaddr = 0; 1236 bdp++; 1237 } 1238 1239 /* Set the last buffer to wrap. */ 1240 bdp--; 1241 bdp->cbd_sc |= BD_SC_WRAP; 1242 1243 return 0; 1244} 1245 1246static int 1247fec_enet_open(struct net_device *ndev) 1248{ 1249 struct fec_enet_private *fep = netdev_priv(ndev); 1250 int ret; 1251 1252 /* I should reset the ring buffers here, but I don't yet know 1253 * a simple way to do that. 1254 */ 1255 1256 ret = fec_enet_alloc_buffers(ndev); 1257 if (ret) 1258 return ret; 1259 1260 /* Probe and connect to PHY when open the interface */ 1261 ret = fec_enet_mii_probe(ndev); 1262 if (ret) { 1263 fec_enet_free_buffers(ndev); 1264 return ret; 1265 } 1266 phy_start(fep->phy_dev); 1267 netif_start_queue(ndev); 1268 fep->opened = 1; 1269 return 0; 1270} 1271 1272static int 1273fec_enet_close(struct net_device *ndev) 1274{ 1275 struct fec_enet_private *fep = netdev_priv(ndev); 1276 1277 /* Don't know what to do yet. */ 1278 fep->opened = 0; 1279 netif_stop_queue(ndev); 1280 fec_stop(ndev); 1281 1282 if (fep->phy_dev) { 1283 phy_stop(fep->phy_dev); 1284 phy_disconnect(fep->phy_dev); 1285 } 1286 1287 fec_enet_free_buffers(ndev); 1288 1289 return 0; 1290} 1291 1292/* Set or clear the multicast filter for this adaptor. 1293 * Skeleton taken from sunlance driver. 1294 * The CPM Ethernet implementation allows Multicast as well as individual 1295 * MAC address filtering. Some of the drivers check to make sure it is 1296 * a group multicast address, and discard those that are not. I guess I 1297 * will do the same for now, but just remove the test if you want 1298 * individual filtering as well (do the upper net layers want or support 1299 * this kind of feature?). 1300 */ 1301 1302#define HASH_BITS 6 /* #bits in hash */ 1303#define CRC32_POLY 0xEDB88320 1304 1305static void set_multicast_list(struct net_device *ndev) 1306{ 1307 struct fec_enet_private *fep = netdev_priv(ndev); 1308 struct netdev_hw_addr *ha; 1309 unsigned int i, bit, data, crc, tmp; 1310 unsigned char hash; 1311 1312 if (ndev->flags & IFF_PROMISC) { 1313 tmp = readl(fep->hwp + FEC_R_CNTRL); 1314 tmp |= 0x8; 1315 writel(tmp, fep->hwp + FEC_R_CNTRL); 1316 return; 1317 } 1318 1319 tmp = readl(fep->hwp + FEC_R_CNTRL); 1320 tmp &= ~0x8; 1321 writel(tmp, fep->hwp + FEC_R_CNTRL); 1322 1323 if (ndev->flags & IFF_ALLMULTI) { 1324 /* Catch all multicast addresses, so set the 1325 * filter to all 1's 1326 */ 1327 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1328 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1329 1330 return; 1331 } 1332 1333 /* Clear filter and add the addresses in hash register 1334 */ 1335 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1336 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1337 1338 netdev_for_each_mc_addr(ha, ndev) { 1339 /* calculate crc32 value of mac address */ 1340 crc = 0xffffffff; 1341 1342 for (i = 0; i < ndev->addr_len; i++) { 1343 data = ha->addr[i]; 1344 for (bit = 0; bit < 8; bit++, data >>= 1) { 1345 crc = (crc >> 1) ^ 1346 (((crc ^ data) & 1) ? CRC32_POLY : 0); 1347 } 1348 } 1349 1350 /* only upper 6 bits (HASH_BITS) are used 1351 * which point to specific bit in he hash registers 1352 */ 1353 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 1354 1355 if (hash > 31) { 1356 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1357 tmp |= 1 << (hash - 32); 1358 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1359 } else { 1360 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1361 tmp |= 1 << hash; 1362 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1363 } 1364 } 1365} 1366 1367/* Set a MAC change in hardware. */ 1368static int 1369fec_set_mac_address(struct net_device *ndev, void *p) 1370{ 1371 struct fec_enet_private *fep = netdev_priv(ndev); 1372 struct sockaddr *addr = p; 1373 1374 if (!is_valid_ether_addr(addr->sa_data)) 1375 return -EADDRNOTAVAIL; 1376 1377 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 1378 1379 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 1380 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 1381 fep->hwp + FEC_ADDR_LOW); 1382 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 1383 fep->hwp + FEC_ADDR_HIGH); 1384 return 0; 1385} 1386 1387#ifdef CONFIG_NET_POLL_CONTROLLER 1388/* 1389 * fec_poll_controller: FEC Poll controller function 1390 * @dev: The FEC network adapter 1391 * 1392 * Polled functionality used by netconsole and others in non interrupt mode 1393 * 1394 */ 1395void fec_poll_controller(struct net_device *dev) 1396{ 1397 int i; 1398 struct fec_enet_private *fep = netdev_priv(dev); 1399 1400 for (i = 0; i < FEC_IRQ_NUM; i++) { 1401 if (fep->irq[i] > 0) { 1402 disable_irq(fep->irq[i]); 1403 fec_enet_interrupt(fep->irq[i], dev); 1404 enable_irq(fep->irq[i]); 1405 } 1406 } 1407} 1408#endif 1409 1410static const struct net_device_ops fec_netdev_ops = { 1411 .ndo_open = fec_enet_open, 1412 .ndo_stop = fec_enet_close, 1413 .ndo_start_xmit = fec_enet_start_xmit, 1414 .ndo_set_rx_mode = set_multicast_list, 1415 .ndo_change_mtu = eth_change_mtu, 1416 .ndo_validate_addr = eth_validate_addr, 1417 .ndo_tx_timeout = fec_timeout, 1418 .ndo_set_mac_address = fec_set_mac_address, 1419 .ndo_do_ioctl = fec_enet_ioctl, 1420#ifdef CONFIG_NET_POLL_CONTROLLER 1421 .ndo_poll_controller = fec_poll_controller, 1422#endif 1423}; 1424 1425 /* 1426 * XXX: We need to clean up on failure exits here. 1427 * 1428 */ 1429static int fec_enet_init(struct net_device *ndev) 1430{ 1431 struct fec_enet_private *fep = netdev_priv(ndev); 1432 struct bufdesc *cbd_base; 1433 struct bufdesc *bdp; 1434 int i; 1435 1436 /* Allocate memory for buffer descriptors. */ 1437 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, 1438 GFP_KERNEL); 1439 if (!cbd_base) { 1440 printk("FEC: allocate descriptor memory failed?\n"); 1441 return -ENOMEM; 1442 } 1443 1444 spin_lock_init(&fep->hw_lock); 1445 1446 fep->netdev = ndev; 1447 1448 /* Get the Ethernet address */ 1449 fec_get_mac(ndev); 1450 1451 /* Set receive and transmit descriptor base. */ 1452 fep->rx_bd_base = cbd_base; 1453 fep->tx_bd_base = cbd_base + RX_RING_SIZE; 1454 1455 /* The FEC Ethernet specific entries in the device structure */ 1456 ndev->watchdog_timeo = TX_TIMEOUT; 1457 ndev->netdev_ops = &fec_netdev_ops; 1458 ndev->ethtool_ops = &fec_enet_ethtool_ops; 1459 1460 /* Initialize the receive buffer descriptors. */ 1461 bdp = fep->rx_bd_base; 1462 for (i = 0; i < RX_RING_SIZE; i++) { 1463 1464 /* Initialize the BD for every fragment in the page. */ 1465 bdp->cbd_sc = 0; 1466 bdp++; 1467 } 1468 1469 /* Set the last buffer to wrap */ 1470 bdp--; 1471 bdp->cbd_sc |= BD_SC_WRAP; 1472 1473 /* ...and the same for transmit */ 1474 bdp = fep->tx_bd_base; 1475 for (i = 0; i < TX_RING_SIZE; i++) { 1476 1477 /* Initialize the BD for every fragment in the page. */ 1478 bdp->cbd_sc = 0; 1479 bdp->cbd_bufaddr = 0; 1480 bdp++; 1481 } 1482 1483 /* Set the last buffer to wrap */ 1484 bdp--; 1485 bdp->cbd_sc |= BD_SC_WRAP; 1486 1487 fec_restart(ndev, 0); 1488 1489 return 0; 1490} 1491 1492#ifdef CONFIG_OF 1493static int __devinit fec_get_phy_mode_dt(struct platform_device *pdev) 1494{ 1495 struct device_node *np = pdev->dev.of_node; 1496 1497 if (np) 1498 return of_get_phy_mode(np); 1499 1500 return -ENODEV; 1501} 1502 1503static void __devinit fec_reset_phy(struct platform_device *pdev) 1504{ 1505 int err, phy_reset; 1506 struct device_node *np = pdev->dev.of_node; 1507 1508 if (!np) 1509 return; 1510 1511 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 1512 err = gpio_request_one(phy_reset, GPIOF_OUT_INIT_LOW, "phy-reset"); 1513 if (err) { 1514 pr_debug("FEC: failed to get gpio phy-reset: %d\n", err); 1515 return; 1516 } 1517 msleep(1); 1518 gpio_set_value(phy_reset, 1); 1519} 1520#else /* CONFIG_OF */ 1521static inline int fec_get_phy_mode_dt(struct platform_device *pdev) 1522{ 1523 return -ENODEV; 1524} 1525 1526static inline void fec_reset_phy(struct platform_device *pdev) 1527{ 1528 /* 1529 * In case of platform probe, the reset has been done 1530 * by machine code. 1531 */ 1532} 1533#endif /* CONFIG_OF */ 1534 1535static int __devinit 1536fec_probe(struct platform_device *pdev) 1537{ 1538 struct fec_enet_private *fep; 1539 struct fec_platform_data *pdata; 1540 struct net_device *ndev; 1541 int i, irq, ret = 0; 1542 struct resource *r; 1543 const struct of_device_id *of_id; 1544 static int dev_id; 1545 1546 of_id = of_match_device(fec_dt_ids, &pdev->dev); 1547 if (of_id) 1548 pdev->id_entry = of_id->data; 1549 1550 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1551 if (!r) 1552 return -ENXIO; 1553 1554 r = request_mem_region(r->start, resource_size(r), pdev->name); 1555 if (!r) 1556 return -EBUSY; 1557 1558 /* Init network device */ 1559 ndev = alloc_etherdev(sizeof(struct fec_enet_private)); 1560 if (!ndev) { 1561 ret = -ENOMEM; 1562 goto failed_alloc_etherdev; 1563 } 1564 1565 SET_NETDEV_DEV(ndev, &pdev->dev); 1566 1567 /* setup board info structure */ 1568 fep = netdev_priv(ndev); 1569 1570 fep->hwp = ioremap(r->start, resource_size(r)); 1571 fep->pdev = pdev; 1572 fep->dev_id = dev_id++; 1573 1574 if (!fep->hwp) { 1575 ret = -ENOMEM; 1576 goto failed_ioremap; 1577 } 1578 1579 platform_set_drvdata(pdev, ndev); 1580 1581 ret = fec_get_phy_mode_dt(pdev); 1582 if (ret < 0) { 1583 pdata = pdev->dev.platform_data; 1584 if (pdata) 1585 fep->phy_interface = pdata->phy; 1586 else 1587 fep->phy_interface = PHY_INTERFACE_MODE_MII; 1588 } else { 1589 fep->phy_interface = ret; 1590 } 1591 1592 fec_reset_phy(pdev); 1593 1594 for (i = 0; i < FEC_IRQ_NUM; i++) { 1595 irq = platform_get_irq(pdev, i); 1596 if (irq < 0) { 1597 if (i) 1598 break; 1599 ret = irq; 1600 goto failed_irq; 1601 } 1602 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); 1603 if (ret) { 1604 while (--i >= 0) { 1605 irq = platform_get_irq(pdev, i); 1606 free_irq(irq, ndev); 1607 } 1608 goto failed_irq; 1609 } 1610 } 1611 1612 fep->clk = clk_get(&pdev->dev, NULL); 1613 if (IS_ERR(fep->clk)) { 1614 ret = PTR_ERR(fep->clk); 1615 goto failed_clk; 1616 } 1617 clk_prepare_enable(fep->clk); 1618 1619 ret = fec_enet_init(ndev); 1620 if (ret) 1621 goto failed_init; 1622 1623 ret = fec_enet_mii_init(pdev); 1624 if (ret) 1625 goto failed_mii_init; 1626 1627 /* Carrier starts down, phylib will bring it up */ 1628 netif_carrier_off(ndev); 1629 1630 ret = register_netdev(ndev); 1631 if (ret) 1632 goto failed_register; 1633 1634 return 0; 1635 1636failed_register: 1637 fec_enet_mii_remove(fep); 1638failed_mii_init: 1639failed_init: 1640 clk_disable_unprepare(fep->clk); 1641 clk_put(fep->clk); 1642failed_clk: 1643 for (i = 0; i < FEC_IRQ_NUM; i++) { 1644 irq = platform_get_irq(pdev, i); 1645 if (irq > 0) 1646 free_irq(irq, ndev); 1647 } 1648failed_irq: 1649 iounmap(fep->hwp); 1650failed_ioremap: 1651 free_netdev(ndev); 1652failed_alloc_etherdev: 1653 release_mem_region(r->start, resource_size(r)); 1654 1655 return ret; 1656} 1657 1658static int __devexit 1659fec_drv_remove(struct platform_device *pdev) 1660{ 1661 struct net_device *ndev = platform_get_drvdata(pdev); 1662 struct fec_enet_private *fep = netdev_priv(ndev); 1663 struct resource *r; 1664 int i; 1665 1666 unregister_netdev(ndev); 1667 fec_enet_mii_remove(fep); 1668 for (i = 0; i < FEC_IRQ_NUM; i++) { 1669 int irq = platform_get_irq(pdev, i); 1670 if (irq > 0) 1671 free_irq(irq, ndev); 1672 } 1673 clk_disable_unprepare(fep->clk); 1674 clk_put(fep->clk); 1675 iounmap(fep->hwp); 1676 free_netdev(ndev); 1677 1678 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1679 BUG_ON(!r); 1680 release_mem_region(r->start, resource_size(r)); 1681 1682 platform_set_drvdata(pdev, NULL); 1683 1684 return 0; 1685} 1686 1687#ifdef CONFIG_PM 1688static int 1689fec_suspend(struct device *dev) 1690{ 1691 struct net_device *ndev = dev_get_drvdata(dev); 1692 struct fec_enet_private *fep = netdev_priv(ndev); 1693 1694 if (netif_running(ndev)) { 1695 fec_stop(ndev); 1696 netif_device_detach(ndev); 1697 } 1698 clk_disable_unprepare(fep->clk); 1699 1700 return 0; 1701} 1702 1703static int 1704fec_resume(struct device *dev) 1705{ 1706 struct net_device *ndev = dev_get_drvdata(dev); 1707 struct fec_enet_private *fep = netdev_priv(ndev); 1708 1709 clk_prepare_enable(fep->clk); 1710 if (netif_running(ndev)) { 1711 fec_restart(ndev, fep->full_duplex); 1712 netif_device_attach(ndev); 1713 } 1714 1715 return 0; 1716} 1717 1718static const struct dev_pm_ops fec_pm_ops = { 1719 .suspend = fec_suspend, 1720 .resume = fec_resume, 1721 .freeze = fec_suspend, 1722 .thaw = fec_resume, 1723 .poweroff = fec_suspend, 1724 .restore = fec_resume, 1725}; 1726#endif 1727 1728static struct platform_driver fec_driver = { 1729 .driver = { 1730 .name = DRIVER_NAME, 1731 .owner = THIS_MODULE, 1732#ifdef CONFIG_PM 1733 .pm = &fec_pm_ops, 1734#endif 1735 .of_match_table = fec_dt_ids, 1736 }, 1737 .id_table = fec_devtype, 1738 .probe = fec_probe, 1739 .remove = __devexit_p(fec_drv_remove), 1740}; 1741 1742module_platform_driver(fec_driver); 1743 1744MODULE_LICENSE("GPL"); 1745