1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29#ifndef _E1000_HW_H_ 30#define _E1000_HW_H_ 31 32#include <linux/types.h> 33 34struct e1000_hw; 35struct e1000_adapter; 36 37#include "defines.h" 38 39#define er32(reg) __er32(hw, E1000_##reg) 40#define ew32(reg,val) __ew32(hw, E1000_##reg, (val)) 41#define e1e_flush() er32(STATUS) 42 43#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 44 (writel((value), ((a)->hw_addr + reg + ((offset) << 2)))) 45 46#define E1000_READ_REG_ARRAY(a, reg, offset) \ 47 (readl((a)->hw_addr + reg + ((offset) << 2))) 48 49enum e1e_registers { 50 E1000_CTRL = 0x00000, /* Device Control - RW */ 51 E1000_STATUS = 0x00008, /* Device Status - RO */ 52 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */ 53 E1000_EERD = 0x00014, /* EEPROM Read - RW */ 54 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */ 55 E1000_FLA = 0x0001C, /* Flash Access - RW */ 56 E1000_MDIC = 0x00020, /* MDI Control - RW */ 57 E1000_SCTL = 0x00024, /* SerDes Control - RW */ 58 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */ 59 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */ 60 E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */ 61 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */ 62 E1000_FCT = 0x00030, /* Flow Control Type - RW */ 63 E1000_VET = 0x00038, /* VLAN Ether Type - RW */ 64 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */ 65 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */ 66 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */ 67 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */ 68 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */ 69 E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */ 70 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */ 71 E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */ 72 E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */ 73#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2)) 74 E1000_RCTL = 0x00100, /* Rx Control - RW */ 75 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */ 76 E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */ 77 E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */ 78 E1000_TCTL = 0x00400, /* Tx Control - RW */ 79 E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */ 80 E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */ 81 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */ 82 E1000_LEDCTL = 0x00E00, /* LED Control - RW */ 83 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */ 84 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */ 85 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */ 86#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */ 87 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */ 88 E1000_PBS = 0x01008, /* Packet Buffer Size */ 89 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */ 90 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */ 91 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */ 92 E1000_PBA_ECC = 0x01100, /* PBA ECC Register */ 93 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */ 94 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */ 95 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */ 96 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */ 97 E1000_RDBAL = 0x02800, /* Rx Descriptor Base Address Low - RW */ 98 E1000_RDBAH = 0x02804, /* Rx Descriptor Base Address High - RW */ 99 E1000_RDLEN = 0x02808, /* Rx Descriptor Length - RW */ 100 E1000_RDH = 0x02810, /* Rx Descriptor Head - RW */ 101 E1000_RDT = 0x02818, /* Rx Descriptor Tail - RW */ 102 E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */ 103 E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */ 104#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8)) 105 E1000_RADV = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */ 106 107/* Convenience macros 108 * 109 * Note: "_n" is the queue number of the register to be written to. 110 * 111 * Example usage: 112 * E1000_RDBAL_REG(current_rx_queue) 113 * 114 */ 115#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8)) 116 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */ 117 E1000_TDBAL = 0x03800, /* Tx Descriptor Base Address Low - RW */ 118 E1000_TDBAH = 0x03804, /* Tx Descriptor Base Address High - RW */ 119 E1000_TDLEN = 0x03808, /* Tx Descriptor Length - RW */ 120 E1000_TDH = 0x03810, /* Tx Descriptor Head - RW */ 121 E1000_TDT = 0x03818, /* Tx Descriptor Tail - RW */ 122 E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */ 123 E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */ 124#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8)) 125 E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */ 126 E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */ 127#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8)) 128 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */ 129 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */ 130 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */ 131 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */ 132 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */ 133 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */ 134 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */ 135 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */ 136 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */ 137 E1000_COLC = 0x04028, /* Collision Count - R/clr */ 138 E1000_DC = 0x04030, /* Defer Count - R/clr */ 139 E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */ 140 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */ 141 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */ 142 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */ 143 E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */ 144 E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */ 145 E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */ 146 E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */ 147 E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */ 148 E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */ 149 E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */ 150 E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */ 151 E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */ 152 E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */ 153 E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */ 154 E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */ 155 E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */ 156 E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */ 157 E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */ 158 E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */ 159 E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */ 160 E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */ 161 E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */ 162 E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */ 163 E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */ 164 E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */ 165 E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */ 166 E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */ 167 E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */ 168 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */ 169 E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */ 170 E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */ 171 E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */ 172 E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */ 173 E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */ 174 E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */ 175 E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */ 176 E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */ 177 E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */ 178 E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */ 179 E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */ 180 E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */ 181 E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */ 182 E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */ 183 E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */ 184 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */ 185 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */ 186 E1000_IAC = 0x04100, /* Interrupt Assertion Count */ 187 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */ 188 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */ 189 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */ 190 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */ 191 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */ 192 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */ 193 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */ 194 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */ 195 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */ 196 E1000_RFCTL = 0x05008, /* Receive Filter Control */ 197 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */ 198 E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */ 199#define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8)) 200#define E1000_RA (E1000_RAL(0)) 201 E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */ 202#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8)) 203 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */ 204 E1000_WUC = 0x05800, /* Wakeup Control - RW */ 205 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */ 206 E1000_WUS = 0x05810, /* Wakeup Status - RO */ 207 E1000_MRQC = 0x05818, /* Multiple Receive Control - RW */ 208 E1000_MANC = 0x05820, /* Management Control - RW */ 209 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */ 210 E1000_HOST_IF = 0x08800, /* Host Interface */ 211 212 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */ 213 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */ 214 E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */ 215#define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4)) 216 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */ 217 E1000_GCR = 0x05B00, /* PCI-Ex Control */ 218 E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */ 219 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */ 220 E1000_SWSM = 0x05B50, /* SW Semaphore */ 221 E1000_FWSM = 0x05B54, /* FW Semaphore */ 222 E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */ 223 E1000_RETA_BASE = 0x05C00, /* Redirection Table - RW */ 224#define E1000_RETA(_n) (E1000_RETA_BASE + ((_n) * 4)) 225 E1000_RSSRK_BASE = 0x05C80, /* RSS Random Key - RW */ 226#define E1000_RSSRK(_n) (E1000_RSSRK_BASE + ((_n) * 4)) 227 E1000_FFLT_DBG = 0x05F04, /* Debug Register */ 228 E1000_PCH_RAICC_BASE = 0x05F50, /* Receive Address Initial CRC */ 229#define E1000_PCH_RAICC(_n) (E1000_PCH_RAICC_BASE + ((_n) * 4)) 230#define E1000_CRC_OFFSET E1000_PCH_RAICC_BASE 231 E1000_HICR = 0x08F00, /* Host Interface Control */ 232}; 233 234#define E1000_MAX_PHY_ADDR 4 235 236/* IGP01E1000 Specific Registers */ 237#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 238#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 239#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 240#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 241#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 242#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 243#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 244#define IGP_PAGE_SHIFT 5 245#define PHY_REG_MASK 0x1F 246 247#define BM_WUC_PAGE 800 248#define BM_WUC_ADDRESS_OPCODE 0x11 249#define BM_WUC_DATA_OPCODE 0x12 250#define BM_WUC_ENABLE_PAGE 769 251#define BM_WUC_ENABLE_REG 17 252#define BM_WUC_ENABLE_BIT (1 << 2) 253#define BM_WUC_HOST_WU_BIT (1 << 4) 254#define BM_WUC_ME_WU_BIT (1 << 5) 255 256#define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 257#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 258#define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 259 260#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 261#define IGP01E1000_PHY_POLARITY_MASK 0x0078 262 263#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 264#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 265 266#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 267 268#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 269#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 270#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 271 272#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 273 274#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 275#define IGP01E1000_PSSR_MDIX 0x0800 276#define IGP01E1000_PSSR_SPEED_MASK 0xC000 277#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 278 279#define IGP02E1000_PHY_CHANNEL_NUM 4 280#define IGP02E1000_PHY_AGC_A 0x11B1 281#define IGP02E1000_PHY_AGC_B 0x12B1 282#define IGP02E1000_PHY_AGC_C 0x14B1 283#define IGP02E1000_PHY_AGC_D 0x18B1 284 285#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ 286#define IGP02E1000_AGC_LENGTH_MASK 0x7F 287#define IGP02E1000_AGC_RANGE 15 288 289/* manage.c */ 290#define E1000_VFTA_ENTRY_SHIFT 5 291#define E1000_VFTA_ENTRY_MASK 0x7F 292#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 293 294#define E1000_HICR_EN 0x01 /* Enable bit - RO */ 295/* Driver sets this bit when done to put command in RAM */ 296#define E1000_HICR_C 0x02 297#define E1000_HICR_FW_RESET_ENABLE 0x40 298#define E1000_HICR_FW_RESET 0x80 299 300#define E1000_FWSM_MODE_MASK 0xE 301#define E1000_FWSM_MODE_SHIFT 1 302 303#define E1000_MNG_IAMT_MODE 0x3 304#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 305#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 306#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 307#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 308#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 309#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 310 311/* nvm.c */ 312#define E1000_STM_OPCODE 0xDB00 313 314#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 315#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 316#define E1000_KMRNCTRLSTA_REN 0x00200000 317#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */ 318#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 319#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ 320#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ 321#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ 322#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 323#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 324#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 325#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ 326 327#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 328#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */ 329#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */ 330#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 331 332/* IFE PHY Extended Status Control */ 333#define IFE_PESC_POLARITY_REVERSED 0x0100 334 335/* IFE PHY Special Control */ 336#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 337#define IFE_PSC_FORCE_POLARITY 0x0020 338 339/* IFE PHY Special Control and LED Control */ 340#define IFE_PSCL_PROBE_MODE 0x0020 341#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 342#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 343 344/* IFE PHY MDIX Control */ 345#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 346#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 347#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */ 348 349#define E1000_CABLE_LENGTH_UNDEFINED 0xFF 350 351#define E1000_DEV_ID_82571EB_COPPER 0x105E 352#define E1000_DEV_ID_82571EB_FIBER 0x105F 353#define E1000_DEV_ID_82571EB_SERDES 0x1060 354#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 355#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 356#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 357#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 358#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 359#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 360#define E1000_DEV_ID_82572EI_COPPER 0x107D 361#define E1000_DEV_ID_82572EI_FIBER 0x107E 362#define E1000_DEV_ID_82572EI_SERDES 0x107F 363#define E1000_DEV_ID_82572EI 0x10B9 364#define E1000_DEV_ID_82573E 0x108B 365#define E1000_DEV_ID_82573E_IAMT 0x108C 366#define E1000_DEV_ID_82573L 0x109A 367#define E1000_DEV_ID_82574L 0x10D3 368#define E1000_DEV_ID_82574LA 0x10F6 369#define E1000_DEV_ID_82583V 0x150C 370 371#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 372#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 373#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 374#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 375 376#define E1000_DEV_ID_ICH8_82567V_3 0x1501 377#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 378#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 379#define E1000_DEV_ID_ICH8_IGP_C 0x104B 380#define E1000_DEV_ID_ICH8_IFE 0x104C 381#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 382#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 383#define E1000_DEV_ID_ICH8_IGP_M 0x104D 384#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 385#define E1000_DEV_ID_ICH9_BM 0x10E5 386#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 387#define E1000_DEV_ID_ICH9_IGP_M 0x10BF 388#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 389#define E1000_DEV_ID_ICH9_IGP_C 0x294C 390#define E1000_DEV_ID_ICH9_IFE 0x10C0 391#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 392#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 393#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 394#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 395#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 396#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 397#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 398#define E1000_DEV_ID_ICH10_D_BM_V 0x1525 399#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 400#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 401#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 402#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 403#define E1000_DEV_ID_PCH2_LV_LM 0x1502 404#define E1000_DEV_ID_PCH2_LV_V 0x1503 405 406#define E1000_REVISION_4 4 407 408#define E1000_FUNC_1 1 409 410#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 411#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 412 413enum e1000_mac_type { 414 e1000_82571, 415 e1000_82572, 416 e1000_82573, 417 e1000_82574, 418 e1000_82583, 419 e1000_80003es2lan, 420 e1000_ich8lan, 421 e1000_ich9lan, 422 e1000_ich10lan, 423 e1000_pchlan, 424 e1000_pch2lan, 425}; 426 427enum e1000_media_type { 428 e1000_media_type_unknown = 0, 429 e1000_media_type_copper = 1, 430 e1000_media_type_fiber = 2, 431 e1000_media_type_internal_serdes = 3, 432 e1000_num_media_types 433}; 434 435enum e1000_nvm_type { 436 e1000_nvm_unknown = 0, 437 e1000_nvm_none, 438 e1000_nvm_eeprom_spi, 439 e1000_nvm_flash_hw, 440 e1000_nvm_flash_sw 441}; 442 443enum e1000_nvm_override { 444 e1000_nvm_override_none = 0, 445 e1000_nvm_override_spi_small, 446 e1000_nvm_override_spi_large 447}; 448 449enum e1000_phy_type { 450 e1000_phy_unknown = 0, 451 e1000_phy_none, 452 e1000_phy_m88, 453 e1000_phy_igp, 454 e1000_phy_igp_2, 455 e1000_phy_gg82563, 456 e1000_phy_igp_3, 457 e1000_phy_ife, 458 e1000_phy_bm, 459 e1000_phy_82578, 460 e1000_phy_82577, 461 e1000_phy_82579, 462}; 463 464enum e1000_bus_width { 465 e1000_bus_width_unknown = 0, 466 e1000_bus_width_pcie_x1, 467 e1000_bus_width_pcie_x2, 468 e1000_bus_width_pcie_x4 = 4, 469 e1000_bus_width_32, 470 e1000_bus_width_64, 471 e1000_bus_width_reserved 472}; 473 474enum e1000_1000t_rx_status { 475 e1000_1000t_rx_status_not_ok = 0, 476 e1000_1000t_rx_status_ok, 477 e1000_1000t_rx_status_undefined = 0xFF 478}; 479 480enum e1000_rev_polarity{ 481 e1000_rev_polarity_normal = 0, 482 e1000_rev_polarity_reversed, 483 e1000_rev_polarity_undefined = 0xFF 484}; 485 486enum e1000_fc_mode { 487 e1000_fc_none = 0, 488 e1000_fc_rx_pause, 489 e1000_fc_tx_pause, 490 e1000_fc_full, 491 e1000_fc_default = 0xFF 492}; 493 494enum e1000_ms_type { 495 e1000_ms_hw_default = 0, 496 e1000_ms_force_master, 497 e1000_ms_force_slave, 498 e1000_ms_auto 499}; 500 501enum e1000_smart_speed { 502 e1000_smart_speed_default = 0, 503 e1000_smart_speed_on, 504 e1000_smart_speed_off 505}; 506 507enum e1000_serdes_link_state { 508 e1000_serdes_link_down = 0, 509 e1000_serdes_link_autoneg_progress, 510 e1000_serdes_link_autoneg_complete, 511 e1000_serdes_link_forced_up 512}; 513 514/* Receive Descriptor */ 515struct e1000_rx_desc { 516 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 517 __le16 length; /* Length of data DMAed into data buffer */ 518 __le16 csum; /* Packet checksum */ 519 u8 status; /* Descriptor status */ 520 u8 errors; /* Descriptor Errors */ 521 __le16 special; 522}; 523 524/* Receive Descriptor - Extended */ 525union e1000_rx_desc_extended { 526 struct { 527 __le64 buffer_addr; 528 __le64 reserved; 529 } read; 530 struct { 531 struct { 532 __le32 mrq; /* Multiple Rx Queues */ 533 union { 534 __le32 rss; /* RSS Hash */ 535 struct { 536 __le16 ip_id; /* IP id */ 537 __le16 csum; /* Packet Checksum */ 538 } csum_ip; 539 } hi_dword; 540 } lower; 541 struct { 542 __le32 status_error; /* ext status/error */ 543 __le16 length; 544 __le16 vlan; /* VLAN tag */ 545 } upper; 546 } wb; /* writeback */ 547}; 548 549#define MAX_PS_BUFFERS 4 550/* Receive Descriptor - Packet Split */ 551union e1000_rx_desc_packet_split { 552 struct { 553 /* one buffer for protocol header(s), three data buffers */ 554 __le64 buffer_addr[MAX_PS_BUFFERS]; 555 } read; 556 struct { 557 struct { 558 __le32 mrq; /* Multiple Rx Queues */ 559 union { 560 __le32 rss; /* RSS Hash */ 561 struct { 562 __le16 ip_id; /* IP id */ 563 __le16 csum; /* Packet Checksum */ 564 } csum_ip; 565 } hi_dword; 566 } lower; 567 struct { 568 __le32 status_error; /* ext status/error */ 569 __le16 length0; /* length of buffer 0 */ 570 __le16 vlan; /* VLAN tag */ 571 } middle; 572 struct { 573 __le16 header_status; 574 __le16 length[3]; /* length of buffers 1-3 */ 575 } upper; 576 __le64 reserved; 577 } wb; /* writeback */ 578}; 579 580/* Transmit Descriptor */ 581struct e1000_tx_desc { 582 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 583 union { 584 __le32 data; 585 struct { 586 __le16 length; /* Data buffer length */ 587 u8 cso; /* Checksum offset */ 588 u8 cmd; /* Descriptor control */ 589 } flags; 590 } lower; 591 union { 592 __le32 data; 593 struct { 594 u8 status; /* Descriptor status */ 595 u8 css; /* Checksum start */ 596 __le16 special; 597 } fields; 598 } upper; 599}; 600 601/* Offload Context Descriptor */ 602struct e1000_context_desc { 603 union { 604 __le32 ip_config; 605 struct { 606 u8 ipcss; /* IP checksum start */ 607 u8 ipcso; /* IP checksum offset */ 608 __le16 ipcse; /* IP checksum end */ 609 } ip_fields; 610 } lower_setup; 611 union { 612 __le32 tcp_config; 613 struct { 614 u8 tucss; /* TCP checksum start */ 615 u8 tucso; /* TCP checksum offset */ 616 __le16 tucse; /* TCP checksum end */ 617 } tcp_fields; 618 } upper_setup; 619 __le32 cmd_and_length; 620 union { 621 __le32 data; 622 struct { 623 u8 status; /* Descriptor status */ 624 u8 hdr_len; /* Header length */ 625 __le16 mss; /* Maximum segment size */ 626 } fields; 627 } tcp_seg_setup; 628}; 629 630/* Offload data descriptor */ 631struct e1000_data_desc { 632 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 633 union { 634 __le32 data; 635 struct { 636 __le16 length; /* Data buffer length */ 637 u8 typ_len_ext; 638 u8 cmd; 639 } flags; 640 } lower; 641 union { 642 __le32 data; 643 struct { 644 u8 status; /* Descriptor status */ 645 u8 popts; /* Packet Options */ 646 __le16 special; /* */ 647 } fields; 648 } upper; 649}; 650 651/* Statistics counters collected by the MAC */ 652struct e1000_hw_stats { 653 u64 crcerrs; 654 u64 algnerrc; 655 u64 symerrs; 656 u64 rxerrc; 657 u64 mpc; 658 u64 scc; 659 u64 ecol; 660 u64 mcc; 661 u64 latecol; 662 u64 colc; 663 u64 dc; 664 u64 tncrs; 665 u64 sec; 666 u64 cexterr; 667 u64 rlec; 668 u64 xonrxc; 669 u64 xontxc; 670 u64 xoffrxc; 671 u64 xofftxc; 672 u64 fcruc; 673 u64 prc64; 674 u64 prc127; 675 u64 prc255; 676 u64 prc511; 677 u64 prc1023; 678 u64 prc1522; 679 u64 gprc; 680 u64 bprc; 681 u64 mprc; 682 u64 gptc; 683 u64 gorc; 684 u64 gotc; 685 u64 rnbc; 686 u64 ruc; 687 u64 rfc; 688 u64 roc; 689 u64 rjc; 690 u64 mgprc; 691 u64 mgpdc; 692 u64 mgptc; 693 u64 tor; 694 u64 tot; 695 u64 tpr; 696 u64 tpt; 697 u64 ptc64; 698 u64 ptc127; 699 u64 ptc255; 700 u64 ptc511; 701 u64 ptc1023; 702 u64 ptc1522; 703 u64 mptc; 704 u64 bptc; 705 u64 tsctc; 706 u64 tsctfc; 707 u64 iac; 708 u64 icrxptc; 709 u64 icrxatc; 710 u64 ictxptc; 711 u64 ictxatc; 712 u64 ictxqec; 713 u64 ictxqmtc; 714 u64 icrxdmtc; 715 u64 icrxoc; 716}; 717 718struct e1000_phy_stats { 719 u32 idle_errors; 720 u32 receive_errors; 721}; 722 723struct e1000_host_mng_dhcp_cookie { 724 u32 signature; 725 u8 status; 726 u8 reserved0; 727 u16 vlan_id; 728 u32 reserved1; 729 u16 reserved2; 730 u8 reserved3; 731 u8 checksum; 732}; 733 734/* Host Interface "Rev 1" */ 735struct e1000_host_command_header { 736 u8 command_id; 737 u8 command_length; 738 u8 command_options; 739 u8 checksum; 740}; 741 742#define E1000_HI_MAX_DATA_LENGTH 252 743struct e1000_host_command_info { 744 struct e1000_host_command_header command_header; 745 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 746}; 747 748/* Host Interface "Rev 2" */ 749struct e1000_host_mng_command_header { 750 u8 command_id; 751 u8 checksum; 752 u16 reserved1; 753 u16 reserved2; 754 u16 command_length; 755}; 756 757#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 758struct e1000_host_mng_command_info { 759 struct e1000_host_mng_command_header command_header; 760 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 761}; 762 763/* Function pointers and static data for the MAC. */ 764struct e1000_mac_operations { 765 s32 (*id_led_init)(struct e1000_hw *); 766 s32 (*blink_led)(struct e1000_hw *); 767 bool (*check_mng_mode)(struct e1000_hw *); 768 s32 (*check_for_link)(struct e1000_hw *); 769 s32 (*cleanup_led)(struct e1000_hw *); 770 void (*clear_hw_cntrs)(struct e1000_hw *); 771 void (*clear_vfta)(struct e1000_hw *); 772 s32 (*get_bus_info)(struct e1000_hw *); 773 void (*set_lan_id)(struct e1000_hw *); 774 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 775 s32 (*led_on)(struct e1000_hw *); 776 s32 (*led_off)(struct e1000_hw *); 777 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 778 s32 (*reset_hw)(struct e1000_hw *); 779 s32 (*init_hw)(struct e1000_hw *); 780 s32 (*setup_link)(struct e1000_hw *); 781 s32 (*setup_physical_interface)(struct e1000_hw *); 782 s32 (*setup_led)(struct e1000_hw *); 783 void (*write_vfta)(struct e1000_hw *, u32, u32); 784 void (*config_collision_dist)(struct e1000_hw *); 785 s32 (*read_mac_addr)(struct e1000_hw *); 786}; 787 788/* 789 * When to use various PHY register access functions: 790 * 791 * Func Caller 792 * Function Does Does When to use 793 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 794 * X_reg L,P,A n/a for simple PHY reg accesses 795 * X_reg_locked P,A L for multiple accesses of different regs 796 * on different pages 797 * X_reg_page A L,P for multiple accesses of different regs 798 * on the same page 799 * 800 * Where X=[read|write], L=locking, P=sets page, A=register access 801 * 802 */ 803struct e1000_phy_operations { 804 s32 (*acquire)(struct e1000_hw *); 805 s32 (*cfg_on_link_up)(struct e1000_hw *); 806 s32 (*check_polarity)(struct e1000_hw *); 807 s32 (*check_reset_block)(struct e1000_hw *); 808 s32 (*commit)(struct e1000_hw *); 809 s32 (*force_speed_duplex)(struct e1000_hw *); 810 s32 (*get_cfg_done)(struct e1000_hw *hw); 811 s32 (*get_cable_length)(struct e1000_hw *); 812 s32 (*get_info)(struct e1000_hw *); 813 s32 (*set_page)(struct e1000_hw *, u16); 814 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 815 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 816 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 817 void (*release)(struct e1000_hw *); 818 s32 (*reset)(struct e1000_hw *); 819 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 820 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 821 s32 (*write_reg)(struct e1000_hw *, u32, u16); 822 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 823 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 824 void (*power_up)(struct e1000_hw *); 825 void (*power_down)(struct e1000_hw *); 826}; 827 828/* Function pointers for the NVM. */ 829struct e1000_nvm_operations { 830 s32 (*acquire)(struct e1000_hw *); 831 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 832 void (*release)(struct e1000_hw *); 833 void (*reload)(struct e1000_hw *); 834 s32 (*update)(struct e1000_hw *); 835 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 836 s32 (*validate)(struct e1000_hw *); 837 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 838}; 839 840struct e1000_mac_info { 841 struct e1000_mac_operations ops; 842 u8 addr[ETH_ALEN]; 843 u8 perm_addr[ETH_ALEN]; 844 845 enum e1000_mac_type type; 846 847 u32 collision_delta; 848 u32 ledctl_default; 849 u32 ledctl_mode1; 850 u32 ledctl_mode2; 851 u32 mc_filter_type; 852 u32 tx_packet_delta; 853 u32 txcw; 854 855 u16 current_ifs_val; 856 u16 ifs_max_val; 857 u16 ifs_min_val; 858 u16 ifs_ratio; 859 u16 ifs_step_size; 860 u16 mta_reg_count; 861 862 /* Maximum size of the MTA register table in all supported adapters */ 863 #define MAX_MTA_REG 128 864 u32 mta_shadow[MAX_MTA_REG]; 865 u16 rar_entry_count; 866 867 u8 forced_speed_duplex; 868 869 bool adaptive_ifs; 870 bool has_fwsm; 871 bool arc_subsystem_valid; 872 bool autoneg; 873 bool autoneg_failed; 874 bool get_link_status; 875 bool in_ifs_mode; 876 bool serdes_has_link; 877 bool tx_pkt_filtering; 878 enum e1000_serdes_link_state serdes_link_state; 879}; 880 881struct e1000_phy_info { 882 struct e1000_phy_operations ops; 883 884 enum e1000_phy_type type; 885 886 enum e1000_1000t_rx_status local_rx; 887 enum e1000_1000t_rx_status remote_rx; 888 enum e1000_ms_type ms_type; 889 enum e1000_ms_type original_ms_type; 890 enum e1000_rev_polarity cable_polarity; 891 enum e1000_smart_speed smart_speed; 892 893 u32 addr; 894 u32 id; 895 u32 reset_delay_us; /* in usec */ 896 u32 revision; 897 898 enum e1000_media_type media_type; 899 900 u16 autoneg_advertised; 901 u16 autoneg_mask; 902 u16 cable_length; 903 u16 max_cable_length; 904 u16 min_cable_length; 905 906 u8 mdix; 907 908 bool disable_polarity_correction; 909 bool is_mdix; 910 bool polarity_correction; 911 bool speed_downgraded; 912 bool autoneg_wait_to_complete; 913}; 914 915struct e1000_nvm_info { 916 struct e1000_nvm_operations ops; 917 918 enum e1000_nvm_type type; 919 enum e1000_nvm_override override; 920 921 u32 flash_bank_size; 922 u32 flash_base_addr; 923 924 u16 word_size; 925 u16 delay_usec; 926 u16 address_bits; 927 u16 opcode_bits; 928 u16 page_size; 929}; 930 931struct e1000_bus_info { 932 enum e1000_bus_width width; 933 934 u16 func; 935}; 936 937struct e1000_fc_info { 938 u32 high_water; /* Flow control high-water mark */ 939 u32 low_water; /* Flow control low-water mark */ 940 u16 pause_time; /* Flow control pause timer */ 941 u16 refresh_time; /* Flow control refresh timer */ 942 bool send_xon; /* Flow control send XON */ 943 bool strict_ieee; /* Strict IEEE mode */ 944 enum e1000_fc_mode current_mode; /* FC mode in effect */ 945 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 946}; 947 948struct e1000_dev_spec_82571 { 949 bool laa_is_present; 950 u32 smb_counter; 951}; 952 953struct e1000_dev_spec_80003es2lan { 954 bool mdic_wa_enable; 955}; 956 957struct e1000_shadow_ram { 958 u16 value; 959 bool modified; 960}; 961 962#define E1000_ICH8_SHADOW_RAM_WORDS 2048 963 964struct e1000_dev_spec_ich8lan { 965 bool kmrn_lock_loss_workaround_enabled; 966 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS]; 967 bool nvm_k1_enabled; 968 bool eee_disable; 969}; 970 971struct e1000_hw { 972 struct e1000_adapter *adapter; 973 974 void __iomem *hw_addr; 975 void __iomem *flash_address; 976 977 struct e1000_mac_info mac; 978 struct e1000_fc_info fc; 979 struct e1000_phy_info phy; 980 struct e1000_nvm_info nvm; 981 struct e1000_bus_info bus; 982 struct e1000_host_mng_dhcp_cookie mng_cookie; 983 984 union { 985 struct e1000_dev_spec_82571 e82571; 986 struct e1000_dev_spec_80003es2lan e80003es2lan; 987 struct e1000_dev_spec_ich8lan ich8lan; 988 } dev_spec; 989}; 990 991#endif 992