1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#include <linux/if_ether.h> 29#include <linux/delay.h> 30#include <linux/pci.h> 31#include <linux/netdevice.h> 32#include <linux/etherdevice.h> 33 34#include "e1000_mac.h" 35 36#include "igb.h" 37 38static s32 igb_set_default_fc(struct e1000_hw *hw); 39static s32 igb_set_fc_watermarks(struct e1000_hw *hw); 40 41/** 42 * igb_get_bus_info_pcie - Get PCIe bus information 43 * @hw: pointer to the HW structure 44 * 45 * Determines and stores the system bus information for a particular 46 * network interface. The following bus information is determined and stored: 47 * bus speed, bus width, type (PCIe), and PCIe function. 48 **/ 49s32 igb_get_bus_info_pcie(struct e1000_hw *hw) 50{ 51 struct e1000_bus_info *bus = &hw->bus; 52 s32 ret_val; 53 u32 reg; 54 u16 pcie_link_status; 55 56 bus->type = e1000_bus_type_pci_express; 57 58 ret_val = igb_read_pcie_cap_reg(hw, 59 PCI_EXP_LNKSTA, 60 &pcie_link_status); 61 if (ret_val) { 62 bus->width = e1000_bus_width_unknown; 63 bus->speed = e1000_bus_speed_unknown; 64 } else { 65 switch (pcie_link_status & PCI_EXP_LNKSTA_CLS) { 66 case PCI_EXP_LNKSTA_CLS_2_5GB: 67 bus->speed = e1000_bus_speed_2500; 68 break; 69 case PCI_EXP_LNKSTA_CLS_5_0GB: 70 bus->speed = e1000_bus_speed_5000; 71 break; 72 default: 73 bus->speed = e1000_bus_speed_unknown; 74 break; 75 } 76 77 bus->width = (enum e1000_bus_width)((pcie_link_status & 78 PCI_EXP_LNKSTA_NLW) >> 79 PCI_EXP_LNKSTA_NLW_SHIFT); 80 } 81 82 reg = rd32(E1000_STATUS); 83 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 84 85 return 0; 86} 87 88/** 89 * igb_clear_vfta - Clear VLAN filter table 90 * @hw: pointer to the HW structure 91 * 92 * Clears the register array which contains the VLAN filter table by 93 * setting all the values to 0. 94 **/ 95void igb_clear_vfta(struct e1000_hw *hw) 96{ 97 u32 offset; 98 99 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 100 array_wr32(E1000_VFTA, offset, 0); 101 wrfl(); 102 } 103} 104 105/** 106 * igb_write_vfta - Write value to VLAN filter table 107 * @hw: pointer to the HW structure 108 * @offset: register offset in VLAN filter table 109 * @value: register value written to VLAN filter table 110 * 111 * Writes value at the given offset in the register array which stores 112 * the VLAN filter table. 113 **/ 114static void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) 115{ 116 array_wr32(E1000_VFTA, offset, value); 117 wrfl(); 118} 119 120/* Due to a hw errata, if the host tries to configure the VFTA register 121 * while performing queries from the BMC or DMA, then the VFTA in some 122 * cases won't be written. 123 */ 124 125/** 126 * igb_clear_vfta_i350 - Clear VLAN filter table 127 * @hw: pointer to the HW structure 128 * 129 * Clears the register array which contains the VLAN filter table by 130 * setting all the values to 0. 131 **/ 132void igb_clear_vfta_i350(struct e1000_hw *hw) 133{ 134 u32 offset; 135 int i; 136 137 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 138 for (i = 0; i < 10; i++) 139 array_wr32(E1000_VFTA, offset, 0); 140 141 wrfl(); 142 } 143} 144 145/** 146 * igb_write_vfta_i350 - Write value to VLAN filter table 147 * @hw: pointer to the HW structure 148 * @offset: register offset in VLAN filter table 149 * @value: register value written to VLAN filter table 150 * 151 * Writes value at the given offset in the register array which stores 152 * the VLAN filter table. 153 **/ 154static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) 155{ 156 int i; 157 158 for (i = 0; i < 10; i++) 159 array_wr32(E1000_VFTA, offset, value); 160 161 wrfl(); 162} 163 164/** 165 * igb_init_rx_addrs - Initialize receive address's 166 * @hw: pointer to the HW structure 167 * @rar_count: receive address registers 168 * 169 * Setups the receive address registers by setting the base receive address 170 * register to the devices MAC address and clearing all the other receive 171 * address registers to 0. 172 **/ 173void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) 174{ 175 u32 i; 176 u8 mac_addr[ETH_ALEN] = {0}; 177 178 /* Setup the receive address */ 179 hw_dbg("Programming MAC Address into RAR[0]\n"); 180 181 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 182 183 /* Zero out the other (rar_entry_count - 1) receive addresses */ 184 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1); 185 for (i = 1; i < rar_count; i++) 186 hw->mac.ops.rar_set(hw, mac_addr, i); 187} 188 189/** 190 * igb_vfta_set - enable or disable vlan in VLAN filter table 191 * @hw: pointer to the HW structure 192 * @vid: VLAN id to add or remove 193 * @add: if true add filter, if false remove 194 * 195 * Sets or clears a bit in the VLAN filter table array based on VLAN id 196 * and if we are adding or removing the filter 197 **/ 198s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, bool add) 199{ 200 u32 index = (vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 201 u32 mask = 1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 202 u32 vfta; 203 struct igb_adapter *adapter = hw->back; 204 s32 ret_val = 0; 205 206 vfta = adapter->shadow_vfta[index]; 207 208 /* bit was set/cleared before we started */ 209 if ((!!(vfta & mask)) == add) { 210 ret_val = -E1000_ERR_CONFIG; 211 } else { 212 if (add) 213 vfta |= mask; 214 else 215 vfta &= ~mask; 216 } 217 if (hw->mac.type == e1000_i350) 218 igb_write_vfta_i350(hw, index, vfta); 219 else 220 igb_write_vfta(hw, index, vfta); 221 adapter->shadow_vfta[index] = vfta; 222 223 return ret_val; 224} 225 226/** 227 * igb_check_alt_mac_addr - Check for alternate MAC addr 228 * @hw: pointer to the HW structure 229 * 230 * Checks the nvm for an alternate MAC address. An alternate MAC address 231 * can be setup by pre-boot software and must be treated like a permanent 232 * address and must override the actual permanent MAC address. If an 233 * alternate MAC address is fopund it is saved in the hw struct and 234 * prgrammed into RAR0 and the cuntion returns success, otherwise the 235 * function returns an error. 236 **/ 237s32 igb_check_alt_mac_addr(struct e1000_hw *hw) 238{ 239 u32 i; 240 s32 ret_val = 0; 241 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 242 u8 alt_mac_addr[ETH_ALEN]; 243 244 /* 245 * Alternate MAC address is handled by the option ROM for 82580 246 * and newer. SW support not required. 247 */ 248 if (hw->mac.type >= e1000_82580) 249 goto out; 250 251 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 252 &nvm_alt_mac_addr_offset); 253 if (ret_val) { 254 hw_dbg("NVM Read Error\n"); 255 goto out; 256 } 257 258 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 259 (nvm_alt_mac_addr_offset == 0x0000)) 260 /* There is no Alternate MAC Address */ 261 goto out; 262 263 if (hw->bus.func == E1000_FUNC_1) 264 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 265 if (hw->bus.func == E1000_FUNC_2) 266 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 267 268 if (hw->bus.func == E1000_FUNC_3) 269 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 270 for (i = 0; i < ETH_ALEN; i += 2) { 271 offset = nvm_alt_mac_addr_offset + (i >> 1); 272 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 273 if (ret_val) { 274 hw_dbg("NVM Read Error\n"); 275 goto out; 276 } 277 278 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 279 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 280 } 281 282 /* if multicast bit is set, the alternate address will not be used */ 283 if (is_multicast_ether_addr(alt_mac_addr)) { 284 hw_dbg("Ignoring Alternate Mac Address with MC bit set\n"); 285 goto out; 286 } 287 288 /* 289 * We have a valid alternate MAC address, and we want to treat it the 290 * same as the normal permanent MAC address stored by the HW into the 291 * RAR. Do this by mapping this address into RAR0. 292 */ 293 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 294 295out: 296 return ret_val; 297} 298 299/** 300 * igb_rar_set - Set receive address register 301 * @hw: pointer to the HW structure 302 * @addr: pointer to the receive address 303 * @index: receive address array register 304 * 305 * Sets the receive address array register at index to the address passed 306 * in by addr. 307 **/ 308void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) 309{ 310 u32 rar_low, rar_high; 311 312 /* 313 * HW expects these in little endian so we reverse the byte order 314 * from network order (big endian) to little endian 315 */ 316 rar_low = ((u32) addr[0] | 317 ((u32) addr[1] << 8) | 318 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 319 320 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 321 322 /* If MAC address zero, no need to set the AV bit */ 323 if (rar_low || rar_high) 324 rar_high |= E1000_RAH_AV; 325 326 /* 327 * Some bridges will combine consecutive 32-bit writes into 328 * a single burst write, which will malfunction on some parts. 329 * The flushes avoid this. 330 */ 331 wr32(E1000_RAL(index), rar_low); 332 wrfl(); 333 wr32(E1000_RAH(index), rar_high); 334 wrfl(); 335} 336 337/** 338 * igb_mta_set - Set multicast filter table address 339 * @hw: pointer to the HW structure 340 * @hash_value: determines the MTA register and bit to set 341 * 342 * The multicast table address is a register array of 32-bit registers. 343 * The hash_value is used to determine what register the bit is in, the 344 * current value is read, the new bit is OR'd in and the new value is 345 * written back into the register. 346 **/ 347void igb_mta_set(struct e1000_hw *hw, u32 hash_value) 348{ 349 u32 hash_bit, hash_reg, mta; 350 351 /* 352 * The MTA is a register array of 32-bit registers. It is 353 * treated like an array of (32*mta_reg_count) bits. We want to 354 * set bit BitArray[hash_value]. So we figure out what register 355 * the bit is in, read it, OR in the new bit, then write 356 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 357 * mask to bits 31:5 of the hash value which gives us the 358 * register we're modifying. The hash bit within that register 359 * is determined by the lower 5 bits of the hash value. 360 */ 361 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 362 hash_bit = hash_value & 0x1F; 363 364 mta = array_rd32(E1000_MTA, hash_reg); 365 366 mta |= (1 << hash_bit); 367 368 array_wr32(E1000_MTA, hash_reg, mta); 369 wrfl(); 370} 371 372/** 373 * igb_hash_mc_addr - Generate a multicast hash value 374 * @hw: pointer to the HW structure 375 * @mc_addr: pointer to a multicast address 376 * 377 * Generates a multicast address hash value which is used to determine 378 * the multicast filter table array address and new table value. See 379 * igb_mta_set() 380 **/ 381static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 382{ 383 u32 hash_value, hash_mask; 384 u8 bit_shift = 0; 385 386 /* Register count multiplied by bits per register */ 387 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 388 389 /* 390 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 391 * where 0xFF would still fall within the hash mask. 392 */ 393 while (hash_mask >> bit_shift != 0xFF) 394 bit_shift++; 395 396 /* 397 * The portion of the address that is used for the hash table 398 * is determined by the mc_filter_type setting. 399 * The algorithm is such that there is a total of 8 bits of shifting. 400 * The bit_shift for a mc_filter_type of 0 represents the number of 401 * left-shifts where the MSB of mc_addr[5] would still fall within 402 * the hash_mask. Case 0 does this exactly. Since there are a total 403 * of 8 bits of shifting, then mc_addr[4] will shift right the 404 * remaining number of bits. Thus 8 - bit_shift. The rest of the 405 * cases are a variation of this algorithm...essentially raising the 406 * number of bits to shift mc_addr[5] left, while still keeping the 407 * 8-bit shifting total. 408 * 409 * For example, given the following Destination MAC Address and an 410 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 411 * we can see that the bit_shift for case 0 is 4. These are the hash 412 * values resulting from each mc_filter_type... 413 * [0] [1] [2] [3] [4] [5] 414 * 01 AA 00 12 34 56 415 * LSB MSB 416 * 417 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 418 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 419 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 420 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 421 */ 422 switch (hw->mac.mc_filter_type) { 423 default: 424 case 0: 425 break; 426 case 1: 427 bit_shift += 1; 428 break; 429 case 2: 430 bit_shift += 2; 431 break; 432 case 3: 433 bit_shift += 4; 434 break; 435 } 436 437 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 438 (((u16) mc_addr[5]) << bit_shift))); 439 440 return hash_value; 441} 442 443/** 444 * igb_update_mc_addr_list - Update Multicast addresses 445 * @hw: pointer to the HW structure 446 * @mc_addr_list: array of multicast addresses to program 447 * @mc_addr_count: number of multicast addresses to program 448 * 449 * Updates entire Multicast Table Array. 450 * The caller must have a packed mc_addr_list of multicast addresses. 451 **/ 452void igb_update_mc_addr_list(struct e1000_hw *hw, 453 u8 *mc_addr_list, u32 mc_addr_count) 454{ 455 u32 hash_value, hash_bit, hash_reg; 456 int i; 457 458 /* clear mta_shadow */ 459 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 460 461 /* update mta_shadow from mc_addr_list */ 462 for (i = 0; (u32) i < mc_addr_count; i++) { 463 hash_value = igb_hash_mc_addr(hw, mc_addr_list); 464 465 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 466 hash_bit = hash_value & 0x1F; 467 468 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 469 mc_addr_list += (ETH_ALEN); 470 } 471 472 /* replace the entire MTA table */ 473 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 474 array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]); 475 wrfl(); 476} 477 478/** 479 * igb_clear_hw_cntrs_base - Clear base hardware counters 480 * @hw: pointer to the HW structure 481 * 482 * Clears the base hardware counters by reading the counter registers. 483 **/ 484void igb_clear_hw_cntrs_base(struct e1000_hw *hw) 485{ 486 rd32(E1000_CRCERRS); 487 rd32(E1000_SYMERRS); 488 rd32(E1000_MPC); 489 rd32(E1000_SCC); 490 rd32(E1000_ECOL); 491 rd32(E1000_MCC); 492 rd32(E1000_LATECOL); 493 rd32(E1000_COLC); 494 rd32(E1000_DC); 495 rd32(E1000_SEC); 496 rd32(E1000_RLEC); 497 rd32(E1000_XONRXC); 498 rd32(E1000_XONTXC); 499 rd32(E1000_XOFFRXC); 500 rd32(E1000_XOFFTXC); 501 rd32(E1000_FCRUC); 502 rd32(E1000_GPRC); 503 rd32(E1000_BPRC); 504 rd32(E1000_MPRC); 505 rd32(E1000_GPTC); 506 rd32(E1000_GORCL); 507 rd32(E1000_GORCH); 508 rd32(E1000_GOTCL); 509 rd32(E1000_GOTCH); 510 rd32(E1000_RNBC); 511 rd32(E1000_RUC); 512 rd32(E1000_RFC); 513 rd32(E1000_ROC); 514 rd32(E1000_RJC); 515 rd32(E1000_TORL); 516 rd32(E1000_TORH); 517 rd32(E1000_TOTL); 518 rd32(E1000_TOTH); 519 rd32(E1000_TPR); 520 rd32(E1000_TPT); 521 rd32(E1000_MPTC); 522 rd32(E1000_BPTC); 523} 524 525/** 526 * igb_check_for_copper_link - Check for link (Copper) 527 * @hw: pointer to the HW structure 528 * 529 * Checks to see of the link status of the hardware has changed. If a 530 * change in link status has been detected, then we read the PHY registers 531 * to get the current speed/duplex if link exists. 532 **/ 533s32 igb_check_for_copper_link(struct e1000_hw *hw) 534{ 535 struct e1000_mac_info *mac = &hw->mac; 536 s32 ret_val; 537 bool link; 538 539 /* 540 * We only want to go out to the PHY registers to see if Auto-Neg 541 * has completed and/or if our link status has changed. The 542 * get_link_status flag is set upon receiving a Link Status 543 * Change or Rx Sequence Error interrupt. 544 */ 545 if (!mac->get_link_status) { 546 ret_val = 0; 547 goto out; 548 } 549 550 /* 551 * First we want to see if the MII Status Register reports 552 * link. If so, then we want to get the current speed/duplex 553 * of the PHY. 554 */ 555 ret_val = igb_phy_has_link(hw, 1, 0, &link); 556 if (ret_val) 557 goto out; 558 559 if (!link) 560 goto out; /* No link detected */ 561 562 mac->get_link_status = false; 563 564 /* 565 * Check if there was DownShift, must be checked 566 * immediately after link-up 567 */ 568 igb_check_downshift(hw); 569 570 /* 571 * If we are forcing speed/duplex, then we simply return since 572 * we have already determined whether we have link or not. 573 */ 574 if (!mac->autoneg) { 575 ret_val = -E1000_ERR_CONFIG; 576 goto out; 577 } 578 579 /* 580 * Auto-Neg is enabled. Auto Speed Detection takes care 581 * of MAC speed/duplex configuration. So we only need to 582 * configure Collision Distance in the MAC. 583 */ 584 igb_config_collision_dist(hw); 585 586 /* 587 * Configure Flow Control now that Auto-Neg has completed. 588 * First, we need to restore the desired flow control 589 * settings because we may have had to re-autoneg with a 590 * different link partner. 591 */ 592 ret_val = igb_config_fc_after_link_up(hw); 593 if (ret_val) 594 hw_dbg("Error configuring flow control\n"); 595 596out: 597 return ret_val; 598} 599 600/** 601 * igb_setup_link - Setup flow control and link settings 602 * @hw: pointer to the HW structure 603 * 604 * Determines which flow control settings to use, then configures flow 605 * control. Calls the appropriate media-specific link configuration 606 * function. Assuming the adapter has a valid link partner, a valid link 607 * should be established. Assumes the hardware has previously been reset 608 * and the transmitter and receiver are not enabled. 609 **/ 610s32 igb_setup_link(struct e1000_hw *hw) 611{ 612 s32 ret_val = 0; 613 614 /* 615 * In the case of the phy reset being blocked, we already have a link. 616 * We do not need to set it up again. 617 */ 618 if (igb_check_reset_block(hw)) 619 goto out; 620 621 /* 622 * If requested flow control is set to default, set flow control 623 * based on the EEPROM flow control settings. 624 */ 625 if (hw->fc.requested_mode == e1000_fc_default) { 626 ret_val = igb_set_default_fc(hw); 627 if (ret_val) 628 goto out; 629 } 630 631 /* 632 * We want to save off the original Flow Control configuration just 633 * in case we get disconnected and then reconnected into a different 634 * hub or switch with different Flow Control capabilities. 635 */ 636 hw->fc.current_mode = hw->fc.requested_mode; 637 638 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 639 640 /* Call the necessary media_type subroutine to configure the link. */ 641 ret_val = hw->mac.ops.setup_physical_interface(hw); 642 if (ret_val) 643 goto out; 644 645 /* 646 * Initialize the flow control address, type, and PAUSE timer 647 * registers to their default values. This is done even if flow 648 * control is disabled, because it does not hurt anything to 649 * initialize these registers. 650 */ 651 hw_dbg("Initializing the Flow Control address, type and timer regs\n"); 652 wr32(E1000_FCT, FLOW_CONTROL_TYPE); 653 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 654 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 655 656 wr32(E1000_FCTTV, hw->fc.pause_time); 657 658 ret_val = igb_set_fc_watermarks(hw); 659 660out: 661 return ret_val; 662} 663 664/** 665 * igb_config_collision_dist - Configure collision distance 666 * @hw: pointer to the HW structure 667 * 668 * Configures the collision distance to the default value and is used 669 * during link setup. Currently no func pointer exists and all 670 * implementations are handled in the generic version of this function. 671 **/ 672void igb_config_collision_dist(struct e1000_hw *hw) 673{ 674 u32 tctl; 675 676 tctl = rd32(E1000_TCTL); 677 678 tctl &= ~E1000_TCTL_COLD; 679 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 680 681 wr32(E1000_TCTL, tctl); 682 wrfl(); 683} 684 685/** 686 * igb_set_fc_watermarks - Set flow control high/low watermarks 687 * @hw: pointer to the HW structure 688 * 689 * Sets the flow control high/low threshold (watermark) registers. If 690 * flow control XON frame transmission is enabled, then set XON frame 691 * tansmission as well. 692 **/ 693static s32 igb_set_fc_watermarks(struct e1000_hw *hw) 694{ 695 s32 ret_val = 0; 696 u32 fcrtl = 0, fcrth = 0; 697 698 /* 699 * Set the flow control receive threshold registers. Normally, 700 * these registers will be set to a default threshold that may be 701 * adjusted later by the driver's runtime code. However, if the 702 * ability to transmit pause frames is not enabled, then these 703 * registers will be set to 0. 704 */ 705 if (hw->fc.current_mode & e1000_fc_tx_pause) { 706 /* 707 * We need to set up the Receive Threshold high and low water 708 * marks as well as (optionally) enabling the transmission of 709 * XON frames. 710 */ 711 fcrtl = hw->fc.low_water; 712 if (hw->fc.send_xon) 713 fcrtl |= E1000_FCRTL_XONE; 714 715 fcrth = hw->fc.high_water; 716 } 717 wr32(E1000_FCRTL, fcrtl); 718 wr32(E1000_FCRTH, fcrth); 719 720 return ret_val; 721} 722 723/** 724 * igb_set_default_fc - Set flow control default values 725 * @hw: pointer to the HW structure 726 * 727 * Read the EEPROM for the default values for flow control and store the 728 * values. 729 **/ 730static s32 igb_set_default_fc(struct e1000_hw *hw) 731{ 732 s32 ret_val = 0; 733 u16 nvm_data; 734 735 /* 736 * Read and store word 0x0F of the EEPROM. This word contains bits 737 * that determine the hardware's default PAUSE (flow control) mode, 738 * a bit that determines whether the HW defaults to enabling or 739 * disabling auto-negotiation, and the direction of the 740 * SW defined pins. If there is no SW over-ride of the flow 741 * control setting, then the variable hw->fc will 742 * be initialized based on a value in the EEPROM. 743 */ 744 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 745 746 if (ret_val) { 747 hw_dbg("NVM Read Error\n"); 748 goto out; 749 } 750 751 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 752 hw->fc.requested_mode = e1000_fc_none; 753 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 754 NVM_WORD0F_ASM_DIR) 755 hw->fc.requested_mode = e1000_fc_tx_pause; 756 else 757 hw->fc.requested_mode = e1000_fc_full; 758 759out: 760 return ret_val; 761} 762 763/** 764 * igb_force_mac_fc - Force the MAC's flow control settings 765 * @hw: pointer to the HW structure 766 * 767 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 768 * device control register to reflect the adapter settings. TFCE and RFCE 769 * need to be explicitly set by software when a copper PHY is used because 770 * autonegotiation is managed by the PHY rather than the MAC. Software must 771 * also configure these bits when link is forced on a fiber connection. 772 **/ 773s32 igb_force_mac_fc(struct e1000_hw *hw) 774{ 775 u32 ctrl; 776 s32 ret_val = 0; 777 778 ctrl = rd32(E1000_CTRL); 779 780 /* 781 * Because we didn't get link via the internal auto-negotiation 782 * mechanism (we either forced link or we got link via PHY 783 * auto-neg), we have to manually enable/disable transmit an 784 * receive flow control. 785 * 786 * The "Case" statement below enables/disable flow control 787 * according to the "hw->fc.current_mode" parameter. 788 * 789 * The possible values of the "fc" parameter are: 790 * 0: Flow control is completely disabled 791 * 1: Rx flow control is enabled (we can receive pause 792 * frames but not send pause frames). 793 * 2: Tx flow control is enabled (we can send pause frames 794 * frames but we do not receive pause frames). 795 * 3: Both Rx and TX flow control (symmetric) is enabled. 796 * other: No other values should be possible at this point. 797 */ 798 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); 799 800 switch (hw->fc.current_mode) { 801 case e1000_fc_none: 802 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 803 break; 804 case e1000_fc_rx_pause: 805 ctrl &= (~E1000_CTRL_TFCE); 806 ctrl |= E1000_CTRL_RFCE; 807 break; 808 case e1000_fc_tx_pause: 809 ctrl &= (~E1000_CTRL_RFCE); 810 ctrl |= E1000_CTRL_TFCE; 811 break; 812 case e1000_fc_full: 813 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 814 break; 815 default: 816 hw_dbg("Flow control param set incorrectly\n"); 817 ret_val = -E1000_ERR_CONFIG; 818 goto out; 819 } 820 821 wr32(E1000_CTRL, ctrl); 822 823out: 824 return ret_val; 825} 826 827/** 828 * igb_config_fc_after_link_up - Configures flow control after link 829 * @hw: pointer to the HW structure 830 * 831 * Checks the status of auto-negotiation after link up to ensure that the 832 * speed and duplex were not forced. If the link needed to be forced, then 833 * flow control needs to be forced also. If auto-negotiation is enabled 834 * and did not fail, then we configure flow control based on our link 835 * partner. 836 **/ 837s32 igb_config_fc_after_link_up(struct e1000_hw *hw) 838{ 839 struct e1000_mac_info *mac = &hw->mac; 840 s32 ret_val = 0; 841 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 842 u16 speed, duplex; 843 844 /* 845 * Check for the case where we have fiber media and auto-neg failed 846 * so we had to force link. In this case, we need to force the 847 * configuration of the MAC to match the "fc" parameter. 848 */ 849 if (mac->autoneg_failed) { 850 if (hw->phy.media_type == e1000_media_type_internal_serdes) 851 ret_val = igb_force_mac_fc(hw); 852 } else { 853 if (hw->phy.media_type == e1000_media_type_copper) 854 ret_val = igb_force_mac_fc(hw); 855 } 856 857 if (ret_val) { 858 hw_dbg("Error forcing flow control settings\n"); 859 goto out; 860 } 861 862 /* 863 * Check for the case where we have copper media and auto-neg is 864 * enabled. In this case, we need to check and see if Auto-Neg 865 * has completed, and if so, how the PHY and link partner has 866 * flow control configured. 867 */ 868 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 869 /* 870 * Read the MII Status Register and check to see if AutoNeg 871 * has completed. We read this twice because this reg has 872 * some "sticky" (latched) bits. 873 */ 874 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, 875 &mii_status_reg); 876 if (ret_val) 877 goto out; 878 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, 879 &mii_status_reg); 880 if (ret_val) 881 goto out; 882 883 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 884 hw_dbg("Copper PHY and Auto Neg " 885 "has not completed.\n"); 886 goto out; 887 } 888 889 /* 890 * The AutoNeg process has completed, so we now need to 891 * read both the Auto Negotiation Advertisement 892 * Register (Address 4) and the Auto_Negotiation Base 893 * Page Ability Register (Address 5) to determine how 894 * flow control was negotiated. 895 */ 896 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 897 &mii_nway_adv_reg); 898 if (ret_val) 899 goto out; 900 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 901 &mii_nway_lp_ability_reg); 902 if (ret_val) 903 goto out; 904 905 /* 906 * Two bits in the Auto Negotiation Advertisement Register 907 * (Address 4) and two bits in the Auto Negotiation Base 908 * Page Ability Register (Address 5) determine flow control 909 * for both the PHY and the link partner. The following 910 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 911 * 1999, describes these PAUSE resolution bits and how flow 912 * control is determined based upon these settings. 913 * NOTE: DC = Don't Care 914 * 915 * LOCAL DEVICE | LINK PARTNER 916 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 917 *-------|---------|-------|---------|-------------------- 918 * 0 | 0 | DC | DC | e1000_fc_none 919 * 0 | 1 | 0 | DC | e1000_fc_none 920 * 0 | 1 | 1 | 0 | e1000_fc_none 921 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 922 * 1 | 0 | 0 | DC | e1000_fc_none 923 * 1 | DC | 1 | DC | e1000_fc_full 924 * 1 | 1 | 0 | 0 | e1000_fc_none 925 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 926 * 927 * Are both PAUSE bits set to 1? If so, this implies 928 * Symmetric Flow Control is enabled at both ends. The 929 * ASM_DIR bits are irrelevant per the spec. 930 * 931 * For Symmetric Flow Control: 932 * 933 * LOCAL DEVICE | LINK PARTNER 934 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 935 *-------|---------|-------|---------|-------------------- 936 * 1 | DC | 1 | DC | E1000_fc_full 937 * 938 */ 939 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 940 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 941 /* 942 * Now we need to check if the user selected RX ONLY 943 * of pause frames. In this case, we had to advertise 944 * FULL flow control because we could not advertise RX 945 * ONLY. Hence, we must now check to see if we need to 946 * turn OFF the TRANSMISSION of PAUSE frames. 947 */ 948 if (hw->fc.requested_mode == e1000_fc_full) { 949 hw->fc.current_mode = e1000_fc_full; 950 hw_dbg("Flow Control = FULL.\r\n"); 951 } else { 952 hw->fc.current_mode = e1000_fc_rx_pause; 953 hw_dbg("Flow Control = " 954 "RX PAUSE frames only.\r\n"); 955 } 956 } 957 /* 958 * For receiving PAUSE frames ONLY. 959 * 960 * LOCAL DEVICE | LINK PARTNER 961 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 962 *-------|---------|-------|---------|-------------------- 963 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 964 */ 965 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 966 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 967 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 968 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 969 hw->fc.current_mode = e1000_fc_tx_pause; 970 hw_dbg("Flow Control = TX PAUSE frames only.\r\n"); 971 } 972 /* 973 * For transmitting PAUSE frames ONLY. 974 * 975 * LOCAL DEVICE | LINK PARTNER 976 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 977 *-------|---------|-------|---------|-------------------- 978 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 979 */ 980 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 981 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 982 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 983 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 984 hw->fc.current_mode = e1000_fc_rx_pause; 985 hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); 986 } 987 /* 988 * Per the IEEE spec, at this point flow control should be 989 * disabled. However, we want to consider that we could 990 * be connected to a legacy switch that doesn't advertise 991 * desired flow control, but can be forced on the link 992 * partner. So if we advertised no flow control, that is 993 * what we will resolve to. If we advertised some kind of 994 * receive capability (Rx Pause Only or Full Flow Control) 995 * and the link partner advertised none, we will configure 996 * ourselves to enable Rx Flow Control only. We can do 997 * this safely for two reasons: If the link partner really 998 * didn't want flow control enabled, and we enable Rx, no 999 * harm done since we won't be receiving any PAUSE frames 1000 * anyway. If the intent on the link partner was to have 1001 * flow control enabled, then by us enabling RX only, we 1002 * can at least receive pause frames and process them. 1003 * This is a good idea because in most cases, since we are 1004 * predominantly a server NIC, more times than not we will 1005 * be asked to delay transmission of packets than asking 1006 * our link partner to pause transmission of frames. 1007 */ 1008 else if ((hw->fc.requested_mode == e1000_fc_none || 1009 hw->fc.requested_mode == e1000_fc_tx_pause) || 1010 hw->fc.strict_ieee) { 1011 hw->fc.current_mode = e1000_fc_none; 1012 hw_dbg("Flow Control = NONE.\r\n"); 1013 } else { 1014 hw->fc.current_mode = e1000_fc_rx_pause; 1015 hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); 1016 } 1017 1018 /* 1019 * Now we need to do one last check... If we auto- 1020 * negotiated to HALF DUPLEX, flow control should not be 1021 * enabled per IEEE 802.3 spec. 1022 */ 1023 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); 1024 if (ret_val) { 1025 hw_dbg("Error getting link speed and duplex\n"); 1026 goto out; 1027 } 1028 1029 if (duplex == HALF_DUPLEX) 1030 hw->fc.current_mode = e1000_fc_none; 1031 1032 /* 1033 * Now we call a subroutine to actually force the MAC 1034 * controller to use the correct flow control settings. 1035 */ 1036 ret_val = igb_force_mac_fc(hw); 1037 if (ret_val) { 1038 hw_dbg("Error forcing flow control settings\n"); 1039 goto out; 1040 } 1041 } 1042 1043out: 1044 return ret_val; 1045} 1046 1047/** 1048 * igb_get_speed_and_duplex_copper - Retrieve current speed/duplex 1049 * @hw: pointer to the HW structure 1050 * @speed: stores the current speed 1051 * @duplex: stores the current duplex 1052 * 1053 * Read the status register for the current speed/duplex and store the current 1054 * speed and duplex for copper connections. 1055 **/ 1056s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, 1057 u16 *duplex) 1058{ 1059 u32 status; 1060 1061 status = rd32(E1000_STATUS); 1062 if (status & E1000_STATUS_SPEED_1000) { 1063 *speed = SPEED_1000; 1064 hw_dbg("1000 Mbs, "); 1065 } else if (status & E1000_STATUS_SPEED_100) { 1066 *speed = SPEED_100; 1067 hw_dbg("100 Mbs, "); 1068 } else { 1069 *speed = SPEED_10; 1070 hw_dbg("10 Mbs, "); 1071 } 1072 1073 if (status & E1000_STATUS_FD) { 1074 *duplex = FULL_DUPLEX; 1075 hw_dbg("Full Duplex\n"); 1076 } else { 1077 *duplex = HALF_DUPLEX; 1078 hw_dbg("Half Duplex\n"); 1079 } 1080 1081 return 0; 1082} 1083 1084/** 1085 * igb_get_hw_semaphore - Acquire hardware semaphore 1086 * @hw: pointer to the HW structure 1087 * 1088 * Acquire the HW semaphore to access the PHY or NVM 1089 **/ 1090s32 igb_get_hw_semaphore(struct e1000_hw *hw) 1091{ 1092 u32 swsm; 1093 s32 ret_val = 0; 1094 s32 timeout = hw->nvm.word_size + 1; 1095 s32 i = 0; 1096 1097 /* Get the SW semaphore */ 1098 while (i < timeout) { 1099 swsm = rd32(E1000_SWSM); 1100 if (!(swsm & E1000_SWSM_SMBI)) 1101 break; 1102 1103 udelay(50); 1104 i++; 1105 } 1106 1107 if (i == timeout) { 1108 hw_dbg("Driver can't access device - SMBI bit is set.\n"); 1109 ret_val = -E1000_ERR_NVM; 1110 goto out; 1111 } 1112 1113 /* Get the FW semaphore. */ 1114 for (i = 0; i < timeout; i++) { 1115 swsm = rd32(E1000_SWSM); 1116 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1117 1118 /* Semaphore acquired if bit latched */ 1119 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) 1120 break; 1121 1122 udelay(50); 1123 } 1124 1125 if (i == timeout) { 1126 /* Release semaphores */ 1127 igb_put_hw_semaphore(hw); 1128 hw_dbg("Driver can't access the NVM\n"); 1129 ret_val = -E1000_ERR_NVM; 1130 goto out; 1131 } 1132 1133out: 1134 return ret_val; 1135} 1136 1137/** 1138 * igb_put_hw_semaphore - Release hardware semaphore 1139 * @hw: pointer to the HW structure 1140 * 1141 * Release hardware semaphore used to access the PHY or NVM 1142 **/ 1143void igb_put_hw_semaphore(struct e1000_hw *hw) 1144{ 1145 u32 swsm; 1146 1147 swsm = rd32(E1000_SWSM); 1148 1149 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1150 1151 wr32(E1000_SWSM, swsm); 1152} 1153 1154/** 1155 * igb_get_auto_rd_done - Check for auto read completion 1156 * @hw: pointer to the HW structure 1157 * 1158 * Check EEPROM for Auto Read done bit. 1159 **/ 1160s32 igb_get_auto_rd_done(struct e1000_hw *hw) 1161{ 1162 s32 i = 0; 1163 s32 ret_val = 0; 1164 1165 1166 while (i < AUTO_READ_DONE_TIMEOUT) { 1167 if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD) 1168 break; 1169 msleep(1); 1170 i++; 1171 } 1172 1173 if (i == AUTO_READ_DONE_TIMEOUT) { 1174 hw_dbg("Auto read by HW from NVM has not completed.\n"); 1175 ret_val = -E1000_ERR_RESET; 1176 goto out; 1177 } 1178 1179out: 1180 return ret_val; 1181} 1182 1183/** 1184 * igb_valid_led_default - Verify a valid default LED config 1185 * @hw: pointer to the HW structure 1186 * @data: pointer to the NVM (EEPROM) 1187 * 1188 * Read the EEPROM for the current default LED configuration. If the 1189 * LED configuration is not valid, set to a valid LED configuration. 1190 **/ 1191static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data) 1192{ 1193 s32 ret_val; 1194 1195 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1196 if (ret_val) { 1197 hw_dbg("NVM Read Error\n"); 1198 goto out; 1199 } 1200 1201 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1202 switch(hw->phy.media_type) { 1203 case e1000_media_type_internal_serdes: 1204 *data = ID_LED_DEFAULT_82575_SERDES; 1205 break; 1206 case e1000_media_type_copper: 1207 default: 1208 *data = ID_LED_DEFAULT; 1209 break; 1210 } 1211 } 1212out: 1213 return ret_val; 1214} 1215 1216/** 1217 * igb_id_led_init - 1218 * @hw: pointer to the HW structure 1219 * 1220 **/ 1221s32 igb_id_led_init(struct e1000_hw *hw) 1222{ 1223 struct e1000_mac_info *mac = &hw->mac; 1224 s32 ret_val; 1225 const u32 ledctl_mask = 0x000000FF; 1226 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1227 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1228 u16 data, i, temp; 1229 const u16 led_mask = 0x0F; 1230 1231 ret_val = igb_valid_led_default(hw, &data); 1232 if (ret_val) 1233 goto out; 1234 1235 mac->ledctl_default = rd32(E1000_LEDCTL); 1236 mac->ledctl_mode1 = mac->ledctl_default; 1237 mac->ledctl_mode2 = mac->ledctl_default; 1238 1239 for (i = 0; i < 4; i++) { 1240 temp = (data >> (i << 2)) & led_mask; 1241 switch (temp) { 1242 case ID_LED_ON1_DEF2: 1243 case ID_LED_ON1_ON2: 1244 case ID_LED_ON1_OFF2: 1245 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1246 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1247 break; 1248 case ID_LED_OFF1_DEF2: 1249 case ID_LED_OFF1_ON2: 1250 case ID_LED_OFF1_OFF2: 1251 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1252 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1253 break; 1254 default: 1255 /* Do nothing */ 1256 break; 1257 } 1258 switch (temp) { 1259 case ID_LED_DEF1_ON2: 1260 case ID_LED_ON1_ON2: 1261 case ID_LED_OFF1_ON2: 1262 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1263 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1264 break; 1265 case ID_LED_DEF1_OFF2: 1266 case ID_LED_ON1_OFF2: 1267 case ID_LED_OFF1_OFF2: 1268 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1269 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1270 break; 1271 default: 1272 /* Do nothing */ 1273 break; 1274 } 1275 } 1276 1277out: 1278 return ret_val; 1279} 1280 1281/** 1282 * igb_cleanup_led - Set LED config to default operation 1283 * @hw: pointer to the HW structure 1284 * 1285 * Remove the current LED configuration and set the LED configuration 1286 * to the default value, saved from the EEPROM. 1287 **/ 1288s32 igb_cleanup_led(struct e1000_hw *hw) 1289{ 1290 wr32(E1000_LEDCTL, hw->mac.ledctl_default); 1291 return 0; 1292} 1293 1294/** 1295 * igb_blink_led - Blink LED 1296 * @hw: pointer to the HW structure 1297 * 1298 * Blink the led's which are set to be on. 1299 **/ 1300s32 igb_blink_led(struct e1000_hw *hw) 1301{ 1302 u32 ledctl_blink = 0; 1303 u32 i; 1304 1305 /* 1306 * set the blink bit for each LED that's "on" (0x0E) 1307 * in ledctl_mode2 1308 */ 1309 ledctl_blink = hw->mac.ledctl_mode2; 1310 for (i = 0; i < 4; i++) 1311 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1312 E1000_LEDCTL_MODE_LED_ON) 1313 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1314 (i * 8)); 1315 1316 wr32(E1000_LEDCTL, ledctl_blink); 1317 1318 return 0; 1319} 1320 1321/** 1322 * igb_led_off - Turn LED off 1323 * @hw: pointer to the HW structure 1324 * 1325 * Turn LED off. 1326 **/ 1327s32 igb_led_off(struct e1000_hw *hw) 1328{ 1329 switch (hw->phy.media_type) { 1330 case e1000_media_type_copper: 1331 wr32(E1000_LEDCTL, hw->mac.ledctl_mode1); 1332 break; 1333 default: 1334 break; 1335 } 1336 1337 return 0; 1338} 1339 1340/** 1341 * igb_disable_pcie_master - Disables PCI-express master access 1342 * @hw: pointer to the HW structure 1343 * 1344 * Returns 0 (0) if successful, else returns -10 1345 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued 1346 * the master requests to be disabled. 1347 * 1348 * Disables PCI-Express master access and verifies there are no pending 1349 * requests. 1350 **/ 1351s32 igb_disable_pcie_master(struct e1000_hw *hw) 1352{ 1353 u32 ctrl; 1354 s32 timeout = MASTER_DISABLE_TIMEOUT; 1355 s32 ret_val = 0; 1356 1357 if (hw->bus.type != e1000_bus_type_pci_express) 1358 goto out; 1359 1360 ctrl = rd32(E1000_CTRL); 1361 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1362 wr32(E1000_CTRL, ctrl); 1363 1364 while (timeout) { 1365 if (!(rd32(E1000_STATUS) & 1366 E1000_STATUS_GIO_MASTER_ENABLE)) 1367 break; 1368 udelay(100); 1369 timeout--; 1370 } 1371 1372 if (!timeout) { 1373 hw_dbg("Master requests are pending.\n"); 1374 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 1375 goto out; 1376 } 1377 1378out: 1379 return ret_val; 1380} 1381 1382/** 1383 * igb_validate_mdi_setting - Verify MDI/MDIx settings 1384 * @hw: pointer to the HW structure 1385 * 1386 * Verify that when not using auto-negotitation that MDI/MDIx is correctly 1387 * set, which is forced to MDI mode only. 1388 **/ 1389s32 igb_validate_mdi_setting(struct e1000_hw *hw) 1390{ 1391 s32 ret_val = 0; 1392 1393 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 1394 hw_dbg("Invalid MDI setting detected\n"); 1395 hw->phy.mdix = 1; 1396 ret_val = -E1000_ERR_CONFIG; 1397 goto out; 1398 } 1399 1400out: 1401 return ret_val; 1402} 1403 1404/** 1405 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register 1406 * @hw: pointer to the HW structure 1407 * @reg: 32bit register offset such as E1000_SCTL 1408 * @offset: register offset to write to 1409 * @data: data to write at register offset 1410 * 1411 * Writes an address/data control type register. There are several of these 1412 * and they all have the format address << 8 | data and bit 31 is polled for 1413 * completion. 1414 **/ 1415s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, 1416 u32 offset, u8 data) 1417{ 1418 u32 i, regvalue = 0; 1419 s32 ret_val = 0; 1420 1421 /* Set up the address and data */ 1422 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 1423 wr32(reg, regvalue); 1424 1425 /* Poll the ready bit to see if the MDI read completed */ 1426 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 1427 udelay(5); 1428 regvalue = rd32(reg); 1429 if (regvalue & E1000_GEN_CTL_READY) 1430 break; 1431 } 1432 if (!(regvalue & E1000_GEN_CTL_READY)) { 1433 hw_dbg("Reg %08x did not indicate ready\n", reg); 1434 ret_val = -E1000_ERR_PHY; 1435 goto out; 1436 } 1437 1438out: 1439 return ret_val; 1440} 1441 1442/** 1443 * igb_enable_mng_pass_thru - Enable processing of ARP's 1444 * @hw: pointer to the HW structure 1445 * 1446 * Verifies the hardware needs to leave interface enabled so that frames can 1447 * be directed to and from the management interface. 1448 **/ 1449bool igb_enable_mng_pass_thru(struct e1000_hw *hw) 1450{ 1451 u32 manc; 1452 u32 fwsm, factps; 1453 bool ret_val = false; 1454 1455 if (!hw->mac.asf_firmware_present) 1456 goto out; 1457 1458 manc = rd32(E1000_MANC); 1459 1460 if (!(manc & E1000_MANC_RCV_TCO_EN)) 1461 goto out; 1462 1463 if (hw->mac.arc_subsystem_valid) { 1464 fwsm = rd32(E1000_FWSM); 1465 factps = rd32(E1000_FACTPS); 1466 1467 if (!(factps & E1000_FACTPS_MNGCG) && 1468 ((fwsm & E1000_FWSM_MODE_MASK) == 1469 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { 1470 ret_val = true; 1471 goto out; 1472 } 1473 } else { 1474 if ((manc & E1000_MANC_SMBUS_EN) && 1475 !(manc & E1000_MANC_ASF_EN)) { 1476 ret_val = true; 1477 goto out; 1478 } 1479 } 1480 1481out: 1482 return ret_val; 1483} 1484