1/******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#include <linux/pci.h> 29#include <linux/delay.h> 30#include <linux/sched.h> 31#include <linux/netdevice.h> 32 33#include "ixgbe.h" 34#include "ixgbe_common.h" 35#include "ixgbe_phy.h" 36 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 43 u16 count); 44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 47static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 48 49static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 50static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw); 51static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw); 52static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw); 53static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw); 54static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 55 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); 56static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num); 57static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); 58static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 59 u16 words, u16 *data); 60static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 61 u16 words, u16 *data); 62static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 63 u16 offset); 64static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); 65 66/** 67 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 68 * @hw: pointer to hardware structure 69 * 70 * Starts the hardware by filling the bus info structure and media type, clears 71 * all on chip counters, initializes receive address registers, multicast 72 * table, VLAN filter table, calls routine to set up link and flow control 73 * settings, and leaves transmit and receive units disabled and uninitialized 74 **/ 75s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 76{ 77 u32 ctrl_ext; 78 79 /* Set the media type */ 80 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 81 82 /* Identify the PHY */ 83 hw->phy.ops.identify(hw); 84 85 /* Clear the VLAN filter table */ 86 hw->mac.ops.clear_vfta(hw); 87 88 /* Clear statistics registers */ 89 hw->mac.ops.clear_hw_cntrs(hw); 90 91 /* Set No Snoop Disable */ 92 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 93 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 94 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 95 IXGBE_WRITE_FLUSH(hw); 96 97 /* Setup flow control */ 98 ixgbe_setup_fc(hw, 0); 99 100 /* Clear adapter stopped flag */ 101 hw->adapter_stopped = false; 102 103 return 0; 104} 105 106/** 107 * ixgbe_start_hw_gen2 - Init sequence for common device family 108 * @hw: pointer to hw structure 109 * 110 * Performs the init sequence common to the second generation 111 * of 10 GbE devices. 112 * Devices in the second generation: 113 * 82599 114 * X540 115 **/ 116s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 117{ 118 u32 i; 119 u32 regval; 120 121 /* Clear the rate limiters */ 122 for (i = 0; i < hw->mac.max_tx_queues; i++) { 123 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 124 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 125 } 126 IXGBE_WRITE_FLUSH(hw); 127 128 /* Disable relaxed ordering */ 129 for (i = 0; i < hw->mac.max_tx_queues; i++) { 130 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 131 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 132 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 133 } 134 135 for (i = 0; i < hw->mac.max_rx_queues; i++) { 136 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 137 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 138 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 139 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 140 } 141 142 return 0; 143} 144 145/** 146 * ixgbe_init_hw_generic - Generic hardware initialization 147 * @hw: pointer to hardware structure 148 * 149 * Initialize the hardware by resetting the hardware, filling the bus info 150 * structure and media type, clears all on chip counters, initializes receive 151 * address registers, multicast table, VLAN filter table, calls routine to set 152 * up link and flow control settings, and leaves transmit and receive units 153 * disabled and uninitialized 154 **/ 155s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 156{ 157 s32 status; 158 159 /* Reset the hardware */ 160 status = hw->mac.ops.reset_hw(hw); 161 162 if (status == 0) { 163 /* Start the HW */ 164 status = hw->mac.ops.start_hw(hw); 165 } 166 167 return status; 168} 169 170/** 171 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 172 * @hw: pointer to hardware structure 173 * 174 * Clears all hardware statistics counters by reading them from the hardware 175 * Statistics counters are clear on read. 176 **/ 177s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 178{ 179 u16 i = 0; 180 181 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 182 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 183 IXGBE_READ_REG(hw, IXGBE_ERRBC); 184 IXGBE_READ_REG(hw, IXGBE_MSPDC); 185 for (i = 0; i < 8; i++) 186 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 187 188 IXGBE_READ_REG(hw, IXGBE_MLFC); 189 IXGBE_READ_REG(hw, IXGBE_MRFC); 190 IXGBE_READ_REG(hw, IXGBE_RLEC); 191 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 192 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 193 if (hw->mac.type >= ixgbe_mac_82599EB) { 194 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 195 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 196 } else { 197 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 198 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 199 } 200 201 for (i = 0; i < 8; i++) { 202 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 203 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 204 if (hw->mac.type >= ixgbe_mac_82599EB) { 205 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 206 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 207 } else { 208 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 209 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 210 } 211 } 212 if (hw->mac.type >= ixgbe_mac_82599EB) 213 for (i = 0; i < 8; i++) 214 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 215 IXGBE_READ_REG(hw, IXGBE_PRC64); 216 IXGBE_READ_REG(hw, IXGBE_PRC127); 217 IXGBE_READ_REG(hw, IXGBE_PRC255); 218 IXGBE_READ_REG(hw, IXGBE_PRC511); 219 IXGBE_READ_REG(hw, IXGBE_PRC1023); 220 IXGBE_READ_REG(hw, IXGBE_PRC1522); 221 IXGBE_READ_REG(hw, IXGBE_GPRC); 222 IXGBE_READ_REG(hw, IXGBE_BPRC); 223 IXGBE_READ_REG(hw, IXGBE_MPRC); 224 IXGBE_READ_REG(hw, IXGBE_GPTC); 225 IXGBE_READ_REG(hw, IXGBE_GORCL); 226 IXGBE_READ_REG(hw, IXGBE_GORCH); 227 IXGBE_READ_REG(hw, IXGBE_GOTCL); 228 IXGBE_READ_REG(hw, IXGBE_GOTCH); 229 if (hw->mac.type == ixgbe_mac_82598EB) 230 for (i = 0; i < 8; i++) 231 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 232 IXGBE_READ_REG(hw, IXGBE_RUC); 233 IXGBE_READ_REG(hw, IXGBE_RFC); 234 IXGBE_READ_REG(hw, IXGBE_ROC); 235 IXGBE_READ_REG(hw, IXGBE_RJC); 236 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 237 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 238 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 239 IXGBE_READ_REG(hw, IXGBE_TORL); 240 IXGBE_READ_REG(hw, IXGBE_TORH); 241 IXGBE_READ_REG(hw, IXGBE_TPR); 242 IXGBE_READ_REG(hw, IXGBE_TPT); 243 IXGBE_READ_REG(hw, IXGBE_PTC64); 244 IXGBE_READ_REG(hw, IXGBE_PTC127); 245 IXGBE_READ_REG(hw, IXGBE_PTC255); 246 IXGBE_READ_REG(hw, IXGBE_PTC511); 247 IXGBE_READ_REG(hw, IXGBE_PTC1023); 248 IXGBE_READ_REG(hw, IXGBE_PTC1522); 249 IXGBE_READ_REG(hw, IXGBE_MPTC); 250 IXGBE_READ_REG(hw, IXGBE_BPTC); 251 for (i = 0; i < 16; i++) { 252 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 253 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 254 if (hw->mac.type >= ixgbe_mac_82599EB) { 255 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 256 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 257 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 258 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 259 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 260 } else { 261 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 262 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 263 } 264 } 265 266 if (hw->mac.type == ixgbe_mac_X540) { 267 if (hw->phy.id == 0) 268 hw->phy.ops.identify(hw); 269 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); 270 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); 271 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); 272 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); 273 } 274 275 return 0; 276} 277 278/** 279 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 280 * @hw: pointer to hardware structure 281 * @pba_num: stores the part number string from the EEPROM 282 * @pba_num_size: part number string buffer length 283 * 284 * Reads the part number string from the EEPROM. 285 **/ 286s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 287 u32 pba_num_size) 288{ 289 s32 ret_val; 290 u16 data; 291 u16 pba_ptr; 292 u16 offset; 293 u16 length; 294 295 if (pba_num == NULL) { 296 hw_dbg(hw, "PBA string buffer was null\n"); 297 return IXGBE_ERR_INVALID_ARGUMENT; 298 } 299 300 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 301 if (ret_val) { 302 hw_dbg(hw, "NVM Read Error\n"); 303 return ret_val; 304 } 305 306 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 307 if (ret_val) { 308 hw_dbg(hw, "NVM Read Error\n"); 309 return ret_val; 310 } 311 312 /* 313 * if data is not ptr guard the PBA must be in legacy format which 314 * means pba_ptr is actually our second data word for the PBA number 315 * and we can decode it into an ascii string 316 */ 317 if (data != IXGBE_PBANUM_PTR_GUARD) { 318 hw_dbg(hw, "NVM PBA number is not stored as string\n"); 319 320 /* we will need 11 characters to store the PBA */ 321 if (pba_num_size < 11) { 322 hw_dbg(hw, "PBA string buffer too small\n"); 323 return IXGBE_ERR_NO_SPACE; 324 } 325 326 /* extract hex string from data and pba_ptr */ 327 pba_num[0] = (data >> 12) & 0xF; 328 pba_num[1] = (data >> 8) & 0xF; 329 pba_num[2] = (data >> 4) & 0xF; 330 pba_num[3] = data & 0xF; 331 pba_num[4] = (pba_ptr >> 12) & 0xF; 332 pba_num[5] = (pba_ptr >> 8) & 0xF; 333 pba_num[6] = '-'; 334 pba_num[7] = 0; 335 pba_num[8] = (pba_ptr >> 4) & 0xF; 336 pba_num[9] = pba_ptr & 0xF; 337 338 /* put a null character on the end of our string */ 339 pba_num[10] = '\0'; 340 341 /* switch all the data but the '-' to hex char */ 342 for (offset = 0; offset < 10; offset++) { 343 if (pba_num[offset] < 0xA) 344 pba_num[offset] += '0'; 345 else if (pba_num[offset] < 0x10) 346 pba_num[offset] += 'A' - 0xA; 347 } 348 349 return 0; 350 } 351 352 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 353 if (ret_val) { 354 hw_dbg(hw, "NVM Read Error\n"); 355 return ret_val; 356 } 357 358 if (length == 0xFFFF || length == 0) { 359 hw_dbg(hw, "NVM PBA number section invalid length\n"); 360 return IXGBE_ERR_PBA_SECTION; 361 } 362 363 /* check if pba_num buffer is big enough */ 364 if (pba_num_size < (((u32)length * 2) - 1)) { 365 hw_dbg(hw, "PBA string buffer too small\n"); 366 return IXGBE_ERR_NO_SPACE; 367 } 368 369 /* trim pba length from start of string */ 370 pba_ptr++; 371 length--; 372 373 for (offset = 0; offset < length; offset++) { 374 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 375 if (ret_val) { 376 hw_dbg(hw, "NVM Read Error\n"); 377 return ret_val; 378 } 379 pba_num[offset * 2] = (u8)(data >> 8); 380 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 381 } 382 pba_num[offset * 2] = '\0'; 383 384 return 0; 385} 386 387/** 388 * ixgbe_get_mac_addr_generic - Generic get MAC address 389 * @hw: pointer to hardware structure 390 * @mac_addr: Adapter MAC address 391 * 392 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 393 * A reset of the adapter must be performed prior to calling this function 394 * in order for the MAC address to have been loaded from the EEPROM into RAR0 395 **/ 396s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 397{ 398 u32 rar_high; 399 u32 rar_low; 400 u16 i; 401 402 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 403 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 404 405 for (i = 0; i < 4; i++) 406 mac_addr[i] = (u8)(rar_low >> (i*8)); 407 408 for (i = 0; i < 2; i++) 409 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 410 411 return 0; 412} 413 414/** 415 * ixgbe_get_bus_info_generic - Generic set PCI bus info 416 * @hw: pointer to hardware structure 417 * 418 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 419 **/ 420s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 421{ 422 struct ixgbe_adapter *adapter = hw->back; 423 struct ixgbe_mac_info *mac = &hw->mac; 424 u16 link_status; 425 426 hw->bus.type = ixgbe_bus_type_pci_express; 427 428 /* Get the negotiated link width and speed from PCI config space */ 429 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS, 430 &link_status); 431 432 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 433 case IXGBE_PCI_LINK_WIDTH_1: 434 hw->bus.width = ixgbe_bus_width_pcie_x1; 435 break; 436 case IXGBE_PCI_LINK_WIDTH_2: 437 hw->bus.width = ixgbe_bus_width_pcie_x2; 438 break; 439 case IXGBE_PCI_LINK_WIDTH_4: 440 hw->bus.width = ixgbe_bus_width_pcie_x4; 441 break; 442 case IXGBE_PCI_LINK_WIDTH_8: 443 hw->bus.width = ixgbe_bus_width_pcie_x8; 444 break; 445 default: 446 hw->bus.width = ixgbe_bus_width_unknown; 447 break; 448 } 449 450 switch (link_status & IXGBE_PCI_LINK_SPEED) { 451 case IXGBE_PCI_LINK_SPEED_2500: 452 hw->bus.speed = ixgbe_bus_speed_2500; 453 break; 454 case IXGBE_PCI_LINK_SPEED_5000: 455 hw->bus.speed = ixgbe_bus_speed_5000; 456 break; 457 default: 458 hw->bus.speed = ixgbe_bus_speed_unknown; 459 break; 460 } 461 462 mac->ops.set_lan_id(hw); 463 464 return 0; 465} 466 467/** 468 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 469 * @hw: pointer to the HW structure 470 * 471 * Determines the LAN function id by reading memory-mapped registers 472 * and swaps the port value if requested. 473 **/ 474void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 475{ 476 struct ixgbe_bus_info *bus = &hw->bus; 477 u32 reg; 478 479 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 480 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 481 bus->lan_id = bus->func; 482 483 /* check for a port swap */ 484 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 485 if (reg & IXGBE_FACTPS_LFS) 486 bus->func ^= 0x1; 487} 488 489/** 490 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 491 * @hw: pointer to hardware structure 492 * 493 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 494 * disables transmit and receive units. The adapter_stopped flag is used by 495 * the shared code and drivers to determine if the adapter is in a stopped 496 * state and should not touch the hardware. 497 **/ 498s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 499{ 500 u32 reg_val; 501 u16 i; 502 503 /* 504 * Set the adapter_stopped flag so other driver functions stop touching 505 * the hardware 506 */ 507 hw->adapter_stopped = true; 508 509 /* Disable the receive unit */ 510 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0); 511 512 /* Clear interrupt mask to stop interrupts from being generated */ 513 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 514 515 /* Clear any pending interrupts, flush previous writes */ 516 IXGBE_READ_REG(hw, IXGBE_EICR); 517 518 /* Disable the transmit unit. Each queue must be disabled. */ 519 for (i = 0; i < hw->mac.max_tx_queues; i++) 520 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 521 522 /* Disable the receive unit by stopping each queue */ 523 for (i = 0; i < hw->mac.max_rx_queues; i++) { 524 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 525 reg_val &= ~IXGBE_RXDCTL_ENABLE; 526 reg_val |= IXGBE_RXDCTL_SWFLSH; 527 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 528 } 529 530 /* flush all queues disables */ 531 IXGBE_WRITE_FLUSH(hw); 532 usleep_range(1000, 2000); 533 534 /* 535 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 536 * access and verify no pending requests 537 */ 538 return ixgbe_disable_pcie_master(hw); 539} 540 541/** 542 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 543 * @hw: pointer to hardware structure 544 * @index: led number to turn on 545 **/ 546s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 547{ 548 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 549 550 /* To turn on the LED, set mode to ON. */ 551 led_reg &= ~IXGBE_LED_MODE_MASK(index); 552 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 553 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 554 IXGBE_WRITE_FLUSH(hw); 555 556 return 0; 557} 558 559/** 560 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 561 * @hw: pointer to hardware structure 562 * @index: led number to turn off 563 **/ 564s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 565{ 566 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 567 568 /* To turn off the LED, set mode to OFF. */ 569 led_reg &= ~IXGBE_LED_MODE_MASK(index); 570 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 571 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 572 IXGBE_WRITE_FLUSH(hw); 573 574 return 0; 575} 576 577/** 578 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 579 * @hw: pointer to hardware structure 580 * 581 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 582 * ixgbe_hw struct in order to set up EEPROM access. 583 **/ 584s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 585{ 586 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 587 u32 eec; 588 u16 eeprom_size; 589 590 if (eeprom->type == ixgbe_eeprom_uninitialized) { 591 eeprom->type = ixgbe_eeprom_none; 592 /* Set default semaphore delay to 10ms which is a well 593 * tested value */ 594 eeprom->semaphore_delay = 10; 595 /* Clear EEPROM page size, it will be initialized as needed */ 596 eeprom->word_page_size = 0; 597 598 /* 599 * Check for EEPROM present first. 600 * If not present leave as none 601 */ 602 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 603 if (eec & IXGBE_EEC_PRES) { 604 eeprom->type = ixgbe_eeprom_spi; 605 606 /* 607 * SPI EEPROM is assumed here. This code would need to 608 * change if a future EEPROM is not SPI. 609 */ 610 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 611 IXGBE_EEC_SIZE_SHIFT); 612 eeprom->word_size = 1 << (eeprom_size + 613 IXGBE_EEPROM_WORD_SIZE_SHIFT); 614 } 615 616 if (eec & IXGBE_EEC_ADDR_SIZE) 617 eeprom->address_bits = 16; 618 else 619 eeprom->address_bits = 8; 620 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: " 621 "%d\n", eeprom->type, eeprom->word_size, 622 eeprom->address_bits); 623 } 624 625 return 0; 626} 627 628/** 629 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 630 * @hw: pointer to hardware structure 631 * @offset: offset within the EEPROM to write 632 * @words: number of words 633 * @data: 16 bit word(s) to write to EEPROM 634 * 635 * Reads 16 bit word(s) from EEPROM through bit-bang method 636 **/ 637s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 638 u16 words, u16 *data) 639{ 640 s32 status = 0; 641 u16 i, count; 642 643 hw->eeprom.ops.init_params(hw); 644 645 if (words == 0) { 646 status = IXGBE_ERR_INVALID_ARGUMENT; 647 goto out; 648 } 649 650 if (offset + words > hw->eeprom.word_size) { 651 status = IXGBE_ERR_EEPROM; 652 goto out; 653 } 654 655 /* 656 * The EEPROM page size cannot be queried from the chip. We do lazy 657 * initialization. It is worth to do that when we write large buffer. 658 */ 659 if ((hw->eeprom.word_page_size == 0) && 660 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 661 ixgbe_detect_eeprom_page_size_generic(hw, offset); 662 663 /* 664 * We cannot hold synchronization semaphores for too long 665 * to avoid other entity starvation. However it is more efficient 666 * to read in bursts than synchronizing access for each word. 667 */ 668 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 669 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 670 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 671 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 672 count, &data[i]); 673 674 if (status != 0) 675 break; 676 } 677 678out: 679 return status; 680} 681 682/** 683 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 684 * @hw: pointer to hardware structure 685 * @offset: offset within the EEPROM to be written to 686 * @words: number of word(s) 687 * @data: 16 bit word(s) to be written to the EEPROM 688 * 689 * If ixgbe_eeprom_update_checksum is not called after this function, the 690 * EEPROM will most likely contain an invalid checksum. 691 **/ 692static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 693 u16 words, u16 *data) 694{ 695 s32 status; 696 u16 word; 697 u16 page_size; 698 u16 i; 699 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 700 701 /* Prepare the EEPROM for writing */ 702 status = ixgbe_acquire_eeprom(hw); 703 704 if (status == 0) { 705 if (ixgbe_ready_eeprom(hw) != 0) { 706 ixgbe_release_eeprom(hw); 707 status = IXGBE_ERR_EEPROM; 708 } 709 } 710 711 if (status == 0) { 712 for (i = 0; i < words; i++) { 713 ixgbe_standby_eeprom(hw); 714 715 /* Send the WRITE ENABLE command (8 bit opcode ) */ 716 ixgbe_shift_out_eeprom_bits(hw, 717 IXGBE_EEPROM_WREN_OPCODE_SPI, 718 IXGBE_EEPROM_OPCODE_BITS); 719 720 ixgbe_standby_eeprom(hw); 721 722 /* 723 * Some SPI eeproms use the 8th address bit embedded 724 * in the opcode 725 */ 726 if ((hw->eeprom.address_bits == 8) && 727 ((offset + i) >= 128)) 728 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 729 730 /* Send the Write command (8-bit opcode + addr) */ 731 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 732 IXGBE_EEPROM_OPCODE_BITS); 733 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 734 hw->eeprom.address_bits); 735 736 page_size = hw->eeprom.word_page_size; 737 738 /* Send the data in burst via SPI*/ 739 do { 740 word = data[i]; 741 word = (word >> 8) | (word << 8); 742 ixgbe_shift_out_eeprom_bits(hw, word, 16); 743 744 if (page_size == 0) 745 break; 746 747 /* do not wrap around page */ 748 if (((offset + i) & (page_size - 1)) == 749 (page_size - 1)) 750 break; 751 } while (++i < words); 752 753 ixgbe_standby_eeprom(hw); 754 usleep_range(10000, 20000); 755 } 756 /* Done with writing - release the EEPROM */ 757 ixgbe_release_eeprom(hw); 758 } 759 760 return status; 761} 762 763/** 764 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 765 * @hw: pointer to hardware structure 766 * @offset: offset within the EEPROM to be written to 767 * @data: 16 bit word to be written to the EEPROM 768 * 769 * If ixgbe_eeprom_update_checksum is not called after this function, the 770 * EEPROM will most likely contain an invalid checksum. 771 **/ 772s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 773{ 774 s32 status; 775 776 hw->eeprom.ops.init_params(hw); 777 778 if (offset >= hw->eeprom.word_size) { 779 status = IXGBE_ERR_EEPROM; 780 goto out; 781 } 782 783 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 784 785out: 786 return status; 787} 788 789/** 790 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 791 * @hw: pointer to hardware structure 792 * @offset: offset within the EEPROM to be read 793 * @words: number of word(s) 794 * @data: read 16 bit words(s) from EEPROM 795 * 796 * Reads 16 bit word(s) from EEPROM through bit-bang method 797 **/ 798s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 799 u16 words, u16 *data) 800{ 801 s32 status = 0; 802 u16 i, count; 803 804 hw->eeprom.ops.init_params(hw); 805 806 if (words == 0) { 807 status = IXGBE_ERR_INVALID_ARGUMENT; 808 goto out; 809 } 810 811 if (offset + words > hw->eeprom.word_size) { 812 status = IXGBE_ERR_EEPROM; 813 goto out; 814 } 815 816 /* 817 * We cannot hold synchronization semaphores for too long 818 * to avoid other entity starvation. However it is more efficient 819 * to read in bursts than synchronizing access for each word. 820 */ 821 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 822 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 823 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 824 825 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 826 count, &data[i]); 827 828 if (status != 0) 829 break; 830 } 831 832out: 833 return status; 834} 835 836/** 837 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 838 * @hw: pointer to hardware structure 839 * @offset: offset within the EEPROM to be read 840 * @words: number of word(s) 841 * @data: read 16 bit word(s) from EEPROM 842 * 843 * Reads 16 bit word(s) from EEPROM through bit-bang method 844 **/ 845static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 846 u16 words, u16 *data) 847{ 848 s32 status; 849 u16 word_in; 850 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 851 u16 i; 852 853 /* Prepare the EEPROM for reading */ 854 status = ixgbe_acquire_eeprom(hw); 855 856 if (status == 0) { 857 if (ixgbe_ready_eeprom(hw) != 0) { 858 ixgbe_release_eeprom(hw); 859 status = IXGBE_ERR_EEPROM; 860 } 861 } 862 863 if (status == 0) { 864 for (i = 0; i < words; i++) { 865 ixgbe_standby_eeprom(hw); 866 /* 867 * Some SPI eeproms use the 8th address bit embedded 868 * in the opcode 869 */ 870 if ((hw->eeprom.address_bits == 8) && 871 ((offset + i) >= 128)) 872 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 873 874 /* Send the READ command (opcode + addr) */ 875 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 876 IXGBE_EEPROM_OPCODE_BITS); 877 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 878 hw->eeprom.address_bits); 879 880 /* Read the data. */ 881 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 882 data[i] = (word_in >> 8) | (word_in << 8); 883 } 884 885 /* End this read operation */ 886 ixgbe_release_eeprom(hw); 887 } 888 889 return status; 890} 891 892/** 893 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 894 * @hw: pointer to hardware structure 895 * @offset: offset within the EEPROM to be read 896 * @data: read 16 bit value from EEPROM 897 * 898 * Reads 16 bit value from EEPROM through bit-bang method 899 **/ 900s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 901 u16 *data) 902{ 903 s32 status; 904 905 hw->eeprom.ops.init_params(hw); 906 907 if (offset >= hw->eeprom.word_size) { 908 status = IXGBE_ERR_EEPROM; 909 goto out; 910 } 911 912 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 913 914out: 915 return status; 916} 917 918/** 919 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 920 * @hw: pointer to hardware structure 921 * @offset: offset of word in the EEPROM to read 922 * @words: number of word(s) 923 * @data: 16 bit word(s) from the EEPROM 924 * 925 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 926 **/ 927s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 928 u16 words, u16 *data) 929{ 930 u32 eerd; 931 s32 status = 0; 932 u32 i; 933 934 hw->eeprom.ops.init_params(hw); 935 936 if (words == 0) { 937 status = IXGBE_ERR_INVALID_ARGUMENT; 938 goto out; 939 } 940 941 if (offset >= hw->eeprom.word_size) { 942 status = IXGBE_ERR_EEPROM; 943 goto out; 944 } 945 946 for (i = 0; i < words; i++) { 947 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) + 948 IXGBE_EEPROM_RW_REG_START; 949 950 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 951 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 952 953 if (status == 0) { 954 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 955 IXGBE_EEPROM_RW_REG_DATA); 956 } else { 957 hw_dbg(hw, "Eeprom read timed out\n"); 958 goto out; 959 } 960 } 961out: 962 return status; 963} 964 965/** 966 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 967 * @hw: pointer to hardware structure 968 * @offset: offset within the EEPROM to be used as a scratch pad 969 * 970 * Discover EEPROM page size by writing marching data at given offset. 971 * This function is called only when we are writing a new large buffer 972 * at given offset so the data would be overwritten anyway. 973 **/ 974static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 975 u16 offset) 976{ 977 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 978 s32 status = 0; 979 u16 i; 980 981 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 982 data[i] = i; 983 984 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 985 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 986 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 987 hw->eeprom.word_page_size = 0; 988 if (status != 0) 989 goto out; 990 991 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 992 if (status != 0) 993 goto out; 994 995 /* 996 * When writing in burst more than the actual page size 997 * EEPROM address wraps around current page. 998 */ 999 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1000 1001 hw_dbg(hw, "Detected EEPROM page size = %d words.", 1002 hw->eeprom.word_page_size); 1003out: 1004 return status; 1005} 1006 1007/** 1008 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1009 * @hw: pointer to hardware structure 1010 * @offset: offset of word in the EEPROM to read 1011 * @data: word read from the EEPROM 1012 * 1013 * Reads a 16 bit word from the EEPROM using the EERD register. 1014 **/ 1015s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1016{ 1017 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1018} 1019 1020/** 1021 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1022 * @hw: pointer to hardware structure 1023 * @offset: offset of word in the EEPROM to write 1024 * @words: number of words 1025 * @data: word(s) write to the EEPROM 1026 * 1027 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1028 **/ 1029s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1030 u16 words, u16 *data) 1031{ 1032 u32 eewr; 1033 s32 status = 0; 1034 u16 i; 1035 1036 hw->eeprom.ops.init_params(hw); 1037 1038 if (words == 0) { 1039 status = IXGBE_ERR_INVALID_ARGUMENT; 1040 goto out; 1041 } 1042 1043 if (offset >= hw->eeprom.word_size) { 1044 status = IXGBE_ERR_EEPROM; 1045 goto out; 1046 } 1047 1048 for (i = 0; i < words; i++) { 1049 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1050 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1051 IXGBE_EEPROM_RW_REG_START; 1052 1053 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1054 if (status != 0) { 1055 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1056 goto out; 1057 } 1058 1059 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1060 1061 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1062 if (status != 0) { 1063 hw_dbg(hw, "Eeprom write EEWR timed out\n"); 1064 goto out; 1065 } 1066 } 1067 1068out: 1069 return status; 1070} 1071 1072/** 1073 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1074 * @hw: pointer to hardware structure 1075 * @offset: offset of word in the EEPROM to write 1076 * @data: word write to the EEPROM 1077 * 1078 * Write a 16 bit word to the EEPROM using the EEWR register. 1079 **/ 1080s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1081{ 1082 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1083} 1084 1085/** 1086 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1087 * @hw: pointer to hardware structure 1088 * @ee_reg: EEPROM flag for polling 1089 * 1090 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1091 * read or write is done respectively. 1092 **/ 1093static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1094{ 1095 u32 i; 1096 u32 reg; 1097 s32 status = IXGBE_ERR_EEPROM; 1098 1099 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1100 if (ee_reg == IXGBE_NVM_POLL_READ) 1101 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1102 else 1103 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1104 1105 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1106 status = 0; 1107 break; 1108 } 1109 udelay(5); 1110 } 1111 return status; 1112} 1113 1114/** 1115 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1116 * @hw: pointer to hardware structure 1117 * 1118 * Prepares EEPROM for access using bit-bang method. This function should 1119 * be called before issuing a command to the EEPROM. 1120 **/ 1121static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1122{ 1123 s32 status = 0; 1124 u32 eec; 1125 u32 i; 1126 1127 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) 1128 status = IXGBE_ERR_SWFW_SYNC; 1129 1130 if (status == 0) { 1131 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1132 1133 /* Request EEPROM Access */ 1134 eec |= IXGBE_EEC_REQ; 1135 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1136 1137 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1138 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1139 if (eec & IXGBE_EEC_GNT) 1140 break; 1141 udelay(5); 1142 } 1143 1144 /* Release if grant not acquired */ 1145 if (!(eec & IXGBE_EEC_GNT)) { 1146 eec &= ~IXGBE_EEC_REQ; 1147 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1148 hw_dbg(hw, "Could not acquire EEPROM grant\n"); 1149 1150 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1151 status = IXGBE_ERR_EEPROM; 1152 } 1153 1154 /* Setup EEPROM for Read/Write */ 1155 if (status == 0) { 1156 /* Clear CS and SK */ 1157 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1158 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1159 IXGBE_WRITE_FLUSH(hw); 1160 udelay(1); 1161 } 1162 } 1163 return status; 1164} 1165 1166/** 1167 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1168 * @hw: pointer to hardware structure 1169 * 1170 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1171 **/ 1172static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1173{ 1174 s32 status = IXGBE_ERR_EEPROM; 1175 u32 timeout = 2000; 1176 u32 i; 1177 u32 swsm; 1178 1179 /* Get SMBI software semaphore between device drivers first */ 1180 for (i = 0; i < timeout; i++) { 1181 /* 1182 * If the SMBI bit is 0 when we read it, then the bit will be 1183 * set and we have the semaphore 1184 */ 1185 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1186 if (!(swsm & IXGBE_SWSM_SMBI)) { 1187 status = 0; 1188 break; 1189 } 1190 udelay(50); 1191 } 1192 1193 if (i == timeout) { 1194 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore " 1195 "not granted.\n"); 1196 /* 1197 * this release is particularly important because our attempts 1198 * above to get the semaphore may have succeeded, and if there 1199 * was a timeout, we should unconditionally clear the semaphore 1200 * bits to free the driver to make progress 1201 */ 1202 ixgbe_release_eeprom_semaphore(hw); 1203 1204 udelay(50); 1205 /* 1206 * one last try 1207 * If the SMBI bit is 0 when we read it, then the bit will be 1208 * set and we have the semaphore 1209 */ 1210 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1211 if (!(swsm & IXGBE_SWSM_SMBI)) 1212 status = 0; 1213 } 1214 1215 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1216 if (status == 0) { 1217 for (i = 0; i < timeout; i++) { 1218 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1219 1220 /* Set the SW EEPROM semaphore bit to request access */ 1221 swsm |= IXGBE_SWSM_SWESMBI; 1222 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1223 1224 /* 1225 * If we set the bit successfully then we got the 1226 * semaphore. 1227 */ 1228 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1229 if (swsm & IXGBE_SWSM_SWESMBI) 1230 break; 1231 1232 udelay(50); 1233 } 1234 1235 /* 1236 * Release semaphores and return error if SW EEPROM semaphore 1237 * was not granted because we don't have access to the EEPROM 1238 */ 1239 if (i >= timeout) { 1240 hw_dbg(hw, "SWESMBI Software EEPROM semaphore " 1241 "not granted.\n"); 1242 ixgbe_release_eeprom_semaphore(hw); 1243 status = IXGBE_ERR_EEPROM; 1244 } 1245 } else { 1246 hw_dbg(hw, "Software semaphore SMBI between device drivers " 1247 "not granted.\n"); 1248 } 1249 1250 return status; 1251} 1252 1253/** 1254 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1255 * @hw: pointer to hardware structure 1256 * 1257 * This function clears hardware semaphore bits. 1258 **/ 1259static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1260{ 1261 u32 swsm; 1262 1263 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1264 1265 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1266 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1267 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1268 IXGBE_WRITE_FLUSH(hw); 1269} 1270 1271/** 1272 * ixgbe_ready_eeprom - Polls for EEPROM ready 1273 * @hw: pointer to hardware structure 1274 **/ 1275static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1276{ 1277 s32 status = 0; 1278 u16 i; 1279 u8 spi_stat_reg; 1280 1281 /* 1282 * Read "Status Register" repeatedly until the LSB is cleared. The 1283 * EEPROM will signal that the command has been completed by clearing 1284 * bit 0 of the internal status register. If it's not cleared within 1285 * 5 milliseconds, then error out. 1286 */ 1287 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1288 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1289 IXGBE_EEPROM_OPCODE_BITS); 1290 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1291 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1292 break; 1293 1294 udelay(5); 1295 ixgbe_standby_eeprom(hw); 1296 } 1297 1298 /* 1299 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1300 * devices (and only 0-5mSec on 5V devices) 1301 */ 1302 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1303 hw_dbg(hw, "SPI EEPROM Status error\n"); 1304 status = IXGBE_ERR_EEPROM; 1305 } 1306 1307 return status; 1308} 1309 1310/** 1311 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1312 * @hw: pointer to hardware structure 1313 **/ 1314static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1315{ 1316 u32 eec; 1317 1318 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1319 1320 /* Toggle CS to flush commands */ 1321 eec |= IXGBE_EEC_CS; 1322 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1323 IXGBE_WRITE_FLUSH(hw); 1324 udelay(1); 1325 eec &= ~IXGBE_EEC_CS; 1326 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1327 IXGBE_WRITE_FLUSH(hw); 1328 udelay(1); 1329} 1330 1331/** 1332 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1333 * @hw: pointer to hardware structure 1334 * @data: data to send to the EEPROM 1335 * @count: number of bits to shift out 1336 **/ 1337static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1338 u16 count) 1339{ 1340 u32 eec; 1341 u32 mask; 1342 u32 i; 1343 1344 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1345 1346 /* 1347 * Mask is used to shift "count" bits of "data" out to the EEPROM 1348 * one bit at a time. Determine the starting bit based on count 1349 */ 1350 mask = 0x01 << (count - 1); 1351 1352 for (i = 0; i < count; i++) { 1353 /* 1354 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1355 * "1", and then raising and then lowering the clock (the SK 1356 * bit controls the clock input to the EEPROM). A "0" is 1357 * shifted out to the EEPROM by setting "DI" to "0" and then 1358 * raising and then lowering the clock. 1359 */ 1360 if (data & mask) 1361 eec |= IXGBE_EEC_DI; 1362 else 1363 eec &= ~IXGBE_EEC_DI; 1364 1365 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1366 IXGBE_WRITE_FLUSH(hw); 1367 1368 udelay(1); 1369 1370 ixgbe_raise_eeprom_clk(hw, &eec); 1371 ixgbe_lower_eeprom_clk(hw, &eec); 1372 1373 /* 1374 * Shift mask to signify next bit of data to shift in to the 1375 * EEPROM 1376 */ 1377 mask = mask >> 1; 1378 } 1379 1380 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1381 eec &= ~IXGBE_EEC_DI; 1382 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1383 IXGBE_WRITE_FLUSH(hw); 1384} 1385 1386/** 1387 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1388 * @hw: pointer to hardware structure 1389 **/ 1390static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1391{ 1392 u32 eec; 1393 u32 i; 1394 u16 data = 0; 1395 1396 /* 1397 * In order to read a register from the EEPROM, we need to shift 1398 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1399 * the clock input to the EEPROM (setting the SK bit), and then reading 1400 * the value of the "DO" bit. During this "shifting in" process the 1401 * "DI" bit should always be clear. 1402 */ 1403 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1404 1405 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1406 1407 for (i = 0; i < count; i++) { 1408 data = data << 1; 1409 ixgbe_raise_eeprom_clk(hw, &eec); 1410 1411 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1412 1413 eec &= ~(IXGBE_EEC_DI); 1414 if (eec & IXGBE_EEC_DO) 1415 data |= 1; 1416 1417 ixgbe_lower_eeprom_clk(hw, &eec); 1418 } 1419 1420 return data; 1421} 1422 1423/** 1424 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1425 * @hw: pointer to hardware structure 1426 * @eec: EEC register's current value 1427 **/ 1428static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1429{ 1430 /* 1431 * Raise the clock input to the EEPROM 1432 * (setting the SK bit), then delay 1433 */ 1434 *eec = *eec | IXGBE_EEC_SK; 1435 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1436 IXGBE_WRITE_FLUSH(hw); 1437 udelay(1); 1438} 1439 1440/** 1441 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1442 * @hw: pointer to hardware structure 1443 * @eecd: EECD's current value 1444 **/ 1445static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1446{ 1447 /* 1448 * Lower the clock input to the EEPROM (clearing the SK bit), then 1449 * delay 1450 */ 1451 *eec = *eec & ~IXGBE_EEC_SK; 1452 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1453 IXGBE_WRITE_FLUSH(hw); 1454 udelay(1); 1455} 1456 1457/** 1458 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1459 * @hw: pointer to hardware structure 1460 **/ 1461static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1462{ 1463 u32 eec; 1464 1465 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1466 1467 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1468 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1469 1470 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1471 IXGBE_WRITE_FLUSH(hw); 1472 1473 udelay(1); 1474 1475 /* Stop requesting EEPROM access */ 1476 eec &= ~IXGBE_EEC_REQ; 1477 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1478 1479 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1480 1481 /* 1482 * Delay before attempt to obtain semaphore again to allow FW 1483 * access. semaphore_delay is in ms we need us for usleep_range 1484 */ 1485 usleep_range(hw->eeprom.semaphore_delay * 1000, 1486 hw->eeprom.semaphore_delay * 2000); 1487} 1488 1489/** 1490 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1491 * @hw: pointer to hardware structure 1492 **/ 1493u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1494{ 1495 u16 i; 1496 u16 j; 1497 u16 checksum = 0; 1498 u16 length = 0; 1499 u16 pointer = 0; 1500 u16 word = 0; 1501 1502 /* Include 0x0-0x3F in the checksum */ 1503 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1504 if (hw->eeprom.ops.read(hw, i, &word) != 0) { 1505 hw_dbg(hw, "EEPROM read failed\n"); 1506 break; 1507 } 1508 checksum += word; 1509 } 1510 1511 /* Include all data from pointers except for the fw pointer */ 1512 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1513 hw->eeprom.ops.read(hw, i, &pointer); 1514 1515 /* Make sure the pointer seems valid */ 1516 if (pointer != 0xFFFF && pointer != 0) { 1517 hw->eeprom.ops.read(hw, pointer, &length); 1518 1519 if (length != 0xFFFF && length != 0) { 1520 for (j = pointer+1; j <= pointer+length; j++) { 1521 hw->eeprom.ops.read(hw, j, &word); 1522 checksum += word; 1523 } 1524 } 1525 } 1526 } 1527 1528 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1529 1530 return checksum; 1531} 1532 1533/** 1534 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1535 * @hw: pointer to hardware structure 1536 * @checksum_val: calculated checksum 1537 * 1538 * Performs checksum calculation and validates the EEPROM checksum. If the 1539 * caller does not need checksum_val, the value can be NULL. 1540 **/ 1541s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1542 u16 *checksum_val) 1543{ 1544 s32 status; 1545 u16 checksum; 1546 u16 read_checksum = 0; 1547 1548 /* 1549 * Read the first word from the EEPROM. If this times out or fails, do 1550 * not continue or we could be in for a very long wait while every 1551 * EEPROM read fails 1552 */ 1553 status = hw->eeprom.ops.read(hw, 0, &checksum); 1554 1555 if (status == 0) { 1556 checksum = hw->eeprom.ops.calc_checksum(hw); 1557 1558 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1559 1560 /* 1561 * Verify read checksum from EEPROM is the same as 1562 * calculated checksum 1563 */ 1564 if (read_checksum != checksum) 1565 status = IXGBE_ERR_EEPROM_CHECKSUM; 1566 1567 /* If the user cares, return the calculated checksum */ 1568 if (checksum_val) 1569 *checksum_val = checksum; 1570 } else { 1571 hw_dbg(hw, "EEPROM read failed\n"); 1572 } 1573 1574 return status; 1575} 1576 1577/** 1578 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1579 * @hw: pointer to hardware structure 1580 **/ 1581s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1582{ 1583 s32 status; 1584 u16 checksum; 1585 1586 /* 1587 * Read the first word from the EEPROM. If this times out or fails, do 1588 * not continue or we could be in for a very long wait while every 1589 * EEPROM read fails 1590 */ 1591 status = hw->eeprom.ops.read(hw, 0, &checksum); 1592 1593 if (status == 0) { 1594 checksum = hw->eeprom.ops.calc_checksum(hw); 1595 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1596 checksum); 1597 } else { 1598 hw_dbg(hw, "EEPROM read failed\n"); 1599 } 1600 1601 return status; 1602} 1603 1604/** 1605 * ixgbe_validate_mac_addr - Validate MAC address 1606 * @mac_addr: pointer to MAC address. 1607 * 1608 * Tests a MAC address to ensure it is a valid Individual Address 1609 **/ 1610s32 ixgbe_validate_mac_addr(u8 *mac_addr) 1611{ 1612 s32 status = 0; 1613 1614 /* Make sure it is not a multicast address */ 1615 if (IXGBE_IS_MULTICAST(mac_addr)) 1616 status = IXGBE_ERR_INVALID_MAC_ADDR; 1617 /* Not a broadcast address */ 1618 else if (IXGBE_IS_BROADCAST(mac_addr)) 1619 status = IXGBE_ERR_INVALID_MAC_ADDR; 1620 /* Reject the zero address */ 1621 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1622 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) 1623 status = IXGBE_ERR_INVALID_MAC_ADDR; 1624 1625 return status; 1626} 1627 1628/** 1629 * ixgbe_set_rar_generic - Set Rx address register 1630 * @hw: pointer to hardware structure 1631 * @index: Receive address register to write 1632 * @addr: Address to put into receive address register 1633 * @vmdq: VMDq "set" or "pool" index 1634 * @enable_addr: set flag that address is active 1635 * 1636 * Puts an ethernet address into a receive address register. 1637 **/ 1638s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1639 u32 enable_addr) 1640{ 1641 u32 rar_low, rar_high; 1642 u32 rar_entries = hw->mac.num_rar_entries; 1643 1644 /* Make sure we are using a valid rar index range */ 1645 if (index >= rar_entries) { 1646 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1647 return IXGBE_ERR_INVALID_ARGUMENT; 1648 } 1649 1650 /* setup VMDq pool selection before this RAR gets enabled */ 1651 hw->mac.ops.set_vmdq(hw, index, vmdq); 1652 1653 /* 1654 * HW expects these in little endian so we reverse the byte 1655 * order from network order (big endian) to little endian 1656 */ 1657 rar_low = ((u32)addr[0] | 1658 ((u32)addr[1] << 8) | 1659 ((u32)addr[2] << 16) | 1660 ((u32)addr[3] << 24)); 1661 /* 1662 * Some parts put the VMDq setting in the extra RAH bits, 1663 * so save everything except the lower 16 bits that hold part 1664 * of the address and the address valid bit. 1665 */ 1666 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1667 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1668 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1669 1670 if (enable_addr != 0) 1671 rar_high |= IXGBE_RAH_AV; 1672 1673 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1674 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1675 1676 return 0; 1677} 1678 1679/** 1680 * ixgbe_clear_rar_generic - Remove Rx address register 1681 * @hw: pointer to hardware structure 1682 * @index: Receive address register to write 1683 * 1684 * Clears an ethernet address from a receive address register. 1685 **/ 1686s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1687{ 1688 u32 rar_high; 1689 u32 rar_entries = hw->mac.num_rar_entries; 1690 1691 /* Make sure we are using a valid rar index range */ 1692 if (index >= rar_entries) { 1693 hw_dbg(hw, "RAR index %d is out of range.\n", index); 1694 return IXGBE_ERR_INVALID_ARGUMENT; 1695 } 1696 1697 /* 1698 * Some parts put the VMDq setting in the extra RAH bits, 1699 * so save everything except the lower 16 bits that hold part 1700 * of the address and the address valid bit. 1701 */ 1702 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1703 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1704 1705 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1706 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1707 1708 /* clear VMDq pool/queue selection for this RAR */ 1709 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1710 1711 return 0; 1712} 1713 1714/** 1715 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1716 * @hw: pointer to hardware structure 1717 * 1718 * Places the MAC address in receive address register 0 and clears the rest 1719 * of the receive address registers. Clears the multicast table. Assumes 1720 * the receiver is in reset when the routine is called. 1721 **/ 1722s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1723{ 1724 u32 i; 1725 u32 rar_entries = hw->mac.num_rar_entries; 1726 1727 /* 1728 * If the current mac address is valid, assume it is a software override 1729 * to the permanent address. 1730 * Otherwise, use the permanent address from the eeprom. 1731 */ 1732 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1733 IXGBE_ERR_INVALID_MAC_ADDR) { 1734 /* Get the MAC address from the RAR0 for later reference */ 1735 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1736 1737 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); 1738 } else { 1739 /* Setup the receive address. */ 1740 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); 1741 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); 1742 1743 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1744 1745 /* clear VMDq pool/queue selection for RAR 0 */ 1746 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 1747 } 1748 hw->addr_ctrl.overflow_promisc = 0; 1749 1750 hw->addr_ctrl.rar_used_count = 1; 1751 1752 /* Zero out the other receive addresses. */ 1753 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); 1754 for (i = 1; i < rar_entries; i++) { 1755 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1756 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1757 } 1758 1759 /* Clear the MTA */ 1760 hw->addr_ctrl.mta_in_use = 0; 1761 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1762 1763 hw_dbg(hw, " Clearing MTA\n"); 1764 for (i = 0; i < hw->mac.mcft_size; i++) 1765 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1766 1767 if (hw->mac.ops.init_uta_tables) 1768 hw->mac.ops.init_uta_tables(hw); 1769 1770 return 0; 1771} 1772 1773/** 1774 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1775 * @hw: pointer to hardware structure 1776 * @mc_addr: the multicast address 1777 * 1778 * Extracts the 12 bits, from a multicast address, to determine which 1779 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1780 * incoming rx multicast addresses, to determine the bit-vector to check in 1781 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1782 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1783 * to mc_filter_type. 1784 **/ 1785static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1786{ 1787 u32 vector = 0; 1788 1789 switch (hw->mac.mc_filter_type) { 1790 case 0: /* use bits [47:36] of the address */ 1791 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1792 break; 1793 case 1: /* use bits [46:35] of the address */ 1794 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1795 break; 1796 case 2: /* use bits [45:34] of the address */ 1797 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1798 break; 1799 case 3: /* use bits [43:32] of the address */ 1800 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1801 break; 1802 default: /* Invalid mc_filter_type */ 1803 hw_dbg(hw, "MC filter type param set incorrectly\n"); 1804 break; 1805 } 1806 1807 /* vector can only be 12-bits or boundary will be exceeded */ 1808 vector &= 0xFFF; 1809 return vector; 1810} 1811 1812/** 1813 * ixgbe_set_mta - Set bit-vector in multicast table 1814 * @hw: pointer to hardware structure 1815 * @hash_value: Multicast address hash value 1816 * 1817 * Sets the bit-vector in the multicast table. 1818 **/ 1819static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1820{ 1821 u32 vector; 1822 u32 vector_bit; 1823 u32 vector_reg; 1824 1825 hw->addr_ctrl.mta_in_use++; 1826 1827 vector = ixgbe_mta_vector(hw, mc_addr); 1828 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); 1829 1830 /* 1831 * The MTA is a register array of 128 32-bit registers. It is treated 1832 * like an array of 4096 bits. We want to set bit 1833 * BitArray[vector_value]. So we figure out what register the bit is 1834 * in, read it, OR in the new bit, then write back the new value. The 1835 * register is determined by the upper 7 bits of the vector value and 1836 * the bit within that register are determined by the lower 5 bits of 1837 * the value. 1838 */ 1839 vector_reg = (vector >> 5) & 0x7F; 1840 vector_bit = vector & 0x1F; 1841 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 1842} 1843 1844/** 1845 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1846 * @hw: pointer to hardware structure 1847 * @netdev: pointer to net device structure 1848 * 1849 * The given list replaces any existing list. Clears the MC addrs from receive 1850 * address registers and the multicast table. Uses unused receive address 1851 * registers for the first multicast addresses, and hashes the rest into the 1852 * multicast table. 1853 **/ 1854s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, 1855 struct net_device *netdev) 1856{ 1857 struct netdev_hw_addr *ha; 1858 u32 i; 1859 1860 /* 1861 * Set the new number of MC addresses that we are being requested to 1862 * use. 1863 */ 1864 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 1865 hw->addr_ctrl.mta_in_use = 0; 1866 1867 /* Clear mta_shadow */ 1868 hw_dbg(hw, " Clearing MTA\n"); 1869 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 1870 1871 /* Update mta shadow */ 1872 netdev_for_each_mc_addr(ha, netdev) { 1873 hw_dbg(hw, " Adding the multicast addresses:\n"); 1874 ixgbe_set_mta(hw, ha->addr); 1875 } 1876 1877 /* Enable mta */ 1878 for (i = 0; i < hw->mac.mcft_size; i++) 1879 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 1880 hw->mac.mta_shadow[i]); 1881 1882 if (hw->addr_ctrl.mta_in_use > 0) 1883 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1884 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1885 1886 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); 1887 return 0; 1888} 1889 1890/** 1891 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1892 * @hw: pointer to hardware structure 1893 * 1894 * Enables multicast address in RAR and the use of the multicast hash table. 1895 **/ 1896s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1897{ 1898 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1899 1900 if (a->mta_in_use > 0) 1901 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1902 hw->mac.mc_filter_type); 1903 1904 return 0; 1905} 1906 1907/** 1908 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1909 * @hw: pointer to hardware structure 1910 * 1911 * Disables multicast address in RAR and the use of the multicast hash table. 1912 **/ 1913s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1914{ 1915 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1916 1917 if (a->mta_in_use > 0) 1918 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1919 1920 return 0; 1921} 1922 1923/** 1924 * ixgbe_fc_enable_generic - Enable flow control 1925 * @hw: pointer to hardware structure 1926 * @packetbuf_num: packet buffer number (0-7) 1927 * 1928 * Enable flow control according to the current settings. 1929 **/ 1930s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 1931{ 1932 s32 ret_val = 0; 1933 u32 mflcn_reg, fccfg_reg; 1934 u32 reg; 1935 u32 fcrtl, fcrth; 1936 1937#ifdef CONFIG_DCB 1938 if (hw->fc.requested_mode == ixgbe_fc_pfc) 1939 goto out; 1940 1941#endif /* CONFIG_DCB */ 1942 /* Negotiate the fc mode to use */ 1943 ret_val = ixgbe_fc_autoneg(hw); 1944 if (ret_val == IXGBE_ERR_FLOW_CONTROL) 1945 goto out; 1946 1947 /* Disable any previous flow control settings */ 1948 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 1949 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); 1950 1951 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 1952 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 1953 1954 /* 1955 * The possible values of fc.current_mode are: 1956 * 0: Flow control is completely disabled 1957 * 1: Rx flow control is enabled (we can receive pause frames, 1958 * but not send pause frames). 1959 * 2: Tx flow control is enabled (we can send pause frames but 1960 * we do not support receiving pause frames). 1961 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1962#ifdef CONFIG_DCB 1963 * 4: Priority Flow Control is enabled. 1964#endif 1965 * other: Invalid. 1966 */ 1967 switch (hw->fc.current_mode) { 1968 case ixgbe_fc_none: 1969 /* 1970 * Flow control is disabled by software override or autoneg. 1971 * The code below will actually disable it in the HW. 1972 */ 1973 break; 1974 case ixgbe_fc_rx_pause: 1975 /* 1976 * Rx Flow control is enabled and Tx Flow control is 1977 * disabled by software override. Since there really 1978 * isn't a way to advertise that we are capable of RX 1979 * Pause ONLY, we will advertise that we support both 1980 * symmetric and asymmetric Rx PAUSE. Later, we will 1981 * disable the adapter's ability to send PAUSE frames. 1982 */ 1983 mflcn_reg |= IXGBE_MFLCN_RFCE; 1984 break; 1985 case ixgbe_fc_tx_pause: 1986 /* 1987 * Tx Flow control is enabled, and Rx Flow control is 1988 * disabled by software override. 1989 */ 1990 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1991 break; 1992 case ixgbe_fc_full: 1993 /* Flow control (both Rx and Tx) is enabled by SW override. */ 1994 mflcn_reg |= IXGBE_MFLCN_RFCE; 1995 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1996 break; 1997#ifdef CONFIG_DCB 1998 case ixgbe_fc_pfc: 1999 goto out; 2000 break; 2001#endif /* CONFIG_DCB */ 2002 default: 2003 hw_dbg(hw, "Flow control param set incorrectly\n"); 2004 ret_val = IXGBE_ERR_CONFIG; 2005 goto out; 2006 break; 2007 } 2008 2009 /* Set 802.3x based flow control settings. */ 2010 mflcn_reg |= IXGBE_MFLCN_DPF; 2011 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2012 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2013 2014 fcrtl = hw->fc.low_water << 10; 2015 2016 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 2017 fcrth = hw->fc.high_water[packetbuf_num] << 10; 2018 fcrth |= IXGBE_FCRTH_FCEN; 2019 if (hw->fc.send_xon) 2020 fcrtl |= IXGBE_FCRTL_XONE; 2021 } else { 2022 /* 2023 * If Tx flow control is disabled, set our high water mark 2024 * to Rx FIFO size minus 32 in order prevent Tx switch 2025 * loopback from stalling on DMA. 2026 */ 2027 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)) - 32; 2028 } 2029 2030 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth); 2031 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl); 2032 2033 /* Configure pause time (2 TCs per register) */ 2034 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 2035 if ((packetbuf_num & 1) == 0) 2036 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 2037 else 2038 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 2039 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 2040 2041 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 2042 2043out: 2044 return ret_val; 2045} 2046 2047/** 2048 * ixgbe_fc_autoneg - Configure flow control 2049 * @hw: pointer to hardware structure 2050 * 2051 * Compares our advertised flow control capabilities to those advertised by 2052 * our link partner, and determines the proper flow control mode to use. 2053 **/ 2054s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2055{ 2056 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2057 ixgbe_link_speed speed; 2058 bool link_up; 2059 2060 if (hw->fc.disable_fc_autoneg) 2061 goto out; 2062 2063 /* 2064 * AN should have completed when the cable was plugged in. 2065 * Look for reasons to bail out. Bail out if: 2066 * - FC autoneg is disabled, or if 2067 * - link is not up. 2068 * 2069 * Since we're being called from an LSC, link is already known to be up. 2070 * So use link_up_wait_to_complete=false. 2071 */ 2072 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2073 if (!link_up) { 2074 ret_val = IXGBE_ERR_FLOW_CONTROL; 2075 goto out; 2076 } 2077 2078 switch (hw->phy.media_type) { 2079 /* Autoneg flow control on fiber adapters */ 2080 case ixgbe_media_type_fiber: 2081 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 2082 ret_val = ixgbe_fc_autoneg_fiber(hw); 2083 break; 2084 2085 /* Autoneg flow control on backplane adapters */ 2086 case ixgbe_media_type_backplane: 2087 ret_val = ixgbe_fc_autoneg_backplane(hw); 2088 break; 2089 2090 /* Autoneg flow control on copper adapters */ 2091 case ixgbe_media_type_copper: 2092 if (ixgbe_device_supports_autoneg_fc(hw) == 0) 2093 ret_val = ixgbe_fc_autoneg_copper(hw); 2094 break; 2095 2096 default: 2097 break; 2098 } 2099 2100out: 2101 if (ret_val == 0) { 2102 hw->fc.fc_was_autonegged = true; 2103 } else { 2104 hw->fc.fc_was_autonegged = false; 2105 hw->fc.current_mode = hw->fc.requested_mode; 2106 } 2107 return ret_val; 2108} 2109 2110/** 2111 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2112 * @hw: pointer to hardware structure 2113 * 2114 * Enable flow control according on 1 gig fiber. 2115 **/ 2116static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2117{ 2118 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2119 s32 ret_val; 2120 2121 /* 2122 * On multispeed fiber at 1g, bail out if 2123 * - link is up but AN did not complete, or if 2124 * - link is up and AN completed but timed out 2125 */ 2126 2127 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2128 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2129 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 2130 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2131 goto out; 2132 } 2133 2134 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2135 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2136 2137 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2138 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2139 IXGBE_PCS1GANA_ASM_PAUSE, 2140 IXGBE_PCS1GANA_SYM_PAUSE, 2141 IXGBE_PCS1GANA_ASM_PAUSE); 2142 2143out: 2144 return ret_val; 2145} 2146 2147/** 2148 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2149 * @hw: pointer to hardware structure 2150 * 2151 * Enable flow control according to IEEE clause 37. 2152 **/ 2153static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2154{ 2155 u32 links2, anlp1_reg, autoc_reg, links; 2156 s32 ret_val; 2157 2158 /* 2159 * On backplane, bail out if 2160 * - backplane autoneg was not completed, or if 2161 * - we are 82599 and link partner is not AN enabled 2162 */ 2163 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2164 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 2165 hw->fc.fc_was_autonegged = false; 2166 hw->fc.current_mode = hw->fc.requested_mode; 2167 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2168 goto out; 2169 } 2170 2171 if (hw->mac.type == ixgbe_mac_82599EB) { 2172 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2173 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 2174 hw->fc.fc_was_autonegged = false; 2175 hw->fc.current_mode = hw->fc.requested_mode; 2176 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2177 goto out; 2178 } 2179 } 2180 /* 2181 * Read the 10g AN autoc and LP ability registers and resolve 2182 * local flow control settings accordingly 2183 */ 2184 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2185 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2186 2187 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2188 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2189 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2190 2191out: 2192 return ret_val; 2193} 2194 2195/** 2196 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2197 * @hw: pointer to hardware structure 2198 * 2199 * Enable flow control according to IEEE clause 37. 2200 **/ 2201static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2202{ 2203 u16 technology_ability_reg = 0; 2204 u16 lp_technology_ability_reg = 0; 2205 2206 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 2207 MDIO_MMD_AN, 2208 &technology_ability_reg); 2209 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, 2210 MDIO_MMD_AN, 2211 &lp_technology_ability_reg); 2212 2213 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2214 (u32)lp_technology_ability_reg, 2215 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2216 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2217} 2218 2219/** 2220 * ixgbe_negotiate_fc - Negotiate flow control 2221 * @hw: pointer to hardware structure 2222 * @adv_reg: flow control advertised settings 2223 * @lp_reg: link partner's flow control settings 2224 * @adv_sym: symmetric pause bit in advertisement 2225 * @adv_asm: asymmetric pause bit in advertisement 2226 * @lp_sym: symmetric pause bit in link partner advertisement 2227 * @lp_asm: asymmetric pause bit in link partner advertisement 2228 * 2229 * Find the intersection between advertised settings and link partner's 2230 * advertised settings 2231 **/ 2232static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2233 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2234{ 2235 if ((!(adv_reg)) || (!(lp_reg))) 2236 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2237 2238 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2239 /* 2240 * Now we need to check if the user selected Rx ONLY 2241 * of pause frames. In this case, we had to advertise 2242 * FULL flow control because we could not advertise RX 2243 * ONLY. Hence, we must now check to see if we need to 2244 * turn OFF the TRANSMISSION of PAUSE frames. 2245 */ 2246 if (hw->fc.requested_mode == ixgbe_fc_full) { 2247 hw->fc.current_mode = ixgbe_fc_full; 2248 hw_dbg(hw, "Flow Control = FULL.\n"); 2249 } else { 2250 hw->fc.current_mode = ixgbe_fc_rx_pause; 2251 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); 2252 } 2253 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2254 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2255 hw->fc.current_mode = ixgbe_fc_tx_pause; 2256 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); 2257 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2258 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2259 hw->fc.current_mode = ixgbe_fc_rx_pause; 2260 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); 2261 } else { 2262 hw->fc.current_mode = ixgbe_fc_none; 2263 hw_dbg(hw, "Flow Control = NONE.\n"); 2264 } 2265 return 0; 2266} 2267 2268/** 2269 * ixgbe_setup_fc - Set up flow control 2270 * @hw: pointer to hardware structure 2271 * 2272 * Called at init time to set up flow control. 2273 **/ 2274static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) 2275{ 2276 s32 ret_val = 0; 2277 u32 reg = 0, reg_bp = 0; 2278 u16 reg_cu = 0; 2279 2280#ifdef CONFIG_DCB 2281 if (hw->fc.requested_mode == ixgbe_fc_pfc) { 2282 hw->fc.current_mode = hw->fc.requested_mode; 2283 goto out; 2284 } 2285 2286#endif /* CONFIG_DCB */ 2287 /* Validate the packetbuf configuration */ 2288 if (packetbuf_num < 0 || packetbuf_num > 7) { 2289 hw_dbg(hw, "Invalid packet buffer number [%d], expected range " 2290 "is 0-7\n", packetbuf_num); 2291 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2292 goto out; 2293 } 2294 2295 /* 2296 * Validate the water mark configuration. Zero water marks are invalid 2297 * because it causes the controller to just blast out fc packets. 2298 */ 2299 if (!hw->fc.low_water || 2300 !hw->fc.high_water[packetbuf_num] || 2301 !hw->fc.pause_time) { 2302 hw_dbg(hw, "Invalid water mark configuration\n"); 2303 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2304 goto out; 2305 } 2306 2307 /* 2308 * Validate the requested mode. Strict IEEE mode does not allow 2309 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 2310 */ 2311 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2312 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict " 2313 "IEEE mode\n"); 2314 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2315 goto out; 2316 } 2317 2318 /* 2319 * 10gig parts do not have a word in the EEPROM to determine the 2320 * default flow control setting, so we explicitly set it to full. 2321 */ 2322 if (hw->fc.requested_mode == ixgbe_fc_default) 2323 hw->fc.requested_mode = ixgbe_fc_full; 2324 2325 /* 2326 * Set up the 1G and 10G flow control advertisement registers so the 2327 * HW will be able to do fc autoneg once the cable is plugged in. If 2328 * we link at 10G, the 1G advertisement is harmless and vice versa. 2329 */ 2330 2331 switch (hw->phy.media_type) { 2332 case ixgbe_media_type_fiber: 2333 case ixgbe_media_type_backplane: 2334 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2335 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2336 break; 2337 2338 case ixgbe_media_type_copper: 2339 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 2340 MDIO_MMD_AN, ®_cu); 2341 break; 2342 2343 default: 2344 ; 2345 } 2346 2347 /* 2348 * The possible values of fc.requested_mode are: 2349 * 0: Flow control is completely disabled 2350 * 1: Rx flow control is enabled (we can receive pause frames, 2351 * but not send pause frames). 2352 * 2: Tx flow control is enabled (we can send pause frames but 2353 * we do not support receiving pause frames). 2354 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2355#ifdef CONFIG_DCB 2356 * 4: Priority Flow Control is enabled. 2357#endif 2358 * other: Invalid. 2359 */ 2360 switch (hw->fc.requested_mode) { 2361 case ixgbe_fc_none: 2362 /* Flow control completely disabled by software override. */ 2363 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2364 if (hw->phy.media_type == ixgbe_media_type_backplane) 2365 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 2366 IXGBE_AUTOC_ASM_PAUSE); 2367 else if (hw->phy.media_type == ixgbe_media_type_copper) 2368 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 2369 break; 2370 case ixgbe_fc_rx_pause: 2371 /* 2372 * Rx Flow control is enabled and Tx Flow control is 2373 * disabled by software override. Since there really 2374 * isn't a way to advertise that we are capable of RX 2375 * Pause ONLY, we will advertise that we support both 2376 * symmetric and asymmetric Rx PAUSE. Later, we will 2377 * disable the adapter's ability to send PAUSE frames. 2378 */ 2379 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2380 if (hw->phy.media_type == ixgbe_media_type_backplane) 2381 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE | 2382 IXGBE_AUTOC_ASM_PAUSE); 2383 else if (hw->phy.media_type == ixgbe_media_type_copper) 2384 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 2385 break; 2386 case ixgbe_fc_tx_pause: 2387 /* 2388 * Tx Flow control is enabled, and Rx Flow control is 2389 * disabled by software override. 2390 */ 2391 reg |= (IXGBE_PCS1GANA_ASM_PAUSE); 2392 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); 2393 if (hw->phy.media_type == ixgbe_media_type_backplane) { 2394 reg_bp |= (IXGBE_AUTOC_ASM_PAUSE); 2395 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE); 2396 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 2397 reg_cu |= (IXGBE_TAF_ASM_PAUSE); 2398 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE); 2399 } 2400 break; 2401 case ixgbe_fc_full: 2402 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2403 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2404 if (hw->phy.media_type == ixgbe_media_type_backplane) 2405 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE | 2406 IXGBE_AUTOC_ASM_PAUSE); 2407 else if (hw->phy.media_type == ixgbe_media_type_copper) 2408 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 2409 break; 2410#ifdef CONFIG_DCB 2411 case ixgbe_fc_pfc: 2412 goto out; 2413 break; 2414#endif /* CONFIG_DCB */ 2415 default: 2416 hw_dbg(hw, "Flow control param set incorrectly\n"); 2417 ret_val = IXGBE_ERR_CONFIG; 2418 goto out; 2419 break; 2420 } 2421 2422 if (hw->mac.type != ixgbe_mac_X540) { 2423 /* 2424 * Enable auto-negotiation between the MAC & PHY; 2425 * the MAC will advertise clause 37 flow control. 2426 */ 2427 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 2428 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 2429 2430 /* Disable AN timeout */ 2431 if (hw->fc.strict_ieee) 2432 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 2433 2434 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 2435 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); 2436 } 2437 2438 /* 2439 * AUTOC restart handles negotiation of 1G and 10G on backplane 2440 * and copper. There is no need to set the PCS1GCTL register. 2441 * 2442 */ 2443 if (hw->phy.media_type == ixgbe_media_type_backplane) { 2444 reg_bp |= IXGBE_AUTOC_AN_RESTART; 2445 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp); 2446 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 2447 (ixgbe_device_supports_autoneg_fc(hw) == 0)) { 2448 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 2449 MDIO_MMD_AN, reg_cu); 2450 } 2451 2452 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 2453out: 2454 return ret_val; 2455} 2456 2457/** 2458 * ixgbe_disable_pcie_master - Disable PCI-express master access 2459 * @hw: pointer to hardware structure 2460 * 2461 * Disables PCI-Express master access and verifies there are no pending 2462 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2463 * bit hasn't caused the master requests to be disabled, else 0 2464 * is returned signifying master requests disabled. 2465 **/ 2466static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2467{ 2468 struct ixgbe_adapter *adapter = hw->back; 2469 s32 status = 0; 2470 u32 i; 2471 u16 value; 2472 2473 /* Always set this bit to ensure any future transactions are blocked */ 2474 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 2475 2476 /* Exit if master requests are blocked */ 2477 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2478 goto out; 2479 2480 /* Poll for master request bit to clear */ 2481 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2482 udelay(100); 2483 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2484 goto out; 2485 } 2486 2487 /* 2488 * Two consecutive resets are required via CTRL.RST per datasheet 2489 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2490 * of this need. The first reset prevents new master requests from 2491 * being issued by our device. We then must wait 1usec or more for any 2492 * remaining completions from the PCIe bus to trickle in, and then reset 2493 * again to clear out any effects they may have had on our device. 2494 */ 2495 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); 2496 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2497 2498 /* 2499 * Before proceeding, make sure that the PCIe block does not have 2500 * transactions pending. 2501 */ 2502 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2503 udelay(100); 2504 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS, 2505 &value); 2506 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2507 goto out; 2508 } 2509 2510 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); 2511 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2512 2513out: 2514 return status; 2515} 2516 2517/** 2518 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2519 * @hw: pointer to hardware structure 2520 * @mask: Mask to specify which semaphore to acquire 2521 * 2522 * Acquires the SWFW semaphore through the GSSR register for the specified 2523 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2524 **/ 2525s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2526{ 2527 u32 gssr; 2528 u32 swmask = mask; 2529 u32 fwmask = mask << 5; 2530 s32 timeout = 200; 2531 2532 while (timeout) { 2533 /* 2534 * SW EEPROM semaphore bit is used for access to all 2535 * SW_FW_SYNC/GSSR bits (not just EEPROM) 2536 */ 2537 if (ixgbe_get_eeprom_semaphore(hw)) 2538 return IXGBE_ERR_SWFW_SYNC; 2539 2540 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2541 if (!(gssr & (fwmask | swmask))) 2542 break; 2543 2544 /* 2545 * Firmware currently using resource (fwmask) or other software 2546 * thread currently using resource (swmask) 2547 */ 2548 ixgbe_release_eeprom_semaphore(hw); 2549 usleep_range(5000, 10000); 2550 timeout--; 2551 } 2552 2553 if (!timeout) { 2554 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n"); 2555 return IXGBE_ERR_SWFW_SYNC; 2556 } 2557 2558 gssr |= swmask; 2559 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2560 2561 ixgbe_release_eeprom_semaphore(hw); 2562 return 0; 2563} 2564 2565/** 2566 * ixgbe_release_swfw_sync - Release SWFW semaphore 2567 * @hw: pointer to hardware structure 2568 * @mask: Mask to specify which semaphore to release 2569 * 2570 * Releases the SWFW semaphore through the GSSR register for the specified 2571 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2572 **/ 2573void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2574{ 2575 u32 gssr; 2576 u32 swmask = mask; 2577 2578 ixgbe_get_eeprom_semaphore(hw); 2579 2580 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2581 gssr &= ~swmask; 2582 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2583 2584 ixgbe_release_eeprom_semaphore(hw); 2585} 2586 2587/** 2588 * ixgbe_disable_rx_buff_generic - Stops the receive data path 2589 * @hw: pointer to hardware structure 2590 * 2591 * Stops the receive data path and waits for the HW to internally 2592 * empty the Rx security block. 2593 **/ 2594s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) 2595{ 2596#define IXGBE_MAX_SECRX_POLL 40 2597 int i; 2598 int secrxreg; 2599 2600 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2601 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2602 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2603 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2604 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2605 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2606 break; 2607 else 2608 /* Use interrupt-safe sleep just in case */ 2609 udelay(10); 2610 } 2611 2612 /* For informational purposes only */ 2613 if (i >= IXGBE_MAX_SECRX_POLL) 2614 hw_dbg(hw, "Rx unit being enabled before security " 2615 "path fully disabled. Continuing with init.\n"); 2616 2617 return 0; 2618 2619} 2620 2621/** 2622 * ixgbe_enable_rx_buff - Enables the receive data path 2623 * @hw: pointer to hardware structure 2624 * 2625 * Enables the receive data path 2626 **/ 2627s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) 2628{ 2629 int secrxreg; 2630 2631 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2632 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2633 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2634 IXGBE_WRITE_FLUSH(hw); 2635 2636 return 0; 2637} 2638 2639/** 2640 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2641 * @hw: pointer to hardware structure 2642 * @regval: register value to write to RXCTRL 2643 * 2644 * Enables the Rx DMA unit 2645 **/ 2646s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2647{ 2648 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2649 2650 return 0; 2651} 2652 2653/** 2654 * ixgbe_blink_led_start_generic - Blink LED based on index. 2655 * @hw: pointer to hardware structure 2656 * @index: led number to blink 2657 **/ 2658s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2659{ 2660 ixgbe_link_speed speed = 0; 2661 bool link_up = false; 2662 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2663 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2664 2665 /* 2666 * Link must be up to auto-blink the LEDs; 2667 * Force it if link is down. 2668 */ 2669 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2670 2671 if (!link_up) { 2672 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2673 autoc_reg |= IXGBE_AUTOC_FLU; 2674 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2675 IXGBE_WRITE_FLUSH(hw); 2676 usleep_range(10000, 20000); 2677 } 2678 2679 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2680 led_reg |= IXGBE_LED_BLINK(index); 2681 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2682 IXGBE_WRITE_FLUSH(hw); 2683 2684 return 0; 2685} 2686 2687/** 2688 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2689 * @hw: pointer to hardware structure 2690 * @index: led number to stop blinking 2691 **/ 2692s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2693{ 2694 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2695 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2696 2697 autoc_reg &= ~IXGBE_AUTOC_FLU; 2698 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2699 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2700 2701 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2702 led_reg &= ~IXGBE_LED_BLINK(index); 2703 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2704 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2705 IXGBE_WRITE_FLUSH(hw); 2706 2707 return 0; 2708} 2709 2710/** 2711 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2712 * @hw: pointer to hardware structure 2713 * @san_mac_offset: SAN MAC address offset 2714 * 2715 * This function will read the EEPROM location for the SAN MAC address 2716 * pointer, and returns the value at that location. This is used in both 2717 * get and set mac_addr routines. 2718 **/ 2719static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2720 u16 *san_mac_offset) 2721{ 2722 /* 2723 * First read the EEPROM pointer to see if the MAC addresses are 2724 * available. 2725 */ 2726 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); 2727 2728 return 0; 2729} 2730 2731/** 2732 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2733 * @hw: pointer to hardware structure 2734 * @san_mac_addr: SAN MAC address 2735 * 2736 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2737 * per-port, so set_lan_id() must be called before reading the addresses. 2738 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2739 * upon for non-SFP connections, so we must call it here. 2740 **/ 2741s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2742{ 2743 u16 san_mac_data, san_mac_offset; 2744 u8 i; 2745 2746 /* 2747 * First read the EEPROM pointer to see if the MAC addresses are 2748 * available. If they're not, no point in calling set_lan_id() here. 2749 */ 2750 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2751 2752 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2753 /* 2754 * No addresses available in this EEPROM. It's not an 2755 * error though, so just wipe the local address and return. 2756 */ 2757 for (i = 0; i < 6; i++) 2758 san_mac_addr[i] = 0xFF; 2759 2760 goto san_mac_addr_out; 2761 } 2762 2763 /* make sure we know which port we need to program */ 2764 hw->mac.ops.set_lan_id(hw); 2765 /* apply the port offset to the address offset */ 2766 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2767 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2768 for (i = 0; i < 3; i++) { 2769 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); 2770 san_mac_addr[i * 2] = (u8)(san_mac_data); 2771 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2772 san_mac_offset++; 2773 } 2774 2775san_mac_addr_out: 2776 return 0; 2777} 2778 2779/** 2780 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2781 * @hw: pointer to hardware structure 2782 * 2783 * Read PCIe configuration space, and get the MSI-X vector count from 2784 * the capabilities table. 2785 **/ 2786u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2787{ 2788 struct ixgbe_adapter *adapter = hw->back; 2789 u16 msix_count; 2790 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS, 2791 &msix_count); 2792 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2793 2794 /* MSI-X count is zero-based in HW, so increment to give proper value */ 2795 msix_count++; 2796 2797 return msix_count; 2798} 2799 2800/** 2801 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2802 * @hw: pointer to hardware struct 2803 * @rar: receive address register index to disassociate 2804 * @vmdq: VMDq pool index to remove from the rar 2805 **/ 2806s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2807{ 2808 u32 mpsar_lo, mpsar_hi; 2809 u32 rar_entries = hw->mac.num_rar_entries; 2810 2811 /* Make sure we are using a valid rar index range */ 2812 if (rar >= rar_entries) { 2813 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2814 return IXGBE_ERR_INVALID_ARGUMENT; 2815 } 2816 2817 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2818 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2819 2820 if (!mpsar_lo && !mpsar_hi) 2821 goto done; 2822 2823 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2824 if (mpsar_lo) { 2825 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2826 mpsar_lo = 0; 2827 } 2828 if (mpsar_hi) { 2829 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2830 mpsar_hi = 0; 2831 } 2832 } else if (vmdq < 32) { 2833 mpsar_lo &= ~(1 << vmdq); 2834 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 2835 } else { 2836 mpsar_hi &= ~(1 << (vmdq - 32)); 2837 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 2838 } 2839 2840 /* was that the last pool using this rar? */ 2841 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 2842 hw->mac.ops.clear_rar(hw, rar); 2843done: 2844 return 0; 2845} 2846 2847/** 2848 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 2849 * @hw: pointer to hardware struct 2850 * @rar: receive address register index to associate with a VMDq index 2851 * @vmdq: VMDq pool index 2852 **/ 2853s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2854{ 2855 u32 mpsar; 2856 u32 rar_entries = hw->mac.num_rar_entries; 2857 2858 /* Make sure we are using a valid rar index range */ 2859 if (rar >= rar_entries) { 2860 hw_dbg(hw, "RAR index %d is out of range.\n", rar); 2861 return IXGBE_ERR_INVALID_ARGUMENT; 2862 } 2863 2864 if (vmdq < 32) { 2865 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2866 mpsar |= 1 << vmdq; 2867 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 2868 } else { 2869 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2870 mpsar |= 1 << (vmdq - 32); 2871 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 2872 } 2873 return 0; 2874} 2875 2876/** 2877 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 2878 * @hw: pointer to hardware structure 2879 **/ 2880s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 2881{ 2882 int i; 2883 2884 for (i = 0; i < 128; i++) 2885 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 2886 2887 return 0; 2888} 2889 2890/** 2891 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 2892 * @hw: pointer to hardware structure 2893 * @vlan: VLAN id to write to VLAN filter 2894 * 2895 * return the VLVF index where this VLAN id should be placed 2896 * 2897 **/ 2898static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) 2899{ 2900 u32 bits = 0; 2901 u32 first_empty_slot = 0; 2902 s32 regindex; 2903 2904 /* short cut the special case */ 2905 if (vlan == 0) 2906 return 0; 2907 2908 /* 2909 * Search for the vlan id in the VLVF entries. Save off the first empty 2910 * slot found along the way 2911 */ 2912 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { 2913 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 2914 if (!bits && !(first_empty_slot)) 2915 first_empty_slot = regindex; 2916 else if ((bits & 0x0FFF) == vlan) 2917 break; 2918 } 2919 2920 /* 2921 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan 2922 * in the VLVF. Else use the first empty VLVF register for this 2923 * vlan id. 2924 */ 2925 if (regindex >= IXGBE_VLVF_ENTRIES) { 2926 if (first_empty_slot) 2927 regindex = first_empty_slot; 2928 else { 2929 hw_dbg(hw, "No space in VLVF.\n"); 2930 regindex = IXGBE_ERR_NO_SPACE; 2931 } 2932 } 2933 2934 return regindex; 2935} 2936 2937/** 2938 * ixgbe_set_vfta_generic - Set VLAN filter table 2939 * @hw: pointer to hardware structure 2940 * @vlan: VLAN id to write to VLAN filter 2941 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2942 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2943 * 2944 * Turn on/off specified VLAN in the VLAN filter table. 2945 **/ 2946s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 2947 bool vlan_on) 2948{ 2949 s32 regindex; 2950 u32 bitindex; 2951 u32 vfta; 2952 u32 bits; 2953 u32 vt; 2954 u32 targetbit; 2955 bool vfta_changed = false; 2956 2957 if (vlan > 4095) 2958 return IXGBE_ERR_PARAM; 2959 2960 /* 2961 * this is a 2 part operation - first the VFTA, then the 2962 * VLVF and VLVFB if VT Mode is set 2963 * We don't write the VFTA until we know the VLVF part succeeded. 2964 */ 2965 2966 /* Part 1 2967 * The VFTA is a bitstring made up of 128 32-bit registers 2968 * that enable the particular VLAN id, much like the MTA: 2969 * bits[11-5]: which register 2970 * bits[4-0]: which bit in the register 2971 */ 2972 regindex = (vlan >> 5) & 0x7F; 2973 bitindex = vlan & 0x1F; 2974 targetbit = (1 << bitindex); 2975 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 2976 2977 if (vlan_on) { 2978 if (!(vfta & targetbit)) { 2979 vfta |= targetbit; 2980 vfta_changed = true; 2981 } 2982 } else { 2983 if ((vfta & targetbit)) { 2984 vfta &= ~targetbit; 2985 vfta_changed = true; 2986 } 2987 } 2988 2989 /* Part 2 2990 * If VT Mode is set 2991 * Either vlan_on 2992 * make sure the vlan is in VLVF 2993 * set the vind bit in the matching VLVFB 2994 * Or !vlan_on 2995 * clear the pool bit and possibly the vind 2996 */ 2997 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2998 if (vt & IXGBE_VT_CTL_VT_ENABLE) { 2999 s32 vlvf_index; 3000 3001 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan); 3002 if (vlvf_index < 0) 3003 return vlvf_index; 3004 3005 if (vlan_on) { 3006 /* set the pool bit */ 3007 if (vind < 32) { 3008 bits = IXGBE_READ_REG(hw, 3009 IXGBE_VLVFB(vlvf_index*2)); 3010 bits |= (1 << vind); 3011 IXGBE_WRITE_REG(hw, 3012 IXGBE_VLVFB(vlvf_index*2), 3013 bits); 3014 } else { 3015 bits = IXGBE_READ_REG(hw, 3016 IXGBE_VLVFB((vlvf_index*2)+1)); 3017 bits |= (1 << (vind-32)); 3018 IXGBE_WRITE_REG(hw, 3019 IXGBE_VLVFB((vlvf_index*2)+1), 3020 bits); 3021 } 3022 } else { 3023 /* clear the pool bit */ 3024 if (vind < 32) { 3025 bits = IXGBE_READ_REG(hw, 3026 IXGBE_VLVFB(vlvf_index*2)); 3027 bits &= ~(1 << vind); 3028 IXGBE_WRITE_REG(hw, 3029 IXGBE_VLVFB(vlvf_index*2), 3030 bits); 3031 bits |= IXGBE_READ_REG(hw, 3032 IXGBE_VLVFB((vlvf_index*2)+1)); 3033 } else { 3034 bits = IXGBE_READ_REG(hw, 3035 IXGBE_VLVFB((vlvf_index*2)+1)); 3036 bits &= ~(1 << (vind-32)); 3037 IXGBE_WRITE_REG(hw, 3038 IXGBE_VLVFB((vlvf_index*2)+1), 3039 bits); 3040 bits |= IXGBE_READ_REG(hw, 3041 IXGBE_VLVFB(vlvf_index*2)); 3042 } 3043 } 3044 3045 /* 3046 * If there are still bits set in the VLVFB registers 3047 * for the VLAN ID indicated we need to see if the 3048 * caller is requesting that we clear the VFTA entry bit. 3049 * If the caller has requested that we clear the VFTA 3050 * entry bit but there are still pools/VFs using this VLAN 3051 * ID entry then ignore the request. We're not worried 3052 * about the case where we're turning the VFTA VLAN ID 3053 * entry bit on, only when requested to turn it off as 3054 * there may be multiple pools and/or VFs using the 3055 * VLAN ID entry. In that case we cannot clear the 3056 * VFTA bit until all pools/VFs using that VLAN ID have also 3057 * been cleared. This will be indicated by "bits" being 3058 * zero. 3059 */ 3060 if (bits) { 3061 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 3062 (IXGBE_VLVF_VIEN | vlan)); 3063 if (!vlan_on) { 3064 /* someone wants to clear the vfta entry 3065 * but some pools/VFs are still using it. 3066 * Ignore it. */ 3067 vfta_changed = false; 3068 } 3069 } 3070 else 3071 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3072 } 3073 3074 if (vfta_changed) 3075 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta); 3076 3077 return 0; 3078} 3079 3080/** 3081 * ixgbe_clear_vfta_generic - Clear VLAN filter table 3082 * @hw: pointer to hardware structure 3083 * 3084 * Clears the VLAN filer table, and the VMDq index associated with the filter 3085 **/ 3086s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3087{ 3088 u32 offset; 3089 3090 for (offset = 0; offset < hw->mac.vft_size; offset++) 3091 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3092 3093 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3094 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3095 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0); 3096 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0); 3097 } 3098 3099 return 0; 3100} 3101 3102/** 3103 * ixgbe_check_mac_link_generic - Determine link and speed status 3104 * @hw: pointer to hardware structure 3105 * @speed: pointer to link speed 3106 * @link_up: true when link is up 3107 * @link_up_wait_to_complete: bool used to wait for link up or not 3108 * 3109 * Reads the links register to determine if link is up and the current speed 3110 **/ 3111s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3112 bool *link_up, bool link_up_wait_to_complete) 3113{ 3114 u32 links_reg, links_orig; 3115 u32 i; 3116 3117 /* clear the old state */ 3118 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 3119 3120 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3121 3122 if (links_orig != links_reg) { 3123 hw_dbg(hw, "LINKS changed from %08X to %08X\n", 3124 links_orig, links_reg); 3125 } 3126 3127 if (link_up_wait_to_complete) { 3128 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3129 if (links_reg & IXGBE_LINKS_UP) { 3130 *link_up = true; 3131 break; 3132 } else { 3133 *link_up = false; 3134 } 3135 msleep(100); 3136 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3137 } 3138 } else { 3139 if (links_reg & IXGBE_LINKS_UP) 3140 *link_up = true; 3141 else 3142 *link_up = false; 3143 } 3144 3145 if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3146 IXGBE_LINKS_SPEED_10G_82599) 3147 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3148 else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3149 IXGBE_LINKS_SPEED_1G_82599) 3150 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3151 else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3152 IXGBE_LINKS_SPEED_100_82599) 3153 *speed = IXGBE_LINK_SPEED_100_FULL; 3154 else 3155 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3156 3157 return 0; 3158} 3159 3160/** 3161 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from 3162 * the EEPROM 3163 * @hw: pointer to hardware structure 3164 * @wwnn_prefix: the alternative WWNN prefix 3165 * @wwpn_prefix: the alternative WWPN prefix 3166 * 3167 * This function will read the EEPROM from the alternative SAN MAC address 3168 * block to check the support for the alternative WWNN/WWPN prefix support. 3169 **/ 3170s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3171 u16 *wwpn_prefix) 3172{ 3173 u16 offset, caps; 3174 u16 alt_san_mac_blk_offset; 3175 3176 /* clear output first */ 3177 *wwnn_prefix = 0xFFFF; 3178 *wwpn_prefix = 0xFFFF; 3179 3180 /* check if alternative SAN MAC is supported */ 3181 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR, 3182 &alt_san_mac_blk_offset); 3183 3184 if ((alt_san_mac_blk_offset == 0) || 3185 (alt_san_mac_blk_offset == 0xFFFF)) 3186 goto wwn_prefix_out; 3187 3188 /* check capability in alternative san mac address block */ 3189 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3190 hw->eeprom.ops.read(hw, offset, &caps); 3191 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3192 goto wwn_prefix_out; 3193 3194 /* get the corresponding prefix for WWNN/WWPN */ 3195 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3196 hw->eeprom.ops.read(hw, offset, wwnn_prefix); 3197 3198 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3199 hw->eeprom.ops.read(hw, offset, wwpn_prefix); 3200 3201wwn_prefix_out: 3202 return 0; 3203} 3204 3205/** 3206 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow 3207 * control 3208 * @hw: pointer to hardware structure 3209 * 3210 * There are several phys that do not support autoneg flow control. This 3211 * function check the device id to see if the associated phy supports 3212 * autoneg flow control. 3213 **/ 3214static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 3215{ 3216 3217 switch (hw->device_id) { 3218 case IXGBE_DEV_ID_X540T: 3219 return 0; 3220 case IXGBE_DEV_ID_82599_T3_LOM: 3221 return 0; 3222 default: 3223 return IXGBE_ERR_FC_NOT_SUPPORTED; 3224 } 3225} 3226 3227/** 3228 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3229 * @hw: pointer to hardware structure 3230 * @enable: enable or disable switch for anti-spoofing 3231 * @pf: Physical Function pool - do not enable anti-spoofing for the PF 3232 * 3233 **/ 3234void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf) 3235{ 3236 int j; 3237 int pf_target_reg = pf >> 3; 3238 int pf_target_shift = pf % 8; 3239 u32 pfvfspoof = 0; 3240 3241 if (hw->mac.type == ixgbe_mac_82598EB) 3242 return; 3243 3244 if (enable) 3245 pfvfspoof = IXGBE_SPOOF_MACAS_MASK; 3246 3247 /* 3248 * PFVFSPOOF register array is size 8 with 8 bits assigned to 3249 * MAC anti-spoof enables in each register array element. 3250 */ 3251 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++) 3252 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 3253 3254 /* If not enabling anti-spoofing then done */ 3255 if (!enable) 3256 return; 3257 3258 /* 3259 * The PF should be allowed to spoof so that it can support 3260 * emulation mode NICs. Reset the bit assigned to the PF 3261 */ 3262 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg)); 3263 pfvfspoof ^= (1 << pf_target_shift); 3264 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof); 3265} 3266 3267/** 3268 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 3269 * @hw: pointer to hardware structure 3270 * @enable: enable or disable switch for VLAN anti-spoofing 3271 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 3272 * 3273 **/ 3274void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3275{ 3276 int vf_target_reg = vf >> 3; 3277 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 3278 u32 pfvfspoof; 3279 3280 if (hw->mac.type == ixgbe_mac_82598EB) 3281 return; 3282 3283 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3284 if (enable) 3285 pfvfspoof |= (1 << vf_target_shift); 3286 else 3287 pfvfspoof &= ~(1 << vf_target_shift); 3288 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3289} 3290 3291/** 3292 * ixgbe_get_device_caps_generic - Get additional device capabilities 3293 * @hw: pointer to hardware structure 3294 * @device_caps: the EEPROM word with the extra device capabilities 3295 * 3296 * This function will read the EEPROM location for the device capabilities, 3297 * and return the word through device_caps. 3298 **/ 3299s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3300{ 3301 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3302 3303 return 0; 3304} 3305 3306/** 3307 * ixgbe_set_rxpba_generic - Initialize RX packet buffer 3308 * @hw: pointer to hardware structure 3309 * @num_pb: number of packet buffers to allocate 3310 * @headroom: reserve n KB of headroom 3311 * @strategy: packet buffer allocation strategy 3312 **/ 3313void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, 3314 int num_pb, 3315 u32 headroom, 3316 int strategy) 3317{ 3318 u32 pbsize = hw->mac.rx_pb_size; 3319 int i = 0; 3320 u32 rxpktsize, txpktsize, txpbthresh; 3321 3322 /* Reserve headroom */ 3323 pbsize -= headroom; 3324 3325 if (!num_pb) 3326 num_pb = 1; 3327 3328 /* Divide remaining packet buffer space amongst the number 3329 * of packet buffers requested using supplied strategy. 3330 */ 3331 switch (strategy) { 3332 case (PBA_STRATEGY_WEIGHTED): 3333 /* pba_80_48 strategy weight first half of packet buffer with 3334 * 5/8 of the packet buffer space. 3335 */ 3336 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8)); 3337 pbsize -= rxpktsize * (num_pb / 2); 3338 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 3339 for (; i < (num_pb / 2); i++) 3340 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3341 /* Fall through to configure remaining packet buffers */ 3342 case (PBA_STRATEGY_EQUAL): 3343 /* Divide the remaining Rx packet buffer evenly among the TCs */ 3344 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 3345 for (; i < num_pb; i++) 3346 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 3347 break; 3348 default: 3349 break; 3350 } 3351 3352 /* 3353 * Setup Tx packet buffer and threshold equally for all TCs 3354 * TXPBTHRESH register is set in K so divide by 1024 and subtract 3355 * 10 since the largest packet we support is just over 9K. 3356 */ 3357 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 3358 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 3359 for (i = 0; i < num_pb; i++) { 3360 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 3361 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 3362 } 3363 3364 /* Clear unused TCs, if any, to zero buffer size*/ 3365 for (; i < IXGBE_MAX_PB; i++) { 3366 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 3367 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 3368 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 3369 } 3370} 3371 3372/** 3373 * ixgbe_calculate_checksum - Calculate checksum for buffer 3374 * @buffer: pointer to EEPROM 3375 * @length: size of EEPROM to calculate a checksum for 3376 * Calculates the checksum for some buffer on a specified length. The 3377 * checksum calculated is returned. 3378 **/ 3379static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 3380{ 3381 u32 i; 3382 u8 sum = 0; 3383 3384 if (!buffer) 3385 return 0; 3386 3387 for (i = 0; i < length; i++) 3388 sum += buffer[i]; 3389 3390 return (u8) (0 - sum); 3391} 3392 3393/** 3394 * ixgbe_host_interface_command - Issue command to manageability block 3395 * @hw: pointer to the HW structure 3396 * @buffer: contains the command to write and where the return status will 3397 * be placed 3398 * @length: length of buffer, must be multiple of 4 bytes 3399 * 3400 * Communicates with the manageability block. On success return 0 3401 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. 3402 **/ 3403static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 3404 u32 length) 3405{ 3406 u32 hicr, i, bi; 3407 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 3408 u8 buf_len, dword_len; 3409 3410 s32 ret_val = 0; 3411 3412 if (length == 0 || length & 0x3 || 3413 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3414 hw_dbg(hw, "Buffer length failure.\n"); 3415 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3416 goto out; 3417 } 3418 3419 /* Check that the host interface is enabled. */ 3420 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3421 if ((hicr & IXGBE_HICR_EN) == 0) { 3422 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); 3423 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3424 goto out; 3425 } 3426 3427 /* Calculate length in DWORDs */ 3428 dword_len = length >> 2; 3429 3430 /* 3431 * The device driver writes the relevant command block 3432 * into the ram area. 3433 */ 3434 for (i = 0; i < dword_len; i++) 3435 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3436 i, cpu_to_le32(buffer[i])); 3437 3438 /* Setting this bit tells the ARC that a new command is pending. */ 3439 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 3440 3441 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) { 3442 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3443 if (!(hicr & IXGBE_HICR_C)) 3444 break; 3445 usleep_range(1000, 2000); 3446 } 3447 3448 /* Check command successful completion. */ 3449 if (i == IXGBE_HI_COMMAND_TIMEOUT || 3450 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) { 3451 hw_dbg(hw, "Command has failed with no status valid.\n"); 3452 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3453 goto out; 3454 } 3455 3456 /* Calculate length in DWORDs */ 3457 dword_len = hdr_size >> 2; 3458 3459 /* first pull in the header so we know the buffer length */ 3460 for (bi = 0; bi < dword_len; bi++) { 3461 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3462 le32_to_cpus(&buffer[bi]); 3463 } 3464 3465 /* If there is any thing in data position pull it in */ 3466 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len; 3467 if (buf_len == 0) 3468 goto out; 3469 3470 if (length < (buf_len + hdr_size)) { 3471 hw_dbg(hw, "Buffer not large enough for reply message.\n"); 3472 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3473 goto out; 3474 } 3475 3476 /* Calculate length in DWORDs, add 3 for odd lengths */ 3477 dword_len = (buf_len + 3) >> 2; 3478 3479 /* Pull in the rest of the buffer (bi is where we left off)*/ 3480 for (; bi <= dword_len; bi++) { 3481 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3482 le32_to_cpus(&buffer[bi]); 3483 } 3484 3485out: 3486 return ret_val; 3487} 3488 3489/** 3490 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 3491 * @hw: pointer to the HW structure 3492 * @maj: driver version major number 3493 * @min: driver version minor number 3494 * @build: driver version build number 3495 * @sub: driver version sub build number 3496 * 3497 * Sends driver version number to firmware through the manageability 3498 * block. On success return 0 3499 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 3500 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 3501 **/ 3502s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 3503 u8 build, u8 sub) 3504{ 3505 struct ixgbe_hic_drv_info fw_cmd; 3506 int i; 3507 s32 ret_val = 0; 3508 3509 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) { 3510 ret_val = IXGBE_ERR_SWFW_SYNC; 3511 goto out; 3512 } 3513 3514 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 3515 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 3516 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 3517 fw_cmd.port_num = (u8)hw->bus.func; 3518 fw_cmd.ver_maj = maj; 3519 fw_cmd.ver_min = min; 3520 fw_cmd.ver_build = build; 3521 fw_cmd.ver_sub = sub; 3522 fw_cmd.hdr.checksum = 0; 3523 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 3524 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 3525 fw_cmd.pad = 0; 3526 fw_cmd.pad2 = 0; 3527 3528 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 3529 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 3530 sizeof(fw_cmd)); 3531 if (ret_val != 0) 3532 continue; 3533 3534 if (fw_cmd.hdr.cmd_or_resp.ret_status == 3535 FW_CEM_RESP_STATUS_SUCCESS) 3536 ret_val = 0; 3537 else 3538 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3539 3540 break; 3541 } 3542 3543 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 3544out: 3545 return ret_val; 3546} 3547 3548/** 3549 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 3550 * @hw: pointer to the hardware structure 3551 * 3552 * The 82599 and x540 MACs can experience issues if TX work is still pending 3553 * when a reset occurs. This function prevents this by flushing the PCIe 3554 * buffers on the system. 3555 **/ 3556void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 3557{ 3558 u32 gcr_ext, hlreg0; 3559 3560 /* 3561 * If double reset is not requested then all transactions should 3562 * already be clear and as such there is no work to do 3563 */ 3564 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 3565 return; 3566 3567 /* 3568 * Set loopback enable to prevent any transmits from being sent 3569 * should the link come up. This assumes that the RXCTRL.RXEN bit 3570 * has already been cleared. 3571 */ 3572 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3573 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 3574 3575 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 3576 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 3577 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 3578 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 3579 3580 /* Flush all writes and allow 20usec for all transactions to clear */ 3581 IXGBE_WRITE_FLUSH(hw); 3582 udelay(20); 3583 3584 /* restore previous register values */ 3585 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3586 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3587} 3588