1/* 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> 4 * 5 * Based on the 64360 driver from: 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> 7 * Rabeeh Khoury <rabeeh@marvell.com> 8 * 9 * Copyright (C) 2003 PMC-Sierra, Inc., 10 * written by Manish Lachwani 11 * 12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> 13 * 14 * Copyright (C) 2004-2006 MontaVista Software, Inc. 15 * Dale Farnsworth <dale@farnsworth.org> 16 * 17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> 18 * <sjhill@realitydiluted.com> 19 * 20 * Copyright (C) 2007-2008 Marvell Semiconductor 21 * Lennert Buytenhek <buytenh@marvell.com> 22 * 23 * This program is free software; you can redistribute it and/or 24 * modify it under the terms of the GNU General Public License 25 * as published by the Free Software Foundation; either version 2 26 * of the License, or (at your option) any later version. 27 * 28 * This program is distributed in the hope that it will be useful, 29 * but WITHOUT ANY WARRANTY; without even the implied warranty of 30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 31 * GNU General Public License for more details. 32 * 33 * You should have received a copy of the GNU General Public License 34 * along with this program; if not, write to the Free Software 35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 36 */ 37 38#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 39 40#include <linux/init.h> 41#include <linux/dma-mapping.h> 42#include <linux/in.h> 43#include <linux/ip.h> 44#include <linux/tcp.h> 45#include <linux/udp.h> 46#include <linux/etherdevice.h> 47#include <linux/delay.h> 48#include <linux/ethtool.h> 49#include <linux/platform_device.h> 50#include <linux/module.h> 51#include <linux/kernel.h> 52#include <linux/spinlock.h> 53#include <linux/workqueue.h> 54#include <linux/phy.h> 55#include <linux/mv643xx_eth.h> 56#include <linux/io.h> 57#include <linux/types.h> 58#include <linux/inet_lro.h> 59#include <linux/slab.h> 60 61static char mv643xx_eth_driver_name[] = "mv643xx_eth"; 62static char mv643xx_eth_driver_version[] = "1.4"; 63 64 65/* 66 * Registers shared between all ports. 67 */ 68#define PHY_ADDR 0x0000 69#define SMI_REG 0x0004 70#define SMI_BUSY 0x10000000 71#define SMI_READ_VALID 0x08000000 72#define SMI_OPCODE_READ 0x04000000 73#define SMI_OPCODE_WRITE 0x00000000 74#define ERR_INT_CAUSE 0x0080 75#define ERR_INT_SMI_DONE 0x00000010 76#define ERR_INT_MASK 0x0084 77#define WINDOW_BASE(w) (0x0200 + ((w) << 3)) 78#define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) 79#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) 80#define WINDOW_BAR_ENABLE 0x0290 81#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) 82 83/* 84 * Main per-port registers. These live at offset 0x0400 for 85 * port #0, 0x0800 for port #1, and 0x0c00 for port #2. 86 */ 87#define PORT_CONFIG 0x0000 88#define UNICAST_PROMISCUOUS_MODE 0x00000001 89#define PORT_CONFIG_EXT 0x0004 90#define MAC_ADDR_LOW 0x0014 91#define MAC_ADDR_HIGH 0x0018 92#define SDMA_CONFIG 0x001c 93#define TX_BURST_SIZE_16_64BIT 0x01000000 94#define TX_BURST_SIZE_4_64BIT 0x00800000 95#define BLM_TX_NO_SWAP 0x00000020 96#define BLM_RX_NO_SWAP 0x00000010 97#define RX_BURST_SIZE_16_64BIT 0x00000008 98#define RX_BURST_SIZE_4_64BIT 0x00000004 99#define PORT_SERIAL_CONTROL 0x003c 100#define SET_MII_SPEED_TO_100 0x01000000 101#define SET_GMII_SPEED_TO_1000 0x00800000 102#define SET_FULL_DUPLEX_MODE 0x00200000 103#define MAX_RX_PACKET_9700BYTE 0x000a0000 104#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000 105#define DO_NOT_FORCE_LINK_FAIL 0x00000400 106#define SERIAL_PORT_CONTROL_RESERVED 0x00000200 107#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008 108#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004 109#define FORCE_LINK_PASS 0x00000002 110#define SERIAL_PORT_ENABLE 0x00000001 111#define PORT_STATUS 0x0044 112#define TX_FIFO_EMPTY 0x00000400 113#define TX_IN_PROGRESS 0x00000080 114#define PORT_SPEED_MASK 0x00000030 115#define PORT_SPEED_1000 0x00000010 116#define PORT_SPEED_100 0x00000020 117#define PORT_SPEED_10 0x00000000 118#define FLOW_CONTROL_ENABLED 0x00000008 119#define FULL_DUPLEX 0x00000004 120#define LINK_UP 0x00000002 121#define TXQ_COMMAND 0x0048 122#define TXQ_FIX_PRIO_CONF 0x004c 123#define TX_BW_RATE 0x0050 124#define TX_BW_MTU 0x0058 125#define TX_BW_BURST 0x005c 126#define INT_CAUSE 0x0060 127#define INT_TX_END 0x07f80000 128#define INT_TX_END_0 0x00080000 129#define INT_RX 0x000003fc 130#define INT_RX_0 0x00000004 131#define INT_EXT 0x00000002 132#define INT_CAUSE_EXT 0x0064 133#define INT_EXT_LINK_PHY 0x00110000 134#define INT_EXT_TX 0x000000ff 135#define INT_MASK 0x0068 136#define INT_MASK_EXT 0x006c 137#define TX_FIFO_URGENT_THRESHOLD 0x0074 138#define RX_DISCARD_FRAME_CNT 0x0084 139#define RX_OVERRUN_FRAME_CNT 0x0088 140#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc 141#define TX_BW_RATE_MOVED 0x00e0 142#define TX_BW_MTU_MOVED 0x00e8 143#define TX_BW_BURST_MOVED 0x00ec 144#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) 145#define RXQ_COMMAND 0x0280 146#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) 147#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) 148#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) 149#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) 150 151/* 152 * Misc per-port registers. 153 */ 154#define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) 155#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) 156#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) 157#define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) 158 159 160/* 161 * SDMA configuration register default value. 162 */ 163#if defined(__BIG_ENDIAN) 164#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 165 (RX_BURST_SIZE_4_64BIT | \ 166 TX_BURST_SIZE_4_64BIT) 167#elif defined(__LITTLE_ENDIAN) 168#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 169 (RX_BURST_SIZE_4_64BIT | \ 170 BLM_RX_NO_SWAP | \ 171 BLM_TX_NO_SWAP | \ 172 TX_BURST_SIZE_4_64BIT) 173#else 174#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 175#endif 176 177 178/* 179 * Misc definitions. 180 */ 181#define DEFAULT_RX_QUEUE_SIZE 128 182#define DEFAULT_TX_QUEUE_SIZE 256 183#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) 184 185 186/* 187 * RX/TX descriptors. 188 */ 189#if defined(__BIG_ENDIAN) 190struct rx_desc { 191 u16 byte_cnt; /* Descriptor buffer byte count */ 192 u16 buf_size; /* Buffer size */ 193 u32 cmd_sts; /* Descriptor command status */ 194 u32 next_desc_ptr; /* Next descriptor pointer */ 195 u32 buf_ptr; /* Descriptor buffer pointer */ 196}; 197 198struct tx_desc { 199 u16 byte_cnt; /* buffer byte count */ 200 u16 l4i_chk; /* CPU provided TCP checksum */ 201 u32 cmd_sts; /* Command/status field */ 202 u32 next_desc_ptr; /* Pointer to next descriptor */ 203 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 204}; 205#elif defined(__LITTLE_ENDIAN) 206struct rx_desc { 207 u32 cmd_sts; /* Descriptor command status */ 208 u16 buf_size; /* Buffer size */ 209 u16 byte_cnt; /* Descriptor buffer byte count */ 210 u32 buf_ptr; /* Descriptor buffer pointer */ 211 u32 next_desc_ptr; /* Next descriptor pointer */ 212}; 213 214struct tx_desc { 215 u32 cmd_sts; /* Command/status field */ 216 u16 l4i_chk; /* CPU provided TCP checksum */ 217 u16 byte_cnt; /* buffer byte count */ 218 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 219 u32 next_desc_ptr; /* Pointer to next descriptor */ 220}; 221#else 222#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 223#endif 224 225/* RX & TX descriptor command */ 226#define BUFFER_OWNED_BY_DMA 0x80000000 227 228/* RX & TX descriptor status */ 229#define ERROR_SUMMARY 0x00000001 230 231/* RX descriptor status */ 232#define LAYER_4_CHECKSUM_OK 0x40000000 233#define RX_ENABLE_INTERRUPT 0x20000000 234#define RX_FIRST_DESC 0x08000000 235#define RX_LAST_DESC 0x04000000 236#define RX_IP_HDR_OK 0x02000000 237#define RX_PKT_IS_IPV4 0x01000000 238#define RX_PKT_IS_ETHERNETV2 0x00800000 239#define RX_PKT_LAYER4_TYPE_MASK 0x00600000 240#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 241#define RX_PKT_IS_VLAN_TAGGED 0x00080000 242 243/* TX descriptor command */ 244#define TX_ENABLE_INTERRUPT 0x00800000 245#define GEN_CRC 0x00400000 246#define TX_FIRST_DESC 0x00200000 247#define TX_LAST_DESC 0x00100000 248#define ZERO_PADDING 0x00080000 249#define GEN_IP_V4_CHECKSUM 0x00040000 250#define GEN_TCP_UDP_CHECKSUM 0x00020000 251#define UDP_FRAME 0x00010000 252#define MAC_HDR_EXTRA_4_BYTES 0x00008000 253#define MAC_HDR_EXTRA_8_BYTES 0x00000200 254 255#define TX_IHL_SHIFT 11 256 257 258/* global *******************************************************************/ 259struct mv643xx_eth_shared_private { 260 /* 261 * Ethernet controller base address. 262 */ 263 void __iomem *base; 264 265 /* 266 * Points at the right SMI instance to use. 267 */ 268 struct mv643xx_eth_shared_private *smi; 269 270 /* 271 * Provides access to local SMI interface. 272 */ 273 struct mii_bus *smi_bus; 274 275 /* 276 * If we have access to the error interrupt pin (which is 277 * somewhat misnamed as it not only reflects internal errors 278 * but also reflects SMI completion), use that to wait for 279 * SMI access completion instead of polling the SMI busy bit. 280 */ 281 int err_interrupt; 282 wait_queue_head_t smi_busy_wait; 283 284 /* 285 * Per-port MBUS window access register value. 286 */ 287 u32 win_protect; 288 289 /* 290 * Hardware-specific parameters. 291 */ 292 unsigned int t_clk; 293 int extended_rx_coal_limit; 294 int tx_bw_control; 295 int tx_csum_limit; 296}; 297 298#define TX_BW_CONTROL_ABSENT 0 299#define TX_BW_CONTROL_OLD_LAYOUT 1 300#define TX_BW_CONTROL_NEW_LAYOUT 2 301 302static int mv643xx_eth_open(struct net_device *dev); 303static int mv643xx_eth_stop(struct net_device *dev); 304 305 306/* per-port *****************************************************************/ 307struct mib_counters { 308 u64 good_octets_received; 309 u32 bad_octets_received; 310 u32 internal_mac_transmit_err; 311 u32 good_frames_received; 312 u32 bad_frames_received; 313 u32 broadcast_frames_received; 314 u32 multicast_frames_received; 315 u32 frames_64_octets; 316 u32 frames_65_to_127_octets; 317 u32 frames_128_to_255_octets; 318 u32 frames_256_to_511_octets; 319 u32 frames_512_to_1023_octets; 320 u32 frames_1024_to_max_octets; 321 u64 good_octets_sent; 322 u32 good_frames_sent; 323 u32 excessive_collision; 324 u32 multicast_frames_sent; 325 u32 broadcast_frames_sent; 326 u32 unrec_mac_control_received; 327 u32 fc_sent; 328 u32 good_fc_received; 329 u32 bad_fc_received; 330 u32 undersize_received; 331 u32 fragments_received; 332 u32 oversize_received; 333 u32 jabber_received; 334 u32 mac_receive_error; 335 u32 bad_crc_event; 336 u32 collision; 337 u32 late_collision; 338 /* Non MIB hardware counters */ 339 u32 rx_discard; 340 u32 rx_overrun; 341}; 342 343struct lro_counters { 344 u32 lro_aggregated; 345 u32 lro_flushed; 346 u32 lro_no_desc; 347}; 348 349struct rx_queue { 350 int index; 351 352 int rx_ring_size; 353 354 int rx_desc_count; 355 int rx_curr_desc; 356 int rx_used_desc; 357 358 struct rx_desc *rx_desc_area; 359 dma_addr_t rx_desc_dma; 360 int rx_desc_area_size; 361 struct sk_buff **rx_skb; 362 363 struct net_lro_mgr lro_mgr; 364 struct net_lro_desc lro_arr[8]; 365}; 366 367struct tx_queue { 368 int index; 369 370 int tx_ring_size; 371 372 int tx_desc_count; 373 int tx_curr_desc; 374 int tx_used_desc; 375 376 struct tx_desc *tx_desc_area; 377 dma_addr_t tx_desc_dma; 378 int tx_desc_area_size; 379 380 struct sk_buff_head tx_skb; 381 382 unsigned long tx_packets; 383 unsigned long tx_bytes; 384 unsigned long tx_dropped; 385}; 386 387struct mv643xx_eth_private { 388 struct mv643xx_eth_shared_private *shared; 389 void __iomem *base; 390 int port_num; 391 392 struct net_device *dev; 393 394 struct phy_device *phy; 395 396 struct timer_list mib_counters_timer; 397 spinlock_t mib_counters_lock; 398 struct mib_counters mib_counters; 399 400 struct lro_counters lro_counters; 401 402 struct work_struct tx_timeout_task; 403 404 struct napi_struct napi; 405 u32 int_mask; 406 u8 oom; 407 u8 work_link; 408 u8 work_tx; 409 u8 work_tx_end; 410 u8 work_rx; 411 u8 work_rx_refill; 412 413 int skb_size; 414 struct sk_buff_head rx_recycle; 415 416 /* 417 * RX state. 418 */ 419 int rx_ring_size; 420 unsigned long rx_desc_sram_addr; 421 int rx_desc_sram_size; 422 int rxq_count; 423 struct timer_list rx_oom; 424 struct rx_queue rxq[8]; 425 426 /* 427 * TX state. 428 */ 429 int tx_ring_size; 430 unsigned long tx_desc_sram_addr; 431 int tx_desc_sram_size; 432 int txq_count; 433 struct tx_queue txq[8]; 434}; 435 436 437/* port register accessors **************************************************/ 438static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) 439{ 440 return readl(mp->shared->base + offset); 441} 442 443static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) 444{ 445 return readl(mp->base + offset); 446} 447 448static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) 449{ 450 writel(data, mp->shared->base + offset); 451} 452 453static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) 454{ 455 writel(data, mp->base + offset); 456} 457 458 459/* rxq/txq helper functions *************************************************/ 460static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) 461{ 462 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); 463} 464 465static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) 466{ 467 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); 468} 469 470static void rxq_enable(struct rx_queue *rxq) 471{ 472 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 473 wrlp(mp, RXQ_COMMAND, 1 << rxq->index); 474} 475 476static void rxq_disable(struct rx_queue *rxq) 477{ 478 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 479 u8 mask = 1 << rxq->index; 480 481 wrlp(mp, RXQ_COMMAND, mask << 8); 482 while (rdlp(mp, RXQ_COMMAND) & mask) 483 udelay(10); 484} 485 486static void txq_reset_hw_ptr(struct tx_queue *txq) 487{ 488 struct mv643xx_eth_private *mp = txq_to_mp(txq); 489 u32 addr; 490 491 addr = (u32)txq->tx_desc_dma; 492 addr += txq->tx_curr_desc * sizeof(struct tx_desc); 493 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); 494} 495 496static void txq_enable(struct tx_queue *txq) 497{ 498 struct mv643xx_eth_private *mp = txq_to_mp(txq); 499 wrlp(mp, TXQ_COMMAND, 1 << txq->index); 500} 501 502static void txq_disable(struct tx_queue *txq) 503{ 504 struct mv643xx_eth_private *mp = txq_to_mp(txq); 505 u8 mask = 1 << txq->index; 506 507 wrlp(mp, TXQ_COMMAND, mask << 8); 508 while (rdlp(mp, TXQ_COMMAND) & mask) 509 udelay(10); 510} 511 512static void txq_maybe_wake(struct tx_queue *txq) 513{ 514 struct mv643xx_eth_private *mp = txq_to_mp(txq); 515 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 516 517 if (netif_tx_queue_stopped(nq)) { 518 __netif_tx_lock(nq, smp_processor_id()); 519 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1) 520 netif_tx_wake_queue(nq); 521 __netif_tx_unlock(nq); 522 } 523} 524 525 526/* rx napi ******************************************************************/ 527static int 528mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph, 529 u64 *hdr_flags, void *priv) 530{ 531 unsigned long cmd_sts = (unsigned long)priv; 532 533 /* 534 * Make sure that this packet is Ethernet II, is not VLAN 535 * tagged, is IPv4, has a valid IP header, and is TCP. 536 */ 537 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 | 538 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK | 539 RX_PKT_IS_VLAN_TAGGED)) != 540 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 | 541 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4)) 542 return -1; 543 544 skb_reset_network_header(skb); 545 skb_set_transport_header(skb, ip_hdrlen(skb)); 546 *iphdr = ip_hdr(skb); 547 *tcph = tcp_hdr(skb); 548 *hdr_flags = LRO_IPV4 | LRO_TCP; 549 550 return 0; 551} 552 553static int rxq_process(struct rx_queue *rxq, int budget) 554{ 555 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 556 struct net_device_stats *stats = &mp->dev->stats; 557 int lro_flush_needed; 558 int rx; 559 560 lro_flush_needed = 0; 561 rx = 0; 562 while (rx < budget && rxq->rx_desc_count) { 563 struct rx_desc *rx_desc; 564 unsigned int cmd_sts; 565 struct sk_buff *skb; 566 u16 byte_cnt; 567 568 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; 569 570 cmd_sts = rx_desc->cmd_sts; 571 if (cmd_sts & BUFFER_OWNED_BY_DMA) 572 break; 573 rmb(); 574 575 skb = rxq->rx_skb[rxq->rx_curr_desc]; 576 rxq->rx_skb[rxq->rx_curr_desc] = NULL; 577 578 rxq->rx_curr_desc++; 579 if (rxq->rx_curr_desc == rxq->rx_ring_size) 580 rxq->rx_curr_desc = 0; 581 582 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr, 583 rx_desc->buf_size, DMA_FROM_DEVICE); 584 rxq->rx_desc_count--; 585 rx++; 586 587 mp->work_rx_refill |= 1 << rxq->index; 588 589 byte_cnt = rx_desc->byte_cnt; 590 591 /* 592 * Update statistics. 593 * 594 * Note that the descriptor byte count includes 2 dummy 595 * bytes automatically inserted by the hardware at the 596 * start of the packet (which we don't count), and a 4 597 * byte CRC at the end of the packet (which we do count). 598 */ 599 stats->rx_packets++; 600 stats->rx_bytes += byte_cnt - 2; 601 602 /* 603 * In case we received a packet without first / last bits 604 * on, or the error summary bit is set, the packet needs 605 * to be dropped. 606 */ 607 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) 608 != (RX_FIRST_DESC | RX_LAST_DESC)) 609 goto err; 610 611 /* 612 * The -4 is for the CRC in the trailer of the 613 * received packet 614 */ 615 skb_put(skb, byte_cnt - 2 - 4); 616 617 if (cmd_sts & LAYER_4_CHECKSUM_OK) 618 skb->ip_summed = CHECKSUM_UNNECESSARY; 619 skb->protocol = eth_type_trans(skb, mp->dev); 620 621 if (skb->dev->features & NETIF_F_LRO && 622 skb->ip_summed == CHECKSUM_UNNECESSARY) { 623 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts); 624 lro_flush_needed = 1; 625 } else 626 netif_receive_skb(skb); 627 628 continue; 629 630err: 631 stats->rx_dropped++; 632 633 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 634 (RX_FIRST_DESC | RX_LAST_DESC)) { 635 if (net_ratelimit()) 636 netdev_err(mp->dev, 637 "received packet spanning multiple descriptors\n"); 638 } 639 640 if (cmd_sts & ERROR_SUMMARY) 641 stats->rx_errors++; 642 643 dev_kfree_skb(skb); 644 } 645 646 if (lro_flush_needed) 647 lro_flush_all(&rxq->lro_mgr); 648 649 if (rx < budget) 650 mp->work_rx &= ~(1 << rxq->index); 651 652 return rx; 653} 654 655static int rxq_refill(struct rx_queue *rxq, int budget) 656{ 657 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 658 int refilled; 659 660 refilled = 0; 661 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { 662 struct sk_buff *skb; 663 int rx; 664 struct rx_desc *rx_desc; 665 int size; 666 667 skb = __skb_dequeue(&mp->rx_recycle); 668 if (skb == NULL) 669 skb = netdev_alloc_skb(mp->dev, mp->skb_size); 670 671 if (skb == NULL) { 672 mp->oom = 1; 673 goto oom; 674 } 675 676 if (SKB_DMA_REALIGN) 677 skb_reserve(skb, SKB_DMA_REALIGN); 678 679 refilled++; 680 rxq->rx_desc_count++; 681 682 rx = rxq->rx_used_desc++; 683 if (rxq->rx_used_desc == rxq->rx_ring_size) 684 rxq->rx_used_desc = 0; 685 686 rx_desc = rxq->rx_desc_area + rx; 687 688 size = skb->end - skb->data; 689 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent, 690 skb->data, size, 691 DMA_FROM_DEVICE); 692 rx_desc->buf_size = size; 693 rxq->rx_skb[rx] = skb; 694 wmb(); 695 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; 696 wmb(); 697 698 /* 699 * The hardware automatically prepends 2 bytes of 700 * dummy data to each received packet, so that the 701 * IP header ends up 16-byte aligned. 702 */ 703 skb_reserve(skb, 2); 704 } 705 706 if (refilled < budget) 707 mp->work_rx_refill &= ~(1 << rxq->index); 708 709oom: 710 return refilled; 711} 712 713 714/* tx ***********************************************************************/ 715static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) 716{ 717 int frag; 718 719 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 720 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; 721 722 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7) 723 return 1; 724 } 725 726 return 0; 727} 728 729static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) 730{ 731 struct mv643xx_eth_private *mp = txq_to_mp(txq); 732 int nr_frags = skb_shinfo(skb)->nr_frags; 733 int frag; 734 735 for (frag = 0; frag < nr_frags; frag++) { 736 skb_frag_t *this_frag; 737 int tx_index; 738 struct tx_desc *desc; 739 740 this_frag = &skb_shinfo(skb)->frags[frag]; 741 tx_index = txq->tx_curr_desc++; 742 if (txq->tx_curr_desc == txq->tx_ring_size) 743 txq->tx_curr_desc = 0; 744 desc = &txq->tx_desc_area[tx_index]; 745 746 /* 747 * The last fragment will generate an interrupt 748 * which will free the skb on TX completion. 749 */ 750 if (frag == nr_frags - 1) { 751 desc->cmd_sts = BUFFER_OWNED_BY_DMA | 752 ZERO_PADDING | TX_LAST_DESC | 753 TX_ENABLE_INTERRUPT; 754 } else { 755 desc->cmd_sts = BUFFER_OWNED_BY_DMA; 756 } 757 758 desc->l4i_chk = 0; 759 desc->byte_cnt = skb_frag_size(this_frag); 760 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent, 761 this_frag, 0, 762 skb_frag_size(this_frag), 763 DMA_TO_DEVICE); 764 } 765} 766 767static inline __be16 sum16_as_be(__sum16 sum) 768{ 769 return (__force __be16)sum; 770} 771 772static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) 773{ 774 struct mv643xx_eth_private *mp = txq_to_mp(txq); 775 int nr_frags = skb_shinfo(skb)->nr_frags; 776 int tx_index; 777 struct tx_desc *desc; 778 u32 cmd_sts; 779 u16 l4i_chk; 780 int length; 781 782 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; 783 l4i_chk = 0; 784 785 if (skb->ip_summed == CHECKSUM_PARTIAL) { 786 int hdr_len; 787 int tag_bytes; 788 789 BUG_ON(skb->protocol != htons(ETH_P_IP) && 790 skb->protocol != htons(ETH_P_8021Q)); 791 792 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data; 793 tag_bytes = hdr_len - ETH_HLEN; 794 if (skb->len - hdr_len > mp->shared->tx_csum_limit || 795 unlikely(tag_bytes & ~12)) { 796 if (skb_checksum_help(skb) == 0) 797 goto no_csum; 798 kfree_skb(skb); 799 return 1; 800 } 801 802 if (tag_bytes & 4) 803 cmd_sts |= MAC_HDR_EXTRA_4_BYTES; 804 if (tag_bytes & 8) 805 cmd_sts |= MAC_HDR_EXTRA_8_BYTES; 806 807 cmd_sts |= GEN_TCP_UDP_CHECKSUM | 808 GEN_IP_V4_CHECKSUM | 809 ip_hdr(skb)->ihl << TX_IHL_SHIFT; 810 811 switch (ip_hdr(skb)->protocol) { 812 case IPPROTO_UDP: 813 cmd_sts |= UDP_FRAME; 814 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); 815 break; 816 case IPPROTO_TCP: 817 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); 818 break; 819 default: 820 BUG(); 821 } 822 } else { 823no_csum: 824 /* Errata BTS #50, IHL must be 5 if no HW checksum */ 825 cmd_sts |= 5 << TX_IHL_SHIFT; 826 } 827 828 tx_index = txq->tx_curr_desc++; 829 if (txq->tx_curr_desc == txq->tx_ring_size) 830 txq->tx_curr_desc = 0; 831 desc = &txq->tx_desc_area[tx_index]; 832 833 if (nr_frags) { 834 txq_submit_frag_skb(txq, skb); 835 length = skb_headlen(skb); 836 } else { 837 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; 838 length = skb->len; 839 } 840 841 desc->l4i_chk = l4i_chk; 842 desc->byte_cnt = length; 843 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data, 844 length, DMA_TO_DEVICE); 845 846 __skb_queue_tail(&txq->tx_skb, skb); 847 848 skb_tx_timestamp(skb); 849 850 /* ensure all other descriptors are written before first cmd_sts */ 851 wmb(); 852 desc->cmd_sts = cmd_sts; 853 854 /* clear TX_END status */ 855 mp->work_tx_end &= ~(1 << txq->index); 856 857 /* ensure all descriptors are written before poking hardware */ 858 wmb(); 859 txq_enable(txq); 860 861 txq->tx_desc_count += nr_frags + 1; 862 863 return 0; 864} 865 866static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) 867{ 868 struct mv643xx_eth_private *mp = netdev_priv(dev); 869 int length, queue; 870 struct tx_queue *txq; 871 struct netdev_queue *nq; 872 873 queue = skb_get_queue_mapping(skb); 874 txq = mp->txq + queue; 875 nq = netdev_get_tx_queue(dev, queue); 876 877 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { 878 txq->tx_dropped++; 879 netdev_printk(KERN_DEBUG, dev, 880 "failed to linearize skb with tiny unaligned fragment\n"); 881 return NETDEV_TX_BUSY; 882 } 883 884 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { 885 if (net_ratelimit()) 886 netdev_err(dev, "tx queue full?!\n"); 887 kfree_skb(skb); 888 return NETDEV_TX_OK; 889 } 890 891 length = skb->len; 892 893 if (!txq_submit_skb(txq, skb)) { 894 int entries_left; 895 896 txq->tx_bytes += length; 897 txq->tx_packets++; 898 899 entries_left = txq->tx_ring_size - txq->tx_desc_count; 900 if (entries_left < MAX_SKB_FRAGS + 1) 901 netif_tx_stop_queue(nq); 902 } 903 904 return NETDEV_TX_OK; 905} 906 907 908/* tx napi ******************************************************************/ 909static void txq_kick(struct tx_queue *txq) 910{ 911 struct mv643xx_eth_private *mp = txq_to_mp(txq); 912 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 913 u32 hw_desc_ptr; 914 u32 expected_ptr; 915 916 __netif_tx_lock(nq, smp_processor_id()); 917 918 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) 919 goto out; 920 921 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); 922 expected_ptr = (u32)txq->tx_desc_dma + 923 txq->tx_curr_desc * sizeof(struct tx_desc); 924 925 if (hw_desc_ptr != expected_ptr) 926 txq_enable(txq); 927 928out: 929 __netif_tx_unlock(nq); 930 931 mp->work_tx_end &= ~(1 << txq->index); 932} 933 934static int txq_reclaim(struct tx_queue *txq, int budget, int force) 935{ 936 struct mv643xx_eth_private *mp = txq_to_mp(txq); 937 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 938 int reclaimed; 939 940 __netif_tx_lock(nq, smp_processor_id()); 941 942 reclaimed = 0; 943 while (reclaimed < budget && txq->tx_desc_count > 0) { 944 int tx_index; 945 struct tx_desc *desc; 946 u32 cmd_sts; 947 struct sk_buff *skb; 948 949 tx_index = txq->tx_used_desc; 950 desc = &txq->tx_desc_area[tx_index]; 951 cmd_sts = desc->cmd_sts; 952 953 if (cmd_sts & BUFFER_OWNED_BY_DMA) { 954 if (!force) 955 break; 956 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; 957 } 958 959 txq->tx_used_desc = tx_index + 1; 960 if (txq->tx_used_desc == txq->tx_ring_size) 961 txq->tx_used_desc = 0; 962 963 reclaimed++; 964 txq->tx_desc_count--; 965 966 skb = NULL; 967 if (cmd_sts & TX_LAST_DESC) 968 skb = __skb_dequeue(&txq->tx_skb); 969 970 if (cmd_sts & ERROR_SUMMARY) { 971 netdev_info(mp->dev, "tx error\n"); 972 mp->dev->stats.tx_errors++; 973 } 974 975 if (cmd_sts & TX_FIRST_DESC) { 976 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr, 977 desc->byte_cnt, DMA_TO_DEVICE); 978 } else { 979 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr, 980 desc->byte_cnt, DMA_TO_DEVICE); 981 } 982 983 if (skb != NULL) { 984 if (skb_queue_len(&mp->rx_recycle) < 985 mp->rx_ring_size && 986 skb_recycle_check(skb, mp->skb_size)) 987 __skb_queue_head(&mp->rx_recycle, skb); 988 else 989 dev_kfree_skb(skb); 990 } 991 } 992 993 __netif_tx_unlock(nq); 994 995 if (reclaimed < budget) 996 mp->work_tx &= ~(1 << txq->index); 997 998 return reclaimed; 999} 1000 1001 1002/* tx rate control **********************************************************/ 1003/* 1004 * Set total maximum TX rate (shared by all TX queues for this port) 1005 * to 'rate' bits per second, with a maximum burst of 'burst' bytes. 1006 */ 1007static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) 1008{ 1009 int token_rate; 1010 int mtu; 1011 int bucket_size; 1012 1013 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); 1014 if (token_rate > 1023) 1015 token_rate = 1023; 1016 1017 mtu = (mp->dev->mtu + 255) >> 8; 1018 if (mtu > 63) 1019 mtu = 63; 1020 1021 bucket_size = (burst + 255) >> 8; 1022 if (bucket_size > 65535) 1023 bucket_size = 65535; 1024 1025 switch (mp->shared->tx_bw_control) { 1026 case TX_BW_CONTROL_OLD_LAYOUT: 1027 wrlp(mp, TX_BW_RATE, token_rate); 1028 wrlp(mp, TX_BW_MTU, mtu); 1029 wrlp(mp, TX_BW_BURST, bucket_size); 1030 break; 1031 case TX_BW_CONTROL_NEW_LAYOUT: 1032 wrlp(mp, TX_BW_RATE_MOVED, token_rate); 1033 wrlp(mp, TX_BW_MTU_MOVED, mtu); 1034 wrlp(mp, TX_BW_BURST_MOVED, bucket_size); 1035 break; 1036 } 1037} 1038 1039static void txq_set_rate(struct tx_queue *txq, int rate, int burst) 1040{ 1041 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1042 int token_rate; 1043 int bucket_size; 1044 1045 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); 1046 if (token_rate > 1023) 1047 token_rate = 1023; 1048 1049 bucket_size = (burst + 255) >> 8; 1050 if (bucket_size > 65535) 1051 bucket_size = 65535; 1052 1053 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); 1054 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); 1055} 1056 1057static void txq_set_fixed_prio_mode(struct tx_queue *txq) 1058{ 1059 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1060 int off; 1061 u32 val; 1062 1063 /* 1064 * Turn on fixed priority mode. 1065 */ 1066 off = 0; 1067 switch (mp->shared->tx_bw_control) { 1068 case TX_BW_CONTROL_OLD_LAYOUT: 1069 off = TXQ_FIX_PRIO_CONF; 1070 break; 1071 case TX_BW_CONTROL_NEW_LAYOUT: 1072 off = TXQ_FIX_PRIO_CONF_MOVED; 1073 break; 1074 } 1075 1076 if (off) { 1077 val = rdlp(mp, off); 1078 val |= 1 << txq->index; 1079 wrlp(mp, off, val); 1080 } 1081} 1082 1083 1084/* mii management interface *************************************************/ 1085static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id) 1086{ 1087 struct mv643xx_eth_shared_private *msp = dev_id; 1088 1089 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) { 1090 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE); 1091 wake_up(&msp->smi_busy_wait); 1092 return IRQ_HANDLED; 1093 } 1094 1095 return IRQ_NONE; 1096} 1097 1098static int smi_is_done(struct mv643xx_eth_shared_private *msp) 1099{ 1100 return !(readl(msp->base + SMI_REG) & SMI_BUSY); 1101} 1102 1103static int smi_wait_ready(struct mv643xx_eth_shared_private *msp) 1104{ 1105 if (msp->err_interrupt == NO_IRQ) { 1106 int i; 1107 1108 for (i = 0; !smi_is_done(msp); i++) { 1109 if (i == 10) 1110 return -ETIMEDOUT; 1111 msleep(10); 1112 } 1113 1114 return 0; 1115 } 1116 1117 if (!smi_is_done(msp)) { 1118 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp), 1119 msecs_to_jiffies(100)); 1120 if (!smi_is_done(msp)) 1121 return -ETIMEDOUT; 1122 } 1123 1124 return 0; 1125} 1126 1127static int smi_bus_read(struct mii_bus *bus, int addr, int reg) 1128{ 1129 struct mv643xx_eth_shared_private *msp = bus->priv; 1130 void __iomem *smi_reg = msp->base + SMI_REG; 1131 int ret; 1132 1133 if (smi_wait_ready(msp)) { 1134 pr_warn("SMI bus busy timeout\n"); 1135 return -ETIMEDOUT; 1136 } 1137 1138 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg); 1139 1140 if (smi_wait_ready(msp)) { 1141 pr_warn("SMI bus busy timeout\n"); 1142 return -ETIMEDOUT; 1143 } 1144 1145 ret = readl(smi_reg); 1146 if (!(ret & SMI_READ_VALID)) { 1147 pr_warn("SMI bus read not valid\n"); 1148 return -ENODEV; 1149 } 1150 1151 return ret & 0xffff; 1152} 1153 1154static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val) 1155{ 1156 struct mv643xx_eth_shared_private *msp = bus->priv; 1157 void __iomem *smi_reg = msp->base + SMI_REG; 1158 1159 if (smi_wait_ready(msp)) { 1160 pr_warn("SMI bus busy timeout\n"); 1161 return -ETIMEDOUT; 1162 } 1163 1164 writel(SMI_OPCODE_WRITE | (reg << 21) | 1165 (addr << 16) | (val & 0xffff), smi_reg); 1166 1167 if (smi_wait_ready(msp)) { 1168 pr_warn("SMI bus busy timeout\n"); 1169 return -ETIMEDOUT; 1170 } 1171 1172 return 0; 1173} 1174 1175 1176/* statistics ***************************************************************/ 1177static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) 1178{ 1179 struct mv643xx_eth_private *mp = netdev_priv(dev); 1180 struct net_device_stats *stats = &dev->stats; 1181 unsigned long tx_packets = 0; 1182 unsigned long tx_bytes = 0; 1183 unsigned long tx_dropped = 0; 1184 int i; 1185 1186 for (i = 0; i < mp->txq_count; i++) { 1187 struct tx_queue *txq = mp->txq + i; 1188 1189 tx_packets += txq->tx_packets; 1190 tx_bytes += txq->tx_bytes; 1191 tx_dropped += txq->tx_dropped; 1192 } 1193 1194 stats->tx_packets = tx_packets; 1195 stats->tx_bytes = tx_bytes; 1196 stats->tx_dropped = tx_dropped; 1197 1198 return stats; 1199} 1200 1201static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp) 1202{ 1203 u32 lro_aggregated = 0; 1204 u32 lro_flushed = 0; 1205 u32 lro_no_desc = 0; 1206 int i; 1207 1208 for (i = 0; i < mp->rxq_count; i++) { 1209 struct rx_queue *rxq = mp->rxq + i; 1210 1211 lro_aggregated += rxq->lro_mgr.stats.aggregated; 1212 lro_flushed += rxq->lro_mgr.stats.flushed; 1213 lro_no_desc += rxq->lro_mgr.stats.no_desc; 1214 } 1215 1216 mp->lro_counters.lro_aggregated = lro_aggregated; 1217 mp->lro_counters.lro_flushed = lro_flushed; 1218 mp->lro_counters.lro_no_desc = lro_no_desc; 1219} 1220 1221static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) 1222{ 1223 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); 1224} 1225 1226static void mib_counters_clear(struct mv643xx_eth_private *mp) 1227{ 1228 int i; 1229 1230 for (i = 0; i < 0x80; i += 4) 1231 mib_read(mp, i); 1232 1233 /* Clear non MIB hw counters also */ 1234 rdlp(mp, RX_DISCARD_FRAME_CNT); 1235 rdlp(mp, RX_OVERRUN_FRAME_CNT); 1236} 1237 1238static void mib_counters_update(struct mv643xx_eth_private *mp) 1239{ 1240 struct mib_counters *p = &mp->mib_counters; 1241 1242 spin_lock_bh(&mp->mib_counters_lock); 1243 p->good_octets_received += mib_read(mp, 0x00); 1244 p->bad_octets_received += mib_read(mp, 0x08); 1245 p->internal_mac_transmit_err += mib_read(mp, 0x0c); 1246 p->good_frames_received += mib_read(mp, 0x10); 1247 p->bad_frames_received += mib_read(mp, 0x14); 1248 p->broadcast_frames_received += mib_read(mp, 0x18); 1249 p->multicast_frames_received += mib_read(mp, 0x1c); 1250 p->frames_64_octets += mib_read(mp, 0x20); 1251 p->frames_65_to_127_octets += mib_read(mp, 0x24); 1252 p->frames_128_to_255_octets += mib_read(mp, 0x28); 1253 p->frames_256_to_511_octets += mib_read(mp, 0x2c); 1254 p->frames_512_to_1023_octets += mib_read(mp, 0x30); 1255 p->frames_1024_to_max_octets += mib_read(mp, 0x34); 1256 p->good_octets_sent += mib_read(mp, 0x38); 1257 p->good_frames_sent += mib_read(mp, 0x40); 1258 p->excessive_collision += mib_read(mp, 0x44); 1259 p->multicast_frames_sent += mib_read(mp, 0x48); 1260 p->broadcast_frames_sent += mib_read(mp, 0x4c); 1261 p->unrec_mac_control_received += mib_read(mp, 0x50); 1262 p->fc_sent += mib_read(mp, 0x54); 1263 p->good_fc_received += mib_read(mp, 0x58); 1264 p->bad_fc_received += mib_read(mp, 0x5c); 1265 p->undersize_received += mib_read(mp, 0x60); 1266 p->fragments_received += mib_read(mp, 0x64); 1267 p->oversize_received += mib_read(mp, 0x68); 1268 p->jabber_received += mib_read(mp, 0x6c); 1269 p->mac_receive_error += mib_read(mp, 0x70); 1270 p->bad_crc_event += mib_read(mp, 0x74); 1271 p->collision += mib_read(mp, 0x78); 1272 p->late_collision += mib_read(mp, 0x7c); 1273 /* Non MIB hardware counters */ 1274 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT); 1275 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT); 1276 spin_unlock_bh(&mp->mib_counters_lock); 1277 1278 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); 1279} 1280 1281static void mib_counters_timer_wrapper(unsigned long _mp) 1282{ 1283 struct mv643xx_eth_private *mp = (void *)_mp; 1284 1285 mib_counters_update(mp); 1286} 1287 1288 1289/* interrupt coalescing *****************************************************/ 1290/* 1291 * Hardware coalescing parameters are set in units of 64 t_clk 1292 * cycles. I.e.: 1293 * 1294 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate 1295 * 1296 * register_value = coal_delay_in_usec * t_clk_rate / 64000000 1297 * 1298 * In the ->set*() methods, we round the computed register value 1299 * to the nearest integer. 1300 */ 1301static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) 1302{ 1303 u32 val = rdlp(mp, SDMA_CONFIG); 1304 u64 temp; 1305 1306 if (mp->shared->extended_rx_coal_limit) 1307 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); 1308 else 1309 temp = (val & 0x003fff00) >> 8; 1310 1311 temp *= 64000000; 1312 do_div(temp, mp->shared->t_clk); 1313 1314 return (unsigned int)temp; 1315} 1316 1317static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1318{ 1319 u64 temp; 1320 u32 val; 1321 1322 temp = (u64)usec * mp->shared->t_clk; 1323 temp += 31999999; 1324 do_div(temp, 64000000); 1325 1326 val = rdlp(mp, SDMA_CONFIG); 1327 if (mp->shared->extended_rx_coal_limit) { 1328 if (temp > 0xffff) 1329 temp = 0xffff; 1330 val &= ~0x023fff80; 1331 val |= (temp & 0x8000) << 10; 1332 val |= (temp & 0x7fff) << 7; 1333 } else { 1334 if (temp > 0x3fff) 1335 temp = 0x3fff; 1336 val &= ~0x003fff00; 1337 val |= (temp & 0x3fff) << 8; 1338 } 1339 wrlp(mp, SDMA_CONFIG, val); 1340} 1341 1342static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) 1343{ 1344 u64 temp; 1345 1346 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; 1347 temp *= 64000000; 1348 do_div(temp, mp->shared->t_clk); 1349 1350 return (unsigned int)temp; 1351} 1352 1353static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1354{ 1355 u64 temp; 1356 1357 temp = (u64)usec * mp->shared->t_clk; 1358 temp += 31999999; 1359 do_div(temp, 64000000); 1360 1361 if (temp > 0x3fff) 1362 temp = 0x3fff; 1363 1364 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); 1365} 1366 1367 1368/* ethtool ******************************************************************/ 1369struct mv643xx_eth_stats { 1370 char stat_string[ETH_GSTRING_LEN]; 1371 int sizeof_stat; 1372 int netdev_off; 1373 int mp_off; 1374}; 1375 1376#define SSTAT(m) \ 1377 { #m, FIELD_SIZEOF(struct net_device_stats, m), \ 1378 offsetof(struct net_device, stats.m), -1 } 1379 1380#define MIBSTAT(m) \ 1381 { #m, FIELD_SIZEOF(struct mib_counters, m), \ 1382 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } 1383 1384#define LROSTAT(m) \ 1385 { #m, FIELD_SIZEOF(struct lro_counters, m), \ 1386 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) } 1387 1388static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { 1389 SSTAT(rx_packets), 1390 SSTAT(tx_packets), 1391 SSTAT(rx_bytes), 1392 SSTAT(tx_bytes), 1393 SSTAT(rx_errors), 1394 SSTAT(tx_errors), 1395 SSTAT(rx_dropped), 1396 SSTAT(tx_dropped), 1397 MIBSTAT(good_octets_received), 1398 MIBSTAT(bad_octets_received), 1399 MIBSTAT(internal_mac_transmit_err), 1400 MIBSTAT(good_frames_received), 1401 MIBSTAT(bad_frames_received), 1402 MIBSTAT(broadcast_frames_received), 1403 MIBSTAT(multicast_frames_received), 1404 MIBSTAT(frames_64_octets), 1405 MIBSTAT(frames_65_to_127_octets), 1406 MIBSTAT(frames_128_to_255_octets), 1407 MIBSTAT(frames_256_to_511_octets), 1408 MIBSTAT(frames_512_to_1023_octets), 1409 MIBSTAT(frames_1024_to_max_octets), 1410 MIBSTAT(good_octets_sent), 1411 MIBSTAT(good_frames_sent), 1412 MIBSTAT(excessive_collision), 1413 MIBSTAT(multicast_frames_sent), 1414 MIBSTAT(broadcast_frames_sent), 1415 MIBSTAT(unrec_mac_control_received), 1416 MIBSTAT(fc_sent), 1417 MIBSTAT(good_fc_received), 1418 MIBSTAT(bad_fc_received), 1419 MIBSTAT(undersize_received), 1420 MIBSTAT(fragments_received), 1421 MIBSTAT(oversize_received), 1422 MIBSTAT(jabber_received), 1423 MIBSTAT(mac_receive_error), 1424 MIBSTAT(bad_crc_event), 1425 MIBSTAT(collision), 1426 MIBSTAT(late_collision), 1427 MIBSTAT(rx_discard), 1428 MIBSTAT(rx_overrun), 1429 LROSTAT(lro_aggregated), 1430 LROSTAT(lro_flushed), 1431 LROSTAT(lro_no_desc), 1432}; 1433 1434static int 1435mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp, 1436 struct ethtool_cmd *cmd) 1437{ 1438 int err; 1439 1440 err = phy_read_status(mp->phy); 1441 if (err == 0) 1442 err = phy_ethtool_gset(mp->phy, cmd); 1443 1444 /* 1445 * The MAC does not support 1000baseT_Half. 1446 */ 1447 cmd->supported &= ~SUPPORTED_1000baseT_Half; 1448 cmd->advertising &= ~ADVERTISED_1000baseT_Half; 1449 1450 return err; 1451} 1452 1453static int 1454mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp, 1455 struct ethtool_cmd *cmd) 1456{ 1457 u32 port_status; 1458 1459 port_status = rdlp(mp, PORT_STATUS); 1460 1461 cmd->supported = SUPPORTED_MII; 1462 cmd->advertising = ADVERTISED_MII; 1463 switch (port_status & PORT_SPEED_MASK) { 1464 case PORT_SPEED_10: 1465 ethtool_cmd_speed_set(cmd, SPEED_10); 1466 break; 1467 case PORT_SPEED_100: 1468 ethtool_cmd_speed_set(cmd, SPEED_100); 1469 break; 1470 case PORT_SPEED_1000: 1471 ethtool_cmd_speed_set(cmd, SPEED_1000); 1472 break; 1473 default: 1474 cmd->speed = -1; 1475 break; 1476 } 1477 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; 1478 cmd->port = PORT_MII; 1479 cmd->phy_address = 0; 1480 cmd->transceiver = XCVR_INTERNAL; 1481 cmd->autoneg = AUTONEG_DISABLE; 1482 cmd->maxtxpkt = 1; 1483 cmd->maxrxpkt = 1; 1484 1485 return 0; 1486} 1487 1488static int 1489mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1490{ 1491 struct mv643xx_eth_private *mp = netdev_priv(dev); 1492 1493 if (mp->phy != NULL) 1494 return mv643xx_eth_get_settings_phy(mp, cmd); 1495 else 1496 return mv643xx_eth_get_settings_phyless(mp, cmd); 1497} 1498 1499static int 1500mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1501{ 1502 struct mv643xx_eth_private *mp = netdev_priv(dev); 1503 1504 if (mp->phy == NULL) 1505 return -EINVAL; 1506 1507 /* 1508 * The MAC does not support 1000baseT_Half. 1509 */ 1510 cmd->advertising &= ~ADVERTISED_1000baseT_Half; 1511 1512 return phy_ethtool_sset(mp->phy, cmd); 1513} 1514 1515static void mv643xx_eth_get_drvinfo(struct net_device *dev, 1516 struct ethtool_drvinfo *drvinfo) 1517{ 1518 strlcpy(drvinfo->driver, mv643xx_eth_driver_name, 1519 sizeof(drvinfo->driver)); 1520 strlcpy(drvinfo->version, mv643xx_eth_driver_version, 1521 sizeof(drvinfo->version)); 1522 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); 1523 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info)); 1524 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); 1525} 1526 1527static int mv643xx_eth_nway_reset(struct net_device *dev) 1528{ 1529 struct mv643xx_eth_private *mp = netdev_priv(dev); 1530 1531 if (mp->phy == NULL) 1532 return -EINVAL; 1533 1534 return genphy_restart_aneg(mp->phy); 1535} 1536 1537static int 1538mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1539{ 1540 struct mv643xx_eth_private *mp = netdev_priv(dev); 1541 1542 ec->rx_coalesce_usecs = get_rx_coal(mp); 1543 ec->tx_coalesce_usecs = get_tx_coal(mp); 1544 1545 return 0; 1546} 1547 1548static int 1549mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1550{ 1551 struct mv643xx_eth_private *mp = netdev_priv(dev); 1552 1553 set_rx_coal(mp, ec->rx_coalesce_usecs); 1554 set_tx_coal(mp, ec->tx_coalesce_usecs); 1555 1556 return 0; 1557} 1558 1559static void 1560mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) 1561{ 1562 struct mv643xx_eth_private *mp = netdev_priv(dev); 1563 1564 er->rx_max_pending = 4096; 1565 er->tx_max_pending = 4096; 1566 1567 er->rx_pending = mp->rx_ring_size; 1568 er->tx_pending = mp->tx_ring_size; 1569} 1570 1571static int 1572mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) 1573{ 1574 struct mv643xx_eth_private *mp = netdev_priv(dev); 1575 1576 if (er->rx_mini_pending || er->rx_jumbo_pending) 1577 return -EINVAL; 1578 1579 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096; 1580 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096; 1581 1582 if (netif_running(dev)) { 1583 mv643xx_eth_stop(dev); 1584 if (mv643xx_eth_open(dev)) { 1585 netdev_err(dev, 1586 "fatal error on re-opening device after ring param change\n"); 1587 return -ENOMEM; 1588 } 1589 } 1590 1591 return 0; 1592} 1593 1594 1595static int 1596mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features) 1597{ 1598 struct mv643xx_eth_private *mp = netdev_priv(dev); 1599 bool rx_csum = features & NETIF_F_RXCSUM; 1600 1601 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); 1602 1603 return 0; 1604} 1605 1606static void mv643xx_eth_get_strings(struct net_device *dev, 1607 uint32_t stringset, uint8_t *data) 1608{ 1609 int i; 1610 1611 if (stringset == ETH_SS_STATS) { 1612 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { 1613 memcpy(data + i * ETH_GSTRING_LEN, 1614 mv643xx_eth_stats[i].stat_string, 1615 ETH_GSTRING_LEN); 1616 } 1617 } 1618} 1619 1620static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, 1621 struct ethtool_stats *stats, 1622 uint64_t *data) 1623{ 1624 struct mv643xx_eth_private *mp = netdev_priv(dev); 1625 int i; 1626 1627 mv643xx_eth_get_stats(dev); 1628 mib_counters_update(mp); 1629 mv643xx_eth_grab_lro_stats(mp); 1630 1631 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { 1632 const struct mv643xx_eth_stats *stat; 1633 void *p; 1634 1635 stat = mv643xx_eth_stats + i; 1636 1637 if (stat->netdev_off >= 0) 1638 p = ((void *)mp->dev) + stat->netdev_off; 1639 else 1640 p = ((void *)mp) + stat->mp_off; 1641 1642 data[i] = (stat->sizeof_stat == 8) ? 1643 *(uint64_t *)p : *(uint32_t *)p; 1644 } 1645} 1646 1647static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) 1648{ 1649 if (sset == ETH_SS_STATS) 1650 return ARRAY_SIZE(mv643xx_eth_stats); 1651 1652 return -EOPNOTSUPP; 1653} 1654 1655static const struct ethtool_ops mv643xx_eth_ethtool_ops = { 1656 .get_settings = mv643xx_eth_get_settings, 1657 .set_settings = mv643xx_eth_set_settings, 1658 .get_drvinfo = mv643xx_eth_get_drvinfo, 1659 .nway_reset = mv643xx_eth_nway_reset, 1660 .get_link = ethtool_op_get_link, 1661 .get_coalesce = mv643xx_eth_get_coalesce, 1662 .set_coalesce = mv643xx_eth_set_coalesce, 1663 .get_ringparam = mv643xx_eth_get_ringparam, 1664 .set_ringparam = mv643xx_eth_set_ringparam, 1665 .get_strings = mv643xx_eth_get_strings, 1666 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, 1667 .get_sset_count = mv643xx_eth_get_sset_count, 1668}; 1669 1670 1671/* address handling *********************************************************/ 1672static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) 1673{ 1674 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); 1675 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); 1676 1677 addr[0] = (mac_h >> 24) & 0xff; 1678 addr[1] = (mac_h >> 16) & 0xff; 1679 addr[2] = (mac_h >> 8) & 0xff; 1680 addr[3] = mac_h & 0xff; 1681 addr[4] = (mac_l >> 8) & 0xff; 1682 addr[5] = mac_l & 0xff; 1683} 1684 1685static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) 1686{ 1687 wrlp(mp, MAC_ADDR_HIGH, 1688 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); 1689 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); 1690} 1691 1692static u32 uc_addr_filter_mask(struct net_device *dev) 1693{ 1694 struct netdev_hw_addr *ha; 1695 u32 nibbles; 1696 1697 if (dev->flags & IFF_PROMISC) 1698 return 0; 1699 1700 nibbles = 1 << (dev->dev_addr[5] & 0x0f); 1701 netdev_for_each_uc_addr(ha, dev) { 1702 if (memcmp(dev->dev_addr, ha->addr, 5)) 1703 return 0; 1704 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0) 1705 return 0; 1706 1707 nibbles |= 1 << (ha->addr[5] & 0x0f); 1708 } 1709 1710 return nibbles; 1711} 1712 1713static void mv643xx_eth_program_unicast_filter(struct net_device *dev) 1714{ 1715 struct mv643xx_eth_private *mp = netdev_priv(dev); 1716 u32 port_config; 1717 u32 nibbles; 1718 int i; 1719 1720 uc_addr_set(mp, dev->dev_addr); 1721 1722 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE; 1723 1724 nibbles = uc_addr_filter_mask(dev); 1725 if (!nibbles) { 1726 port_config |= UNICAST_PROMISCUOUS_MODE; 1727 nibbles = 0xffff; 1728 } 1729 1730 for (i = 0; i < 16; i += 4) { 1731 int off = UNICAST_TABLE(mp->port_num) + i; 1732 u32 v; 1733 1734 v = 0; 1735 if (nibbles & 1) 1736 v |= 0x00000001; 1737 if (nibbles & 2) 1738 v |= 0x00000100; 1739 if (nibbles & 4) 1740 v |= 0x00010000; 1741 if (nibbles & 8) 1742 v |= 0x01000000; 1743 nibbles >>= 4; 1744 1745 wrl(mp, off, v); 1746 } 1747 1748 wrlp(mp, PORT_CONFIG, port_config); 1749} 1750 1751static int addr_crc(unsigned char *addr) 1752{ 1753 int crc = 0; 1754 int i; 1755 1756 for (i = 0; i < 6; i++) { 1757 int j; 1758 1759 crc = (crc ^ addr[i]) << 8; 1760 for (j = 7; j >= 0; j--) { 1761 if (crc & (0x100 << j)) 1762 crc ^= 0x107 << j; 1763 } 1764 } 1765 1766 return crc; 1767} 1768 1769static void mv643xx_eth_program_multicast_filter(struct net_device *dev) 1770{ 1771 struct mv643xx_eth_private *mp = netdev_priv(dev); 1772 u32 *mc_spec; 1773 u32 *mc_other; 1774 struct netdev_hw_addr *ha; 1775 int i; 1776 1777 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1778 int port_num; 1779 u32 accept; 1780 1781oom: 1782 port_num = mp->port_num; 1783 accept = 0x01010101; 1784 for (i = 0; i < 0x100; i += 4) { 1785 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); 1786 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); 1787 } 1788 return; 1789 } 1790 1791 mc_spec = kmalloc(0x200, GFP_ATOMIC); 1792 if (mc_spec == NULL) 1793 goto oom; 1794 mc_other = mc_spec + (0x100 >> 2); 1795 1796 memset(mc_spec, 0, 0x100); 1797 memset(mc_other, 0, 0x100); 1798 1799 netdev_for_each_mc_addr(ha, dev) { 1800 u8 *a = ha->addr; 1801 u32 *table; 1802 int entry; 1803 1804 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { 1805 table = mc_spec; 1806 entry = a[5]; 1807 } else { 1808 table = mc_other; 1809 entry = addr_crc(a); 1810 } 1811 1812 table[entry >> 2] |= 1 << (8 * (entry & 3)); 1813 } 1814 1815 for (i = 0; i < 0x100; i += 4) { 1816 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]); 1817 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]); 1818 } 1819 1820 kfree(mc_spec); 1821} 1822 1823static void mv643xx_eth_set_rx_mode(struct net_device *dev) 1824{ 1825 mv643xx_eth_program_unicast_filter(dev); 1826 mv643xx_eth_program_multicast_filter(dev); 1827} 1828 1829static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) 1830{ 1831 struct sockaddr *sa = addr; 1832 1833 if (!is_valid_ether_addr(sa->sa_data)) 1834 return -EADDRNOTAVAIL; 1835 1836 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); 1837 1838 netif_addr_lock_bh(dev); 1839 mv643xx_eth_program_unicast_filter(dev); 1840 netif_addr_unlock_bh(dev); 1841 1842 return 0; 1843} 1844 1845 1846/* rx/tx queue initialisation ***********************************************/ 1847static int rxq_init(struct mv643xx_eth_private *mp, int index) 1848{ 1849 struct rx_queue *rxq = mp->rxq + index; 1850 struct rx_desc *rx_desc; 1851 int size; 1852 int i; 1853 1854 rxq->index = index; 1855 1856 rxq->rx_ring_size = mp->rx_ring_size; 1857 1858 rxq->rx_desc_count = 0; 1859 rxq->rx_curr_desc = 0; 1860 rxq->rx_used_desc = 0; 1861 1862 size = rxq->rx_ring_size * sizeof(struct rx_desc); 1863 1864 if (index == 0 && size <= mp->rx_desc_sram_size) { 1865 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, 1866 mp->rx_desc_sram_size); 1867 rxq->rx_desc_dma = mp->rx_desc_sram_addr; 1868 } else { 1869 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 1870 size, &rxq->rx_desc_dma, 1871 GFP_KERNEL); 1872 } 1873 1874 if (rxq->rx_desc_area == NULL) { 1875 netdev_err(mp->dev, 1876 "can't allocate rx ring (%d bytes)\n", size); 1877 goto out; 1878 } 1879 memset(rxq->rx_desc_area, 0, size); 1880 1881 rxq->rx_desc_area_size = size; 1882 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb), 1883 GFP_KERNEL); 1884 if (rxq->rx_skb == NULL) { 1885 netdev_err(mp->dev, "can't allocate rx skb ring\n"); 1886 goto out_free; 1887 } 1888 1889 rx_desc = (struct rx_desc *)rxq->rx_desc_area; 1890 for (i = 0; i < rxq->rx_ring_size; i++) { 1891 int nexti; 1892 1893 nexti = i + 1; 1894 if (nexti == rxq->rx_ring_size) 1895 nexti = 0; 1896 1897 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + 1898 nexti * sizeof(struct rx_desc); 1899 } 1900 1901 rxq->lro_mgr.dev = mp->dev; 1902 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats)); 1903 rxq->lro_mgr.features = LRO_F_NAPI; 1904 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; 1905 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; 1906 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr); 1907 rxq->lro_mgr.max_aggr = 32; 1908 rxq->lro_mgr.frag_align_pad = 0; 1909 rxq->lro_mgr.lro_arr = rxq->lro_arr; 1910 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header; 1911 1912 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr)); 1913 1914 return 0; 1915 1916 1917out_free: 1918 if (index == 0 && size <= mp->rx_desc_sram_size) 1919 iounmap(rxq->rx_desc_area); 1920 else 1921 dma_free_coherent(mp->dev->dev.parent, size, 1922 rxq->rx_desc_area, 1923 rxq->rx_desc_dma); 1924 1925out: 1926 return -ENOMEM; 1927} 1928 1929static void rxq_deinit(struct rx_queue *rxq) 1930{ 1931 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 1932 int i; 1933 1934 rxq_disable(rxq); 1935 1936 for (i = 0; i < rxq->rx_ring_size; i++) { 1937 if (rxq->rx_skb[i]) { 1938 dev_kfree_skb(rxq->rx_skb[i]); 1939 rxq->rx_desc_count--; 1940 } 1941 } 1942 1943 if (rxq->rx_desc_count) { 1944 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n", 1945 rxq->rx_desc_count); 1946 } 1947 1948 if (rxq->index == 0 && 1949 rxq->rx_desc_area_size <= mp->rx_desc_sram_size) 1950 iounmap(rxq->rx_desc_area); 1951 else 1952 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size, 1953 rxq->rx_desc_area, rxq->rx_desc_dma); 1954 1955 kfree(rxq->rx_skb); 1956} 1957 1958static int txq_init(struct mv643xx_eth_private *mp, int index) 1959{ 1960 struct tx_queue *txq = mp->txq + index; 1961 struct tx_desc *tx_desc; 1962 int size; 1963 int i; 1964 1965 txq->index = index; 1966 1967 txq->tx_ring_size = mp->tx_ring_size; 1968 1969 txq->tx_desc_count = 0; 1970 txq->tx_curr_desc = 0; 1971 txq->tx_used_desc = 0; 1972 1973 size = txq->tx_ring_size * sizeof(struct tx_desc); 1974 1975 if (index == 0 && size <= mp->tx_desc_sram_size) { 1976 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, 1977 mp->tx_desc_sram_size); 1978 txq->tx_desc_dma = mp->tx_desc_sram_addr; 1979 } else { 1980 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 1981 size, &txq->tx_desc_dma, 1982 GFP_KERNEL); 1983 } 1984 1985 if (txq->tx_desc_area == NULL) { 1986 netdev_err(mp->dev, 1987 "can't allocate tx ring (%d bytes)\n", size); 1988 return -ENOMEM; 1989 } 1990 memset(txq->tx_desc_area, 0, size); 1991 1992 txq->tx_desc_area_size = size; 1993 1994 tx_desc = (struct tx_desc *)txq->tx_desc_area; 1995 for (i = 0; i < txq->tx_ring_size; i++) { 1996 struct tx_desc *txd = tx_desc + i; 1997 int nexti; 1998 1999 nexti = i + 1; 2000 if (nexti == txq->tx_ring_size) 2001 nexti = 0; 2002 2003 txd->cmd_sts = 0; 2004 txd->next_desc_ptr = txq->tx_desc_dma + 2005 nexti * sizeof(struct tx_desc); 2006 } 2007 2008 skb_queue_head_init(&txq->tx_skb); 2009 2010 return 0; 2011} 2012 2013static void txq_deinit(struct tx_queue *txq) 2014{ 2015 struct mv643xx_eth_private *mp = txq_to_mp(txq); 2016 2017 txq_disable(txq); 2018 txq_reclaim(txq, txq->tx_ring_size, 1); 2019 2020 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); 2021 2022 if (txq->index == 0 && 2023 txq->tx_desc_area_size <= mp->tx_desc_sram_size) 2024 iounmap(txq->tx_desc_area); 2025 else 2026 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, 2027 txq->tx_desc_area, txq->tx_desc_dma); 2028} 2029 2030 2031/* netdev ops and related ***************************************************/ 2032static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) 2033{ 2034 u32 int_cause; 2035 u32 int_cause_ext; 2036 2037 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask; 2038 if (int_cause == 0) 2039 return 0; 2040 2041 int_cause_ext = 0; 2042 if (int_cause & INT_EXT) { 2043 int_cause &= ~INT_EXT; 2044 int_cause_ext = rdlp(mp, INT_CAUSE_EXT); 2045 } 2046 2047 if (int_cause) { 2048 wrlp(mp, INT_CAUSE, ~int_cause); 2049 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & 2050 ~(rdlp(mp, TXQ_COMMAND) & 0xff); 2051 mp->work_rx |= (int_cause & INT_RX) >> 2; 2052 } 2053 2054 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; 2055 if (int_cause_ext) { 2056 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); 2057 if (int_cause_ext & INT_EXT_LINK_PHY) 2058 mp->work_link = 1; 2059 mp->work_tx |= int_cause_ext & INT_EXT_TX; 2060 } 2061 2062 return 1; 2063} 2064 2065static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) 2066{ 2067 struct net_device *dev = (struct net_device *)dev_id; 2068 struct mv643xx_eth_private *mp = netdev_priv(dev); 2069 2070 if (unlikely(!mv643xx_eth_collect_events(mp))) 2071 return IRQ_NONE; 2072 2073 wrlp(mp, INT_MASK, 0); 2074 napi_schedule(&mp->napi); 2075 2076 return IRQ_HANDLED; 2077} 2078 2079static void handle_link_event(struct mv643xx_eth_private *mp) 2080{ 2081 struct net_device *dev = mp->dev; 2082 u32 port_status; 2083 int speed; 2084 int duplex; 2085 int fc; 2086 2087 port_status = rdlp(mp, PORT_STATUS); 2088 if (!(port_status & LINK_UP)) { 2089 if (netif_carrier_ok(dev)) { 2090 int i; 2091 2092 netdev_info(dev, "link down\n"); 2093 2094 netif_carrier_off(dev); 2095 2096 for (i = 0; i < mp->txq_count; i++) { 2097 struct tx_queue *txq = mp->txq + i; 2098 2099 txq_reclaim(txq, txq->tx_ring_size, 1); 2100 txq_reset_hw_ptr(txq); 2101 } 2102 } 2103 return; 2104 } 2105 2106 switch (port_status & PORT_SPEED_MASK) { 2107 case PORT_SPEED_10: 2108 speed = 10; 2109 break; 2110 case PORT_SPEED_100: 2111 speed = 100; 2112 break; 2113 case PORT_SPEED_1000: 2114 speed = 1000; 2115 break; 2116 default: 2117 speed = -1; 2118 break; 2119 } 2120 duplex = (port_status & FULL_DUPLEX) ? 1 : 0; 2121 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; 2122 2123 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n", 2124 speed, duplex ? "full" : "half", fc ? "en" : "dis"); 2125 2126 if (!netif_carrier_ok(dev)) 2127 netif_carrier_on(dev); 2128} 2129 2130static int mv643xx_eth_poll(struct napi_struct *napi, int budget) 2131{ 2132 struct mv643xx_eth_private *mp; 2133 int work_done; 2134 2135 mp = container_of(napi, struct mv643xx_eth_private, napi); 2136 2137 if (unlikely(mp->oom)) { 2138 mp->oom = 0; 2139 del_timer(&mp->rx_oom); 2140 } 2141 2142 work_done = 0; 2143 while (work_done < budget) { 2144 u8 queue_mask; 2145 int queue; 2146 int work_tbd; 2147 2148 if (mp->work_link) { 2149 mp->work_link = 0; 2150 handle_link_event(mp); 2151 work_done++; 2152 continue; 2153 } 2154 2155 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; 2156 if (likely(!mp->oom)) 2157 queue_mask |= mp->work_rx_refill; 2158 2159 if (!queue_mask) { 2160 if (mv643xx_eth_collect_events(mp)) 2161 continue; 2162 break; 2163 } 2164 2165 queue = fls(queue_mask) - 1; 2166 queue_mask = 1 << queue; 2167 2168 work_tbd = budget - work_done; 2169 if (work_tbd > 16) 2170 work_tbd = 16; 2171 2172 if (mp->work_tx_end & queue_mask) { 2173 txq_kick(mp->txq + queue); 2174 } else if (mp->work_tx & queue_mask) { 2175 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); 2176 txq_maybe_wake(mp->txq + queue); 2177 } else if (mp->work_rx & queue_mask) { 2178 work_done += rxq_process(mp->rxq + queue, work_tbd); 2179 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { 2180 work_done += rxq_refill(mp->rxq + queue, work_tbd); 2181 } else { 2182 BUG(); 2183 } 2184 } 2185 2186 if (work_done < budget) { 2187 if (mp->oom) 2188 mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); 2189 napi_complete(napi); 2190 wrlp(mp, INT_MASK, mp->int_mask); 2191 } 2192 2193 return work_done; 2194} 2195 2196static inline void oom_timer_wrapper(unsigned long data) 2197{ 2198 struct mv643xx_eth_private *mp = (void *)data; 2199 2200 napi_schedule(&mp->napi); 2201} 2202 2203static void phy_reset(struct mv643xx_eth_private *mp) 2204{ 2205 int data; 2206 2207 data = phy_read(mp->phy, MII_BMCR); 2208 if (data < 0) 2209 return; 2210 2211 data |= BMCR_RESET; 2212 if (phy_write(mp->phy, MII_BMCR, data) < 0) 2213 return; 2214 2215 do { 2216 data = phy_read(mp->phy, MII_BMCR); 2217 } while (data >= 0 && data & BMCR_RESET); 2218} 2219 2220static void port_start(struct mv643xx_eth_private *mp) 2221{ 2222 u32 pscr; 2223 int i; 2224 2225 /* 2226 * Perform PHY reset, if there is a PHY. 2227 */ 2228 if (mp->phy != NULL) { 2229 struct ethtool_cmd cmd; 2230 2231 mv643xx_eth_get_settings(mp->dev, &cmd); 2232 phy_reset(mp); 2233 mv643xx_eth_set_settings(mp->dev, &cmd); 2234 } 2235 2236 /* 2237 * Configure basic link parameters. 2238 */ 2239 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 2240 2241 pscr |= SERIAL_PORT_ENABLE; 2242 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2243 2244 pscr |= DO_NOT_FORCE_LINK_FAIL; 2245 if (mp->phy == NULL) 2246 pscr |= FORCE_LINK_PASS; 2247 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2248 2249 /* 2250 * Configure TX path and queues. 2251 */ 2252 tx_set_rate(mp, 1000000000, 16777216); 2253 for (i = 0; i < mp->txq_count; i++) { 2254 struct tx_queue *txq = mp->txq + i; 2255 2256 txq_reset_hw_ptr(txq); 2257 txq_set_rate(txq, 1000000000, 16777216); 2258 txq_set_fixed_prio_mode(txq); 2259 } 2260 2261 /* 2262 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast 2263 * frames to RX queue #0, and include the pseudo-header when 2264 * calculating receive checksums. 2265 */ 2266 mv643xx_eth_set_features(mp->dev, mp->dev->features); 2267 2268 /* 2269 * Treat BPDUs as normal multicasts, and disable partition mode. 2270 */ 2271 wrlp(mp, PORT_CONFIG_EXT, 0x00000000); 2272 2273 /* 2274 * Add configured unicast addresses to address filter table. 2275 */ 2276 mv643xx_eth_program_unicast_filter(mp->dev); 2277 2278 /* 2279 * Enable the receive queues. 2280 */ 2281 for (i = 0; i < mp->rxq_count; i++) { 2282 struct rx_queue *rxq = mp->rxq + i; 2283 u32 addr; 2284 2285 addr = (u32)rxq->rx_desc_dma; 2286 addr += rxq->rx_curr_desc * sizeof(struct rx_desc); 2287 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); 2288 2289 rxq_enable(rxq); 2290 } 2291} 2292 2293static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) 2294{ 2295 int skb_size; 2296 2297 /* 2298 * Reserve 2+14 bytes for an ethernet header (the hardware 2299 * automatically prepends 2 bytes of dummy data to each 2300 * received packet), 16 bytes for up to four VLAN tags, and 2301 * 4 bytes for the trailing FCS -- 36 bytes total. 2302 */ 2303 skb_size = mp->dev->mtu + 36; 2304 2305 /* 2306 * Make sure that the skb size is a multiple of 8 bytes, as 2307 * the lower three bits of the receive descriptor's buffer 2308 * size field are ignored by the hardware. 2309 */ 2310 mp->skb_size = (skb_size + 7) & ~7; 2311 2312 /* 2313 * If NET_SKB_PAD is smaller than a cache line, 2314 * netdev_alloc_skb() will cause skb->data to be misaligned 2315 * to a cache line boundary. If this is the case, include 2316 * some extra space to allow re-aligning the data area. 2317 */ 2318 mp->skb_size += SKB_DMA_REALIGN; 2319} 2320 2321static int mv643xx_eth_open(struct net_device *dev) 2322{ 2323 struct mv643xx_eth_private *mp = netdev_priv(dev); 2324 int err; 2325 int i; 2326 2327 wrlp(mp, INT_CAUSE, 0); 2328 wrlp(mp, INT_CAUSE_EXT, 0); 2329 rdlp(mp, INT_CAUSE_EXT); 2330 2331 err = request_irq(dev->irq, mv643xx_eth_irq, 2332 IRQF_SHARED, dev->name, dev); 2333 if (err) { 2334 netdev_err(dev, "can't assign irq\n"); 2335 return -EAGAIN; 2336 } 2337 2338 mv643xx_eth_recalc_skb_size(mp); 2339 2340 napi_enable(&mp->napi); 2341 2342 skb_queue_head_init(&mp->rx_recycle); 2343 2344 mp->int_mask = INT_EXT; 2345 2346 for (i = 0; i < mp->rxq_count; i++) { 2347 err = rxq_init(mp, i); 2348 if (err) { 2349 while (--i >= 0) 2350 rxq_deinit(mp->rxq + i); 2351 goto out; 2352 } 2353 2354 rxq_refill(mp->rxq + i, INT_MAX); 2355 mp->int_mask |= INT_RX_0 << i; 2356 } 2357 2358 if (mp->oom) { 2359 mp->rx_oom.expires = jiffies + (HZ / 10); 2360 add_timer(&mp->rx_oom); 2361 } 2362 2363 for (i = 0; i < mp->txq_count; i++) { 2364 err = txq_init(mp, i); 2365 if (err) { 2366 while (--i >= 0) 2367 txq_deinit(mp->txq + i); 2368 goto out_free; 2369 } 2370 mp->int_mask |= INT_TX_END_0 << i; 2371 } 2372 2373 port_start(mp); 2374 2375 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); 2376 wrlp(mp, INT_MASK, mp->int_mask); 2377 2378 return 0; 2379 2380 2381out_free: 2382 for (i = 0; i < mp->rxq_count; i++) 2383 rxq_deinit(mp->rxq + i); 2384out: 2385 free_irq(dev->irq, dev); 2386 2387 return err; 2388} 2389 2390static void port_reset(struct mv643xx_eth_private *mp) 2391{ 2392 unsigned int data; 2393 int i; 2394 2395 for (i = 0; i < mp->rxq_count; i++) 2396 rxq_disable(mp->rxq + i); 2397 for (i = 0; i < mp->txq_count; i++) 2398 txq_disable(mp->txq + i); 2399 2400 while (1) { 2401 u32 ps = rdlp(mp, PORT_STATUS); 2402 2403 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) 2404 break; 2405 udelay(10); 2406 } 2407 2408 /* Reset the Enable bit in the Configuration Register */ 2409 data = rdlp(mp, PORT_SERIAL_CONTROL); 2410 data &= ~(SERIAL_PORT_ENABLE | 2411 DO_NOT_FORCE_LINK_FAIL | 2412 FORCE_LINK_PASS); 2413 wrlp(mp, PORT_SERIAL_CONTROL, data); 2414} 2415 2416static int mv643xx_eth_stop(struct net_device *dev) 2417{ 2418 struct mv643xx_eth_private *mp = netdev_priv(dev); 2419 int i; 2420 2421 wrlp(mp, INT_MASK_EXT, 0x00000000); 2422 wrlp(mp, INT_MASK, 0x00000000); 2423 rdlp(mp, INT_MASK); 2424 2425 napi_disable(&mp->napi); 2426 2427 del_timer_sync(&mp->rx_oom); 2428 2429 netif_carrier_off(dev); 2430 2431 free_irq(dev->irq, dev); 2432 2433 port_reset(mp); 2434 mv643xx_eth_get_stats(dev); 2435 mib_counters_update(mp); 2436 del_timer_sync(&mp->mib_counters_timer); 2437 2438 skb_queue_purge(&mp->rx_recycle); 2439 2440 for (i = 0; i < mp->rxq_count; i++) 2441 rxq_deinit(mp->rxq + i); 2442 for (i = 0; i < mp->txq_count; i++) 2443 txq_deinit(mp->txq + i); 2444 2445 return 0; 2446} 2447 2448static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2449{ 2450 struct mv643xx_eth_private *mp = netdev_priv(dev); 2451 2452 if (mp->phy != NULL) 2453 return phy_mii_ioctl(mp->phy, ifr, cmd); 2454 2455 return -EOPNOTSUPP; 2456} 2457 2458static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) 2459{ 2460 struct mv643xx_eth_private *mp = netdev_priv(dev); 2461 2462 if (new_mtu < 64 || new_mtu > 9500) 2463 return -EINVAL; 2464 2465 dev->mtu = new_mtu; 2466 mv643xx_eth_recalc_skb_size(mp); 2467 tx_set_rate(mp, 1000000000, 16777216); 2468 2469 if (!netif_running(dev)) 2470 return 0; 2471 2472 /* 2473 * Stop and then re-open the interface. This will allocate RX 2474 * skbs of the new MTU. 2475 * There is a possible danger that the open will not succeed, 2476 * due to memory being full. 2477 */ 2478 mv643xx_eth_stop(dev); 2479 if (mv643xx_eth_open(dev)) { 2480 netdev_err(dev, 2481 "fatal error on re-opening device after MTU change\n"); 2482 } 2483 2484 return 0; 2485} 2486 2487static void tx_timeout_task(struct work_struct *ugly) 2488{ 2489 struct mv643xx_eth_private *mp; 2490 2491 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); 2492 if (netif_running(mp->dev)) { 2493 netif_tx_stop_all_queues(mp->dev); 2494 port_reset(mp); 2495 port_start(mp); 2496 netif_tx_wake_all_queues(mp->dev); 2497 } 2498} 2499 2500static void mv643xx_eth_tx_timeout(struct net_device *dev) 2501{ 2502 struct mv643xx_eth_private *mp = netdev_priv(dev); 2503 2504 netdev_info(dev, "tx timeout\n"); 2505 2506 schedule_work(&mp->tx_timeout_task); 2507} 2508 2509#ifdef CONFIG_NET_POLL_CONTROLLER 2510static void mv643xx_eth_netpoll(struct net_device *dev) 2511{ 2512 struct mv643xx_eth_private *mp = netdev_priv(dev); 2513 2514 wrlp(mp, INT_MASK, 0x00000000); 2515 rdlp(mp, INT_MASK); 2516 2517 mv643xx_eth_irq(dev->irq, dev); 2518 2519 wrlp(mp, INT_MASK, mp->int_mask); 2520} 2521#endif 2522 2523 2524/* platform glue ************************************************************/ 2525static void 2526mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, 2527 const struct mbus_dram_target_info *dram) 2528{ 2529 void __iomem *base = msp->base; 2530 u32 win_enable; 2531 u32 win_protect; 2532 int i; 2533 2534 for (i = 0; i < 6; i++) { 2535 writel(0, base + WINDOW_BASE(i)); 2536 writel(0, base + WINDOW_SIZE(i)); 2537 if (i < 4) 2538 writel(0, base + WINDOW_REMAP_HIGH(i)); 2539 } 2540 2541 win_enable = 0x3f; 2542 win_protect = 0; 2543 2544 for (i = 0; i < dram->num_cs; i++) { 2545 const struct mbus_dram_window *cs = dram->cs + i; 2546 2547 writel((cs->base & 0xffff0000) | 2548 (cs->mbus_attr << 8) | 2549 dram->mbus_dram_target_id, base + WINDOW_BASE(i)); 2550 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); 2551 2552 win_enable &= ~(1 << i); 2553 win_protect |= 3 << (2 * i); 2554 } 2555 2556 writel(win_enable, base + WINDOW_BAR_ENABLE); 2557 msp->win_protect = win_protect; 2558} 2559 2560static void infer_hw_params(struct mv643xx_eth_shared_private *msp) 2561{ 2562 /* 2563 * Check whether we have a 14-bit coal limit field in bits 2564 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the 2565 * SDMA config register. 2566 */ 2567 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); 2568 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) 2569 msp->extended_rx_coal_limit = 1; 2570 else 2571 msp->extended_rx_coal_limit = 0; 2572 2573 /* 2574 * Check whether the MAC supports TX rate control, and if 2575 * yes, whether its associated registers are in the old or 2576 * the new place. 2577 */ 2578 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); 2579 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { 2580 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; 2581 } else { 2582 writel(7, msp->base + 0x0400 + TX_BW_RATE); 2583 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) 2584 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; 2585 else 2586 msp->tx_bw_control = TX_BW_CONTROL_ABSENT; 2587 } 2588} 2589 2590static int mv643xx_eth_shared_probe(struct platform_device *pdev) 2591{ 2592 static int mv643xx_eth_version_printed; 2593 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; 2594 struct mv643xx_eth_shared_private *msp; 2595 const struct mbus_dram_target_info *dram; 2596 struct resource *res; 2597 int ret; 2598 2599 if (!mv643xx_eth_version_printed++) 2600 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n", 2601 mv643xx_eth_driver_version); 2602 2603 ret = -EINVAL; 2604 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2605 if (res == NULL) 2606 goto out; 2607 2608 ret = -ENOMEM; 2609 msp = kzalloc(sizeof(*msp), GFP_KERNEL); 2610 if (msp == NULL) 2611 goto out; 2612 2613 msp->base = ioremap(res->start, resource_size(res)); 2614 if (msp->base == NULL) 2615 goto out_free; 2616 2617 /* 2618 * Set up and register SMI bus. 2619 */ 2620 if (pd == NULL || pd->shared_smi == NULL) { 2621 msp->smi_bus = mdiobus_alloc(); 2622 if (msp->smi_bus == NULL) 2623 goto out_unmap; 2624 2625 msp->smi_bus->priv = msp; 2626 msp->smi_bus->name = "mv643xx_eth smi"; 2627 msp->smi_bus->read = smi_bus_read; 2628 msp->smi_bus->write = smi_bus_write, 2629 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d", 2630 pdev->name, pdev->id); 2631 msp->smi_bus->parent = &pdev->dev; 2632 msp->smi_bus->phy_mask = 0xffffffff; 2633 if (mdiobus_register(msp->smi_bus) < 0) 2634 goto out_free_mii_bus; 2635 msp->smi = msp; 2636 } else { 2637 msp->smi = platform_get_drvdata(pd->shared_smi); 2638 } 2639 2640 msp->err_interrupt = NO_IRQ; 2641 init_waitqueue_head(&msp->smi_busy_wait); 2642 2643 /* 2644 * Check whether the error interrupt is hooked up. 2645 */ 2646 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 2647 if (res != NULL) { 2648 int err; 2649 2650 err = request_irq(res->start, mv643xx_eth_err_irq, 2651 IRQF_SHARED, "mv643xx_eth", msp); 2652 if (!err) { 2653 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK); 2654 msp->err_interrupt = res->start; 2655 } 2656 } 2657 2658 /* 2659 * (Re-)program MBUS remapping windows if we are asked to. 2660 */ 2661 dram = mv_mbus_dram_info(); 2662 if (dram) 2663 mv643xx_eth_conf_mbus_windows(msp, dram); 2664 2665 /* 2666 * Detect hardware parameters. 2667 */ 2668 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; 2669 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ? 2670 pd->tx_csum_limit : 9 * 1024; 2671 infer_hw_params(msp); 2672 2673 platform_set_drvdata(pdev, msp); 2674 2675 return 0; 2676 2677out_free_mii_bus: 2678 mdiobus_free(msp->smi_bus); 2679out_unmap: 2680 iounmap(msp->base); 2681out_free: 2682 kfree(msp); 2683out: 2684 return ret; 2685} 2686 2687static int mv643xx_eth_shared_remove(struct platform_device *pdev) 2688{ 2689 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); 2690 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; 2691 2692 if (pd == NULL || pd->shared_smi == NULL) { 2693 mdiobus_unregister(msp->smi_bus); 2694 mdiobus_free(msp->smi_bus); 2695 } 2696 if (msp->err_interrupt != NO_IRQ) 2697 free_irq(msp->err_interrupt, msp); 2698 iounmap(msp->base); 2699 kfree(msp); 2700 2701 return 0; 2702} 2703 2704static struct platform_driver mv643xx_eth_shared_driver = { 2705 .probe = mv643xx_eth_shared_probe, 2706 .remove = mv643xx_eth_shared_remove, 2707 .driver = { 2708 .name = MV643XX_ETH_SHARED_NAME, 2709 .owner = THIS_MODULE, 2710 }, 2711}; 2712 2713static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) 2714{ 2715 int addr_shift = 5 * mp->port_num; 2716 u32 data; 2717 2718 data = rdl(mp, PHY_ADDR); 2719 data &= ~(0x1f << addr_shift); 2720 data |= (phy_addr & 0x1f) << addr_shift; 2721 wrl(mp, PHY_ADDR, data); 2722} 2723 2724static int phy_addr_get(struct mv643xx_eth_private *mp) 2725{ 2726 unsigned int data; 2727 2728 data = rdl(mp, PHY_ADDR); 2729 2730 return (data >> (5 * mp->port_num)) & 0x1f; 2731} 2732 2733static void set_params(struct mv643xx_eth_private *mp, 2734 struct mv643xx_eth_platform_data *pd) 2735{ 2736 struct net_device *dev = mp->dev; 2737 2738 if (is_valid_ether_addr(pd->mac_addr)) 2739 memcpy(dev->dev_addr, pd->mac_addr, 6); 2740 else 2741 uc_addr_get(mp, dev->dev_addr); 2742 2743 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; 2744 if (pd->rx_queue_size) 2745 mp->rx_ring_size = pd->rx_queue_size; 2746 mp->rx_desc_sram_addr = pd->rx_sram_addr; 2747 mp->rx_desc_sram_size = pd->rx_sram_size; 2748 2749 mp->rxq_count = pd->rx_queue_count ? : 1; 2750 2751 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE; 2752 if (pd->tx_queue_size) 2753 mp->tx_ring_size = pd->tx_queue_size; 2754 mp->tx_desc_sram_addr = pd->tx_sram_addr; 2755 mp->tx_desc_sram_size = pd->tx_sram_size; 2756 2757 mp->txq_count = pd->tx_queue_count ? : 1; 2758} 2759 2760static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, 2761 int phy_addr) 2762{ 2763 struct mii_bus *bus = mp->shared->smi->smi_bus; 2764 struct phy_device *phydev; 2765 int start; 2766 int num; 2767 int i; 2768 2769 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { 2770 start = phy_addr_get(mp) & 0x1f; 2771 num = 32; 2772 } else { 2773 start = phy_addr & 0x1f; 2774 num = 1; 2775 } 2776 2777 phydev = NULL; 2778 for (i = 0; i < num; i++) { 2779 int addr = (start + i) & 0x1f; 2780 2781 if (bus->phy_map[addr] == NULL) 2782 mdiobus_scan(bus, addr); 2783 2784 if (phydev == NULL) { 2785 phydev = bus->phy_map[addr]; 2786 if (phydev != NULL) 2787 phy_addr_set(mp, addr); 2788 } 2789 } 2790 2791 return phydev; 2792} 2793 2794static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) 2795{ 2796 struct phy_device *phy = mp->phy; 2797 2798 phy_reset(mp); 2799 2800 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII); 2801 2802 if (speed == 0) { 2803 phy->autoneg = AUTONEG_ENABLE; 2804 phy->speed = 0; 2805 phy->duplex = 0; 2806 phy->advertising = phy->supported | ADVERTISED_Autoneg; 2807 } else { 2808 phy->autoneg = AUTONEG_DISABLE; 2809 phy->advertising = 0; 2810 phy->speed = speed; 2811 phy->duplex = duplex; 2812 } 2813 phy_start_aneg(phy); 2814} 2815 2816static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) 2817{ 2818 u32 pscr; 2819 2820 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 2821 if (pscr & SERIAL_PORT_ENABLE) { 2822 pscr &= ~SERIAL_PORT_ENABLE; 2823 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2824 } 2825 2826 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; 2827 if (mp->phy == NULL) { 2828 pscr |= DISABLE_AUTO_NEG_SPEED_GMII; 2829 if (speed == SPEED_1000) 2830 pscr |= SET_GMII_SPEED_TO_1000; 2831 else if (speed == SPEED_100) 2832 pscr |= SET_MII_SPEED_TO_100; 2833 2834 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; 2835 2836 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; 2837 if (duplex == DUPLEX_FULL) 2838 pscr |= SET_FULL_DUPLEX_MODE; 2839 } 2840 2841 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2842} 2843 2844static const struct net_device_ops mv643xx_eth_netdev_ops = { 2845 .ndo_open = mv643xx_eth_open, 2846 .ndo_stop = mv643xx_eth_stop, 2847 .ndo_start_xmit = mv643xx_eth_xmit, 2848 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode, 2849 .ndo_set_mac_address = mv643xx_eth_set_mac_address, 2850 .ndo_validate_addr = eth_validate_addr, 2851 .ndo_do_ioctl = mv643xx_eth_ioctl, 2852 .ndo_change_mtu = mv643xx_eth_change_mtu, 2853 .ndo_set_features = mv643xx_eth_set_features, 2854 .ndo_tx_timeout = mv643xx_eth_tx_timeout, 2855 .ndo_get_stats = mv643xx_eth_get_stats, 2856#ifdef CONFIG_NET_POLL_CONTROLLER 2857 .ndo_poll_controller = mv643xx_eth_netpoll, 2858#endif 2859}; 2860 2861static int mv643xx_eth_probe(struct platform_device *pdev) 2862{ 2863 struct mv643xx_eth_platform_data *pd; 2864 struct mv643xx_eth_private *mp; 2865 struct net_device *dev; 2866 struct resource *res; 2867 int err; 2868 2869 pd = pdev->dev.platform_data; 2870 if (pd == NULL) { 2871 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n"); 2872 return -ENODEV; 2873 } 2874 2875 if (pd->shared == NULL) { 2876 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n"); 2877 return -ENODEV; 2878 } 2879 2880 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); 2881 if (!dev) 2882 return -ENOMEM; 2883 2884 mp = netdev_priv(dev); 2885 platform_set_drvdata(pdev, mp); 2886 2887 mp->shared = platform_get_drvdata(pd->shared); 2888 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); 2889 mp->port_num = pd->port_number; 2890 2891 mp->dev = dev; 2892 2893 set_params(mp, pd); 2894 netif_set_real_num_tx_queues(dev, mp->txq_count); 2895 netif_set_real_num_rx_queues(dev, mp->rxq_count); 2896 2897 if (pd->phy_addr != MV643XX_ETH_PHY_NONE) 2898 mp->phy = phy_scan(mp, pd->phy_addr); 2899 2900 if (mp->phy != NULL) 2901 phy_init(mp, pd->speed, pd->duplex); 2902 2903 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); 2904 2905 init_pscr(mp, pd->speed, pd->duplex); 2906 2907 2908 mib_counters_clear(mp); 2909 2910 init_timer(&mp->mib_counters_timer); 2911 mp->mib_counters_timer.data = (unsigned long)mp; 2912 mp->mib_counters_timer.function = mib_counters_timer_wrapper; 2913 mp->mib_counters_timer.expires = jiffies + 30 * HZ; 2914 add_timer(&mp->mib_counters_timer); 2915 2916 spin_lock_init(&mp->mib_counters_lock); 2917 2918 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); 2919 2920 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128); 2921 2922 init_timer(&mp->rx_oom); 2923 mp->rx_oom.data = (unsigned long)mp; 2924 mp->rx_oom.function = oom_timer_wrapper; 2925 2926 2927 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 2928 BUG_ON(!res); 2929 dev->irq = res->start; 2930 2931 dev->netdev_ops = &mv643xx_eth_netdev_ops; 2932 2933 dev->watchdog_timeo = 2 * HZ; 2934 dev->base_addr = 0; 2935 2936 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | 2937 NETIF_F_RXCSUM | NETIF_F_LRO; 2938 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; 2939 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM; 2940 2941 dev->priv_flags |= IFF_UNICAST_FLT; 2942 2943 SET_NETDEV_DEV(dev, &pdev->dev); 2944 2945 if (mp->shared->win_protect) 2946 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); 2947 2948 netif_carrier_off(dev); 2949 2950 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); 2951 2952 set_rx_coal(mp, 250); 2953 set_tx_coal(mp, 0); 2954 2955 err = register_netdev(dev); 2956 if (err) 2957 goto out; 2958 2959 netdev_notice(dev, "port %d with MAC address %pM\n", 2960 mp->port_num, dev->dev_addr); 2961 2962 if (mp->tx_desc_sram_size > 0) 2963 netdev_notice(dev, "configured with sram\n"); 2964 2965 return 0; 2966 2967out: 2968 free_netdev(dev); 2969 2970 return err; 2971} 2972 2973static int mv643xx_eth_remove(struct platform_device *pdev) 2974{ 2975 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 2976 2977 unregister_netdev(mp->dev); 2978 if (mp->phy != NULL) 2979 phy_detach(mp->phy); 2980 cancel_work_sync(&mp->tx_timeout_task); 2981 free_netdev(mp->dev); 2982 2983 platform_set_drvdata(pdev, NULL); 2984 2985 return 0; 2986} 2987 2988static void mv643xx_eth_shutdown(struct platform_device *pdev) 2989{ 2990 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 2991 2992 /* Mask all interrupts on ethernet port */ 2993 wrlp(mp, INT_MASK, 0); 2994 rdlp(mp, INT_MASK); 2995 2996 if (netif_running(mp->dev)) 2997 port_reset(mp); 2998} 2999 3000static struct platform_driver mv643xx_eth_driver = { 3001 .probe = mv643xx_eth_probe, 3002 .remove = mv643xx_eth_remove, 3003 .shutdown = mv643xx_eth_shutdown, 3004 .driver = { 3005 .name = MV643XX_ETH_NAME, 3006 .owner = THIS_MODULE, 3007 }, 3008}; 3009 3010static int __init mv643xx_eth_init_module(void) 3011{ 3012 int rc; 3013 3014 rc = platform_driver_register(&mv643xx_eth_shared_driver); 3015 if (!rc) { 3016 rc = platform_driver_register(&mv643xx_eth_driver); 3017 if (rc) 3018 platform_driver_unregister(&mv643xx_eth_shared_driver); 3019 } 3020 3021 return rc; 3022} 3023module_init(mv643xx_eth_init_module); 3024 3025static void __exit mv643xx_eth_cleanup_module(void) 3026{ 3027 platform_driver_unregister(&mv643xx_eth_driver); 3028 platform_driver_unregister(&mv643xx_eth_shared_driver); 3029} 3030module_exit(mv643xx_eth_cleanup_module); 3031 3032MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " 3033 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); 3034MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); 3035MODULE_LICENSE("GPL"); 3036MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); 3037MODULE_ALIAS("platform:" MV643XX_ETH_NAME); 3038