1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
19 */
20#include "pch_gbe.h"
21#include "pch_gbe_phy.h"
22
23/* bus type values */
24#define pch_gbe_bus_type_unknown	0
25#define pch_gbe_bus_type_pci		1
26#define pch_gbe_bus_type_pcix		2
27#define pch_gbe_bus_type_pci_express	3
28#define pch_gbe_bus_type_reserved	4
29
30/* bus speed values */
31#define pch_gbe_bus_speed_unknown	0
32#define pch_gbe_bus_speed_33		1
33#define pch_gbe_bus_speed_66		2
34#define pch_gbe_bus_speed_100		3
35#define pch_gbe_bus_speed_120		4
36#define pch_gbe_bus_speed_133		5
37#define pch_gbe_bus_speed_2500		6
38#define pch_gbe_bus_speed_reserved	7
39
40/* bus width values */
41#define pch_gbe_bus_width_unknown	0
42#define pch_gbe_bus_width_pcie_x1	1
43#define pch_gbe_bus_width_pcie_x2	2
44#define pch_gbe_bus_width_pcie_x4	4
45#define pch_gbe_bus_width_32		5
46#define pch_gbe_bus_width_64		6
47#define pch_gbe_bus_width_reserved	7
48
49/**
50 * pch_gbe_plat_get_bus_info - Obtain bus information for adapter
51 * @hw:	Pointer to the HW structure
52 */
53static void pch_gbe_plat_get_bus_info(struct pch_gbe_hw *hw)
54{
55	hw->bus.type  = pch_gbe_bus_type_pci_express;
56	hw->bus.speed = pch_gbe_bus_speed_2500;
57	hw->bus.width = pch_gbe_bus_width_pcie_x1;
58}
59
60/**
61 * pch_gbe_plat_init_hw - Initialize hardware
62 * @hw:	Pointer to the HW structure
63 * Returns
64 *	0:		Successfully
65 *	Negative value:	Failed-EBUSY
66 */
67static s32 pch_gbe_plat_init_hw(struct pch_gbe_hw *hw)
68{
69	s32 ret_val;
70
71	ret_val = pch_gbe_phy_get_id(hw);
72	if (ret_val) {
73		pr_err("pch_gbe_phy_get_id error\n");
74		return ret_val;
75	}
76	pch_gbe_phy_init_setting(hw);
77	/* Setup Mac interface option RGMII */
78#ifdef PCH_GBE_MAC_IFOP_RGMII
79	pch_gbe_phy_set_rgmii(hw);
80#endif
81	return ret_val;
82}
83
84static const struct pch_gbe_functions pch_gbe_ops = {
85	.get_bus_info      = pch_gbe_plat_get_bus_info,
86	.init_hw           = pch_gbe_plat_init_hw,
87	.read_phy_reg      = pch_gbe_phy_read_reg_miic,
88	.write_phy_reg     = pch_gbe_phy_write_reg_miic,
89	.reset_phy         = pch_gbe_phy_hw_reset,
90	.sw_reset_phy      = pch_gbe_phy_sw_reset,
91	.power_up_phy      = pch_gbe_phy_power_up,
92	.power_down_phy    = pch_gbe_phy_power_down,
93	.read_mac_addr     = pch_gbe_mac_read_mac_addr
94};
95
96/**
97 * pch_gbe_plat_init_function_pointers - Init func ptrs
98 * @hw:	Pointer to the HW structure
99 */
100static void pch_gbe_plat_init_function_pointers(struct pch_gbe_hw *hw)
101{
102	/* Set PHY parameter */
103	hw->phy.reset_delay_us     = PCH_GBE_PHY_RESET_DELAY_US;
104	/* Set function pointers */
105	hw->func = &pch_gbe_ops;
106}
107
108/**
109 * pch_gbe_hal_setup_init_funcs - Initializes function pointers
110 * @hw:	Pointer to the HW structure
111 * Returns
112 *	0:	Successfully
113 *	ENOSYS:	Function is not registered
114 */
115inline s32 pch_gbe_hal_setup_init_funcs(struct pch_gbe_hw *hw)
116{
117	if (!hw->reg) {
118		pr_err("ERROR: Registers not mapped\n");
119		return -ENOSYS;
120	}
121	pch_gbe_plat_init_function_pointers(hw);
122	return 0;
123}
124
125/**
126 * pch_gbe_hal_get_bus_info - Obtain bus information for adapter
127 * @hw:	Pointer to the HW structure
128 */
129inline void pch_gbe_hal_get_bus_info(struct pch_gbe_hw *hw)
130{
131	if (!hw->func->get_bus_info)
132		pr_err("ERROR: configuration\n");
133	else
134		hw->func->get_bus_info(hw);
135}
136
137/**
138 * pch_gbe_hal_init_hw - Initialize hardware
139 * @hw:	Pointer to the HW structure
140 * Returns
141 *	0:	Successfully
142 *	ENOSYS:	Function is not registered
143 */
144inline s32 pch_gbe_hal_init_hw(struct pch_gbe_hw *hw)
145{
146	if (!hw->func->init_hw) {
147		pr_err("ERROR: configuration\n");
148		return -ENOSYS;
149	}
150	return hw->func->init_hw(hw);
151}
152
153/**
154 * pch_gbe_hal_read_phy_reg - Reads PHY register
155 * @hw:	    Pointer to the HW structure
156 * @offset: The register to read
157 * @data:   The buffer to store the 16-bit read.
158 * Returns
159 *	0:	Successfully
160 *	Negative value:	Failed
161 */
162inline s32 pch_gbe_hal_read_phy_reg(struct pch_gbe_hw *hw, u32 offset,
163					u16 *data)
164{
165	if (!hw->func->read_phy_reg)
166		return 0;
167	return hw->func->read_phy_reg(hw, offset, data);
168}
169
170/**
171 * pch_gbe_hal_write_phy_reg - Writes PHY register
172 * @hw:	    Pointer to the HW structure
173 * @offset: The register to read
174 * @data:   The value to write.
175 * Returns
176 *	0:	Successfully
177 *	Negative value:	Failed
178 */
179inline s32 pch_gbe_hal_write_phy_reg(struct pch_gbe_hw *hw, u32 offset,
180					u16 data)
181{
182	if (!hw->func->write_phy_reg)
183		return 0;
184	return hw->func->write_phy_reg(hw, offset, data);
185}
186
187/**
188 * pch_gbe_hal_phy_hw_reset - Hard PHY reset
189 * @hw:	    Pointer to the HW structure
190 */
191inline void pch_gbe_hal_phy_hw_reset(struct pch_gbe_hw *hw)
192{
193	if (!hw->func->reset_phy)
194		pr_err("ERROR: configuration\n");
195	else
196		hw->func->reset_phy(hw);
197}
198
199/**
200 * pch_gbe_hal_phy_sw_reset - Soft PHY reset
201 * @hw:	    Pointer to the HW structure
202 */
203inline void pch_gbe_hal_phy_sw_reset(struct pch_gbe_hw *hw)
204{
205	if (!hw->func->sw_reset_phy)
206		pr_err("ERROR: configuration\n");
207	else
208		hw->func->sw_reset_phy(hw);
209}
210
211/**
212 * pch_gbe_hal_read_mac_addr - Reads MAC address
213 * @hw:	Pointer to the HW structure
214 * Returns
215 *	0:	Successfully
216 *	ENOSYS:	Function is not registered
217 */
218inline s32 pch_gbe_hal_read_mac_addr(struct pch_gbe_hw *hw)
219{
220	if (!hw->func->read_mac_addr) {
221		pr_err("ERROR: configuration\n");
222		return -ENOSYS;
223	}
224	return hw->func->read_mac_addr(hw);
225}
226
227/**
228 * pch_gbe_hal_power_up_phy - Power up PHY
229 * @hw:	Pointer to the HW structure
230 */
231inline void pch_gbe_hal_power_up_phy(struct pch_gbe_hw *hw)
232{
233	if (hw->func->power_up_phy)
234		hw->func->power_up_phy(hw);
235}
236
237/**
238 * pch_gbe_hal_power_down_phy - Power down PHY
239 * @hw:	Pointer to the HW structure
240 */
241inline void pch_gbe_hal_power_down_phy(struct pch_gbe_hw *hw)
242{
243	if (hw->func->power_down_phy)
244		hw->func->power_down_phy(hw);
245}
246