1/* 2 3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux. 4 5 Maintained by Jeff Garzik <jgarzik@pobox.com> 6 Copyright 2000-2002 Jeff Garzik 7 8 Much code comes from Donald Becker's rtl8139.c driver, 9 versions 1.13 and older. This driver was originally based 10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13: 11 12 -----<snip>----- 13 14 Written 1997-2001 by Donald Becker. 15 This software may be used and distributed according to the 16 terms of the GNU General Public License (GPL), incorporated 17 herein by reference. Drivers based on or derived from this 18 code fall under the GPL and must retain the authorship, 19 copyright and license notice. This file is not a complete 20 program and may only be used when the entire operating 21 system is licensed under the GPL. 22 23 This driver is for boards based on the RTL8129 and RTL8139 24 PCI ethernet chips. 25 26 The author may be reached as becker@scyld.com, or C/O Scyld 27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis 28 MD 21403 29 30 Support and updates available at 31 http://www.scyld.com/network/rtl8139.html 32 33 Twister-tuning table provided by Kinston 34 <shangh@realtek.com.tw>. 35 36 -----<snip>----- 37 38 This software may be used and distributed according to the terms 39 of the GNU General Public License, incorporated herein by reference. 40 41 Contributors: 42 43 Donald Becker - he wrote the original driver, kudos to him! 44 (but please don't e-mail him for support, this isn't his driver) 45 46 Tigran Aivazian - bug fixes, skbuff free cleanup 47 48 Martin Mares - suggestions for PCI cleanup 49 50 David S. Miller - PCI DMA and softnet updates 51 52 Ernst Gill - fixes ported from BSD driver 53 54 Daniel Kobras - identified specific locations of 55 posted MMIO write bugginess 56 57 Gerard Sharp - bug fix, testing and feedback 58 59 David Ford - Rx ring wrap fix 60 61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me 62 to find and fix a crucial bug on older chipsets. 63 64 Donald Becker/Chris Butterworth/Marcus Westergren - 65 Noticed various Rx packet size-related buglets. 66 67 Santiago Garcia Mantinan - testing and feedback 68 69 Jens David - 2.2.x kernel backports 70 71 Martin Dennett - incredibly helpful insight on undocumented 72 features of the 8139 chips 73 74 Jean-Jacques Michel - bug fix 75 76 Tobias Ringström - Rx interrupt status checking suggestion 77 78 Andrew Morton - Clear blocked signals, avoid 79 buffer overrun setting current->comm. 80 81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls 82 83 Robert Kuebel - Save kernel thread from dying on any signal. 84 85 Submitting bug reports: 86 87 "rtl8139-diag -mmmaaavvveefN" output 88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log 89 90*/ 91 92#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 93 94#define DRV_NAME "8139too" 95#define DRV_VERSION "0.9.28" 96 97 98#include <linux/module.h> 99#include <linux/kernel.h> 100#include <linux/compiler.h> 101#include <linux/pci.h> 102#include <linux/init.h> 103#include <linux/interrupt.h> 104#include <linux/netdevice.h> 105#include <linux/etherdevice.h> 106#include <linux/rtnetlink.h> 107#include <linux/delay.h> 108#include <linux/ethtool.h> 109#include <linux/mii.h> 110#include <linux/completion.h> 111#include <linux/crc32.h> 112#include <linux/io.h> 113#include <linux/uaccess.h> 114#include <linux/gfp.h> 115#include <asm/irq.h> 116 117#define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION 118 119/* Default Message level */ 120#define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ 121 NETIF_MSG_PROBE | \ 122 NETIF_MSG_LINK) 123 124 125/* define to 1, 2 or 3 to enable copious debugging info */ 126#define RTL8139_DEBUG 0 127 128/* define to 1 to disable lightweight runtime debugging checks */ 129#undef RTL8139_NDEBUG 130 131 132#ifdef RTL8139_NDEBUG 133# define assert(expr) do {} while (0) 134#else 135# define assert(expr) \ 136 if (unlikely(!(expr))) { \ 137 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \ 138 #expr, __FILE__, __func__, __LINE__); \ 139 } 140#endif 141 142 143/* A few user-configurable values. */ 144/* media options */ 145#define MAX_UNITS 8 146static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 147static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 148 149/* Whether to use MMIO or PIO. Default to MMIO. */ 150#ifdef CONFIG_8139TOO_PIO 151static int use_io = 1; 152#else 153static int use_io = 0; 154#endif 155 156/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 157 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 158static int multicast_filter_limit = 32; 159 160/* bitmapped message enable number */ 161static int debug = -1; 162 163/* 164 * Receive ring size 165 * Warning: 64K ring has hardware issues and may lock up. 166 */ 167#if defined(CONFIG_SH_DREAMCAST) 168#define RX_BUF_IDX 0 /* 8K ring */ 169#else 170#define RX_BUF_IDX 2 /* 32K ring */ 171#endif 172#define RX_BUF_LEN (8192 << RX_BUF_IDX) 173#define RX_BUF_PAD 16 174#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */ 175 176#if RX_BUF_LEN == 65536 177#define RX_BUF_TOT_LEN RX_BUF_LEN 178#else 179#define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD) 180#endif 181 182/* Number of Tx descriptor registers. */ 183#define NUM_TX_DESC 4 184 185/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/ 186#define MAX_ETH_FRAME_SIZE 1536 187 188/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */ 189#define TX_BUF_SIZE MAX_ETH_FRAME_SIZE 190#define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC) 191 192/* PCI Tuning Parameters 193 Threshold is bytes transferred to chip before transmission starts. */ 194#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 195 196/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ 197#define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */ 198#define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */ 199#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 200#define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */ 201 202/* Operational parameters that usually are not changed. */ 203/* Time in jiffies before concluding the transmitter is hung. */ 204#define TX_TIMEOUT (6*HZ) 205 206 207enum { 208 HAS_MII_XCVR = 0x010000, 209 HAS_CHIP_XCVR = 0x020000, 210 HAS_LNK_CHNG = 0x040000, 211}; 212 213#define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */ 214#define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */ 215#define RTL_MIN_IO_SIZE 0x80 216#define RTL8139B_IO_SIZE 256 217 218#define RTL8129_CAPS HAS_MII_XCVR 219#define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG) 220 221typedef enum { 222 RTL8139 = 0, 223 RTL8129, 224} board_t; 225 226 227/* indexed by board_t, above */ 228static const struct { 229 const char *name; 230 u32 hw_flags; 231} board_info[] __devinitdata = { 232 { "RealTek RTL8139", RTL8139_CAPS }, 233 { "RealTek RTL8129", RTL8129_CAPS }, 234}; 235 236 237static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = { 238 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 239 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 240 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 241 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 242 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 243 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 244 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 245 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 246 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 247 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 248 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 249 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 250 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 251 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 252 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 253 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 254 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 255 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 256 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 257 258#ifdef CONFIG_SH_SECUREEDGE5410 259 /* Bogus 8139 silicon reports 8129 without external PROM :-( */ 260 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 261#endif 262#ifdef CONFIG_8139TOO_8129 263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 }, 264#endif 265 266 /* some crazy cards report invalid vendor ids like 267 * 0x0001 here. The other ids are valid and constant, 268 * so we simply don't match on the main vendor id. 269 */ 270 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 }, 271 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 }, 272 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 }, 273 274 {0,} 275}; 276MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl); 277 278static struct { 279 const char str[ETH_GSTRING_LEN]; 280} ethtool_stats_keys[] = { 281 { "early_rx" }, 282 { "tx_buf_mapped" }, 283 { "tx_timeouts" }, 284 { "rx_lost_in_ring" }, 285}; 286 287/* The rest of these values should never change. */ 288 289/* Symbolic offsets to registers. */ 290enum RTL8139_registers { 291 MAC0 = 0, /* Ethernet hardware address. */ 292 MAR0 = 8, /* Multicast filter. */ 293 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */ 294 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 295 RxBuf = 0x30, 296 ChipCmd = 0x37, 297 RxBufPtr = 0x38, 298 RxBufAddr = 0x3A, 299 IntrMask = 0x3C, 300 IntrStatus = 0x3E, 301 TxConfig = 0x40, 302 RxConfig = 0x44, 303 Timer = 0x48, /* A general-purpose counter. */ 304 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 305 Cfg9346 = 0x50, 306 Config0 = 0x51, 307 Config1 = 0x52, 308 TimerInt = 0x54, 309 MediaStatus = 0x58, 310 Config3 = 0x59, 311 Config4 = 0x5A, /* absent on RTL-8139A */ 312 HltClk = 0x5B, 313 MultiIntr = 0x5C, 314 TxSummary = 0x60, 315 BasicModeCtrl = 0x62, 316 BasicModeStatus = 0x64, 317 NWayAdvert = 0x66, 318 NWayLPAR = 0x68, 319 NWayExpansion = 0x6A, 320 /* Undocumented registers, but required for proper operation. */ 321 FIFOTMS = 0x70, /* FIFO Control and test. */ 322 CSCR = 0x74, /* Chip Status and Configuration Register. */ 323 PARA78 = 0x78, 324 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */ 325 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 326 Config5 = 0xD8, /* absent on RTL-8139A */ 327}; 328 329enum ClearBitMasks { 330 MultiIntrClear = 0xF000, 331 ChipCmdClear = 0xE2, 332 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 333}; 334 335enum ChipCmdBits { 336 CmdReset = 0x10, 337 CmdRxEnb = 0x08, 338 CmdTxEnb = 0x04, 339 RxBufEmpty = 0x01, 340}; 341 342/* Interrupt register bits, using my own meaningful names. */ 343enum IntrStatusBits { 344 PCIErr = 0x8000, 345 PCSTimeout = 0x4000, 346 RxFIFOOver = 0x40, 347 RxUnderrun = 0x20, 348 RxOverflow = 0x10, 349 TxErr = 0x08, 350 TxOK = 0x04, 351 RxErr = 0x02, 352 RxOK = 0x01, 353 354 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 355}; 356 357enum TxStatusBits { 358 TxHostOwns = 0x2000, 359 TxUnderrun = 0x4000, 360 TxStatOK = 0x8000, 361 TxOutOfWindow = 0x20000000, 362 TxAborted = 0x40000000, 363 TxCarrierLost = 0x80000000, 364}; 365enum RxStatusBits { 366 RxMulticast = 0x8000, 367 RxPhysical = 0x4000, 368 RxBroadcast = 0x2000, 369 RxBadSymbol = 0x0020, 370 RxRunt = 0x0010, 371 RxTooLong = 0x0008, 372 RxCRCErr = 0x0004, 373 RxBadAlign = 0x0002, 374 RxStatusOK = 0x0001, 375}; 376 377/* Bits in RxConfig. */ 378enum rx_mode_bits { 379 AcceptErr = 0x20, 380 AcceptRunt = 0x10, 381 AcceptBroadcast = 0x08, 382 AcceptMulticast = 0x04, 383 AcceptMyPhys = 0x02, 384 AcceptAllPhys = 0x01, 385}; 386 387/* Bits in TxConfig. */ 388enum tx_config_bits { 389 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 390 TxIFGShift = 24, 391 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 392 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 393 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 394 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 395 396 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 397 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */ 398 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 399 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */ 400 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */ 401 402 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 403}; 404 405/* Bits in Config1 */ 406enum Config1Bits { 407 Cfg1_PM_Enable = 0x01, 408 Cfg1_VPD_Enable = 0x02, 409 Cfg1_PIO = 0x04, 410 Cfg1_MMIO = 0x08, 411 LWAKE = 0x10, /* not on 8139, 8139A */ 412 Cfg1_Driver_Load = 0x20, 413 Cfg1_LED0 = 0x40, 414 Cfg1_LED1 = 0x80, 415 SLEEP = (1 << 1), /* only on 8139, 8139A */ 416 PWRDN = (1 << 0), /* only on 8139, 8139A */ 417}; 418 419/* Bits in Config3 */ 420enum Config3Bits { 421 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 422 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 423 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 424 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 425 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 426 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 427 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 428 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 429}; 430 431/* Bits in Config4 */ 432enum Config4Bits { 433 LWPTN = (1 << 2), /* not on 8139, 8139A */ 434}; 435 436/* Bits in Config5 */ 437enum Config5Bits { 438 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 439 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 440 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 441 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */ 442 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 443 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 444 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 445}; 446 447enum RxConfigBits { 448 /* rx fifo threshold */ 449 RxCfgFIFOShift = 13, 450 RxCfgFIFONone = (7 << RxCfgFIFOShift), 451 452 /* Max DMA burst */ 453 RxCfgDMAShift = 8, 454 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 455 456 /* rx ring buffer length */ 457 RxCfgRcv8K = 0, 458 RxCfgRcv16K = (1 << 11), 459 RxCfgRcv32K = (1 << 12), 460 RxCfgRcv64K = (1 << 11) | (1 << 12), 461 462 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 463 RxNoWrap = (1 << 7), 464}; 465 466/* Twister tuning parameters from RealTek. 467 Completely undocumented, but required to tune bad links on some boards. */ 468enum CSCRBits { 469 CSCR_LinkOKBit = 0x0400, 470 CSCR_LinkChangeBit = 0x0800, 471 CSCR_LinkStatusBits = 0x0f000, 472 CSCR_LinkDownOffCmd = 0x003c0, 473 CSCR_LinkDownCmd = 0x0f3c0, 474}; 475 476enum Cfg9346Bits { 477 Cfg9346_Lock = 0x00, 478 Cfg9346_Unlock = 0xC0, 479}; 480 481typedef enum { 482 CH_8139 = 0, 483 CH_8139_K, 484 CH_8139A, 485 CH_8139A_G, 486 CH_8139B, 487 CH_8130, 488 CH_8139C, 489 CH_8100, 490 CH_8100B_8139D, 491 CH_8101, 492} chip_t; 493 494enum chip_flags { 495 HasHltClk = (1 << 0), 496 HasLWake = (1 << 1), 497}; 498 499#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 500 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 501#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 502 503/* directly indexed by chip_t, above */ 504static const struct { 505 const char *name; 506 u32 version; /* from RTL8139C/RTL8139D docs */ 507 u32 flags; 508} rtl_chip_info[] = { 509 { "RTL-8139", 510 HW_REVID(1, 0, 0, 0, 0, 0, 0), 511 HasHltClk, 512 }, 513 514 { "RTL-8139 rev K", 515 HW_REVID(1, 1, 0, 0, 0, 0, 0), 516 HasHltClk, 517 }, 518 519 { "RTL-8139A", 520 HW_REVID(1, 1, 1, 0, 0, 0, 0), 521 HasHltClk, /* XXX undocumented? */ 522 }, 523 524 { "RTL-8139A rev G", 525 HW_REVID(1, 1, 1, 0, 0, 1, 0), 526 HasHltClk, /* XXX undocumented? */ 527 }, 528 529 { "RTL-8139B", 530 HW_REVID(1, 1, 1, 1, 0, 0, 0), 531 HasLWake, 532 }, 533 534 { "RTL-8130", 535 HW_REVID(1, 1, 1, 1, 1, 0, 0), 536 HasLWake, 537 }, 538 539 { "RTL-8139C", 540 HW_REVID(1, 1, 1, 0, 1, 0, 0), 541 HasLWake, 542 }, 543 544 { "RTL-8100", 545 HW_REVID(1, 1, 1, 1, 0, 1, 0), 546 HasLWake, 547 }, 548 549 { "RTL-8100B/8139D", 550 HW_REVID(1, 1, 1, 0, 1, 0, 1), 551 HasHltClk /* XXX undocumented? */ 552 | HasLWake, 553 }, 554 555 { "RTL-8101", 556 HW_REVID(1, 1, 1, 0, 1, 1, 1), 557 HasLWake, 558 }, 559}; 560 561struct rtl_extra_stats { 562 unsigned long early_rx; 563 unsigned long tx_buf_mapped; 564 unsigned long tx_timeouts; 565 unsigned long rx_lost_in_ring; 566}; 567 568struct rtl8139_stats { 569 u64 packets; 570 u64 bytes; 571 struct u64_stats_sync syncp; 572}; 573 574struct rtl8139_private { 575 void __iomem *mmio_addr; 576 int drv_flags; 577 struct pci_dev *pci_dev; 578 u32 msg_enable; 579 struct napi_struct napi; 580 struct net_device *dev; 581 582 unsigned char *rx_ring; 583 unsigned int cur_rx; /* RX buf index of next pkt */ 584 struct rtl8139_stats rx_stats; 585 dma_addr_t rx_ring_dma; 586 587 unsigned int tx_flag; 588 unsigned long cur_tx; 589 unsigned long dirty_tx; 590 struct rtl8139_stats tx_stats; 591 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */ 592 unsigned char *tx_bufs; /* Tx bounce buffer region. */ 593 dma_addr_t tx_bufs_dma; 594 595 signed char phys[4]; /* MII device addresses. */ 596 597 /* Twister tune state. */ 598 char twistie, twist_row, twist_col; 599 600 unsigned int watchdog_fired : 1; 601 unsigned int default_port : 4; /* Last dev->if_port value. */ 602 unsigned int have_thread : 1; 603 604 spinlock_t lock; 605 spinlock_t rx_lock; 606 607 chip_t chipset; 608 u32 rx_config; 609 struct rtl_extra_stats xstats; 610 611 struct delayed_work thread; 612 613 struct mii_if_info mii; 614 unsigned int regs_len; 615 unsigned long fifo_copy_timeout; 616}; 617 618MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>"); 619MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver"); 620MODULE_LICENSE("GPL"); 621MODULE_VERSION(DRV_VERSION); 622 623module_param(use_io, int, 0); 624MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO"); 625module_param(multicast_filter_limit, int, 0); 626module_param_array(media, int, NULL, 0); 627module_param_array(full_duplex, int, NULL, 0); 628module_param(debug, int, 0); 629MODULE_PARM_DESC (debug, "8139too bitmapped message enable number"); 630MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses"); 631MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps"); 632MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)"); 633 634static int read_eeprom (void __iomem *ioaddr, int location, int addr_len); 635static int rtl8139_open (struct net_device *dev); 636static int mdio_read (struct net_device *dev, int phy_id, int location); 637static void mdio_write (struct net_device *dev, int phy_id, int location, 638 int val); 639static void rtl8139_start_thread(struct rtl8139_private *tp); 640static void rtl8139_tx_timeout (struct net_device *dev); 641static void rtl8139_init_ring (struct net_device *dev); 642static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 643 struct net_device *dev); 644#ifdef CONFIG_NET_POLL_CONTROLLER 645static void rtl8139_poll_controller(struct net_device *dev); 646#endif 647static int rtl8139_set_mac_address(struct net_device *dev, void *p); 648static int rtl8139_poll(struct napi_struct *napi, int budget); 649static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance); 650static int rtl8139_close (struct net_device *dev); 651static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); 652static struct rtnl_link_stats64 *rtl8139_get_stats64(struct net_device *dev, 653 struct rtnl_link_stats64 654 *stats); 655static void rtl8139_set_rx_mode (struct net_device *dev); 656static void __set_rx_mode (struct net_device *dev); 657static void rtl8139_hw_start (struct net_device *dev); 658static void rtl8139_thread (struct work_struct *work); 659static void rtl8139_tx_timeout_task(struct work_struct *work); 660static const struct ethtool_ops rtl8139_ethtool_ops; 661 662/* write MMIO register, with flush */ 663/* Flush avoids rtl8139 bug w/ posted MMIO writes */ 664#define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0) 665#define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0) 666#define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0) 667 668/* write MMIO register */ 669#define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg)) 670#define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg)) 671#define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg)) 672 673/* read MMIO register */ 674#define RTL_R8(reg) ioread8 (ioaddr + (reg)) 675#define RTL_R16(reg) ioread16 (ioaddr + (reg)) 676#define RTL_R32(reg) ioread32 (ioaddr + (reg)) 677 678 679static const u16 rtl8139_intr_mask = 680 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | 681 TxErr | TxOK | RxErr | RxOK; 682 683static const u16 rtl8139_norx_intr_mask = 684 PCIErr | PCSTimeout | RxUnderrun | 685 TxErr | TxOK | RxErr ; 686 687#if RX_BUF_IDX == 0 688static const unsigned int rtl8139_rx_config = 689 RxCfgRcv8K | RxNoWrap | 690 (RX_FIFO_THRESH << RxCfgFIFOShift) | 691 (RX_DMA_BURST << RxCfgDMAShift); 692#elif RX_BUF_IDX == 1 693static const unsigned int rtl8139_rx_config = 694 RxCfgRcv16K | RxNoWrap | 695 (RX_FIFO_THRESH << RxCfgFIFOShift) | 696 (RX_DMA_BURST << RxCfgDMAShift); 697#elif RX_BUF_IDX == 2 698static const unsigned int rtl8139_rx_config = 699 RxCfgRcv32K | RxNoWrap | 700 (RX_FIFO_THRESH << RxCfgFIFOShift) | 701 (RX_DMA_BURST << RxCfgDMAShift); 702#elif RX_BUF_IDX == 3 703static const unsigned int rtl8139_rx_config = 704 RxCfgRcv64K | 705 (RX_FIFO_THRESH << RxCfgFIFOShift) | 706 (RX_DMA_BURST << RxCfgDMAShift); 707#else 708#error "Invalid configuration for 8139_RXBUF_IDX" 709#endif 710 711static const unsigned int rtl8139_tx_config = 712 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift); 713 714static void __rtl8139_cleanup_dev (struct net_device *dev) 715{ 716 struct rtl8139_private *tp = netdev_priv(dev); 717 struct pci_dev *pdev; 718 719 assert (dev != NULL); 720 assert (tp->pci_dev != NULL); 721 pdev = tp->pci_dev; 722 723 if (tp->mmio_addr) 724 pci_iounmap (pdev, tp->mmio_addr); 725 726 /* it's ok to call this even if we have no regions to free */ 727 pci_release_regions (pdev); 728 729 free_netdev(dev); 730 pci_set_drvdata (pdev, NULL); 731} 732 733 734static void rtl8139_chip_reset (void __iomem *ioaddr) 735{ 736 int i; 737 738 /* Soft reset the chip. */ 739 RTL_W8 (ChipCmd, CmdReset); 740 741 /* Check that the chip has finished the reset. */ 742 for (i = 1000; i > 0; i--) { 743 barrier(); 744 if ((RTL_R8 (ChipCmd) & CmdReset) == 0) 745 break; 746 udelay (10); 747 } 748} 749 750 751static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev) 752{ 753 void __iomem *ioaddr; 754 struct net_device *dev; 755 struct rtl8139_private *tp; 756 u8 tmp8; 757 int rc, disable_dev_on_err = 0; 758 unsigned int i; 759 unsigned long pio_start, pio_end, pio_flags, pio_len; 760 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len; 761 u32 version; 762 763 assert (pdev != NULL); 764 765 /* dev and priv zeroed in alloc_etherdev */ 766 dev = alloc_etherdev (sizeof (*tp)); 767 if (dev == NULL) 768 return ERR_PTR(-ENOMEM); 769 770 SET_NETDEV_DEV(dev, &pdev->dev); 771 772 tp = netdev_priv(dev); 773 tp->pci_dev = pdev; 774 775 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 776 rc = pci_enable_device (pdev); 777 if (rc) 778 goto err_out; 779 780 pio_start = pci_resource_start (pdev, 0); 781 pio_end = pci_resource_end (pdev, 0); 782 pio_flags = pci_resource_flags (pdev, 0); 783 pio_len = pci_resource_len (pdev, 0); 784 785 mmio_start = pci_resource_start (pdev, 1); 786 mmio_end = pci_resource_end (pdev, 1); 787 mmio_flags = pci_resource_flags (pdev, 1); 788 mmio_len = pci_resource_len (pdev, 1); 789 790 /* set this immediately, we need to know before 791 * we talk to the chip directly */ 792 pr_debug("PIO region size == 0x%02lX\n", pio_len); 793 pr_debug("MMIO region size == 0x%02lX\n", mmio_len); 794 795retry: 796 if (use_io) { 797 /* make sure PCI base addr 0 is PIO */ 798 if (!(pio_flags & IORESOURCE_IO)) { 799 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n"); 800 rc = -ENODEV; 801 goto err_out; 802 } 803 /* check for weird/broken PCI region reporting */ 804 if (pio_len < RTL_MIN_IO_SIZE) { 805 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n"); 806 rc = -ENODEV; 807 goto err_out; 808 } 809 } else { 810 /* make sure PCI base addr 1 is MMIO */ 811 if (!(mmio_flags & IORESOURCE_MEM)) { 812 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n"); 813 rc = -ENODEV; 814 goto err_out; 815 } 816 if (mmio_len < RTL_MIN_IO_SIZE) { 817 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n"); 818 rc = -ENODEV; 819 goto err_out; 820 } 821 } 822 823 rc = pci_request_regions (pdev, DRV_NAME); 824 if (rc) 825 goto err_out; 826 disable_dev_on_err = 1; 827 828 /* enable PCI bus-mastering */ 829 pci_set_master (pdev); 830 831 if (use_io) { 832 ioaddr = pci_iomap(pdev, 0, 0); 833 if (!ioaddr) { 834 dev_err(&pdev->dev, "cannot map PIO, aborting\n"); 835 rc = -EIO; 836 goto err_out; 837 } 838 dev->base_addr = pio_start; 839 tp->regs_len = pio_len; 840 } else { 841 /* ioremap MMIO region */ 842 ioaddr = pci_iomap(pdev, 1, 0); 843 if (ioaddr == NULL) { 844 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n"); 845 pci_release_regions(pdev); 846 use_io = 1; 847 goto retry; 848 } 849 dev->base_addr = (long) ioaddr; 850 tp->regs_len = mmio_len; 851 } 852 tp->mmio_addr = ioaddr; 853 854 /* Bring old chips out of low-power mode. */ 855 RTL_W8 (HltClk, 'R'); 856 857 /* check for missing/broken hardware */ 858 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) { 859 dev_err(&pdev->dev, "Chip not responding, ignoring board\n"); 860 rc = -EIO; 861 goto err_out; 862 } 863 864 /* identify chip attached to board */ 865 version = RTL_R32 (TxConfig) & HW_REVID_MASK; 866 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++) 867 if (version == rtl_chip_info[i].version) { 868 tp->chipset = i; 869 goto match; 870 } 871 872 /* if unknown chip, assume array element #0, original RTL-8139 in this case */ 873 i = 0; 874 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n"); 875 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig)); 876 tp->chipset = 0; 877 878match: 879 pr_debug("chipset id (%d) == index %d, '%s'\n", 880 version, i, rtl_chip_info[i].name); 881 882 if (tp->chipset >= CH_8139B) { 883 u8 new_tmp8 = tmp8 = RTL_R8 (Config1); 884 pr_debug("PCI PM wakeup\n"); 885 if ((rtl_chip_info[tp->chipset].flags & HasLWake) && 886 (tmp8 & LWAKE)) 887 new_tmp8 &= ~LWAKE; 888 new_tmp8 |= Cfg1_PM_Enable; 889 if (new_tmp8 != tmp8) { 890 RTL_W8 (Cfg9346, Cfg9346_Unlock); 891 RTL_W8 (Config1, tmp8); 892 RTL_W8 (Cfg9346, Cfg9346_Lock); 893 } 894 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 895 tmp8 = RTL_R8 (Config4); 896 if (tmp8 & LWPTN) { 897 RTL_W8 (Cfg9346, Cfg9346_Unlock); 898 RTL_W8 (Config4, tmp8 & ~LWPTN); 899 RTL_W8 (Cfg9346, Cfg9346_Lock); 900 } 901 } 902 } else { 903 pr_debug("Old chip wakeup\n"); 904 tmp8 = RTL_R8 (Config1); 905 tmp8 &= ~(SLEEP | PWRDN); 906 RTL_W8 (Config1, tmp8); 907 } 908 909 rtl8139_chip_reset (ioaddr); 910 911 return dev; 912 913err_out: 914 __rtl8139_cleanup_dev (dev); 915 if (disable_dev_on_err) 916 pci_disable_device (pdev); 917 return ERR_PTR(rc); 918} 919 920static int rtl8139_set_features(struct net_device *dev, netdev_features_t features) 921{ 922 struct rtl8139_private *tp = netdev_priv(dev); 923 unsigned long flags; 924 netdev_features_t changed = features ^ dev->features; 925 void __iomem *ioaddr = tp->mmio_addr; 926 927 if (!(changed & (NETIF_F_RXALL))) 928 return 0; 929 930 spin_lock_irqsave(&tp->lock, flags); 931 932 if (changed & NETIF_F_RXALL) { 933 int rx_mode = tp->rx_config; 934 if (features & NETIF_F_RXALL) 935 rx_mode |= (AcceptErr | AcceptRunt); 936 else 937 rx_mode &= ~(AcceptErr | AcceptRunt); 938 tp->rx_config = rtl8139_rx_config | rx_mode; 939 RTL_W32_F(RxConfig, tp->rx_config); 940 } 941 942 spin_unlock_irqrestore(&tp->lock, flags); 943 944 return 0; 945} 946 947static const struct net_device_ops rtl8139_netdev_ops = { 948 .ndo_open = rtl8139_open, 949 .ndo_stop = rtl8139_close, 950 .ndo_get_stats64 = rtl8139_get_stats64, 951 .ndo_change_mtu = eth_change_mtu, 952 .ndo_validate_addr = eth_validate_addr, 953 .ndo_set_mac_address = rtl8139_set_mac_address, 954 .ndo_start_xmit = rtl8139_start_xmit, 955 .ndo_set_rx_mode = rtl8139_set_rx_mode, 956 .ndo_do_ioctl = netdev_ioctl, 957 .ndo_tx_timeout = rtl8139_tx_timeout, 958#ifdef CONFIG_NET_POLL_CONTROLLER 959 .ndo_poll_controller = rtl8139_poll_controller, 960#endif 961 .ndo_set_features = rtl8139_set_features, 962}; 963 964static int __devinit rtl8139_init_one (struct pci_dev *pdev, 965 const struct pci_device_id *ent) 966{ 967 struct net_device *dev = NULL; 968 struct rtl8139_private *tp; 969 int i, addr_len, option; 970 void __iomem *ioaddr; 971 static int board_idx = -1; 972 973 assert (pdev != NULL); 974 assert (ent != NULL); 975 976 board_idx++; 977 978 /* when we're built into the kernel, the driver version message 979 * is only printed if at least one 8139 board has been found 980 */ 981#ifndef MODULE 982 { 983 static int printed_version; 984 if (!printed_version++) 985 pr_info(RTL8139_DRIVER_NAME "\n"); 986 } 987#endif 988 989 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 990 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) { 991 dev_info(&pdev->dev, 992 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n", 993 pdev->vendor, pdev->device, pdev->revision); 994 return -ENODEV; 995 } 996 997 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 998 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && 999 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS && 1000 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) { 1001 pr_info("OQO Model 2 detected. Forcing PIO\n"); 1002 use_io = 1; 1003 } 1004 1005 dev = rtl8139_init_board (pdev); 1006 if (IS_ERR(dev)) 1007 return PTR_ERR(dev); 1008 1009 assert (dev != NULL); 1010 tp = netdev_priv(dev); 1011 tp->dev = dev; 1012 1013 ioaddr = tp->mmio_addr; 1014 assert (ioaddr != NULL); 1015 1016 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6; 1017 for (i = 0; i < 3; i++) 1018 ((__le16 *) (dev->dev_addr))[i] = 1019 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len)); 1020 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 1021 1022 /* The Rtl8139-specific entries in the device structure. */ 1023 dev->netdev_ops = &rtl8139_netdev_ops; 1024 dev->ethtool_ops = &rtl8139_ethtool_ops; 1025 dev->watchdog_timeo = TX_TIMEOUT; 1026 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64); 1027 1028 /* note: the hardware is not capable of sg/csum/highdma, however 1029 * through the use of skb_copy_and_csum_dev we enable these 1030 * features 1031 */ 1032 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA; 1033 dev->vlan_features = dev->features; 1034 1035 dev->hw_features |= NETIF_F_RXALL; 1036 dev->hw_features |= NETIF_F_RXFCS; 1037 1038 dev->irq = pdev->irq; 1039 1040 /* tp zeroed and aligned in alloc_etherdev */ 1041 tp = netdev_priv(dev); 1042 1043 /* note: tp->chipset set in rtl8139_init_board */ 1044 tp->drv_flags = board_info[ent->driver_data].hw_flags; 1045 tp->mmio_addr = ioaddr; 1046 tp->msg_enable = 1047 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1)); 1048 spin_lock_init (&tp->lock); 1049 spin_lock_init (&tp->rx_lock); 1050 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1051 tp->mii.dev = dev; 1052 tp->mii.mdio_read = mdio_read; 1053 tp->mii.mdio_write = mdio_write; 1054 tp->mii.phy_id_mask = 0x3f; 1055 tp->mii.reg_num_mask = 0x1f; 1056 1057 /* dev is fully set up and ready to use now */ 1058 pr_debug("about to register device named %s (%p)...\n", 1059 dev->name, dev); 1060 i = register_netdev (dev); 1061 if (i) goto err_out; 1062 1063 pci_set_drvdata (pdev, dev); 1064 1065 netdev_info(dev, "%s at 0x%lx, %pM, IRQ %d\n", 1066 board_info[ent->driver_data].name, 1067 dev->base_addr, dev->dev_addr, dev->irq); 1068 1069 netdev_dbg(dev, "Identified 8139 chip type '%s'\n", 1070 rtl_chip_info[tp->chipset].name); 1071 1072 /* Find the connected MII xcvrs. 1073 Doing this in open() would allow detecting external xcvrs later, but 1074 takes too much time. */ 1075#ifdef CONFIG_8139TOO_8129 1076 if (tp->drv_flags & HAS_MII_XCVR) { 1077 int phy, phy_idx = 0; 1078 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) { 1079 int mii_status = mdio_read(dev, phy, 1); 1080 if (mii_status != 0xffff && mii_status != 0x0000) { 1081 u16 advertising = mdio_read(dev, phy, 4); 1082 tp->phys[phy_idx++] = phy; 1083 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n", 1084 phy, mii_status, advertising); 1085 } 1086 } 1087 if (phy_idx == 0) { 1088 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n"); 1089 tp->phys[0] = 32; 1090 } 1091 } else 1092#endif 1093 tp->phys[0] = 32; 1094 tp->mii.phy_id = tp->phys[0]; 1095 1096 /* The lower four bits are the media type. */ 1097 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 1098 if (option > 0) { 1099 tp->mii.full_duplex = (option & 0x210) ? 1 : 0; 1100 tp->default_port = option & 0xFF; 1101 if (tp->default_port) 1102 tp->mii.force_media = 1; 1103 } 1104 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0) 1105 tp->mii.full_duplex = full_duplex[board_idx]; 1106 if (tp->mii.full_duplex) { 1107 netdev_info(dev, "Media type forced to Full Duplex\n"); 1108 /* Changing the MII-advertised media because might prevent 1109 re-connection. */ 1110 tp->mii.force_media = 1; 1111 } 1112 if (tp->default_port) { 1113 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n", 1114 (option & 0x20 ? 100 : 10), 1115 (option & 0x10 ? "full" : "half")); 1116 mdio_write(dev, tp->phys[0], 0, 1117 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */ 1118 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */ 1119 } 1120 1121 /* Put the chip into low-power mode. */ 1122 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1123 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 1124 1125 return 0; 1126 1127err_out: 1128 __rtl8139_cleanup_dev (dev); 1129 pci_disable_device (pdev); 1130 return i; 1131} 1132 1133 1134static void __devexit rtl8139_remove_one (struct pci_dev *pdev) 1135{ 1136 struct net_device *dev = pci_get_drvdata (pdev); 1137 struct rtl8139_private *tp = netdev_priv(dev); 1138 1139 assert (dev != NULL); 1140 1141 cancel_delayed_work_sync(&tp->thread); 1142 1143 unregister_netdev (dev); 1144 1145 __rtl8139_cleanup_dev (dev); 1146 pci_disable_device (pdev); 1147} 1148 1149 1150/* Serial EEPROM section. */ 1151 1152/* EEPROM_Ctrl bits. */ 1153#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 1154#define EE_CS 0x08 /* EEPROM chip select. */ 1155#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 1156#define EE_WRITE_0 0x00 1157#define EE_WRITE_1 0x02 1158#define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 1159#define EE_ENB (0x80 | EE_CS) 1160 1161/* Delay between EEPROM clock transitions. 1162 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. 1163 */ 1164 1165#define eeprom_delay() (void)RTL_R8(Cfg9346) 1166 1167/* The EEPROM commands include the alway-set leading bit. */ 1168#define EE_WRITE_CMD (5) 1169#define EE_READ_CMD (6) 1170#define EE_ERASE_CMD (7) 1171 1172static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len) 1173{ 1174 int i; 1175 unsigned retval = 0; 1176 int read_cmd = location | (EE_READ_CMD << addr_len); 1177 1178 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS); 1179 RTL_W8 (Cfg9346, EE_ENB); 1180 eeprom_delay (); 1181 1182 /* Shift the read command bits out. */ 1183 for (i = 4 + addr_len; i >= 0; i--) { 1184 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 1185 RTL_W8 (Cfg9346, EE_ENB | dataval); 1186 eeprom_delay (); 1187 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK); 1188 eeprom_delay (); 1189 } 1190 RTL_W8 (Cfg9346, EE_ENB); 1191 eeprom_delay (); 1192 1193 for (i = 16; i > 0; i--) { 1194 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK); 1195 eeprom_delay (); 1196 retval = 1197 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 : 1198 0); 1199 RTL_W8 (Cfg9346, EE_ENB); 1200 eeprom_delay (); 1201 } 1202 1203 /* Terminate the EEPROM access. */ 1204 RTL_W8 (Cfg9346, ~EE_CS); 1205 eeprom_delay (); 1206 1207 return retval; 1208} 1209 1210/* MII serial management: mostly bogus for now. */ 1211/* Read and write the MII management registers using software-generated 1212 serial MDIO protocol. 1213 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually 1214 met by back-to-back PCI I/O cycles, but we insert a delay to avoid 1215 "overclocking" issues. */ 1216#define MDIO_DIR 0x80 1217#define MDIO_DATA_OUT 0x04 1218#define MDIO_DATA_IN 0x02 1219#define MDIO_CLK 0x01 1220#define MDIO_WRITE0 (MDIO_DIR) 1221#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT) 1222 1223#define mdio_delay() RTL_R8(Config4) 1224 1225 1226static const char mii_2_8139_map[8] = { 1227 BasicModeCtrl, 1228 BasicModeStatus, 1229 0, 1230 0, 1231 NWayAdvert, 1232 NWayLPAR, 1233 NWayExpansion, 1234 0 1235}; 1236 1237 1238#ifdef CONFIG_8139TOO_8129 1239/* Syncronize the MII management interface by shifting 32 one bits out. */ 1240static void mdio_sync (void __iomem *ioaddr) 1241{ 1242 int i; 1243 1244 for (i = 32; i >= 0; i--) { 1245 RTL_W8 (Config4, MDIO_WRITE1); 1246 mdio_delay (); 1247 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK); 1248 mdio_delay (); 1249 } 1250} 1251#endif 1252 1253static int mdio_read (struct net_device *dev, int phy_id, int location) 1254{ 1255 struct rtl8139_private *tp = netdev_priv(dev); 1256 int retval = 0; 1257#ifdef CONFIG_8139TOO_8129 1258 void __iomem *ioaddr = tp->mmio_addr; 1259 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; 1260 int i; 1261#endif 1262 1263 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1264 void __iomem *ioaddr = tp->mmio_addr; 1265 return location < 8 && mii_2_8139_map[location] ? 1266 RTL_R16 (mii_2_8139_map[location]) : 0; 1267 } 1268 1269#ifdef CONFIG_8139TOO_8129 1270 mdio_sync (ioaddr); 1271 /* Shift the read command bits out. */ 1272 for (i = 15; i >= 0; i--) { 1273 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0; 1274 1275 RTL_W8 (Config4, MDIO_DIR | dataval); 1276 mdio_delay (); 1277 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK); 1278 mdio_delay (); 1279 } 1280 1281 /* Read the two transition, 16 data, and wire-idle bits. */ 1282 for (i = 19; i > 0; i--) { 1283 RTL_W8 (Config4, 0); 1284 mdio_delay (); 1285 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0); 1286 RTL_W8 (Config4, MDIO_CLK); 1287 mdio_delay (); 1288 } 1289#endif 1290 1291 return (retval >> 1) & 0xffff; 1292} 1293 1294 1295static void mdio_write (struct net_device *dev, int phy_id, int location, 1296 int value) 1297{ 1298 struct rtl8139_private *tp = netdev_priv(dev); 1299#ifdef CONFIG_8139TOO_8129 1300 void __iomem *ioaddr = tp->mmio_addr; 1301 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value; 1302 int i; 1303#endif 1304 1305 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1306 void __iomem *ioaddr = tp->mmio_addr; 1307 if (location == 0) { 1308 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1309 RTL_W16 (BasicModeCtrl, value); 1310 RTL_W8 (Cfg9346, Cfg9346_Lock); 1311 } else if (location < 8 && mii_2_8139_map[location]) 1312 RTL_W16 (mii_2_8139_map[location], value); 1313 return; 1314 } 1315 1316#ifdef CONFIG_8139TOO_8129 1317 mdio_sync (ioaddr); 1318 1319 /* Shift the command bits out. */ 1320 for (i = 31; i >= 0; i--) { 1321 int dataval = 1322 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; 1323 RTL_W8 (Config4, dataval); 1324 mdio_delay (); 1325 RTL_W8 (Config4, dataval | MDIO_CLK); 1326 mdio_delay (); 1327 } 1328 /* Clear out extra bits. */ 1329 for (i = 2; i > 0; i--) { 1330 RTL_W8 (Config4, 0); 1331 mdio_delay (); 1332 RTL_W8 (Config4, MDIO_CLK); 1333 mdio_delay (); 1334 } 1335#endif 1336} 1337 1338 1339static int rtl8139_open (struct net_device *dev) 1340{ 1341 struct rtl8139_private *tp = netdev_priv(dev); 1342 int retval; 1343 void __iomem *ioaddr = tp->mmio_addr; 1344 1345 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev); 1346 if (retval) 1347 return retval; 1348 1349 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1350 &tp->tx_bufs_dma, GFP_KERNEL); 1351 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1352 &tp->rx_ring_dma, GFP_KERNEL); 1353 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) { 1354 free_irq(dev->irq, dev); 1355 1356 if (tp->tx_bufs) 1357 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1358 tp->tx_bufs, tp->tx_bufs_dma); 1359 if (tp->rx_ring) 1360 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1361 tp->rx_ring, tp->rx_ring_dma); 1362 1363 return -ENOMEM; 1364 1365 } 1366 1367 napi_enable(&tp->napi); 1368 1369 tp->mii.full_duplex = tp->mii.force_media; 1370 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000; 1371 1372 rtl8139_init_ring (dev); 1373 rtl8139_hw_start (dev); 1374 netif_start_queue (dev); 1375 1376 netif_dbg(tp, ifup, dev, 1377 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n", 1378 __func__, 1379 (unsigned long long)pci_resource_start (tp->pci_dev, 1), 1380 dev->irq, RTL_R8 (MediaStatus), 1381 tp->mii.full_duplex ? "full" : "half"); 1382 1383 rtl8139_start_thread(tp); 1384 1385 return 0; 1386} 1387 1388 1389static void rtl_check_media (struct net_device *dev, unsigned int init_media) 1390{ 1391 struct rtl8139_private *tp = netdev_priv(dev); 1392 1393 if (tp->phys[0] >= 0) { 1394 mii_check_media(&tp->mii, netif_msg_link(tp), init_media); 1395 } 1396} 1397 1398/* Start the hardware at open or resume. */ 1399static void rtl8139_hw_start (struct net_device *dev) 1400{ 1401 struct rtl8139_private *tp = netdev_priv(dev); 1402 void __iomem *ioaddr = tp->mmio_addr; 1403 u32 i; 1404 u8 tmp; 1405 1406 /* Bring old chips out of low-power mode. */ 1407 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1408 RTL_W8 (HltClk, 'R'); 1409 1410 rtl8139_chip_reset (ioaddr); 1411 1412 /* unlock Config[01234] and BMCR register writes */ 1413 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1414 /* Restore our idea of the MAC address. */ 1415 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0))); 1416 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4))); 1417 1418 tp->cur_rx = 0; 1419 1420 /* init Rx ring buffer DMA address */ 1421 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1422 1423 /* Must enable Tx/Rx before setting transfer thresholds! */ 1424 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1425 1426 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1427 RTL_W32 (RxConfig, tp->rx_config); 1428 RTL_W32 (TxConfig, rtl8139_tx_config); 1429 1430 rtl_check_media (dev, 1); 1431 1432 if (tp->chipset >= CH_8139B) { 1433 /* Disable magic packet scanning, which is enabled 1434 * when PM is enabled in Config1. It can be reenabled 1435 * via ETHTOOL_SWOL if desired. */ 1436 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic); 1437 } 1438 1439 netdev_dbg(dev, "init buffer addresses\n"); 1440 1441 /* Lock Config[01234] and BMCR register writes */ 1442 RTL_W8 (Cfg9346, Cfg9346_Lock); 1443 1444 /* init Tx buffer DMA addresses */ 1445 for (i = 0; i < NUM_TX_DESC; i++) 1446 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs)); 1447 1448 RTL_W32 (RxMissed, 0); 1449 1450 rtl8139_set_rx_mode (dev); 1451 1452 /* no early-rx interrupts */ 1453 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear); 1454 1455 /* make sure RxTx has started */ 1456 tmp = RTL_R8 (ChipCmd); 1457 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb))) 1458 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1459 1460 /* Enable all known interrupts by setting the interrupt mask. */ 1461 RTL_W16 (IntrMask, rtl8139_intr_mask); 1462} 1463 1464 1465/* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1466static void rtl8139_init_ring (struct net_device *dev) 1467{ 1468 struct rtl8139_private *tp = netdev_priv(dev); 1469 int i; 1470 1471 tp->cur_rx = 0; 1472 tp->cur_tx = 0; 1473 tp->dirty_tx = 0; 1474 1475 for (i = 0; i < NUM_TX_DESC; i++) 1476 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE]; 1477} 1478 1479 1480/* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */ 1481static int next_tick = 3 * HZ; 1482 1483#ifndef CONFIG_8139TOO_TUNE_TWISTER 1484static inline void rtl8139_tune_twister (struct net_device *dev, 1485 struct rtl8139_private *tp) {} 1486#else 1487enum TwisterParamVals { 1488 PARA78_default = 0x78fa8388, 1489 PARA7c_default = 0xcb38de43, /* param[0][3] */ 1490 PARA7c_xxx = 0xcb38de43, 1491}; 1492 1493static const unsigned long param[4][4] = { 1494 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, 1495 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1496 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1497 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} 1498}; 1499 1500static void rtl8139_tune_twister (struct net_device *dev, 1501 struct rtl8139_private *tp) 1502{ 1503 int linkcase; 1504 void __iomem *ioaddr = tp->mmio_addr; 1505 1506 /* This is a complicated state machine to configure the "twister" for 1507 impedance/echos based on the cable length. 1508 All of this is magic and undocumented. 1509 */ 1510 switch (tp->twistie) { 1511 case 1: 1512 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) { 1513 /* We have link beat, let us tune the twister. */ 1514 RTL_W16 (CSCR, CSCR_LinkDownOffCmd); 1515 tp->twistie = 2; /* Change to state 2. */ 1516 next_tick = HZ / 10; 1517 } else { 1518 /* Just put in some reasonable defaults for when beat returns. */ 1519 RTL_W16 (CSCR, CSCR_LinkDownCmd); 1520 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */ 1521 RTL_W32 (PARA78, PARA78_default); 1522 RTL_W32 (PARA7c, PARA7c_default); 1523 tp->twistie = 0; /* Bail from future actions. */ 1524 } 1525 break; 1526 case 2: 1527 /* Read how long it took to hear the echo. */ 1528 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits; 1529 if (linkcase == 0x7000) 1530 tp->twist_row = 3; 1531 else if (linkcase == 0x3000) 1532 tp->twist_row = 2; 1533 else if (linkcase == 0x1000) 1534 tp->twist_row = 1; 1535 else 1536 tp->twist_row = 0; 1537 tp->twist_col = 0; 1538 tp->twistie = 3; /* Change to state 2. */ 1539 next_tick = HZ / 10; 1540 break; 1541 case 3: 1542 /* Put out four tuning parameters, one per 100msec. */ 1543 if (tp->twist_col == 0) 1544 RTL_W16 (FIFOTMS, 0); 1545 RTL_W32 (PARA7c, param[(int) tp->twist_row] 1546 [(int) tp->twist_col]); 1547 next_tick = HZ / 10; 1548 if (++tp->twist_col >= 4) { 1549 /* For short cables we are done. 1550 For long cables (row == 3) check for mistune. */ 1551 tp->twistie = 1552 (tp->twist_row == 3) ? 4 : 0; 1553 } 1554 break; 1555 case 4: 1556 /* Special case for long cables: check for mistune. */ 1557 if ((RTL_R16 (CSCR) & 1558 CSCR_LinkStatusBits) == 0x7000) { 1559 tp->twistie = 0; 1560 break; 1561 } else { 1562 RTL_W32 (PARA7c, 0xfb38de03); 1563 tp->twistie = 5; 1564 next_tick = HZ / 10; 1565 } 1566 break; 1567 case 5: 1568 /* Retune for shorter cable (column 2). */ 1569 RTL_W32 (FIFOTMS, 0x20); 1570 RTL_W32 (PARA78, PARA78_default); 1571 RTL_W32 (PARA7c, PARA7c_default); 1572 RTL_W32 (FIFOTMS, 0x00); 1573 tp->twist_row = 2; 1574 tp->twist_col = 0; 1575 tp->twistie = 3; 1576 next_tick = HZ / 10; 1577 break; 1578 1579 default: 1580 /* do nothing */ 1581 break; 1582 } 1583} 1584#endif /* CONFIG_8139TOO_TUNE_TWISTER */ 1585 1586static inline void rtl8139_thread_iter (struct net_device *dev, 1587 struct rtl8139_private *tp, 1588 void __iomem *ioaddr) 1589{ 1590 int mii_lpa; 1591 1592 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA); 1593 1594 if (!tp->mii.force_media && mii_lpa != 0xffff) { 1595 int duplex = ((mii_lpa & LPA_100FULL) || 1596 (mii_lpa & 0x01C0) == 0x0040); 1597 if (tp->mii.full_duplex != duplex) { 1598 tp->mii.full_duplex = duplex; 1599 1600 if (mii_lpa) { 1601 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n", 1602 tp->mii.full_duplex ? "full" : "half", 1603 tp->phys[0], mii_lpa); 1604 } else { 1605 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n"); 1606 } 1607#if 0 1608 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1609 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20); 1610 RTL_W8 (Cfg9346, Cfg9346_Lock); 1611#endif 1612 } 1613 } 1614 1615 next_tick = HZ * 60; 1616 1617 rtl8139_tune_twister (dev, tp); 1618 1619 netdev_dbg(dev, "Media selection tick, Link partner %04x\n", 1620 RTL_R16(NWayLPAR)); 1621 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n", 1622 RTL_R16(IntrMask), RTL_R16(IntrStatus)); 1623 netdev_dbg(dev, "Chip config %02x %02x\n", 1624 RTL_R8(Config0), RTL_R8(Config1)); 1625} 1626 1627static void rtl8139_thread (struct work_struct *work) 1628{ 1629 struct rtl8139_private *tp = 1630 container_of(work, struct rtl8139_private, thread.work); 1631 struct net_device *dev = tp->mii.dev; 1632 unsigned long thr_delay = next_tick; 1633 1634 rtnl_lock(); 1635 1636 if (!netif_running(dev)) 1637 goto out_unlock; 1638 1639 if (tp->watchdog_fired) { 1640 tp->watchdog_fired = 0; 1641 rtl8139_tx_timeout_task(work); 1642 } else 1643 rtl8139_thread_iter(dev, tp, tp->mmio_addr); 1644 1645 if (tp->have_thread) 1646 schedule_delayed_work(&tp->thread, thr_delay); 1647out_unlock: 1648 rtnl_unlock (); 1649} 1650 1651static void rtl8139_start_thread(struct rtl8139_private *tp) 1652{ 1653 tp->twistie = 0; 1654 if (tp->chipset == CH_8139_K) 1655 tp->twistie = 1; 1656 else if (tp->drv_flags & HAS_LNK_CHNG) 1657 return; 1658 1659 tp->have_thread = 1; 1660 tp->watchdog_fired = 0; 1661 1662 schedule_delayed_work(&tp->thread, next_tick); 1663} 1664 1665static inline void rtl8139_tx_clear (struct rtl8139_private *tp) 1666{ 1667 tp->cur_tx = 0; 1668 tp->dirty_tx = 0; 1669 1670 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */ 1671} 1672 1673static void rtl8139_tx_timeout_task (struct work_struct *work) 1674{ 1675 struct rtl8139_private *tp = 1676 container_of(work, struct rtl8139_private, thread.work); 1677 struct net_device *dev = tp->mii.dev; 1678 void __iomem *ioaddr = tp->mmio_addr; 1679 int i; 1680 u8 tmp8; 1681 1682 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n", 1683 RTL_R8(ChipCmd), RTL_R16(IntrStatus), 1684 RTL_R16(IntrMask), RTL_R8(MediaStatus)); 1685 /* Emit info to figure out what went wrong. */ 1686 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n", 1687 tp->cur_tx, tp->dirty_tx); 1688 for (i = 0; i < NUM_TX_DESC; i++) 1689 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n", 1690 i, RTL_R32(TxStatus0 + (i * 4)), 1691 i == tp->dirty_tx % NUM_TX_DESC ? 1692 " (queue head)" : ""); 1693 1694 tp->xstats.tx_timeouts++; 1695 1696 /* disable Tx ASAP, if not already */ 1697 tmp8 = RTL_R8 (ChipCmd); 1698 if (tmp8 & CmdTxEnb) 1699 RTL_W8 (ChipCmd, CmdRxEnb); 1700 1701 spin_lock_bh(&tp->rx_lock); 1702 /* Disable interrupts by clearing the interrupt mask. */ 1703 RTL_W16 (IntrMask, 0x0000); 1704 1705 /* Stop a shared interrupt from scavenging while we are. */ 1706 spin_lock_irq(&tp->lock); 1707 rtl8139_tx_clear (tp); 1708 spin_unlock_irq(&tp->lock); 1709 1710 /* ...and finally, reset everything */ 1711 if (netif_running(dev)) { 1712 rtl8139_hw_start (dev); 1713 netif_wake_queue (dev); 1714 } 1715 spin_unlock_bh(&tp->rx_lock); 1716} 1717 1718static void rtl8139_tx_timeout (struct net_device *dev) 1719{ 1720 struct rtl8139_private *tp = netdev_priv(dev); 1721 1722 tp->watchdog_fired = 1; 1723 if (!tp->have_thread) { 1724 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1725 schedule_delayed_work(&tp->thread, next_tick); 1726 } 1727} 1728 1729static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 1730 struct net_device *dev) 1731{ 1732 struct rtl8139_private *tp = netdev_priv(dev); 1733 void __iomem *ioaddr = tp->mmio_addr; 1734 unsigned int entry; 1735 unsigned int len = skb->len; 1736 unsigned long flags; 1737 1738 /* Calculate the next Tx descriptor entry. */ 1739 entry = tp->cur_tx % NUM_TX_DESC; 1740 1741 /* Note: the chip doesn't have auto-pad! */ 1742 if (likely(len < TX_BUF_SIZE)) { 1743 if (len < ETH_ZLEN) 1744 memset(tp->tx_buf[entry], 0, ETH_ZLEN); 1745 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]); 1746 dev_kfree_skb(skb); 1747 } else { 1748 dev_kfree_skb(skb); 1749 dev->stats.tx_dropped++; 1750 return NETDEV_TX_OK; 1751 } 1752 1753 spin_lock_irqsave(&tp->lock, flags); 1754 /* 1755 * Writing to TxStatus triggers a DMA transfer of the data 1756 * copied to tp->tx_buf[entry] above. Use a memory barrier 1757 * to make sure that the device sees the updated data. 1758 */ 1759 wmb(); 1760 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)), 1761 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN)); 1762 1763 tp->cur_tx++; 1764 1765 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) 1766 netif_stop_queue (dev); 1767 spin_unlock_irqrestore(&tp->lock, flags); 1768 1769 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n", 1770 len, entry); 1771 1772 return NETDEV_TX_OK; 1773} 1774 1775 1776static void rtl8139_tx_interrupt (struct net_device *dev, 1777 struct rtl8139_private *tp, 1778 void __iomem *ioaddr) 1779{ 1780 unsigned long dirty_tx, tx_left; 1781 1782 assert (dev != NULL); 1783 assert (ioaddr != NULL); 1784 1785 dirty_tx = tp->dirty_tx; 1786 tx_left = tp->cur_tx - dirty_tx; 1787 while (tx_left > 0) { 1788 int entry = dirty_tx % NUM_TX_DESC; 1789 int txstatus; 1790 1791 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32))); 1792 1793 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted))) 1794 break; /* It still hasn't been Txed */ 1795 1796 /* Note: TxCarrierLost is always asserted at 100mbps. */ 1797 if (txstatus & (TxOutOfWindow | TxAborted)) { 1798 /* There was an major error, log it. */ 1799 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n", 1800 txstatus); 1801 dev->stats.tx_errors++; 1802 if (txstatus & TxAborted) { 1803 dev->stats.tx_aborted_errors++; 1804 RTL_W32 (TxConfig, TxClearAbt); 1805 RTL_W16 (IntrStatus, TxErr); 1806 wmb(); 1807 } 1808 if (txstatus & TxCarrierLost) 1809 dev->stats.tx_carrier_errors++; 1810 if (txstatus & TxOutOfWindow) 1811 dev->stats.tx_window_errors++; 1812 } else { 1813 if (txstatus & TxUnderrun) { 1814 /* Add 64 to the Tx FIFO threshold. */ 1815 if (tp->tx_flag < 0x00300000) 1816 tp->tx_flag += 0x00020000; 1817 dev->stats.tx_fifo_errors++; 1818 } 1819 dev->stats.collisions += (txstatus >> 24) & 15; 1820 u64_stats_update_begin(&tp->tx_stats.syncp); 1821 tp->tx_stats.packets++; 1822 tp->tx_stats.bytes += txstatus & 0x7ff; 1823 u64_stats_update_end(&tp->tx_stats.syncp); 1824 } 1825 1826 dirty_tx++; 1827 tx_left--; 1828 } 1829 1830#ifndef RTL8139_NDEBUG 1831 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) { 1832 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n", 1833 dirty_tx, tp->cur_tx); 1834 dirty_tx += NUM_TX_DESC; 1835 } 1836#endif /* RTL8139_NDEBUG */ 1837 1838 /* only wake the queue if we did work, and the queue is stopped */ 1839 if (tp->dirty_tx != dirty_tx) { 1840 tp->dirty_tx = dirty_tx; 1841 mb(); 1842 netif_wake_queue (dev); 1843 } 1844} 1845 1846 1847/* TODO: clean this up! Rx reset need not be this intensive */ 1848static void rtl8139_rx_err (u32 rx_status, struct net_device *dev, 1849 struct rtl8139_private *tp, void __iomem *ioaddr) 1850{ 1851 u8 tmp8; 1852#ifdef CONFIG_8139_OLD_RX_RESET 1853 int tmp_work; 1854#endif 1855 1856 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n", 1857 rx_status); 1858 dev->stats.rx_errors++; 1859 if (!(rx_status & RxStatusOK)) { 1860 if (rx_status & RxTooLong) { 1861 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n", 1862 rx_status); 1863 /* A.C.: The chip hangs here. */ 1864 } 1865 if (rx_status & (RxBadSymbol | RxBadAlign)) 1866 dev->stats.rx_frame_errors++; 1867 if (rx_status & (RxRunt | RxTooLong)) 1868 dev->stats.rx_length_errors++; 1869 if (rx_status & RxCRCErr) 1870 dev->stats.rx_crc_errors++; 1871 } else { 1872 tp->xstats.rx_lost_in_ring++; 1873 } 1874 1875#ifndef CONFIG_8139_OLD_RX_RESET 1876 tmp8 = RTL_R8 (ChipCmd); 1877 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb); 1878 RTL_W8 (ChipCmd, tmp8); 1879 RTL_W32 (RxConfig, tp->rx_config); 1880 tp->cur_rx = 0; 1881#else 1882 /* Reset the receiver, based on RealTek recommendation. (Bug?) */ 1883 1884 /* disable receive */ 1885 RTL_W8_F (ChipCmd, CmdTxEnb); 1886 tmp_work = 200; 1887 while (--tmp_work > 0) { 1888 udelay(1); 1889 tmp8 = RTL_R8 (ChipCmd); 1890 if (!(tmp8 & CmdRxEnb)) 1891 break; 1892 } 1893 if (tmp_work <= 0) 1894 netdev_warn(dev, "rx stop wait too long\n"); 1895 /* restart receive */ 1896 tmp_work = 200; 1897 while (--tmp_work > 0) { 1898 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb); 1899 udelay(1); 1900 tmp8 = RTL_R8 (ChipCmd); 1901 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb)) 1902 break; 1903 } 1904 if (tmp_work <= 0) 1905 netdev_warn(dev, "tx/rx enable wait too long\n"); 1906 1907 /* and reinitialize all rx related registers */ 1908 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1909 /* Must enable Tx/Rx before setting transfer thresholds! */ 1910 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1911 1912 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1913 RTL_W32 (RxConfig, tp->rx_config); 1914 tp->cur_rx = 0; 1915 1916 netdev_dbg(dev, "init buffer addresses\n"); 1917 1918 /* Lock Config[01234] and BMCR register writes */ 1919 RTL_W8 (Cfg9346, Cfg9346_Lock); 1920 1921 /* init Rx ring buffer DMA address */ 1922 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1923 1924 /* A.C.: Reset the multicast list. */ 1925 __set_rx_mode (dev); 1926#endif 1927} 1928 1929#if RX_BUF_IDX == 3 1930static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring, 1931 u32 offset, unsigned int size) 1932{ 1933 u32 left = RX_BUF_LEN - offset; 1934 1935 if (size > left) { 1936 skb_copy_to_linear_data(skb, ring + offset, left); 1937 skb_copy_to_linear_data_offset(skb, left, ring, size - left); 1938 } else 1939 skb_copy_to_linear_data(skb, ring + offset, size); 1940} 1941#endif 1942 1943static void rtl8139_isr_ack(struct rtl8139_private *tp) 1944{ 1945 void __iomem *ioaddr = tp->mmio_addr; 1946 u16 status; 1947 1948 status = RTL_R16 (IntrStatus) & RxAckBits; 1949 1950 /* Clear out errors and receive interrupts */ 1951 if (likely(status != 0)) { 1952 if (unlikely(status & (RxFIFOOver | RxOverflow))) { 1953 tp->dev->stats.rx_errors++; 1954 if (status & RxFIFOOver) 1955 tp->dev->stats.rx_fifo_errors++; 1956 } 1957 RTL_W16_F (IntrStatus, RxAckBits); 1958 } 1959} 1960 1961static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp, 1962 int budget) 1963{ 1964 void __iomem *ioaddr = tp->mmio_addr; 1965 int received = 0; 1966 unsigned char *rx_ring = tp->rx_ring; 1967 unsigned int cur_rx = tp->cur_rx; 1968 unsigned int rx_size = 0; 1969 1970 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 1971 __func__, (u16)cur_rx, 1972 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 1973 1974 while (netif_running(dev) && received < budget && 1975 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) { 1976 u32 ring_offset = cur_rx % RX_BUF_LEN; 1977 u32 rx_status; 1978 unsigned int pkt_size; 1979 struct sk_buff *skb; 1980 1981 rmb(); 1982 1983 /* read size+status of next frame from DMA ring buffer */ 1984 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset)); 1985 rx_size = rx_status >> 16; 1986 if (likely(!(dev->features & NETIF_F_RXFCS))) 1987 pkt_size = rx_size - 4; 1988 else 1989 pkt_size = rx_size; 1990 1991 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n", 1992 __func__, rx_status, rx_size, cur_rx); 1993#if RTL8139_DEBUG > 2 1994 print_hex_dump(KERN_DEBUG, "Frame contents: ", 1995 DUMP_PREFIX_OFFSET, 16, 1, 1996 &rx_ring[ring_offset], 70, true); 1997#endif 1998 1999 /* Packet copy from FIFO still in progress. 2000 * Theoretically, this should never happen 2001 * since EarlyRx is disabled. 2002 */ 2003 if (unlikely(rx_size == 0xfff0)) { 2004 if (!tp->fifo_copy_timeout) 2005 tp->fifo_copy_timeout = jiffies + 2; 2006 else if (time_after(jiffies, tp->fifo_copy_timeout)) { 2007 netdev_dbg(dev, "hung FIFO. Reset\n"); 2008 rx_size = 0; 2009 goto no_early_rx; 2010 } 2011 netif_dbg(tp, intr, dev, "fifo copy in progress\n"); 2012 tp->xstats.early_rx++; 2013 break; 2014 } 2015 2016no_early_rx: 2017 tp->fifo_copy_timeout = 0; 2018 2019 /* If Rx err or invalid rx_size/rx_status received 2020 * (which happens if we get lost in the ring), 2021 * Rx process gets reset, so we abort any further 2022 * Rx processing. 2023 */ 2024 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) || 2025 (rx_size < 8) || 2026 (!(rx_status & RxStatusOK)))) { 2027 if ((dev->features & NETIF_F_RXALL) && 2028 (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) && 2029 (rx_size >= 8) && 2030 (!(rx_status & RxStatusOK))) { 2031 /* Length is at least mostly OK, but pkt has 2032 * error. I'm hoping we can handle some of these 2033 * errors without resetting the chip. --Ben 2034 */ 2035 dev->stats.rx_errors++; 2036 if (rx_status & RxCRCErr) { 2037 dev->stats.rx_crc_errors++; 2038 goto keep_pkt; 2039 } 2040 if (rx_status & RxRunt) { 2041 dev->stats.rx_length_errors++; 2042 goto keep_pkt; 2043 } 2044 } 2045 rtl8139_rx_err (rx_status, dev, tp, ioaddr); 2046 received = -1; 2047 goto out; 2048 } 2049 2050keep_pkt: 2051 /* Malloc up new buffer, compatible with net-2e. */ 2052 /* Omit the four octet CRC from the length. */ 2053 2054 skb = netdev_alloc_skb_ip_align(dev, pkt_size); 2055 if (likely(skb)) { 2056#if RX_BUF_IDX == 3 2057 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size); 2058#else 2059 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size); 2060#endif 2061 skb_put (skb, pkt_size); 2062 2063 skb->protocol = eth_type_trans (skb, dev); 2064 2065 u64_stats_update_begin(&tp->rx_stats.syncp); 2066 tp->rx_stats.packets++; 2067 tp->rx_stats.bytes += pkt_size; 2068 u64_stats_update_end(&tp->rx_stats.syncp); 2069 2070 netif_receive_skb (skb); 2071 } else { 2072 if (net_ratelimit()) 2073 netdev_warn(dev, "Memory squeeze, dropping packet\n"); 2074 dev->stats.rx_dropped++; 2075 } 2076 received++; 2077 2078 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; 2079 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16)); 2080 2081 rtl8139_isr_ack(tp); 2082 } 2083 2084 if (unlikely(!received || rx_size == 0xfff0)) 2085 rtl8139_isr_ack(tp); 2086 2087 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 2088 __func__, cur_rx, 2089 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 2090 2091 tp->cur_rx = cur_rx; 2092 2093 /* 2094 * The receive buffer should be mostly empty. 2095 * Tell NAPI to reenable the Rx irq. 2096 */ 2097 if (tp->fifo_copy_timeout) 2098 received = budget; 2099 2100out: 2101 return received; 2102} 2103 2104 2105static void rtl8139_weird_interrupt (struct net_device *dev, 2106 struct rtl8139_private *tp, 2107 void __iomem *ioaddr, 2108 int status, int link_changed) 2109{ 2110 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status); 2111 2112 assert (dev != NULL); 2113 assert (tp != NULL); 2114 assert (ioaddr != NULL); 2115 2116 /* Update the error count. */ 2117 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2118 RTL_W32 (RxMissed, 0); 2119 2120 if ((status & RxUnderrun) && link_changed && 2121 (tp->drv_flags & HAS_LNK_CHNG)) { 2122 rtl_check_media(dev, 0); 2123 status &= ~RxUnderrun; 2124 } 2125 2126 if (status & (RxUnderrun | RxErr)) 2127 dev->stats.rx_errors++; 2128 2129 if (status & PCSTimeout) 2130 dev->stats.rx_length_errors++; 2131 if (status & RxUnderrun) 2132 dev->stats.rx_fifo_errors++; 2133 if (status & PCIErr) { 2134 u16 pci_cmd_status; 2135 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status); 2136 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status); 2137 2138 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status); 2139 } 2140} 2141 2142static int rtl8139_poll(struct napi_struct *napi, int budget) 2143{ 2144 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi); 2145 struct net_device *dev = tp->dev; 2146 void __iomem *ioaddr = tp->mmio_addr; 2147 int work_done; 2148 2149 spin_lock(&tp->rx_lock); 2150 work_done = 0; 2151 if (likely(RTL_R16(IntrStatus) & RxAckBits)) 2152 work_done += rtl8139_rx(dev, tp, budget); 2153 2154 if (work_done < budget) { 2155 unsigned long flags; 2156 /* 2157 * Order is important since data can get interrupted 2158 * again when we think we are done. 2159 */ 2160 spin_lock_irqsave(&tp->lock, flags); 2161 __napi_complete(napi); 2162 RTL_W16_F(IntrMask, rtl8139_intr_mask); 2163 spin_unlock_irqrestore(&tp->lock, flags); 2164 } 2165 spin_unlock(&tp->rx_lock); 2166 2167 return work_done; 2168} 2169 2170/* The interrupt handler does all of the Rx thread work and cleans up 2171 after the Tx thread. */ 2172static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance) 2173{ 2174 struct net_device *dev = (struct net_device *) dev_instance; 2175 struct rtl8139_private *tp = netdev_priv(dev); 2176 void __iomem *ioaddr = tp->mmio_addr; 2177 u16 status, ackstat; 2178 int link_changed = 0; /* avoid bogus "uninit" warning */ 2179 int handled = 0; 2180 2181 spin_lock (&tp->lock); 2182 status = RTL_R16 (IntrStatus); 2183 2184 /* shared irq? */ 2185 if (unlikely((status & rtl8139_intr_mask) == 0)) 2186 goto out; 2187 2188 handled = 1; 2189 2190 /* h/w no longer present (hotplug?) or major error, bail */ 2191 if (unlikely(status == 0xFFFF)) 2192 goto out; 2193 2194 /* close possible race's with dev_close */ 2195 if (unlikely(!netif_running(dev))) { 2196 RTL_W16 (IntrMask, 0); 2197 goto out; 2198 } 2199 2200 /* Acknowledge all of the current interrupt sources ASAP, but 2201 an first get an additional status bit from CSCR. */ 2202 if (unlikely(status & RxUnderrun)) 2203 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit; 2204 2205 ackstat = status & ~(RxAckBits | TxErr); 2206 if (ackstat) 2207 RTL_W16 (IntrStatus, ackstat); 2208 2209 /* Receive packets are processed by poll routine. 2210 If not running start it now. */ 2211 if (status & RxAckBits){ 2212 if (napi_schedule_prep(&tp->napi)) { 2213 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask); 2214 __napi_schedule(&tp->napi); 2215 } 2216 } 2217 2218 /* Check uncommon events with one test. */ 2219 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr))) 2220 rtl8139_weird_interrupt (dev, tp, ioaddr, 2221 status, link_changed); 2222 2223 if (status & (TxOK | TxErr)) { 2224 rtl8139_tx_interrupt (dev, tp, ioaddr); 2225 if (status & TxErr) 2226 RTL_W16 (IntrStatus, TxErr); 2227 } 2228 out: 2229 spin_unlock (&tp->lock); 2230 2231 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n", 2232 RTL_R16(IntrStatus)); 2233 return IRQ_RETVAL(handled); 2234} 2235 2236#ifdef CONFIG_NET_POLL_CONTROLLER 2237/* 2238 * Polling receive - used by netconsole and other diagnostic tools 2239 * to allow network i/o with interrupts disabled. 2240 */ 2241static void rtl8139_poll_controller(struct net_device *dev) 2242{ 2243 disable_irq(dev->irq); 2244 rtl8139_interrupt(dev->irq, dev); 2245 enable_irq(dev->irq); 2246} 2247#endif 2248 2249static int rtl8139_set_mac_address(struct net_device *dev, void *p) 2250{ 2251 struct rtl8139_private *tp = netdev_priv(dev); 2252 void __iomem *ioaddr = tp->mmio_addr; 2253 struct sockaddr *addr = p; 2254 2255 if (!is_valid_ether_addr(addr->sa_data)) 2256 return -EADDRNOTAVAIL; 2257 2258 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 2259 2260 spin_lock_irq(&tp->lock); 2261 2262 RTL_W8_F(Cfg9346, Cfg9346_Unlock); 2263 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0))); 2264 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4))); 2265 RTL_W8_F(Cfg9346, Cfg9346_Lock); 2266 2267 spin_unlock_irq(&tp->lock); 2268 2269 return 0; 2270} 2271 2272static int rtl8139_close (struct net_device *dev) 2273{ 2274 struct rtl8139_private *tp = netdev_priv(dev); 2275 void __iomem *ioaddr = tp->mmio_addr; 2276 unsigned long flags; 2277 2278 netif_stop_queue(dev); 2279 napi_disable(&tp->napi); 2280 2281 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n", 2282 RTL_R16(IntrStatus)); 2283 2284 spin_lock_irqsave (&tp->lock, flags); 2285 2286 /* Stop the chip's Tx and Rx DMA processes. */ 2287 RTL_W8 (ChipCmd, 0); 2288 2289 /* Disable interrupts by clearing the interrupt mask. */ 2290 RTL_W16 (IntrMask, 0); 2291 2292 /* Update the error counts. */ 2293 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2294 RTL_W32 (RxMissed, 0); 2295 2296 spin_unlock_irqrestore (&tp->lock, flags); 2297 2298 free_irq (dev->irq, dev); 2299 2300 rtl8139_tx_clear (tp); 2301 2302 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 2303 tp->rx_ring, tp->rx_ring_dma); 2304 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 2305 tp->tx_bufs, tp->tx_bufs_dma); 2306 tp->rx_ring = NULL; 2307 tp->tx_bufs = NULL; 2308 2309 /* Green! Put the chip in low-power mode. */ 2310 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2311 2312 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 2313 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 2314 2315 return 0; 2316} 2317 2318 2319/* Get the ethtool Wake-on-LAN settings. Assumes that wol points to 2320 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and 2321 other threads or interrupts aren't messing with the 8139. */ 2322static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2323{ 2324 struct rtl8139_private *tp = netdev_priv(dev); 2325 void __iomem *ioaddr = tp->mmio_addr; 2326 2327 spin_lock_irq(&tp->lock); 2328 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 2329 u8 cfg3 = RTL_R8 (Config3); 2330 u8 cfg5 = RTL_R8 (Config5); 2331 2332 wol->supported = WAKE_PHY | WAKE_MAGIC 2333 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; 2334 2335 wol->wolopts = 0; 2336 if (cfg3 & Cfg3_LinkUp) 2337 wol->wolopts |= WAKE_PHY; 2338 if (cfg3 & Cfg3_Magic) 2339 wol->wolopts |= WAKE_MAGIC; 2340 /* (KON)FIXME: See how netdev_set_wol() handles the 2341 following constants. */ 2342 if (cfg5 & Cfg5_UWF) 2343 wol->wolopts |= WAKE_UCAST; 2344 if (cfg5 & Cfg5_MWF) 2345 wol->wolopts |= WAKE_MCAST; 2346 if (cfg5 & Cfg5_BWF) 2347 wol->wolopts |= WAKE_BCAST; 2348 } 2349 spin_unlock_irq(&tp->lock); 2350} 2351 2352 2353/* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes 2354 that wol points to kernel memory and other threads or interrupts 2355 aren't messing with the 8139. */ 2356static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2357{ 2358 struct rtl8139_private *tp = netdev_priv(dev); 2359 void __iomem *ioaddr = tp->mmio_addr; 2360 u32 support; 2361 u8 cfg3, cfg5; 2362 2363 support = ((rtl_chip_info[tp->chipset].flags & HasLWake) 2364 ? (WAKE_PHY | WAKE_MAGIC 2365 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST) 2366 : 0); 2367 if (wol->wolopts & ~support) 2368 return -EINVAL; 2369 2370 spin_lock_irq(&tp->lock); 2371 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic); 2372 if (wol->wolopts & WAKE_PHY) 2373 cfg3 |= Cfg3_LinkUp; 2374 if (wol->wolopts & WAKE_MAGIC) 2375 cfg3 |= Cfg3_Magic; 2376 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2377 RTL_W8 (Config3, cfg3); 2378 RTL_W8 (Cfg9346, Cfg9346_Lock); 2379 2380 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF); 2381 /* (KON)FIXME: These are untested. We may have to set the 2382 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no 2383 documentation. */ 2384 if (wol->wolopts & WAKE_UCAST) 2385 cfg5 |= Cfg5_UWF; 2386 if (wol->wolopts & WAKE_MCAST) 2387 cfg5 |= Cfg5_MWF; 2388 if (wol->wolopts & WAKE_BCAST) 2389 cfg5 |= Cfg5_BWF; 2390 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */ 2391 spin_unlock_irq(&tp->lock); 2392 2393 return 0; 2394} 2395 2396static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2397{ 2398 struct rtl8139_private *tp = netdev_priv(dev); 2399 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 2400 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 2401 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 2402 info->regdump_len = tp->regs_len; 2403} 2404 2405static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2406{ 2407 struct rtl8139_private *tp = netdev_priv(dev); 2408 spin_lock_irq(&tp->lock); 2409 mii_ethtool_gset(&tp->mii, cmd); 2410 spin_unlock_irq(&tp->lock); 2411 return 0; 2412} 2413 2414static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2415{ 2416 struct rtl8139_private *tp = netdev_priv(dev); 2417 int rc; 2418 spin_lock_irq(&tp->lock); 2419 rc = mii_ethtool_sset(&tp->mii, cmd); 2420 spin_unlock_irq(&tp->lock); 2421 return rc; 2422} 2423 2424static int rtl8139_nway_reset(struct net_device *dev) 2425{ 2426 struct rtl8139_private *tp = netdev_priv(dev); 2427 return mii_nway_restart(&tp->mii); 2428} 2429 2430static u32 rtl8139_get_link(struct net_device *dev) 2431{ 2432 struct rtl8139_private *tp = netdev_priv(dev); 2433 return mii_link_ok(&tp->mii); 2434} 2435 2436static u32 rtl8139_get_msglevel(struct net_device *dev) 2437{ 2438 struct rtl8139_private *tp = netdev_priv(dev); 2439 return tp->msg_enable; 2440} 2441 2442static void rtl8139_set_msglevel(struct net_device *dev, u32 datum) 2443{ 2444 struct rtl8139_private *tp = netdev_priv(dev); 2445 tp->msg_enable = datum; 2446} 2447 2448static int rtl8139_get_regs_len(struct net_device *dev) 2449{ 2450 struct rtl8139_private *tp; 2451 /* TODO: we are too slack to do reg dumping for pio, for now */ 2452 if (use_io) 2453 return 0; 2454 tp = netdev_priv(dev); 2455 return tp->regs_len; 2456} 2457 2458static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf) 2459{ 2460 struct rtl8139_private *tp; 2461 2462 /* TODO: we are too slack to do reg dumping for pio, for now */ 2463 if (use_io) 2464 return; 2465 tp = netdev_priv(dev); 2466 2467 regs->version = RTL_REGS_VER; 2468 2469 spin_lock_irq(&tp->lock); 2470 memcpy_fromio(regbuf, tp->mmio_addr, regs->len); 2471 spin_unlock_irq(&tp->lock); 2472} 2473 2474static int rtl8139_get_sset_count(struct net_device *dev, int sset) 2475{ 2476 switch (sset) { 2477 case ETH_SS_STATS: 2478 return RTL_NUM_STATS; 2479 default: 2480 return -EOPNOTSUPP; 2481 } 2482} 2483 2484static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) 2485{ 2486 struct rtl8139_private *tp = netdev_priv(dev); 2487 2488 data[0] = tp->xstats.early_rx; 2489 data[1] = tp->xstats.tx_buf_mapped; 2490 data[2] = tp->xstats.tx_timeouts; 2491 data[3] = tp->xstats.rx_lost_in_ring; 2492} 2493 2494static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2495{ 2496 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); 2497} 2498 2499static const struct ethtool_ops rtl8139_ethtool_ops = { 2500 .get_drvinfo = rtl8139_get_drvinfo, 2501 .get_settings = rtl8139_get_settings, 2502 .set_settings = rtl8139_set_settings, 2503 .get_regs_len = rtl8139_get_regs_len, 2504 .get_regs = rtl8139_get_regs, 2505 .nway_reset = rtl8139_nway_reset, 2506 .get_link = rtl8139_get_link, 2507 .get_msglevel = rtl8139_get_msglevel, 2508 .set_msglevel = rtl8139_set_msglevel, 2509 .get_wol = rtl8139_get_wol, 2510 .set_wol = rtl8139_set_wol, 2511 .get_strings = rtl8139_get_strings, 2512 .get_sset_count = rtl8139_get_sset_count, 2513 .get_ethtool_stats = rtl8139_get_ethtool_stats, 2514}; 2515 2516static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2517{ 2518 struct rtl8139_private *tp = netdev_priv(dev); 2519 int rc; 2520 2521 if (!netif_running(dev)) 2522 return -EINVAL; 2523 2524 spin_lock_irq(&tp->lock); 2525 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL); 2526 spin_unlock_irq(&tp->lock); 2527 2528 return rc; 2529} 2530 2531 2532static struct rtnl_link_stats64 * 2533rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 2534{ 2535 struct rtl8139_private *tp = netdev_priv(dev); 2536 void __iomem *ioaddr = tp->mmio_addr; 2537 unsigned long flags; 2538 unsigned int start; 2539 2540 if (netif_running(dev)) { 2541 spin_lock_irqsave (&tp->lock, flags); 2542 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2543 RTL_W32 (RxMissed, 0); 2544 spin_unlock_irqrestore (&tp->lock, flags); 2545 } 2546 2547 netdev_stats_to_stats64(stats, &dev->stats); 2548 2549 do { 2550 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp); 2551 stats->rx_packets = tp->rx_stats.packets; 2552 stats->rx_bytes = tp->rx_stats.bytes; 2553 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start)); 2554 2555 do { 2556 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp); 2557 stats->tx_packets = tp->tx_stats.packets; 2558 stats->tx_bytes = tp->tx_stats.bytes; 2559 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start)); 2560 2561 return stats; 2562} 2563 2564/* Set or clear the multicast filter for this adaptor. 2565 This routine is not state sensitive and need not be SMP locked. */ 2566 2567static void __set_rx_mode (struct net_device *dev) 2568{ 2569 struct rtl8139_private *tp = netdev_priv(dev); 2570 void __iomem *ioaddr = tp->mmio_addr; 2571 u32 mc_filter[2]; /* Multicast hash filter */ 2572 int rx_mode; 2573 u32 tmp; 2574 2575 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n", 2576 dev->flags, RTL_R32(RxConfig)); 2577 2578 /* Note: do not reorder, GCC is clever about common statements. */ 2579 if (dev->flags & IFF_PROMISC) { 2580 rx_mode = 2581 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | 2582 AcceptAllPhys; 2583 mc_filter[1] = mc_filter[0] = 0xffffffff; 2584 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 2585 (dev->flags & IFF_ALLMULTI)) { 2586 /* Too many to filter perfectly -- accept all multicasts. */ 2587 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 2588 mc_filter[1] = mc_filter[0] = 0xffffffff; 2589 } else { 2590 struct netdev_hw_addr *ha; 2591 rx_mode = AcceptBroadcast | AcceptMyPhys; 2592 mc_filter[1] = mc_filter[0] = 0; 2593 netdev_for_each_mc_addr(ha, dev) { 2594 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2595 2596 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2597 rx_mode |= AcceptMulticast; 2598 } 2599 } 2600 2601 if (dev->features & NETIF_F_RXALL) 2602 rx_mode |= (AcceptErr | AcceptRunt); 2603 2604 /* We can safely update without stopping the chip. */ 2605 tmp = rtl8139_rx_config | rx_mode; 2606 if (tp->rx_config != tmp) { 2607 RTL_W32_F (RxConfig, tmp); 2608 tp->rx_config = tmp; 2609 } 2610 RTL_W32_F (MAR0 + 0, mc_filter[0]); 2611 RTL_W32_F (MAR0 + 4, mc_filter[1]); 2612} 2613 2614static void rtl8139_set_rx_mode (struct net_device *dev) 2615{ 2616 unsigned long flags; 2617 struct rtl8139_private *tp = netdev_priv(dev); 2618 2619 spin_lock_irqsave (&tp->lock, flags); 2620 __set_rx_mode(dev); 2621 spin_unlock_irqrestore (&tp->lock, flags); 2622} 2623 2624#ifdef CONFIG_PM 2625 2626static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state) 2627{ 2628 struct net_device *dev = pci_get_drvdata (pdev); 2629 struct rtl8139_private *tp = netdev_priv(dev); 2630 void __iomem *ioaddr = tp->mmio_addr; 2631 unsigned long flags; 2632 2633 pci_save_state (pdev); 2634 2635 if (!netif_running (dev)) 2636 return 0; 2637 2638 netif_device_detach (dev); 2639 2640 spin_lock_irqsave (&tp->lock, flags); 2641 2642 /* Disable interrupts, stop Tx and Rx. */ 2643 RTL_W16 (IntrMask, 0); 2644 RTL_W8 (ChipCmd, 0); 2645 2646 /* Update the error counts. */ 2647 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2648 RTL_W32 (RxMissed, 0); 2649 2650 spin_unlock_irqrestore (&tp->lock, flags); 2651 2652 pci_set_power_state (pdev, PCI_D3hot); 2653 2654 return 0; 2655} 2656 2657 2658static int rtl8139_resume (struct pci_dev *pdev) 2659{ 2660 struct net_device *dev = pci_get_drvdata (pdev); 2661 2662 pci_restore_state (pdev); 2663 if (!netif_running (dev)) 2664 return 0; 2665 pci_set_power_state (pdev, PCI_D0); 2666 rtl8139_init_ring (dev); 2667 rtl8139_hw_start (dev); 2668 netif_device_attach (dev); 2669 return 0; 2670} 2671 2672#endif /* CONFIG_PM */ 2673 2674 2675static struct pci_driver rtl8139_pci_driver = { 2676 .name = DRV_NAME, 2677 .id_table = rtl8139_pci_tbl, 2678 .probe = rtl8139_init_one, 2679 .remove = __devexit_p(rtl8139_remove_one), 2680#ifdef CONFIG_PM 2681 .suspend = rtl8139_suspend, 2682 .resume = rtl8139_resume, 2683#endif /* CONFIG_PM */ 2684}; 2685 2686 2687static int __init rtl8139_init_module (void) 2688{ 2689 /* when we're a module, we always print a version message, 2690 * even if no 8139 board is found. 2691 */ 2692#ifdef MODULE 2693 pr_info(RTL8139_DRIVER_NAME "\n"); 2694#endif 2695 2696 return pci_register_driver(&rtl8139_pci_driver); 2697} 2698 2699 2700static void __exit rtl8139_cleanup_module (void) 2701{ 2702 pci_unregister_driver (&rtl8139_pci_driver); 2703} 2704 2705 2706module_init(rtl8139_init_module); 2707module_exit(rtl8139_cleanup_module); 2708