1 /*************************************************************************** 2 * 3 * Copyright (C) 2007,2008 SMSC 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 * 19 *************************************************************************** 20 */ 21 22#include <linux/interrupt.h> 23#include <linux/kernel.h> 24#include <linux/netdevice.h> 25#include <linux/phy.h> 26#include <linux/pci.h> 27#include <linux/if_vlan.h> 28#include <linux/dma-mapping.h> 29#include <linux/crc32.h> 30#include <linux/slab.h> 31#include <linux/module.h> 32#include <asm/unaligned.h> 33#include "smsc9420.h" 34 35#define DRV_NAME "smsc9420" 36#define PFX DRV_NAME ": " 37#define DRV_MDIONAME "smsc9420-mdio" 38#define DRV_DESCRIPTION "SMSC LAN9420 driver" 39#define DRV_VERSION "1.01" 40 41MODULE_LICENSE("GPL"); 42MODULE_VERSION(DRV_VERSION); 43 44struct smsc9420_dma_desc { 45 u32 status; 46 u32 length; 47 u32 buffer1; 48 u32 buffer2; 49}; 50 51struct smsc9420_ring_info { 52 struct sk_buff *skb; 53 dma_addr_t mapping; 54}; 55 56struct smsc9420_pdata { 57 void __iomem *base_addr; 58 struct pci_dev *pdev; 59 struct net_device *dev; 60 61 struct smsc9420_dma_desc *rx_ring; 62 struct smsc9420_dma_desc *tx_ring; 63 struct smsc9420_ring_info *tx_buffers; 64 struct smsc9420_ring_info *rx_buffers; 65 dma_addr_t rx_dma_addr; 66 dma_addr_t tx_dma_addr; 67 int tx_ring_head, tx_ring_tail; 68 int rx_ring_head, rx_ring_tail; 69 70 spinlock_t int_lock; 71 spinlock_t phy_lock; 72 73 struct napi_struct napi; 74 75 bool software_irq_signal; 76 bool rx_csum; 77 u32 msg_enable; 78 79 struct phy_device *phy_dev; 80 struct mii_bus *mii_bus; 81 int phy_irq[PHY_MAX_ADDR]; 82 int last_duplex; 83 int last_carrier; 84}; 85 86static DEFINE_PCI_DEVICE_TABLE(smsc9420_id_table) = { 87 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, }, 88 { 0, } 89}; 90 91MODULE_DEVICE_TABLE(pci, smsc9420_id_table); 92 93#define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 94 95static uint smsc_debug; 96static uint debug = -1; 97module_param(debug, uint, 0); 98MODULE_PARM_DESC(debug, "debug level"); 99 100#define smsc_dbg(TYPE, f, a...) \ 101do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ 102 printk(KERN_DEBUG PFX f "\n", ## a); \ 103} while (0) 104 105#define smsc_info(TYPE, f, a...) \ 106do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ 107 printk(KERN_INFO PFX f "\n", ## a); \ 108} while (0) 109 110#define smsc_warn(TYPE, f, a...) \ 111do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \ 112 printk(KERN_WARNING PFX f "\n", ## a); \ 113} while (0) 114 115static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset) 116{ 117 return ioread32(pd->base_addr + offset); 118} 119 120static inline void 121smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value) 122{ 123 iowrite32(value, pd->base_addr + offset); 124} 125 126static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd) 127{ 128 /* to ensure PCI write completion, we must perform a PCI read */ 129 smsc9420_reg_read(pd, ID_REV); 130} 131 132static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx) 133{ 134 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv; 135 unsigned long flags; 136 u32 addr; 137 int i, reg = -EIO; 138 139 spin_lock_irqsave(&pd->phy_lock, flags); 140 141 /* confirm MII not busy */ 142 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) { 143 smsc_warn(DRV, "MII is busy???"); 144 goto out; 145 } 146 147 /* set the address, index & direction (read from PHY) */ 148 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | 149 MII_ACCESS_MII_READ_; 150 smsc9420_reg_write(pd, MII_ACCESS, addr); 151 152 /* wait for read to complete with 50us timeout */ 153 for (i = 0; i < 5; i++) { 154 if (!(smsc9420_reg_read(pd, MII_ACCESS) & 155 MII_ACCESS_MII_BUSY_)) { 156 reg = (u16)smsc9420_reg_read(pd, MII_DATA); 157 goto out; 158 } 159 udelay(10); 160 } 161 162 smsc_warn(DRV, "MII busy timeout!"); 163 164out: 165 spin_unlock_irqrestore(&pd->phy_lock, flags); 166 return reg; 167} 168 169static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx, 170 u16 val) 171{ 172 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv; 173 unsigned long flags; 174 u32 addr; 175 int i, reg = -EIO; 176 177 spin_lock_irqsave(&pd->phy_lock, flags); 178 179 /* confirm MII not busy */ 180 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) { 181 smsc_warn(DRV, "MII is busy???"); 182 goto out; 183 } 184 185 /* put the data to write in the MAC */ 186 smsc9420_reg_write(pd, MII_DATA, (u32)val); 187 188 /* set the address, index & direction (write to PHY) */ 189 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) | 190 MII_ACCESS_MII_WRITE_; 191 smsc9420_reg_write(pd, MII_ACCESS, addr); 192 193 /* wait for write to complete with 50us timeout */ 194 for (i = 0; i < 5; i++) { 195 if (!(smsc9420_reg_read(pd, MII_ACCESS) & 196 MII_ACCESS_MII_BUSY_)) { 197 reg = 0; 198 goto out; 199 } 200 udelay(10); 201 } 202 203 smsc_warn(DRV, "MII busy timeout!"); 204 205out: 206 spin_unlock_irqrestore(&pd->phy_lock, flags); 207 return reg; 208} 209 210/* Returns hash bit number for given MAC address 211 * Example: 212 * 01 00 5E 00 00 01 -> returns bit number 31 */ 213static u32 smsc9420_hash(u8 addr[ETH_ALEN]) 214{ 215 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f; 216} 217 218static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd) 219{ 220 int timeout = 100000; 221 222 BUG_ON(!pd); 223 224 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) { 225 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy"); 226 return -EIO; 227 } 228 229 smsc9420_reg_write(pd, E2P_CMD, 230 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_)); 231 232 do { 233 udelay(10); 234 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_)) 235 return 0; 236 } while (timeout--); 237 238 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out"); 239 return -EIO; 240} 241 242/* Standard ioctls for mii-tool */ 243static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 244{ 245 struct smsc9420_pdata *pd = netdev_priv(dev); 246 247 if (!netif_running(dev) || !pd->phy_dev) 248 return -EINVAL; 249 250 return phy_mii_ioctl(pd->phy_dev, ifr, cmd); 251} 252 253static int smsc9420_ethtool_get_settings(struct net_device *dev, 254 struct ethtool_cmd *cmd) 255{ 256 struct smsc9420_pdata *pd = netdev_priv(dev); 257 258 if (!pd->phy_dev) 259 return -ENODEV; 260 261 cmd->maxtxpkt = 1; 262 cmd->maxrxpkt = 1; 263 return phy_ethtool_gset(pd->phy_dev, cmd); 264} 265 266static int smsc9420_ethtool_set_settings(struct net_device *dev, 267 struct ethtool_cmd *cmd) 268{ 269 struct smsc9420_pdata *pd = netdev_priv(dev); 270 271 if (!pd->phy_dev) 272 return -ENODEV; 273 274 return phy_ethtool_sset(pd->phy_dev, cmd); 275} 276 277static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev, 278 struct ethtool_drvinfo *drvinfo) 279{ 280 struct smsc9420_pdata *pd = netdev_priv(netdev); 281 282 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); 283 strlcpy(drvinfo->bus_info, pci_name(pd->pdev), 284 sizeof(drvinfo->bus_info)); 285 strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version)); 286} 287 288static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev) 289{ 290 struct smsc9420_pdata *pd = netdev_priv(netdev); 291 return pd->msg_enable; 292} 293 294static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data) 295{ 296 struct smsc9420_pdata *pd = netdev_priv(netdev); 297 pd->msg_enable = data; 298} 299 300static int smsc9420_ethtool_nway_reset(struct net_device *netdev) 301{ 302 struct smsc9420_pdata *pd = netdev_priv(netdev); 303 304 if (!pd->phy_dev) 305 return -ENODEV; 306 307 return phy_start_aneg(pd->phy_dev); 308} 309 310static int smsc9420_ethtool_getregslen(struct net_device *dev) 311{ 312 /* all smsc9420 registers plus all phy registers */ 313 return 0x100 + (32 * sizeof(u32)); 314} 315 316static void 317smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs, 318 void *buf) 319{ 320 struct smsc9420_pdata *pd = netdev_priv(dev); 321 struct phy_device *phy_dev = pd->phy_dev; 322 unsigned int i, j = 0; 323 u32 *data = buf; 324 325 regs->version = smsc9420_reg_read(pd, ID_REV); 326 for (i = 0; i < 0x100; i += (sizeof(u32))) 327 data[j++] = smsc9420_reg_read(pd, i); 328 329 // cannot read phy registers if the net device is down 330 if (!phy_dev) 331 return; 332 333 for (i = 0; i <= 31; i++) 334 data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i); 335} 336 337static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd) 338{ 339 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG); 340 temp &= ~GPIO_CFG_EEPR_EN_; 341 smsc9420_reg_write(pd, GPIO_CFG, temp); 342 msleep(1); 343} 344 345static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op) 346{ 347 int timeout = 100; 348 u32 e2cmd; 349 350 smsc_dbg(HW, "op 0x%08x", op); 351 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) { 352 smsc_warn(HW, "Busy at start"); 353 return -EBUSY; 354 } 355 356 e2cmd = op | E2P_CMD_EPC_BUSY_; 357 smsc9420_reg_write(pd, E2P_CMD, e2cmd); 358 359 do { 360 msleep(1); 361 e2cmd = smsc9420_reg_read(pd, E2P_CMD); 362 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout)); 363 364 if (!timeout) { 365 smsc_info(HW, "TIMED OUT"); 366 return -EAGAIN; 367 } 368 369 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) { 370 smsc_info(HW, "Error occurred during eeprom operation"); 371 return -EINVAL; 372 } 373 374 return 0; 375} 376 377static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd, 378 u8 address, u8 *data) 379{ 380 u32 op = E2P_CMD_EPC_CMD_READ_ | address; 381 int ret; 382 383 smsc_dbg(HW, "address 0x%x", address); 384 ret = smsc9420_eeprom_send_cmd(pd, op); 385 386 if (!ret) 387 data[address] = smsc9420_reg_read(pd, E2P_DATA); 388 389 return ret; 390} 391 392static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd, 393 u8 address, u8 data) 394{ 395 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address; 396 int ret; 397 398 smsc_dbg(HW, "address 0x%x, data 0x%x", address, data); 399 ret = smsc9420_eeprom_send_cmd(pd, op); 400 401 if (!ret) { 402 op = E2P_CMD_EPC_CMD_WRITE_ | address; 403 smsc9420_reg_write(pd, E2P_DATA, (u32)data); 404 ret = smsc9420_eeprom_send_cmd(pd, op); 405 } 406 407 return ret; 408} 409 410static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev) 411{ 412 return SMSC9420_EEPROM_SIZE; 413} 414 415static int smsc9420_ethtool_get_eeprom(struct net_device *dev, 416 struct ethtool_eeprom *eeprom, u8 *data) 417{ 418 struct smsc9420_pdata *pd = netdev_priv(dev); 419 u8 eeprom_data[SMSC9420_EEPROM_SIZE]; 420 int len, i; 421 422 smsc9420_eeprom_enable_access(pd); 423 424 len = min(eeprom->len, SMSC9420_EEPROM_SIZE); 425 for (i = 0; i < len; i++) { 426 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data); 427 if (ret < 0) { 428 eeprom->len = 0; 429 return ret; 430 } 431 } 432 433 memcpy(data, &eeprom_data[eeprom->offset], len); 434 eeprom->magic = SMSC9420_EEPROM_MAGIC; 435 eeprom->len = len; 436 return 0; 437} 438 439static int smsc9420_ethtool_set_eeprom(struct net_device *dev, 440 struct ethtool_eeprom *eeprom, u8 *data) 441{ 442 struct smsc9420_pdata *pd = netdev_priv(dev); 443 int ret; 444 445 if (eeprom->magic != SMSC9420_EEPROM_MAGIC) 446 return -EINVAL; 447 448 smsc9420_eeprom_enable_access(pd); 449 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_); 450 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data); 451 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_); 452 453 /* Single byte write, according to man page */ 454 eeprom->len = 1; 455 456 return ret; 457} 458 459static const struct ethtool_ops smsc9420_ethtool_ops = { 460 .get_settings = smsc9420_ethtool_get_settings, 461 .set_settings = smsc9420_ethtool_set_settings, 462 .get_drvinfo = smsc9420_ethtool_get_drvinfo, 463 .get_msglevel = smsc9420_ethtool_get_msglevel, 464 .set_msglevel = smsc9420_ethtool_set_msglevel, 465 .nway_reset = smsc9420_ethtool_nway_reset, 466 .get_link = ethtool_op_get_link, 467 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len, 468 .get_eeprom = smsc9420_ethtool_get_eeprom, 469 .set_eeprom = smsc9420_ethtool_set_eeprom, 470 .get_regs_len = smsc9420_ethtool_getregslen, 471 .get_regs = smsc9420_ethtool_getregs, 472}; 473 474/* Sets the device MAC address to dev_addr */ 475static void smsc9420_set_mac_address(struct net_device *dev) 476{ 477 struct smsc9420_pdata *pd = netdev_priv(dev); 478 u8 *dev_addr = dev->dev_addr; 479 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4]; 480 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | 481 (dev_addr[1] << 8) | dev_addr[0]; 482 483 smsc9420_reg_write(pd, ADDRH, mac_high16); 484 smsc9420_reg_write(pd, ADDRL, mac_low32); 485} 486 487static void smsc9420_check_mac_address(struct net_device *dev) 488{ 489 struct smsc9420_pdata *pd = netdev_priv(dev); 490 491 /* Check if mac address has been specified when bringing interface up */ 492 if (is_valid_ether_addr(dev->dev_addr)) { 493 smsc9420_set_mac_address(dev); 494 smsc_dbg(PROBE, "MAC Address is specified by configuration"); 495 } else { 496 /* Try reading mac address from device. if EEPROM is present 497 * it will already have been set */ 498 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH); 499 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL); 500 dev->dev_addr[0] = (u8)(mac_low32); 501 dev->dev_addr[1] = (u8)(mac_low32 >> 8); 502 dev->dev_addr[2] = (u8)(mac_low32 >> 16); 503 dev->dev_addr[3] = (u8)(mac_low32 >> 24); 504 dev->dev_addr[4] = (u8)(mac_high16); 505 dev->dev_addr[5] = (u8)(mac_high16 >> 8); 506 507 if (is_valid_ether_addr(dev->dev_addr)) { 508 /* eeprom values are valid so use them */ 509 smsc_dbg(PROBE, "Mac Address is read from EEPROM"); 510 } else { 511 /* eeprom values are invalid, generate random MAC */ 512 eth_hw_addr_random(dev); 513 smsc9420_set_mac_address(dev); 514 smsc_dbg(PROBE, "MAC Address is set to random"); 515 } 516 } 517} 518 519static void smsc9420_stop_tx(struct smsc9420_pdata *pd) 520{ 521 u32 dmac_control, mac_cr, dma_intr_ena; 522 int timeout = 1000; 523 524 /* disable TX DMAC */ 525 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); 526 dmac_control &= (~DMAC_CONTROL_ST_); 527 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); 528 529 /* Wait max 10ms for transmit process to stop */ 530 while (--timeout) { 531 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_) 532 break; 533 udelay(10); 534 } 535 536 if (!timeout) 537 smsc_warn(IFDOWN, "TX DMAC failed to stop"); 538 539 /* ACK Tx DMAC stop bit */ 540 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_); 541 542 /* mask TX DMAC interrupts */ 543 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 544 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_); 545 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 546 smsc9420_pci_flush_write(pd); 547 548 /* stop MAC TX */ 549 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_); 550 smsc9420_reg_write(pd, MAC_CR, mac_cr); 551 smsc9420_pci_flush_write(pd); 552} 553 554static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd) 555{ 556 int i; 557 558 BUG_ON(!pd->tx_ring); 559 560 if (!pd->tx_buffers) 561 return; 562 563 for (i = 0; i < TX_RING_SIZE; i++) { 564 struct sk_buff *skb = pd->tx_buffers[i].skb; 565 566 if (skb) { 567 BUG_ON(!pd->tx_buffers[i].mapping); 568 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping, 569 skb->len, PCI_DMA_TODEVICE); 570 dev_kfree_skb_any(skb); 571 } 572 573 pd->tx_ring[i].status = 0; 574 pd->tx_ring[i].length = 0; 575 pd->tx_ring[i].buffer1 = 0; 576 pd->tx_ring[i].buffer2 = 0; 577 } 578 wmb(); 579 580 kfree(pd->tx_buffers); 581 pd->tx_buffers = NULL; 582 583 pd->tx_ring_head = 0; 584 pd->tx_ring_tail = 0; 585} 586 587static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd) 588{ 589 int i; 590 591 BUG_ON(!pd->rx_ring); 592 593 if (!pd->rx_buffers) 594 return; 595 596 for (i = 0; i < RX_RING_SIZE; i++) { 597 if (pd->rx_buffers[i].skb) 598 dev_kfree_skb_any(pd->rx_buffers[i].skb); 599 600 if (pd->rx_buffers[i].mapping) 601 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping, 602 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 603 604 pd->rx_ring[i].status = 0; 605 pd->rx_ring[i].length = 0; 606 pd->rx_ring[i].buffer1 = 0; 607 pd->rx_ring[i].buffer2 = 0; 608 } 609 wmb(); 610 611 kfree(pd->rx_buffers); 612 pd->rx_buffers = NULL; 613 614 pd->rx_ring_head = 0; 615 pd->rx_ring_tail = 0; 616} 617 618static void smsc9420_stop_rx(struct smsc9420_pdata *pd) 619{ 620 int timeout = 1000; 621 u32 mac_cr, dmac_control, dma_intr_ena; 622 623 /* mask RX DMAC interrupts */ 624 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 625 dma_intr_ena &= (~DMAC_INTR_ENA_RX_); 626 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 627 smsc9420_pci_flush_write(pd); 628 629 /* stop RX MAC prior to stoping DMA */ 630 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_); 631 smsc9420_reg_write(pd, MAC_CR, mac_cr); 632 smsc9420_pci_flush_write(pd); 633 634 /* stop RX DMAC */ 635 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); 636 dmac_control &= (~DMAC_CONTROL_SR_); 637 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); 638 smsc9420_pci_flush_write(pd); 639 640 /* wait up to 10ms for receive to stop */ 641 while (--timeout) { 642 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_) 643 break; 644 udelay(10); 645 } 646 647 if (!timeout) 648 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout."); 649 650 /* ACK the Rx DMAC stop bit */ 651 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_); 652} 653 654static irqreturn_t smsc9420_isr(int irq, void *dev_id) 655{ 656 struct smsc9420_pdata *pd = dev_id; 657 u32 int_cfg, int_sts, int_ctl; 658 irqreturn_t ret = IRQ_NONE; 659 ulong flags; 660 661 BUG_ON(!pd); 662 BUG_ON(!pd->base_addr); 663 664 int_cfg = smsc9420_reg_read(pd, INT_CFG); 665 666 /* check if it's our interrupt */ 667 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) != 668 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) 669 return IRQ_NONE; 670 671 int_sts = smsc9420_reg_read(pd, INT_STAT); 672 673 if (likely(INT_STAT_DMAC_INT_ & int_sts)) { 674 u32 status = smsc9420_reg_read(pd, DMAC_STATUS); 675 u32 ints_to_clear = 0; 676 677 if (status & DMAC_STS_TX_) { 678 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_); 679 netif_wake_queue(pd->dev); 680 } 681 682 if (status & DMAC_STS_RX_) { 683 /* mask RX DMAC interrupts */ 684 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 685 dma_intr_ena &= (~DMAC_INTR_ENA_RX_); 686 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 687 smsc9420_pci_flush_write(pd); 688 689 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_); 690 napi_schedule(&pd->napi); 691 } 692 693 if (ints_to_clear) 694 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear); 695 696 ret = IRQ_HANDLED; 697 } 698 699 if (unlikely(INT_STAT_SW_INT_ & int_sts)) { 700 /* mask software interrupt */ 701 spin_lock_irqsave(&pd->int_lock, flags); 702 int_ctl = smsc9420_reg_read(pd, INT_CTL); 703 int_ctl &= (~INT_CTL_SW_INT_EN_); 704 smsc9420_reg_write(pd, INT_CTL, int_ctl); 705 spin_unlock_irqrestore(&pd->int_lock, flags); 706 707 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_); 708 pd->software_irq_signal = true; 709 smp_wmb(); 710 711 ret = IRQ_HANDLED; 712 } 713 714 /* to ensure PCI write completion, we must perform a PCI read */ 715 smsc9420_pci_flush_write(pd); 716 717 return ret; 718} 719 720#ifdef CONFIG_NET_POLL_CONTROLLER 721static void smsc9420_poll_controller(struct net_device *dev) 722{ 723 disable_irq(dev->irq); 724 smsc9420_isr(0, dev); 725 enable_irq(dev->irq); 726} 727#endif /* CONFIG_NET_POLL_CONTROLLER */ 728 729static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd) 730{ 731 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_); 732 smsc9420_reg_read(pd, BUS_MODE); 733 udelay(2); 734 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_) 735 smsc_warn(DRV, "Software reset not cleared"); 736} 737 738static int smsc9420_stop(struct net_device *dev) 739{ 740 struct smsc9420_pdata *pd = netdev_priv(dev); 741 u32 int_cfg; 742 ulong flags; 743 744 BUG_ON(!pd); 745 BUG_ON(!pd->phy_dev); 746 747 /* disable master interrupt */ 748 spin_lock_irqsave(&pd->int_lock, flags); 749 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 750 smsc9420_reg_write(pd, INT_CFG, int_cfg); 751 spin_unlock_irqrestore(&pd->int_lock, flags); 752 753 netif_tx_disable(dev); 754 napi_disable(&pd->napi); 755 756 smsc9420_stop_tx(pd); 757 smsc9420_free_tx_ring(pd); 758 759 smsc9420_stop_rx(pd); 760 smsc9420_free_rx_ring(pd); 761 762 free_irq(dev->irq, pd); 763 764 smsc9420_dmac_soft_reset(pd); 765 766 phy_stop(pd->phy_dev); 767 768 phy_disconnect(pd->phy_dev); 769 pd->phy_dev = NULL; 770 mdiobus_unregister(pd->mii_bus); 771 mdiobus_free(pd->mii_bus); 772 773 return 0; 774} 775 776static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status) 777{ 778 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) { 779 dev->stats.rx_errors++; 780 if (desc_status & RDES0_DESCRIPTOR_ERROR_) 781 dev->stats.rx_over_errors++; 782 else if (desc_status & (RDES0_FRAME_TOO_LONG_ | 783 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_)) 784 dev->stats.rx_frame_errors++; 785 else if (desc_status & RDES0_CRC_ERROR_) 786 dev->stats.rx_crc_errors++; 787 } 788 789 if (unlikely(desc_status & RDES0_LENGTH_ERROR_)) 790 dev->stats.rx_length_errors++; 791 792 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) && 793 (desc_status & RDES0_FIRST_DESCRIPTOR_)))) 794 dev->stats.rx_length_errors++; 795 796 if (desc_status & RDES0_MULTICAST_FRAME_) 797 dev->stats.multicast++; 798} 799 800static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index, 801 const u32 status) 802{ 803 struct net_device *dev = pd->dev; 804 struct sk_buff *skb; 805 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_) 806 >> RDES0_FRAME_LENGTH_SHFT_; 807 808 /* remove crc from packet lendth */ 809 packet_length -= 4; 810 811 if (pd->rx_csum) 812 packet_length -= 2; 813 814 dev->stats.rx_packets++; 815 dev->stats.rx_bytes += packet_length; 816 817 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping, 818 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 819 pd->rx_buffers[index].mapping = 0; 820 821 skb = pd->rx_buffers[index].skb; 822 pd->rx_buffers[index].skb = NULL; 823 824 if (pd->rx_csum) { 825 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) + 826 NET_IP_ALIGN + packet_length + 4); 827 put_unaligned_le16(hw_csum, &skb->csum); 828 skb->ip_summed = CHECKSUM_COMPLETE; 829 } 830 831 skb_reserve(skb, NET_IP_ALIGN); 832 skb_put(skb, packet_length); 833 834 skb->protocol = eth_type_trans(skb, dev); 835 836 netif_receive_skb(skb); 837} 838 839static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index) 840{ 841 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ); 842 dma_addr_t mapping; 843 844 BUG_ON(pd->rx_buffers[index].skb); 845 BUG_ON(pd->rx_buffers[index].mapping); 846 847 if (unlikely(!skb)) { 848 smsc_warn(RX_ERR, "Failed to allocate new skb!"); 849 return -ENOMEM; 850 } 851 852 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb), 853 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 854 if (pci_dma_mapping_error(pd->pdev, mapping)) { 855 dev_kfree_skb_any(skb); 856 smsc_warn(RX_ERR, "pci_map_single failed!"); 857 return -ENOMEM; 858 } 859 860 pd->rx_buffers[index].skb = skb; 861 pd->rx_buffers[index].mapping = mapping; 862 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN; 863 pd->rx_ring[index].status = RDES0_OWN_; 864 wmb(); 865 866 return 0; 867} 868 869static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd) 870{ 871 while (pd->rx_ring_tail != pd->rx_ring_head) { 872 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail)) 873 break; 874 875 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE; 876 } 877} 878 879static int smsc9420_rx_poll(struct napi_struct *napi, int budget) 880{ 881 struct smsc9420_pdata *pd = 882 container_of(napi, struct smsc9420_pdata, napi); 883 struct net_device *dev = pd->dev; 884 u32 drop_frame_cnt, dma_intr_ena, status; 885 int work_done; 886 887 for (work_done = 0; work_done < budget; work_done++) { 888 rmb(); 889 status = pd->rx_ring[pd->rx_ring_head].status; 890 891 /* stop if DMAC owns this dma descriptor */ 892 if (status & RDES0_OWN_) 893 break; 894 895 smsc9420_rx_count_stats(dev, status); 896 smsc9420_rx_handoff(pd, pd->rx_ring_head, status); 897 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE; 898 smsc9420_alloc_new_rx_buffers(pd); 899 } 900 901 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR); 902 dev->stats.rx_dropped += 903 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF); 904 905 /* Kick RXDMA */ 906 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1); 907 smsc9420_pci_flush_write(pd); 908 909 if (work_done < budget) { 910 napi_complete(&pd->napi); 911 912 /* re-enable RX DMA interrupts */ 913 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 914 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_); 915 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 916 smsc9420_pci_flush_write(pd); 917 } 918 return work_done; 919} 920 921static void 922smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length) 923{ 924 if (unlikely(status & TDES0_ERROR_SUMMARY_)) { 925 dev->stats.tx_errors++; 926 if (status & (TDES0_EXCESSIVE_DEFERRAL_ | 927 TDES0_EXCESSIVE_COLLISIONS_)) 928 dev->stats.tx_aborted_errors++; 929 930 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_)) 931 dev->stats.tx_carrier_errors++; 932 } else { 933 dev->stats.tx_packets++; 934 dev->stats.tx_bytes += (length & 0x7FF); 935 } 936 937 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) { 938 dev->stats.collisions += 16; 939 } else { 940 dev->stats.collisions += 941 (status & TDES0_COLLISION_COUNT_MASK_) >> 942 TDES0_COLLISION_COUNT_SHFT_; 943 } 944 945 if (unlikely(status & TDES0_HEARTBEAT_FAIL_)) 946 dev->stats.tx_heartbeat_errors++; 947} 948 949/* Check for completed dma transfers, update stats and free skbs */ 950static void smsc9420_complete_tx(struct net_device *dev) 951{ 952 struct smsc9420_pdata *pd = netdev_priv(dev); 953 954 while (pd->tx_ring_tail != pd->tx_ring_head) { 955 int index = pd->tx_ring_tail; 956 u32 status, length; 957 958 rmb(); 959 status = pd->tx_ring[index].status; 960 length = pd->tx_ring[index].length; 961 962 /* Check if DMA still owns this descriptor */ 963 if (unlikely(TDES0_OWN_ & status)) 964 break; 965 966 smsc9420_tx_update_stats(dev, status, length); 967 968 BUG_ON(!pd->tx_buffers[index].skb); 969 BUG_ON(!pd->tx_buffers[index].mapping); 970 971 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping, 972 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE); 973 pd->tx_buffers[index].mapping = 0; 974 975 dev_kfree_skb_any(pd->tx_buffers[index].skb); 976 pd->tx_buffers[index].skb = NULL; 977 978 pd->tx_ring[index].buffer1 = 0; 979 wmb(); 980 981 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE; 982 } 983} 984 985static netdev_tx_t smsc9420_hard_start_xmit(struct sk_buff *skb, 986 struct net_device *dev) 987{ 988 struct smsc9420_pdata *pd = netdev_priv(dev); 989 dma_addr_t mapping; 990 int index = pd->tx_ring_head; 991 u32 tmp_desc1; 992 bool about_to_take_last_desc = 993 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail); 994 995 smsc9420_complete_tx(dev); 996 997 rmb(); 998 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_); 999 BUG_ON(pd->tx_buffers[index].skb); 1000 BUG_ON(pd->tx_buffers[index].mapping); 1001 1002 mapping = pci_map_single(pd->pdev, skb->data, 1003 skb->len, PCI_DMA_TODEVICE); 1004 if (pci_dma_mapping_error(pd->pdev, mapping)) { 1005 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet"); 1006 return NETDEV_TX_BUSY; 1007 } 1008 1009 pd->tx_buffers[index].skb = skb; 1010 pd->tx_buffers[index].mapping = mapping; 1011 1012 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF)); 1013 if (unlikely(about_to_take_last_desc)) { 1014 tmp_desc1 |= TDES1_IC_; 1015 netif_stop_queue(pd->dev); 1016 } 1017 1018 /* check if we are at the last descriptor and need to set EOR */ 1019 if (unlikely(index == (TX_RING_SIZE - 1))) 1020 tmp_desc1 |= TDES1_TER_; 1021 1022 pd->tx_ring[index].buffer1 = mapping; 1023 pd->tx_ring[index].length = tmp_desc1; 1024 wmb(); 1025 1026 /* increment head */ 1027 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE; 1028 1029 /* assign ownership to DMAC */ 1030 pd->tx_ring[index].status = TDES0_OWN_; 1031 wmb(); 1032 1033 skb_tx_timestamp(skb); 1034 1035 /* kick the DMA */ 1036 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1); 1037 smsc9420_pci_flush_write(pd); 1038 1039 return NETDEV_TX_OK; 1040} 1041 1042static struct net_device_stats *smsc9420_get_stats(struct net_device *dev) 1043{ 1044 struct smsc9420_pdata *pd = netdev_priv(dev); 1045 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR); 1046 dev->stats.rx_dropped += 1047 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF); 1048 return &dev->stats; 1049} 1050 1051static void smsc9420_set_multicast_list(struct net_device *dev) 1052{ 1053 struct smsc9420_pdata *pd = netdev_priv(dev); 1054 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR); 1055 1056 if (dev->flags & IFF_PROMISC) { 1057 smsc_dbg(HW, "Promiscuous Mode Enabled"); 1058 mac_cr |= MAC_CR_PRMS_; 1059 mac_cr &= (~MAC_CR_MCPAS_); 1060 mac_cr &= (~MAC_CR_HPFILT_); 1061 } else if (dev->flags & IFF_ALLMULTI) { 1062 smsc_dbg(HW, "Receive all Multicast Enabled"); 1063 mac_cr &= (~MAC_CR_PRMS_); 1064 mac_cr |= MAC_CR_MCPAS_; 1065 mac_cr &= (~MAC_CR_HPFILT_); 1066 } else if (!netdev_mc_empty(dev)) { 1067 struct netdev_hw_addr *ha; 1068 u32 hash_lo = 0, hash_hi = 0; 1069 1070 smsc_dbg(HW, "Multicast filter enabled"); 1071 netdev_for_each_mc_addr(ha, dev) { 1072 u32 bit_num = smsc9420_hash(ha->addr); 1073 u32 mask = 1 << (bit_num & 0x1F); 1074 1075 if (bit_num & 0x20) 1076 hash_hi |= mask; 1077 else 1078 hash_lo |= mask; 1079 1080 } 1081 smsc9420_reg_write(pd, HASHH, hash_hi); 1082 smsc9420_reg_write(pd, HASHL, hash_lo); 1083 1084 mac_cr &= (~MAC_CR_PRMS_); 1085 mac_cr &= (~MAC_CR_MCPAS_); 1086 mac_cr |= MAC_CR_HPFILT_; 1087 } else { 1088 smsc_dbg(HW, "Receive own packets only."); 1089 smsc9420_reg_write(pd, HASHH, 0); 1090 smsc9420_reg_write(pd, HASHL, 0); 1091 1092 mac_cr &= (~MAC_CR_PRMS_); 1093 mac_cr &= (~MAC_CR_MCPAS_); 1094 mac_cr &= (~MAC_CR_HPFILT_); 1095 } 1096 1097 smsc9420_reg_write(pd, MAC_CR, mac_cr); 1098 smsc9420_pci_flush_write(pd); 1099} 1100 1101static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd) 1102{ 1103 struct phy_device *phy_dev = pd->phy_dev; 1104 u32 flow; 1105 1106 if (phy_dev->duplex == DUPLEX_FULL) { 1107 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE); 1108 u16 rmtadv = phy_read(phy_dev, MII_LPA); 1109 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); 1110 1111 if (cap & FLOW_CTRL_RX) 1112 flow = 0xFFFF0002; 1113 else 1114 flow = 0; 1115 1116 smsc_info(LINK, "rx pause %s, tx pause %s", 1117 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"), 1118 (cap & FLOW_CTRL_TX ? "enabled" : "disabled")); 1119 } else { 1120 smsc_info(LINK, "half duplex"); 1121 flow = 0; 1122 } 1123 1124 smsc9420_reg_write(pd, FLOW, flow); 1125} 1126 1127/* Update link mode if anything has changed. Called periodically when the 1128 * PHY is in polling mode, even if nothing has changed. */ 1129static void smsc9420_phy_adjust_link(struct net_device *dev) 1130{ 1131 struct smsc9420_pdata *pd = netdev_priv(dev); 1132 struct phy_device *phy_dev = pd->phy_dev; 1133 int carrier; 1134 1135 if (phy_dev->duplex != pd->last_duplex) { 1136 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR); 1137 if (phy_dev->duplex) { 1138 smsc_dbg(LINK, "full duplex mode"); 1139 mac_cr |= MAC_CR_FDPX_; 1140 } else { 1141 smsc_dbg(LINK, "half duplex mode"); 1142 mac_cr &= ~MAC_CR_FDPX_; 1143 } 1144 smsc9420_reg_write(pd, MAC_CR, mac_cr); 1145 1146 smsc9420_phy_update_flowcontrol(pd); 1147 pd->last_duplex = phy_dev->duplex; 1148 } 1149 1150 carrier = netif_carrier_ok(dev); 1151 if (carrier != pd->last_carrier) { 1152 if (carrier) 1153 smsc_dbg(LINK, "carrier OK"); 1154 else 1155 smsc_dbg(LINK, "no carrier"); 1156 pd->last_carrier = carrier; 1157 } 1158} 1159 1160static int smsc9420_mii_probe(struct net_device *dev) 1161{ 1162 struct smsc9420_pdata *pd = netdev_priv(dev); 1163 struct phy_device *phydev = NULL; 1164 1165 BUG_ON(pd->phy_dev); 1166 1167 /* Device only supports internal PHY at address 1 */ 1168 if (!pd->mii_bus->phy_map[1]) { 1169 pr_err("%s: no PHY found at address 1\n", dev->name); 1170 return -ENODEV; 1171 } 1172 1173 phydev = pd->mii_bus->phy_map[1]; 1174 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr, 1175 phydev->phy_id); 1176 1177 phydev = phy_connect(dev, dev_name(&phydev->dev), 1178 smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII); 1179 1180 if (IS_ERR(phydev)) { 1181 pr_err("%s: Could not attach to PHY\n", dev->name); 1182 return PTR_ERR(phydev); 1183 } 1184 1185 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 1186 dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq); 1187 1188 /* mask with MAC supported features */ 1189 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | 1190 SUPPORTED_Asym_Pause); 1191 phydev->advertising = phydev->supported; 1192 1193 pd->phy_dev = phydev; 1194 pd->last_duplex = -1; 1195 pd->last_carrier = -1; 1196 1197 return 0; 1198} 1199 1200static int smsc9420_mii_init(struct net_device *dev) 1201{ 1202 struct smsc9420_pdata *pd = netdev_priv(dev); 1203 int err = -ENXIO, i; 1204 1205 pd->mii_bus = mdiobus_alloc(); 1206 if (!pd->mii_bus) { 1207 err = -ENOMEM; 1208 goto err_out_1; 1209 } 1210 pd->mii_bus->name = DRV_MDIONAME; 1211 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x", 1212 (pd->pdev->bus->number << 8) | pd->pdev->devfn); 1213 pd->mii_bus->priv = pd; 1214 pd->mii_bus->read = smsc9420_mii_read; 1215 pd->mii_bus->write = smsc9420_mii_write; 1216 pd->mii_bus->irq = pd->phy_irq; 1217 for (i = 0; i < PHY_MAX_ADDR; ++i) 1218 pd->mii_bus->irq[i] = PHY_POLL; 1219 1220 /* Mask all PHYs except ID 1 (internal) */ 1221 pd->mii_bus->phy_mask = ~(1 << 1); 1222 1223 if (mdiobus_register(pd->mii_bus)) { 1224 smsc_warn(PROBE, "Error registering mii bus"); 1225 goto err_out_free_bus_2; 1226 } 1227 1228 if (smsc9420_mii_probe(dev) < 0) { 1229 smsc_warn(PROBE, "Error probing mii bus"); 1230 goto err_out_unregister_bus_3; 1231 } 1232 1233 return 0; 1234 1235err_out_unregister_bus_3: 1236 mdiobus_unregister(pd->mii_bus); 1237err_out_free_bus_2: 1238 mdiobus_free(pd->mii_bus); 1239err_out_1: 1240 return err; 1241} 1242 1243static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd) 1244{ 1245 int i; 1246 1247 BUG_ON(!pd->tx_ring); 1248 1249 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) * 1250 TX_RING_SIZE), GFP_KERNEL); 1251 if (!pd->tx_buffers) { 1252 smsc_warn(IFUP, "Failed to allocated tx_buffers"); 1253 return -ENOMEM; 1254 } 1255 1256 /* Initialize the TX Ring */ 1257 for (i = 0; i < TX_RING_SIZE; i++) { 1258 pd->tx_buffers[i].skb = NULL; 1259 pd->tx_buffers[i].mapping = 0; 1260 pd->tx_ring[i].status = 0; 1261 pd->tx_ring[i].length = 0; 1262 pd->tx_ring[i].buffer1 = 0; 1263 pd->tx_ring[i].buffer2 = 0; 1264 } 1265 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_; 1266 wmb(); 1267 1268 pd->tx_ring_head = 0; 1269 pd->tx_ring_tail = 0; 1270 1271 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr); 1272 smsc9420_pci_flush_write(pd); 1273 1274 return 0; 1275} 1276 1277static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd) 1278{ 1279 int i; 1280 1281 BUG_ON(!pd->rx_ring); 1282 1283 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) * 1284 RX_RING_SIZE), GFP_KERNEL); 1285 if (pd->rx_buffers == NULL) { 1286 smsc_warn(IFUP, "Failed to allocated rx_buffers"); 1287 goto out; 1288 } 1289 1290 /* initialize the rx ring */ 1291 for (i = 0; i < RX_RING_SIZE; i++) { 1292 pd->rx_ring[i].status = 0; 1293 pd->rx_ring[i].length = PKT_BUF_SZ; 1294 pd->rx_ring[i].buffer2 = 0; 1295 pd->rx_buffers[i].skb = NULL; 1296 pd->rx_buffers[i].mapping = 0; 1297 } 1298 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_); 1299 1300 /* now allocate the entire ring of skbs */ 1301 for (i = 0; i < RX_RING_SIZE; i++) { 1302 if (smsc9420_alloc_rx_buffer(pd, i)) { 1303 smsc_warn(IFUP, "failed to allocate rx skb %d", i); 1304 goto out_free_rx_skbs; 1305 } 1306 } 1307 1308 pd->rx_ring_head = 0; 1309 pd->rx_ring_tail = 0; 1310 1311 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q); 1312 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1)); 1313 1314 if (pd->rx_csum) { 1315 /* Enable RX COE */ 1316 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN; 1317 smsc9420_reg_write(pd, COE_CR, coe); 1318 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe); 1319 } 1320 1321 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr); 1322 smsc9420_pci_flush_write(pd); 1323 1324 return 0; 1325 1326out_free_rx_skbs: 1327 smsc9420_free_rx_ring(pd); 1328out: 1329 return -ENOMEM; 1330} 1331 1332static int smsc9420_open(struct net_device *dev) 1333{ 1334 struct smsc9420_pdata *pd; 1335 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl; 1336 unsigned long flags; 1337 int result = 0, timeout; 1338 1339 BUG_ON(!dev); 1340 pd = netdev_priv(dev); 1341 BUG_ON(!pd); 1342 1343 if (!is_valid_ether_addr(dev->dev_addr)) { 1344 smsc_warn(IFUP, "dev_addr is not a valid MAC address"); 1345 result = -EADDRNOTAVAIL; 1346 goto out_0; 1347 } 1348 1349 netif_carrier_off(dev); 1350 1351 /* disable, mask and acknowledge all interrupts */ 1352 spin_lock_irqsave(&pd->int_lock, flags); 1353 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 1354 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1355 smsc9420_reg_write(pd, INT_CTL, 0); 1356 spin_unlock_irqrestore(&pd->int_lock, flags); 1357 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0); 1358 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF); 1359 smsc9420_pci_flush_write(pd); 1360 1361 if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED, 1362 DRV_NAME, pd)) { 1363 smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq); 1364 result = -ENODEV; 1365 goto out_0; 1366 } 1367 1368 smsc9420_dmac_soft_reset(pd); 1369 1370 /* make sure MAC_CR is sane */ 1371 smsc9420_reg_write(pd, MAC_CR, 0); 1372 1373 smsc9420_set_mac_address(dev); 1374 1375 /* Configure GPIO pins to drive LEDs */ 1376 smsc9420_reg_write(pd, GPIO_CFG, 1377 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_)); 1378 1379 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16; 1380 1381#ifdef __BIG_ENDIAN 1382 bus_mode |= BUS_MODE_DBO_; 1383#endif 1384 1385 smsc9420_reg_write(pd, BUS_MODE, bus_mode); 1386 1387 smsc9420_pci_flush_write(pd); 1388 1389 /* set bus master bridge arbitration priority for Rx and TX DMA */ 1390 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1); 1391 1392 smsc9420_reg_write(pd, DMAC_CONTROL, 1393 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_)); 1394 1395 smsc9420_pci_flush_write(pd); 1396 1397 /* test the IRQ connection to the ISR */ 1398 smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq); 1399 pd->software_irq_signal = false; 1400 1401 spin_lock_irqsave(&pd->int_lock, flags); 1402 /* configure interrupt deassertion timer and enable interrupts */ 1403 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_; 1404 int_cfg &= ~(INT_CFG_INT_DEAS_MASK); 1405 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK); 1406 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1407 1408 /* unmask software interrupt */ 1409 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_; 1410 smsc9420_reg_write(pd, INT_CTL, int_ctl); 1411 spin_unlock_irqrestore(&pd->int_lock, flags); 1412 smsc9420_pci_flush_write(pd); 1413 1414 timeout = 1000; 1415 while (timeout--) { 1416 if (pd->software_irq_signal) 1417 break; 1418 msleep(1); 1419 } 1420 1421 /* disable interrupts */ 1422 spin_lock_irqsave(&pd->int_lock, flags); 1423 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 1424 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1425 spin_unlock_irqrestore(&pd->int_lock, flags); 1426 1427 if (!pd->software_irq_signal) { 1428 smsc_warn(IFUP, "ISR failed signaling test"); 1429 result = -ENODEV; 1430 goto out_free_irq_1; 1431 } 1432 1433 smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq); 1434 1435 result = smsc9420_alloc_tx_ring(pd); 1436 if (result) { 1437 smsc_warn(IFUP, "Failed to Initialize tx dma ring"); 1438 result = -ENOMEM; 1439 goto out_free_irq_1; 1440 } 1441 1442 result = smsc9420_alloc_rx_ring(pd); 1443 if (result) { 1444 smsc_warn(IFUP, "Failed to Initialize rx dma ring"); 1445 result = -ENOMEM; 1446 goto out_free_tx_ring_2; 1447 } 1448 1449 result = smsc9420_mii_init(dev); 1450 if (result) { 1451 smsc_warn(IFUP, "Failed to initialize Phy"); 1452 result = -ENODEV; 1453 goto out_free_rx_ring_3; 1454 } 1455 1456 /* Bring the PHY up */ 1457 phy_start(pd->phy_dev); 1458 1459 napi_enable(&pd->napi); 1460 1461 /* start tx and rx */ 1462 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_; 1463 smsc9420_reg_write(pd, MAC_CR, mac_cr); 1464 1465 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL); 1466 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_; 1467 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control); 1468 smsc9420_pci_flush_write(pd); 1469 1470 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA); 1471 dma_intr_ena |= 1472 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_); 1473 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena); 1474 smsc9420_pci_flush_write(pd); 1475 1476 netif_wake_queue(dev); 1477 1478 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1); 1479 1480 /* enable interrupts */ 1481 spin_lock_irqsave(&pd->int_lock, flags); 1482 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_; 1483 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1484 spin_unlock_irqrestore(&pd->int_lock, flags); 1485 1486 return 0; 1487 1488out_free_rx_ring_3: 1489 smsc9420_free_rx_ring(pd); 1490out_free_tx_ring_2: 1491 smsc9420_free_tx_ring(pd); 1492out_free_irq_1: 1493 free_irq(dev->irq, pd); 1494out_0: 1495 return result; 1496} 1497 1498#ifdef CONFIG_PM 1499 1500static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state) 1501{ 1502 struct net_device *dev = pci_get_drvdata(pdev); 1503 struct smsc9420_pdata *pd = netdev_priv(dev); 1504 u32 int_cfg; 1505 ulong flags; 1506 1507 /* disable interrupts */ 1508 spin_lock_irqsave(&pd->int_lock, flags); 1509 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_); 1510 smsc9420_reg_write(pd, INT_CFG, int_cfg); 1511 spin_unlock_irqrestore(&pd->int_lock, flags); 1512 1513 if (netif_running(dev)) { 1514 netif_tx_disable(dev); 1515 smsc9420_stop_tx(pd); 1516 smsc9420_free_tx_ring(pd); 1517 1518 napi_disable(&pd->napi); 1519 smsc9420_stop_rx(pd); 1520 smsc9420_free_rx_ring(pd); 1521 1522 free_irq(dev->irq, pd); 1523 1524 netif_device_detach(dev); 1525 } 1526 1527 pci_save_state(pdev); 1528 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); 1529 pci_disable_device(pdev); 1530 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1531 1532 return 0; 1533} 1534 1535static int smsc9420_resume(struct pci_dev *pdev) 1536{ 1537 struct net_device *dev = pci_get_drvdata(pdev); 1538 struct smsc9420_pdata *pd = netdev_priv(dev); 1539 int err; 1540 1541 pci_set_power_state(pdev, PCI_D0); 1542 pci_restore_state(pdev); 1543 1544 err = pci_enable_device(pdev); 1545 if (err) 1546 return err; 1547 1548 pci_set_master(pdev); 1549 1550 err = pci_enable_wake(pdev, 0, 0); 1551 if (err) 1552 smsc_warn(IFUP, "pci_enable_wake failed: %d", err); 1553 1554 if (netif_running(dev)) { 1555 err = smsc9420_open(dev); 1556 netif_device_attach(dev); 1557 } 1558 return err; 1559} 1560 1561#endif /* CONFIG_PM */ 1562 1563static const struct net_device_ops smsc9420_netdev_ops = { 1564 .ndo_open = smsc9420_open, 1565 .ndo_stop = smsc9420_stop, 1566 .ndo_start_xmit = smsc9420_hard_start_xmit, 1567 .ndo_get_stats = smsc9420_get_stats, 1568 .ndo_set_rx_mode = smsc9420_set_multicast_list, 1569 .ndo_do_ioctl = smsc9420_do_ioctl, 1570 .ndo_validate_addr = eth_validate_addr, 1571 .ndo_set_mac_address = eth_mac_addr, 1572#ifdef CONFIG_NET_POLL_CONTROLLER 1573 .ndo_poll_controller = smsc9420_poll_controller, 1574#endif /* CONFIG_NET_POLL_CONTROLLER */ 1575}; 1576 1577static int __devinit 1578smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1579{ 1580 struct net_device *dev; 1581 struct smsc9420_pdata *pd; 1582 void __iomem *virt_addr; 1583 int result = 0; 1584 u32 id_rev; 1585 1586 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n"); 1587 1588 /* First do the PCI initialisation */ 1589 result = pci_enable_device(pdev); 1590 if (unlikely(result)) { 1591 printk(KERN_ERR "Cannot enable smsc9420\n"); 1592 goto out_0; 1593 } 1594 1595 pci_set_master(pdev); 1596 1597 dev = alloc_etherdev(sizeof(*pd)); 1598 if (!dev) 1599 goto out_disable_pci_device_1; 1600 1601 SET_NETDEV_DEV(dev, &pdev->dev); 1602 1603 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) { 1604 printk(KERN_ERR "Cannot find PCI device base address\n"); 1605 goto out_free_netdev_2; 1606 } 1607 1608 if ((pci_request_regions(pdev, DRV_NAME))) { 1609 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n"); 1610 goto out_free_netdev_2; 1611 } 1612 1613 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 1614 printk(KERN_ERR "No usable DMA configuration, aborting.\n"); 1615 goto out_free_regions_3; 1616 } 1617 1618 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR), 1619 pci_resource_len(pdev, SMSC_BAR)); 1620 if (!virt_addr) { 1621 printk(KERN_ERR "Cannot map device registers, aborting.\n"); 1622 goto out_free_regions_3; 1623 } 1624 1625 /* registers are double mapped with 0 offset for LE and 0x200 for BE */ 1626 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET; 1627 1628 dev->base_addr = (ulong)virt_addr; 1629 1630 pd = netdev_priv(dev); 1631 1632 /* pci descriptors are created in the PCI consistent area */ 1633 pd->rx_ring = pci_alloc_consistent(pdev, 1634 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE + 1635 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE, 1636 &pd->rx_dma_addr); 1637 1638 if (!pd->rx_ring) 1639 goto out_free_io_4; 1640 1641 /* descriptors are aligned due to the nature of pci_alloc_consistent */ 1642 pd->tx_ring = (struct smsc9420_dma_desc *) 1643 (pd->rx_ring + RX_RING_SIZE); 1644 pd->tx_dma_addr = pd->rx_dma_addr + 1645 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE; 1646 1647 pd->pdev = pdev; 1648 pd->dev = dev; 1649 pd->base_addr = virt_addr; 1650 pd->msg_enable = smsc_debug; 1651 pd->rx_csum = true; 1652 1653 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr); 1654 1655 id_rev = smsc9420_reg_read(pd, ID_REV); 1656 switch (id_rev & 0xFFFF0000) { 1657 case 0x94200000: 1658 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev); 1659 break; 1660 default: 1661 smsc_warn(PROBE, "LAN9420 NOT identified"); 1662 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev); 1663 goto out_free_dmadesc_5; 1664 } 1665 1666 smsc9420_dmac_soft_reset(pd); 1667 smsc9420_eeprom_reload(pd); 1668 smsc9420_check_mac_address(dev); 1669 1670 dev->netdev_ops = &smsc9420_netdev_ops; 1671 dev->ethtool_ops = &smsc9420_ethtool_ops; 1672 dev->irq = pdev->irq; 1673 1674 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT); 1675 1676 result = register_netdev(dev); 1677 if (result) { 1678 smsc_warn(PROBE, "error %i registering device", result); 1679 goto out_free_dmadesc_5; 1680 } 1681 1682 pci_set_drvdata(pdev, dev); 1683 1684 spin_lock_init(&pd->int_lock); 1685 spin_lock_init(&pd->phy_lock); 1686 1687 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr); 1688 1689 return 0; 1690 1691out_free_dmadesc_5: 1692 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) * 1693 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr); 1694out_free_io_4: 1695 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET); 1696out_free_regions_3: 1697 pci_release_regions(pdev); 1698out_free_netdev_2: 1699 free_netdev(dev); 1700out_disable_pci_device_1: 1701 pci_disable_device(pdev); 1702out_0: 1703 return -ENODEV; 1704} 1705 1706static void __devexit smsc9420_remove(struct pci_dev *pdev) 1707{ 1708 struct net_device *dev; 1709 struct smsc9420_pdata *pd; 1710 1711 dev = pci_get_drvdata(pdev); 1712 if (!dev) 1713 return; 1714 1715 pci_set_drvdata(pdev, NULL); 1716 1717 pd = netdev_priv(dev); 1718 unregister_netdev(dev); 1719 1720 /* tx_buffers and rx_buffers are freed in stop */ 1721 BUG_ON(pd->tx_buffers); 1722 BUG_ON(pd->rx_buffers); 1723 1724 BUG_ON(!pd->tx_ring); 1725 BUG_ON(!pd->rx_ring); 1726 1727 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) * 1728 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr); 1729 1730 iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET); 1731 pci_release_regions(pdev); 1732 free_netdev(dev); 1733 pci_disable_device(pdev); 1734} 1735 1736static struct pci_driver smsc9420_driver = { 1737 .name = DRV_NAME, 1738 .id_table = smsc9420_id_table, 1739 .probe = smsc9420_probe, 1740 .remove = __devexit_p(smsc9420_remove), 1741#ifdef CONFIG_PM 1742 .suspend = smsc9420_suspend, 1743 .resume = smsc9420_resume, 1744#endif /* CONFIG_PM */ 1745}; 1746 1747static int __init smsc9420_init_module(void) 1748{ 1749 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT); 1750 1751 return pci_register_driver(&smsc9420_driver); 1752} 1753 1754static void __exit smsc9420_exit_module(void) 1755{ 1756 pci_unregister_driver(&smsc9420_driver); 1757} 1758 1759module_init(smsc9420_init_module); 1760module_exit(smsc9420_exit_module); 1761