1/******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29*******************************************************************************/ 30 31#include <linux/kernel.h> 32#include <linux/interrupt.h> 33#include <linux/ip.h> 34#include <linux/tcp.h> 35#include <linux/skbuff.h> 36#include <linux/ethtool.h> 37#include <linux/if_ether.h> 38#include <linux/crc32.h> 39#include <linux/mii.h> 40#include <linux/if.h> 41#include <linux/if_vlan.h> 42#include <linux/dma-mapping.h> 43#include <linux/slab.h> 44#include <linux/prefetch.h> 45#ifdef CONFIG_STMMAC_DEBUG_FS 46#include <linux/debugfs.h> 47#include <linux/seq_file.h> 48#endif 49#include "stmmac.h" 50 51#undef STMMAC_DEBUG 52/*#define STMMAC_DEBUG*/ 53#ifdef STMMAC_DEBUG 54#define DBG(nlevel, klevel, fmt, args...) \ 55 ((void)(netif_msg_##nlevel(priv) && \ 56 printk(KERN_##klevel fmt, ## args))) 57#else 58#define DBG(nlevel, klevel, fmt, args...) do { } while (0) 59#endif 60 61#undef STMMAC_RX_DEBUG 62/*#define STMMAC_RX_DEBUG*/ 63#ifdef STMMAC_RX_DEBUG 64#define RX_DBG(fmt, args...) printk(fmt, ## args) 65#else 66#define RX_DBG(fmt, args...) do { } while (0) 67#endif 68 69#undef STMMAC_XMIT_DEBUG 70/*#define STMMAC_XMIT_DEBUG*/ 71#ifdef STMMAC_TX_DEBUG 72#define TX_DBG(fmt, args...) printk(fmt, ## args) 73#else 74#define TX_DBG(fmt, args...) do { } while (0) 75#endif 76 77#define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 78#define JUMBO_LEN 9000 79 80/* Module parameters */ 81#define TX_TIMEO 5000 /* default 5 seconds */ 82static int watchdog = TX_TIMEO; 83module_param(watchdog, int, S_IRUGO | S_IWUSR); 84MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds"); 85 86static int debug = -1; /* -1: default, 0: no output, 16: all */ 87module_param(debug, int, S_IRUGO | S_IWUSR); 88MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)"); 89 90int phyaddr = -1; 91module_param(phyaddr, int, S_IRUGO); 92MODULE_PARM_DESC(phyaddr, "Physical device address"); 93 94#define DMA_TX_SIZE 256 95static int dma_txsize = DMA_TX_SIZE; 96module_param(dma_txsize, int, S_IRUGO | S_IWUSR); 97MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); 98 99#define DMA_RX_SIZE 256 100static int dma_rxsize = DMA_RX_SIZE; 101module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); 102MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); 103 104static int flow_ctrl = FLOW_OFF; 105module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 106MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 107 108static int pause = PAUSE_TIME; 109module_param(pause, int, S_IRUGO | S_IWUSR); 110MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 111 112#define TC_DEFAULT 64 113static int tc = TC_DEFAULT; 114module_param(tc, int, S_IRUGO | S_IWUSR); 115MODULE_PARM_DESC(tc, "DMA threshold control value"); 116 117/* Pay attention to tune this parameter; take care of both 118 * hardware capability and network stabitily/performance impact. 119 * Many tests showed that ~4ms latency seems to be good enough. */ 120#ifdef CONFIG_STMMAC_TIMER 121#define DEFAULT_PERIODIC_RATE 256 122static int tmrate = DEFAULT_PERIODIC_RATE; 123module_param(tmrate, int, S_IRUGO | S_IWUSR); 124MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)"); 125#endif 126 127#define DMA_BUFFER_SIZE BUF_SIZE_2KiB 128static int buf_sz = DMA_BUFFER_SIZE; 129module_param(buf_sz, int, S_IRUGO | S_IWUSR); 130MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 131 132static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 133 NETIF_MSG_LINK | NETIF_MSG_IFUP | 134 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 135 136static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 137 138#ifdef CONFIG_STMMAC_DEBUG_FS 139static int stmmac_init_fs(struct net_device *dev); 140static void stmmac_exit_fs(void); 141#endif 142 143/** 144 * stmmac_verify_args - verify the driver parameters. 145 * Description: it verifies if some wrong parameter is passed to the driver. 146 * Note that wrong parameters are replaced with the default values. 147 */ 148static void stmmac_verify_args(void) 149{ 150 if (unlikely(watchdog < 0)) 151 watchdog = TX_TIMEO; 152 if (unlikely(dma_rxsize < 0)) 153 dma_rxsize = DMA_RX_SIZE; 154 if (unlikely(dma_txsize < 0)) 155 dma_txsize = DMA_TX_SIZE; 156 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) 157 buf_sz = DMA_BUFFER_SIZE; 158 if (unlikely(flow_ctrl > 1)) 159 flow_ctrl = FLOW_AUTO; 160 else if (likely(flow_ctrl < 0)) 161 flow_ctrl = FLOW_OFF; 162 if (unlikely((pause < 0) || (pause > 0xffff))) 163 pause = PAUSE_TIME; 164} 165 166#if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG) 167static void print_pkt(unsigned char *buf, int len) 168{ 169 int j; 170 pr_info("len = %d byte, buf addr: 0x%p", len, buf); 171 for (j = 0; j < len; j++) { 172 if ((j % 16) == 0) 173 pr_info("\n %03x:", j); 174 pr_info(" %02x", buf[j]); 175 } 176 pr_info("\n"); 177} 178#endif 179 180/* minimum number of free TX descriptors required to wake up TX process */ 181#define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) 182 183static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 184{ 185 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; 186} 187 188/* On some ST platforms, some HW system configuraton registers have to be 189 * set according to the link speed negotiated. 190 */ 191static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 192{ 193 struct phy_device *phydev = priv->phydev; 194 195 if (likely(priv->plat->fix_mac_speed)) 196 priv->plat->fix_mac_speed(priv->plat->bsp_priv, 197 phydev->speed); 198} 199 200/** 201 * stmmac_adjust_link 202 * @dev: net device structure 203 * Description: it adjusts the link parameters. 204 */ 205static void stmmac_adjust_link(struct net_device *dev) 206{ 207 struct stmmac_priv *priv = netdev_priv(dev); 208 struct phy_device *phydev = priv->phydev; 209 unsigned long flags; 210 int new_state = 0; 211 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 212 213 if (phydev == NULL) 214 return; 215 216 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n", 217 phydev->addr, phydev->link); 218 219 spin_lock_irqsave(&priv->lock, flags); 220 if (phydev->link) { 221 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 222 223 /* Now we make sure that we can be in full duplex mode. 224 * If not, we operate in half-duplex mode. */ 225 if (phydev->duplex != priv->oldduplex) { 226 new_state = 1; 227 if (!(phydev->duplex)) 228 ctrl &= ~priv->hw->link.duplex; 229 else 230 ctrl |= priv->hw->link.duplex; 231 priv->oldduplex = phydev->duplex; 232 } 233 /* Flow Control operation */ 234 if (phydev->pause) 235 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, 236 fc, pause_time); 237 238 if (phydev->speed != priv->speed) { 239 new_state = 1; 240 switch (phydev->speed) { 241 case 1000: 242 if (likely(priv->plat->has_gmac)) 243 ctrl &= ~priv->hw->link.port; 244 stmmac_hw_fix_mac_speed(priv); 245 break; 246 case 100: 247 case 10: 248 if (priv->plat->has_gmac) { 249 ctrl |= priv->hw->link.port; 250 if (phydev->speed == SPEED_100) { 251 ctrl |= priv->hw->link.speed; 252 } else { 253 ctrl &= ~(priv->hw->link.speed); 254 } 255 } else { 256 ctrl &= ~priv->hw->link.port; 257 } 258 stmmac_hw_fix_mac_speed(priv); 259 break; 260 default: 261 if (netif_msg_link(priv)) 262 pr_warning("%s: Speed (%d) is not 10" 263 " or 100!\n", dev->name, phydev->speed); 264 break; 265 } 266 267 priv->speed = phydev->speed; 268 } 269 270 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 271 272 if (!priv->oldlink) { 273 new_state = 1; 274 priv->oldlink = 1; 275 } 276 } else if (priv->oldlink) { 277 new_state = 1; 278 priv->oldlink = 0; 279 priv->speed = 0; 280 priv->oldduplex = -1; 281 } 282 283 if (new_state && netif_msg_link(priv)) 284 phy_print_status(phydev); 285 286 spin_unlock_irqrestore(&priv->lock, flags); 287 288 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n"); 289} 290 291/** 292 * stmmac_init_phy - PHY initialization 293 * @dev: net device structure 294 * Description: it initializes the driver's PHY state, and attaches the PHY 295 * to the mac driver. 296 * Return value: 297 * 0 on success 298 */ 299static int stmmac_init_phy(struct net_device *dev) 300{ 301 struct stmmac_priv *priv = netdev_priv(dev); 302 struct phy_device *phydev; 303 char phy_id[MII_BUS_ID_SIZE + 3]; 304 char bus_id[MII_BUS_ID_SIZE]; 305 int interface = priv->plat->interface; 306 priv->oldlink = 0; 307 priv->speed = 0; 308 priv->oldduplex = -1; 309 310 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", priv->plat->bus_id); 311 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 312 priv->plat->phy_addr); 313 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id); 314 315 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface); 316 317 if (IS_ERR(phydev)) { 318 pr_err("%s: Could not attach to PHY\n", dev->name); 319 return PTR_ERR(phydev); 320 } 321 322 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 323 if ((interface == PHY_INTERFACE_MODE_MII) || 324 (interface == PHY_INTERFACE_MODE_RMII)) 325 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 326 SUPPORTED_1000baseT_Full); 327 328 /* 329 * Broken HW is sometimes missing the pull-up resistor on the 330 * MDIO line, which results in reads to non-existent devices returning 331 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 332 * device as well. 333 * Note: phydev->phy_id is the result of reading the UID PHY registers. 334 */ 335 if (phydev->phy_id == 0) { 336 phy_disconnect(phydev); 337 return -ENODEV; 338 } 339 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 340 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 341 342 priv->phydev = phydev; 343 344 return 0; 345} 346 347/** 348 * display_ring 349 * @p: pointer to the ring. 350 * @size: size of the ring. 351 * Description: display all the descriptors within the ring. 352 */ 353static void display_ring(struct dma_desc *p, int size) 354{ 355 struct tmp_s { 356 u64 a; 357 unsigned int b; 358 unsigned int c; 359 }; 360 int i; 361 for (i = 0; i < size; i++) { 362 struct tmp_s *x = (struct tmp_s *)(p + i); 363 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", 364 i, (unsigned int)virt_to_phys(&p[i]), 365 (unsigned int)(x->a), (unsigned int)((x->a) >> 32), 366 x->b, x->c); 367 pr_info("\n"); 368 } 369} 370 371static int stmmac_set_bfsize(int mtu, int bufsize) 372{ 373 int ret = bufsize; 374 375 if (mtu >= BUF_SIZE_4KiB) 376 ret = BUF_SIZE_8KiB; 377 else if (mtu >= BUF_SIZE_2KiB) 378 ret = BUF_SIZE_4KiB; 379 else if (mtu >= DMA_BUFFER_SIZE) 380 ret = BUF_SIZE_2KiB; 381 else 382 ret = DMA_BUFFER_SIZE; 383 384 return ret; 385} 386 387/** 388 * init_dma_desc_rings - init the RX/TX descriptor rings 389 * @dev: net device structure 390 * Description: this function initializes the DMA RX/TX descriptors 391 * and allocates the socket buffers. It suppors the chained and ring 392 * modes. 393 */ 394static void init_dma_desc_rings(struct net_device *dev) 395{ 396 int i; 397 struct stmmac_priv *priv = netdev_priv(dev); 398 struct sk_buff *skb; 399 unsigned int txsize = priv->dma_tx_size; 400 unsigned int rxsize = priv->dma_rx_size; 401 unsigned int bfsize; 402 int dis_ic = 0; 403 int des3_as_data_buf = 0; 404 405 /* Set the max buffer size according to the DESC mode 406 * and the MTU. Note that RING mode allows 16KiB bsize. */ 407 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu); 408 409 if (bfsize == BUF_SIZE_16KiB) 410 des3_as_data_buf = 1; 411 else 412 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 413 414#ifdef CONFIG_STMMAC_TIMER 415 /* Disable interrupts on completion for the reception if timer is on */ 416 if (likely(priv->tm->enable)) 417 dis_ic = 1; 418#endif 419 420 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n", 421 txsize, rxsize, bfsize); 422 423 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL); 424 priv->rx_skbuff = 425 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL); 426 priv->dma_rx = 427 (struct dma_desc *)dma_alloc_coherent(priv->device, 428 rxsize * 429 sizeof(struct dma_desc), 430 &priv->dma_rx_phy, 431 GFP_KERNEL); 432 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize, 433 GFP_KERNEL); 434 priv->dma_tx = 435 (struct dma_desc *)dma_alloc_coherent(priv->device, 436 txsize * 437 sizeof(struct dma_desc), 438 &priv->dma_tx_phy, 439 GFP_KERNEL); 440 441 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) { 442 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__); 443 return; 444 } 445 446 DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, " 447 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", 448 dev->name, priv->dma_rx, priv->dma_tx, 449 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); 450 451 /* RX INITIALIZATION */ 452 DBG(probe, INFO, "stmmac: SKB addresses:\n" 453 "skb\t\tskb data\tdma data\n"); 454 455 for (i = 0; i < rxsize; i++) { 456 struct dma_desc *p = priv->dma_rx + i; 457 458 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN, 459 GFP_KERNEL); 460 if (unlikely(skb == NULL)) { 461 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 462 break; 463 } 464 skb_reserve(skb, NET_IP_ALIGN); 465 priv->rx_skbuff[i] = skb; 466 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 467 bfsize, DMA_FROM_DEVICE); 468 469 p->des2 = priv->rx_skbuff_dma[i]; 470 471 priv->hw->ring->init_desc3(des3_as_data_buf, p); 472 473 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 474 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]); 475 } 476 priv->cur_rx = 0; 477 priv->dirty_rx = (unsigned int)(i - rxsize); 478 priv->dma_buf_sz = bfsize; 479 buf_sz = bfsize; 480 481 /* TX INITIALIZATION */ 482 for (i = 0; i < txsize; i++) { 483 priv->tx_skbuff[i] = NULL; 484 priv->dma_tx[i].des2 = 0; 485 } 486 487 /* In case of Chained mode this sets the des3 to the next 488 * element in the chain */ 489 priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize); 490 priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize); 491 492 priv->dirty_tx = 0; 493 priv->cur_tx = 0; 494 495 /* Clear the Rx/Tx descriptors */ 496 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic); 497 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize); 498 499 if (netif_msg_hw(priv)) { 500 pr_info("RX descriptor ring:\n"); 501 display_ring(priv->dma_rx, rxsize); 502 pr_info("TX descriptor ring:\n"); 503 display_ring(priv->dma_tx, txsize); 504 } 505} 506 507static void dma_free_rx_skbufs(struct stmmac_priv *priv) 508{ 509 int i; 510 511 for (i = 0; i < priv->dma_rx_size; i++) { 512 if (priv->rx_skbuff[i]) { 513 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 514 priv->dma_buf_sz, DMA_FROM_DEVICE); 515 dev_kfree_skb_any(priv->rx_skbuff[i]); 516 } 517 priv->rx_skbuff[i] = NULL; 518 } 519} 520 521static void dma_free_tx_skbufs(struct stmmac_priv *priv) 522{ 523 int i; 524 525 for (i = 0; i < priv->dma_tx_size; i++) { 526 if (priv->tx_skbuff[i] != NULL) { 527 struct dma_desc *p = priv->dma_tx + i; 528 if (p->des2) 529 dma_unmap_single(priv->device, p->des2, 530 priv->hw->desc->get_tx_len(p), 531 DMA_TO_DEVICE); 532 dev_kfree_skb_any(priv->tx_skbuff[i]); 533 priv->tx_skbuff[i] = NULL; 534 } 535 } 536} 537 538static void free_dma_desc_resources(struct stmmac_priv *priv) 539{ 540 /* Release the DMA TX/RX socket buffers */ 541 dma_free_rx_skbufs(priv); 542 dma_free_tx_skbufs(priv); 543 544 /* Free the region of consistent memory previously allocated for 545 * the DMA */ 546 dma_free_coherent(priv->device, 547 priv->dma_tx_size * sizeof(struct dma_desc), 548 priv->dma_tx, priv->dma_tx_phy); 549 dma_free_coherent(priv->device, 550 priv->dma_rx_size * sizeof(struct dma_desc), 551 priv->dma_rx, priv->dma_rx_phy); 552 kfree(priv->rx_skbuff_dma); 553 kfree(priv->rx_skbuff); 554 kfree(priv->tx_skbuff); 555} 556 557/** 558 * stmmac_dma_operation_mode - HW DMA operation mode 559 * @priv : pointer to the private device structure. 560 * Description: it sets the DMA operation mode: tx/rx DMA thresholds 561 * or Store-And-Forward capability. 562 */ 563static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 564{ 565 if (likely(priv->plat->force_sf_dma_mode || 566 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) { 567 /* 568 * In case of GMAC, SF mode can be enabled 569 * to perform the TX COE in HW. This depends on: 570 * 1) TX COE if actually supported 571 * 2) There is no bugged Jumbo frame support 572 * that needs to not insert csum in the TDES. 573 */ 574 priv->hw->dma->dma_mode(priv->ioaddr, 575 SF_DMA_MODE, SF_DMA_MODE); 576 tc = SF_DMA_MODE; 577 } else 578 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 579} 580 581/** 582 * stmmac_tx: 583 * @priv: private driver structure 584 * Description: it reclaims resources after transmission completes. 585 */ 586static void stmmac_tx(struct stmmac_priv *priv) 587{ 588 unsigned int txsize = priv->dma_tx_size; 589 590 spin_lock(&priv->tx_lock); 591 592 while (priv->dirty_tx != priv->cur_tx) { 593 int last; 594 unsigned int entry = priv->dirty_tx % txsize; 595 struct sk_buff *skb = priv->tx_skbuff[entry]; 596 struct dma_desc *p = priv->dma_tx + entry; 597 598 /* Check if the descriptor is owned by the DMA. */ 599 if (priv->hw->desc->get_tx_owner(p)) 600 break; 601 602 /* Verify tx error by looking at the last segment */ 603 last = priv->hw->desc->get_tx_ls(p); 604 if (likely(last)) { 605 int tx_error = 606 priv->hw->desc->tx_status(&priv->dev->stats, 607 &priv->xstats, p, 608 priv->ioaddr); 609 if (likely(tx_error == 0)) { 610 priv->dev->stats.tx_packets++; 611 priv->xstats.tx_pkt_n++; 612 } else 613 priv->dev->stats.tx_errors++; 614 } 615 TX_DBG("%s: curr %d, dirty %d\n", __func__, 616 priv->cur_tx, priv->dirty_tx); 617 618 if (likely(p->des2)) 619 dma_unmap_single(priv->device, p->des2, 620 priv->hw->desc->get_tx_len(p), 621 DMA_TO_DEVICE); 622 priv->hw->ring->clean_desc3(p); 623 624 if (likely(skb != NULL)) { 625 /* 626 * If there's room in the queue (limit it to size) 627 * we add this skb back into the pool, 628 * if it's the right size. 629 */ 630 if ((skb_queue_len(&priv->rx_recycle) < 631 priv->dma_rx_size) && 632 skb_recycle_check(skb, priv->dma_buf_sz)) 633 __skb_queue_head(&priv->rx_recycle, skb); 634 else 635 dev_kfree_skb(skb); 636 637 priv->tx_skbuff[entry] = NULL; 638 } 639 640 priv->hw->desc->release_tx_desc(p); 641 642 entry = (++priv->dirty_tx) % txsize; 643 } 644 if (unlikely(netif_queue_stopped(priv->dev) && 645 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { 646 netif_tx_lock(priv->dev); 647 if (netif_queue_stopped(priv->dev) && 648 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { 649 TX_DBG("%s: restart transmit\n", __func__); 650 netif_wake_queue(priv->dev); 651 } 652 netif_tx_unlock(priv->dev); 653 } 654 spin_unlock(&priv->tx_lock); 655} 656 657static inline void stmmac_enable_irq(struct stmmac_priv *priv) 658{ 659#ifdef CONFIG_STMMAC_TIMER 660 if (likely(priv->tm->enable)) 661 priv->tm->timer_start(tmrate); 662 else 663#endif 664 priv->hw->dma->enable_dma_irq(priv->ioaddr); 665} 666 667static inline void stmmac_disable_irq(struct stmmac_priv *priv) 668{ 669#ifdef CONFIG_STMMAC_TIMER 670 if (likely(priv->tm->enable)) 671 priv->tm->timer_stop(); 672 else 673#endif 674 priv->hw->dma->disable_dma_irq(priv->ioaddr); 675} 676 677static int stmmac_has_work(struct stmmac_priv *priv) 678{ 679 unsigned int has_work = 0; 680 int rxret, tx_work = 0; 681 682 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx + 683 (priv->cur_rx % priv->dma_rx_size)); 684 685 if (priv->dirty_tx != priv->cur_tx) 686 tx_work = 1; 687 688 if (likely(!rxret || tx_work)) 689 has_work = 1; 690 691 return has_work; 692} 693 694static inline void _stmmac_schedule(struct stmmac_priv *priv) 695{ 696 if (likely(stmmac_has_work(priv))) { 697 stmmac_disable_irq(priv); 698 napi_schedule(&priv->napi); 699 } 700} 701 702#ifdef CONFIG_STMMAC_TIMER 703void stmmac_schedule(struct net_device *dev) 704{ 705 struct stmmac_priv *priv = netdev_priv(dev); 706 707 priv->xstats.sched_timer_n++; 708 709 _stmmac_schedule(priv); 710} 711 712static void stmmac_no_timer_started(unsigned int x) 713{; 714}; 715 716static void stmmac_no_timer_stopped(void) 717{; 718}; 719#endif 720 721/** 722 * stmmac_tx_err: 723 * @priv: pointer to the private device structure 724 * Description: it cleans the descriptors and restarts the transmission 725 * in case of errors. 726 */ 727static void stmmac_tx_err(struct stmmac_priv *priv) 728{ 729 netif_stop_queue(priv->dev); 730 731 priv->hw->dma->stop_tx(priv->ioaddr); 732 dma_free_tx_skbufs(priv); 733 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); 734 priv->dirty_tx = 0; 735 priv->cur_tx = 0; 736 priv->hw->dma->start_tx(priv->ioaddr); 737 738 priv->dev->stats.tx_errors++; 739 netif_wake_queue(priv->dev); 740} 741 742 743static void stmmac_dma_interrupt(struct stmmac_priv *priv) 744{ 745 int status; 746 747 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 748 if (likely(status == handle_tx_rx)) 749 _stmmac_schedule(priv); 750 751 else if (unlikely(status == tx_hard_error_bump_tc)) { 752 /* Try to bump up the dma threshold on this failure */ 753 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { 754 tc += 64; 755 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 756 priv->xstats.threshold = tc; 757 } 758 } else if (unlikely(status == tx_hard_error)) 759 stmmac_tx_err(priv); 760} 761 762static void stmmac_mmc_setup(struct stmmac_priv *priv) 763{ 764 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 765 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 766 767 /* Mask MMC irq, counters are managed in SW and registers 768 * are cleared on each READ eventually. */ 769 dwmac_mmc_intr_all_mask(priv->ioaddr); 770 771 if (priv->dma_cap.rmon) { 772 dwmac_mmc_ctrl(priv->ioaddr, mode); 773 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 774 } else 775 pr_info(" No MAC Management Counters available\n"); 776} 777 778static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) 779{ 780 u32 hwid = priv->hw->synopsys_uid; 781 782 /* Only check valid Synopsys Id because old MAC chips 783 * have no HW registers where get the ID */ 784 if (likely(hwid)) { 785 u32 uid = ((hwid & 0x0000ff00) >> 8); 786 u32 synid = (hwid & 0x000000ff); 787 788 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", 789 uid, synid); 790 791 return synid; 792 } 793 return 0; 794} 795 796/** 797 * stmmac_selec_desc_mode 798 * @dev : device pointer 799 * Description: select the Enhanced/Alternate or Normal descriptors */ 800static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 801{ 802 if (priv->plat->enh_desc) { 803 pr_info(" Enhanced/Alternate descriptors\n"); 804 priv->hw->desc = &enh_desc_ops; 805 } else { 806 pr_info(" Normal descriptors\n"); 807 priv->hw->desc = &ndesc_ops; 808 } 809} 810 811/** 812 * stmmac_get_hw_features 813 * @priv : private device pointer 814 * Description: 815 * new GMAC chip generations have a new register to indicate the 816 * presence of the optional feature/functions. 817 * This can be also used to override the value passed through the 818 * platform and necessary for old MAC10/100 and GMAC chips. 819 */ 820static int stmmac_get_hw_features(struct stmmac_priv *priv) 821{ 822 u32 hw_cap = 0; 823 824 if (priv->hw->dma->get_hw_feature) { 825 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); 826 827 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); 828 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; 829 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; 830 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; 831 priv->dma_cap.multi_addr = 832 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5; 833 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; 834 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; 835 priv->dma_cap.pmt_remote_wake_up = 836 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; 837 priv->dma_cap.pmt_magic_frame = 838 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; 839 /* MMC */ 840 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; 841 /* IEEE 1588-2002*/ 842 priv->dma_cap.time_stamp = 843 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; 844 /* IEEE 1588-2008*/ 845 priv->dma_cap.atime_stamp = 846 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; 847 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 848 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; 849 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; 850 /* TX and RX csum */ 851 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; 852 priv->dma_cap.rx_coe_type1 = 853 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; 854 priv->dma_cap.rx_coe_type2 = 855 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; 856 priv->dma_cap.rxfifo_over_2048 = 857 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; 858 /* TX and RX number of channels */ 859 priv->dma_cap.number_rx_channel = 860 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; 861 priv->dma_cap.number_tx_channel = 862 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; 863 /* Alternate (enhanced) DESC mode*/ 864 priv->dma_cap.enh_desc = 865 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; 866 867 } 868 869 return hw_cap; 870} 871 872static void stmmac_check_ether_addr(struct stmmac_priv *priv) 873{ 874 /* verify if the MAC address is valid, in case of failures it 875 * generates a random MAC address */ 876 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 877 priv->hw->mac->get_umac_addr((void __iomem *) 878 priv->dev->base_addr, 879 priv->dev->dev_addr, 0); 880 if (!is_valid_ether_addr(priv->dev->dev_addr)) 881 eth_hw_addr_random(priv->dev); 882 } 883 pr_warning("%s: device MAC address %pM\n", priv->dev->name, 884 priv->dev->dev_addr); 885} 886 887/** 888 * stmmac_open - open entry point of the driver 889 * @dev : pointer to the device structure. 890 * Description: 891 * This function is the open entry point of the driver. 892 * Return value: 893 * 0 on success and an appropriate (-)ve integer as defined in errno.h 894 * file on failure. 895 */ 896static int stmmac_open(struct net_device *dev) 897{ 898 struct stmmac_priv *priv = netdev_priv(dev); 899 int ret; 900 901 stmmac_check_ether_addr(priv); 902 903 /* MDIO bus Registration */ 904 ret = stmmac_mdio_register(dev); 905 if (ret < 0) { 906 pr_debug("%s: MDIO bus (id: %d) registration failed", 907 __func__, priv->plat->bus_id); 908 return ret; 909 } 910 911#ifdef CONFIG_STMMAC_TIMER 912 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL); 913 if (unlikely(priv->tm == NULL)) 914 return -ENOMEM; 915 916 priv->tm->freq = tmrate; 917 918 /* Test if the external timer can be actually used. 919 * In case of failure continue without timer. */ 920 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) { 921 pr_warning("stmmaceth: cannot attach the external timer.\n"); 922 priv->tm->freq = 0; 923 priv->tm->timer_start = stmmac_no_timer_started; 924 priv->tm->timer_stop = stmmac_no_timer_stopped; 925 } else 926 priv->tm->enable = 1; 927#endif 928 ret = stmmac_init_phy(dev); 929 if (unlikely(ret)) { 930 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret); 931 goto open_error; 932 } 933 934 /* Create and initialize the TX/RX descriptors chains. */ 935 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); 936 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); 937 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 938 init_dma_desc_rings(dev); 939 940 /* DMA initialization and SW reset */ 941 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl, 942 priv->dma_tx_phy, priv->dma_rx_phy); 943 if (ret < 0) { 944 pr_err("%s: DMA initialization failed\n", __func__); 945 goto open_error; 946 } 947 948 /* Copy the MAC addr into the HW */ 949 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); 950 951 /* If required, perform hw setup of the bus. */ 952 if (priv->plat->bus_setup) 953 priv->plat->bus_setup(priv->ioaddr); 954 955 /* Initialize the MAC Core */ 956 priv->hw->mac->core_init(priv->ioaddr); 957 958 /* Request the IRQ lines */ 959 ret = request_irq(dev->irq, stmmac_interrupt, 960 IRQF_SHARED, dev->name, dev); 961 if (unlikely(ret < 0)) { 962 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 963 __func__, dev->irq, ret); 964 goto open_error; 965 } 966 967 /* Request the Wake IRQ in case of another line is used for WoL */ 968 if (priv->wol_irq != dev->irq) { 969 ret = request_irq(priv->wol_irq, stmmac_interrupt, 970 IRQF_SHARED, dev->name, dev); 971 if (unlikely(ret < 0)) { 972 pr_err("%s: ERROR: allocating the ext WoL IRQ %d " 973 "(error: %d)\n", __func__, priv->wol_irq, ret); 974 goto open_error_wolirq; 975 } 976 } 977 978 /* Enable the MAC Rx/Tx */ 979 stmmac_set_mac(priv->ioaddr, true); 980 981 /* Set the HW DMA mode and the COE */ 982 stmmac_dma_operation_mode(priv); 983 984 /* Extra statistics */ 985 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 986 priv->xstats.threshold = tc; 987 988 stmmac_mmc_setup(priv); 989 990#ifdef CONFIG_STMMAC_DEBUG_FS 991 ret = stmmac_init_fs(dev); 992 if (ret < 0) 993 pr_warning("%s: failed debugFS registration\n", __func__); 994#endif 995 /* Start the ball rolling... */ 996 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); 997 priv->hw->dma->start_tx(priv->ioaddr); 998 priv->hw->dma->start_rx(priv->ioaddr); 999 1000#ifdef CONFIG_STMMAC_TIMER 1001 priv->tm->timer_start(tmrate); 1002#endif 1003 1004 /* Dump DMA/MAC registers */ 1005 if (netif_msg_hw(priv)) { 1006 priv->hw->mac->dump_regs(priv->ioaddr); 1007 priv->hw->dma->dump_regs(priv->ioaddr); 1008 } 1009 1010 if (priv->phydev) 1011 phy_start(priv->phydev); 1012 1013 napi_enable(&priv->napi); 1014 skb_queue_head_init(&priv->rx_recycle); 1015 netif_start_queue(dev); 1016 1017 return 0; 1018 1019open_error_wolirq: 1020 free_irq(dev->irq, dev); 1021 1022open_error: 1023#ifdef CONFIG_STMMAC_TIMER 1024 kfree(priv->tm); 1025#endif 1026 if (priv->phydev) 1027 phy_disconnect(priv->phydev); 1028 1029 return ret; 1030} 1031 1032/** 1033 * stmmac_release - close entry point of the driver 1034 * @dev : device pointer. 1035 * Description: 1036 * This is the stop entry point of the driver. 1037 */ 1038static int stmmac_release(struct net_device *dev) 1039{ 1040 struct stmmac_priv *priv = netdev_priv(dev); 1041 1042 /* Stop and disconnect the PHY */ 1043 if (priv->phydev) { 1044 phy_stop(priv->phydev); 1045 phy_disconnect(priv->phydev); 1046 priv->phydev = NULL; 1047 } 1048 1049 netif_stop_queue(dev); 1050 1051#ifdef CONFIG_STMMAC_TIMER 1052 /* Stop and release the timer */ 1053 stmmac_close_ext_timer(); 1054 if (priv->tm != NULL) 1055 kfree(priv->tm); 1056#endif 1057 napi_disable(&priv->napi); 1058 skb_queue_purge(&priv->rx_recycle); 1059 1060 /* Free the IRQ lines */ 1061 free_irq(dev->irq, dev); 1062 if (priv->wol_irq != dev->irq) 1063 free_irq(priv->wol_irq, dev); 1064 1065 /* Stop TX/RX DMA and clear the descriptors */ 1066 priv->hw->dma->stop_tx(priv->ioaddr); 1067 priv->hw->dma->stop_rx(priv->ioaddr); 1068 1069 /* Release and free the Rx/Tx resources */ 1070 free_dma_desc_resources(priv); 1071 1072 /* Disable the MAC Rx/Tx */ 1073 stmmac_set_mac(priv->ioaddr, false); 1074 1075 netif_carrier_off(dev); 1076 1077#ifdef CONFIG_STMMAC_DEBUG_FS 1078 stmmac_exit_fs(); 1079#endif 1080 stmmac_mdio_unregister(dev); 1081 1082 return 0; 1083} 1084 1085/** 1086 * stmmac_xmit: 1087 * @skb : the socket buffer 1088 * @dev : device pointer 1089 * Description : Tx entry point of the driver. 1090 */ 1091static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 1092{ 1093 struct stmmac_priv *priv = netdev_priv(dev); 1094 unsigned int txsize = priv->dma_tx_size; 1095 unsigned int entry; 1096 int i, csum_insertion = 0; 1097 int nfrags = skb_shinfo(skb)->nr_frags; 1098 struct dma_desc *desc, *first; 1099 unsigned int nopaged_len = skb_headlen(skb); 1100 1101 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 1102 if (!netif_queue_stopped(dev)) { 1103 netif_stop_queue(dev); 1104 /* This is a hard error, log it. */ 1105 pr_err("%s: BUG! Tx Ring full when queue awake\n", 1106 __func__); 1107 } 1108 return NETDEV_TX_BUSY; 1109 } 1110 1111 spin_lock(&priv->tx_lock); 1112 1113 entry = priv->cur_tx % txsize; 1114 1115#ifdef STMMAC_XMIT_DEBUG 1116 if ((skb->len > ETH_FRAME_LEN) || nfrags) 1117 pr_info("stmmac xmit:\n" 1118 "\tskb addr %p - len: %d - nopaged_len: %d\n" 1119 "\tn_frags: %d - ip_summed: %d - %s gso\n", 1120 skb, skb->len, nopaged_len, nfrags, skb->ip_summed, 1121 !skb_is_gso(skb) ? "isn't" : "is"); 1122#endif 1123 1124 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 1125 1126 desc = priv->dma_tx + entry; 1127 first = desc; 1128 1129#ifdef STMMAC_XMIT_DEBUG 1130 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN)) 1131 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n" 1132 "\t\tn_frags: %d, ip_summed: %d\n", 1133 skb->len, nopaged_len, nfrags, skb->ip_summed); 1134#endif 1135 priv->tx_skbuff[entry] = skb; 1136 1137 if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) { 1138 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion); 1139 desc = priv->dma_tx + entry; 1140 } else { 1141 desc->des2 = dma_map_single(priv->device, skb->data, 1142 nopaged_len, DMA_TO_DEVICE); 1143 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, 1144 csum_insertion); 1145 } 1146 1147 for (i = 0; i < nfrags; i++) { 1148 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1149 int len = skb_frag_size(frag); 1150 1151 entry = (++priv->cur_tx) % txsize; 1152 desc = priv->dma_tx + entry; 1153 1154 TX_DBG("\t[entry %d] segment len: %d\n", entry, len); 1155 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, 1156 DMA_TO_DEVICE); 1157 priv->tx_skbuff[entry] = NULL; 1158 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion); 1159 wmb(); 1160 priv->hw->desc->set_tx_owner(desc); 1161 } 1162 1163 /* Interrupt on completition only for the latest segment */ 1164 priv->hw->desc->close_tx_desc(desc); 1165 1166#ifdef CONFIG_STMMAC_TIMER 1167 /* Clean IC while using timer */ 1168 if (likely(priv->tm->enable)) 1169 priv->hw->desc->clear_tx_ic(desc); 1170#endif 1171 1172 wmb(); 1173 1174 /* To avoid raise condition */ 1175 priv->hw->desc->set_tx_owner(first); 1176 1177 priv->cur_tx++; 1178 1179#ifdef STMMAC_XMIT_DEBUG 1180 if (netif_msg_pktdata(priv)) { 1181 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, " 1182 "first=%p, nfrags=%d\n", 1183 (priv->cur_tx % txsize), (priv->dirty_tx % txsize), 1184 entry, first, nfrags); 1185 display_ring(priv->dma_tx, txsize); 1186 pr_info(">>> frame to be transmitted: "); 1187 print_pkt(skb->data, skb->len); 1188 } 1189#endif 1190 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 1191 TX_DBG("%s: stop transmitted packets\n", __func__); 1192 netif_stop_queue(dev); 1193 } 1194 1195 dev->stats.tx_bytes += skb->len; 1196 1197 skb_tx_timestamp(skb); 1198 1199 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 1200 1201 spin_unlock(&priv->tx_lock); 1202 1203 return NETDEV_TX_OK; 1204} 1205 1206static inline void stmmac_rx_refill(struct stmmac_priv *priv) 1207{ 1208 unsigned int rxsize = priv->dma_rx_size; 1209 int bfsize = priv->dma_buf_sz; 1210 struct dma_desc *p = priv->dma_rx; 1211 1212 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { 1213 unsigned int entry = priv->dirty_rx % rxsize; 1214 if (likely(priv->rx_skbuff[entry] == NULL)) { 1215 struct sk_buff *skb; 1216 1217 skb = __skb_dequeue(&priv->rx_recycle); 1218 if (skb == NULL) 1219 skb = netdev_alloc_skb_ip_align(priv->dev, 1220 bfsize); 1221 1222 if (unlikely(skb == NULL)) 1223 break; 1224 1225 priv->rx_skbuff[entry] = skb; 1226 priv->rx_skbuff_dma[entry] = 1227 dma_map_single(priv->device, skb->data, bfsize, 1228 DMA_FROM_DEVICE); 1229 1230 (p + entry)->des2 = priv->rx_skbuff_dma[entry]; 1231 1232 if (unlikely(priv->plat->has_gmac)) 1233 priv->hw->ring->refill_desc3(bfsize, p + entry); 1234 1235 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry); 1236 } 1237 wmb(); 1238 priv->hw->desc->set_rx_owner(p + entry); 1239 } 1240} 1241 1242static int stmmac_rx(struct stmmac_priv *priv, int limit) 1243{ 1244 unsigned int rxsize = priv->dma_rx_size; 1245 unsigned int entry = priv->cur_rx % rxsize; 1246 unsigned int next_entry; 1247 unsigned int count = 0; 1248 struct dma_desc *p = priv->dma_rx + entry; 1249 struct dma_desc *p_next; 1250 1251#ifdef STMMAC_RX_DEBUG 1252 if (netif_msg_hw(priv)) { 1253 pr_debug(">>> stmmac_rx: descriptor ring:\n"); 1254 display_ring(priv->dma_rx, rxsize); 1255 } 1256#endif 1257 count = 0; 1258 while (!priv->hw->desc->get_rx_owner(p)) { 1259 int status; 1260 1261 if (count >= limit) 1262 break; 1263 1264 count++; 1265 1266 next_entry = (++priv->cur_rx) % rxsize; 1267 p_next = priv->dma_rx + next_entry; 1268 prefetch(p_next); 1269 1270 /* read the status of the incoming frame */ 1271 status = (priv->hw->desc->rx_status(&priv->dev->stats, 1272 &priv->xstats, p)); 1273 if (unlikely(status == discard_frame)) 1274 priv->dev->stats.rx_errors++; 1275 else { 1276 struct sk_buff *skb; 1277 int frame_len; 1278 1279 frame_len = priv->hw->desc->get_rx_frame_len(p); 1280 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 1281 * Type frames (LLC/LLC-SNAP) */ 1282 if (unlikely(status != llc_snap)) 1283 frame_len -= ETH_FCS_LEN; 1284#ifdef STMMAC_RX_DEBUG 1285 if (frame_len > ETH_FRAME_LEN) 1286 pr_debug("\tRX frame size %d, COE status: %d\n", 1287 frame_len, status); 1288 1289 if (netif_msg_hw(priv)) 1290 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 1291 p, entry, p->des2); 1292#endif 1293 skb = priv->rx_skbuff[entry]; 1294 if (unlikely(!skb)) { 1295 pr_err("%s: Inconsistent Rx descriptor chain\n", 1296 priv->dev->name); 1297 priv->dev->stats.rx_dropped++; 1298 break; 1299 } 1300 prefetch(skb->data - NET_IP_ALIGN); 1301 priv->rx_skbuff[entry] = NULL; 1302 1303 skb_put(skb, frame_len); 1304 dma_unmap_single(priv->device, 1305 priv->rx_skbuff_dma[entry], 1306 priv->dma_buf_sz, DMA_FROM_DEVICE); 1307#ifdef STMMAC_RX_DEBUG 1308 if (netif_msg_pktdata(priv)) { 1309 pr_info(" frame received (%dbytes)", frame_len); 1310 print_pkt(skb->data, frame_len); 1311 } 1312#endif 1313 skb->protocol = eth_type_trans(skb, priv->dev); 1314 1315 if (unlikely(!priv->rx_coe)) { 1316 /* No RX COE for old mac10/100 devices */ 1317 skb_checksum_none_assert(skb); 1318 netif_receive_skb(skb); 1319 } else { 1320 skb->ip_summed = CHECKSUM_UNNECESSARY; 1321 napi_gro_receive(&priv->napi, skb); 1322 } 1323 1324 priv->dev->stats.rx_packets++; 1325 priv->dev->stats.rx_bytes += frame_len; 1326 } 1327 entry = next_entry; 1328 p = p_next; /* use prefetched values */ 1329 } 1330 1331 stmmac_rx_refill(priv); 1332 1333 priv->xstats.rx_pkt_n += count; 1334 1335 return count; 1336} 1337 1338/** 1339 * stmmac_poll - stmmac poll method (NAPI) 1340 * @napi : pointer to the napi structure. 1341 * @budget : maximum number of packets that the current CPU can receive from 1342 * all interfaces. 1343 * Description : 1344 * This function implements the the reception process. 1345 * Also it runs the TX completion thread 1346 */ 1347static int stmmac_poll(struct napi_struct *napi, int budget) 1348{ 1349 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 1350 int work_done = 0; 1351 1352 priv->xstats.poll_n++; 1353 stmmac_tx(priv); 1354 work_done = stmmac_rx(priv, budget); 1355 1356 if (work_done < budget) { 1357 napi_complete(napi); 1358 stmmac_enable_irq(priv); 1359 } 1360 return work_done; 1361} 1362 1363/** 1364 * stmmac_tx_timeout 1365 * @dev : Pointer to net device structure 1366 * Description: this function is called when a packet transmission fails to 1367 * complete within a reasonable tmrate. The driver will mark the error in the 1368 * netdev structure and arrange for the device to be reset to a sane state 1369 * in order to transmit a new packet. 1370 */ 1371static void stmmac_tx_timeout(struct net_device *dev) 1372{ 1373 struct stmmac_priv *priv = netdev_priv(dev); 1374 1375 /* Clear Tx resources and restart transmitting again */ 1376 stmmac_tx_err(priv); 1377} 1378 1379/* Configuration changes (passed on by ifconfig) */ 1380static int stmmac_config(struct net_device *dev, struct ifmap *map) 1381{ 1382 if (dev->flags & IFF_UP) /* can't act on a running interface */ 1383 return -EBUSY; 1384 1385 /* Don't allow changing the I/O address */ 1386 if (map->base_addr != dev->base_addr) { 1387 pr_warning("%s: can't change I/O address\n", dev->name); 1388 return -EOPNOTSUPP; 1389 } 1390 1391 /* Don't allow changing the IRQ */ 1392 if (map->irq != dev->irq) { 1393 pr_warning("%s: can't change IRQ number %d\n", 1394 dev->name, dev->irq); 1395 return -EOPNOTSUPP; 1396 } 1397 1398 /* ignore other fields */ 1399 return 0; 1400} 1401 1402/** 1403 * stmmac_set_rx_mode - entry point for multicast addressing 1404 * @dev : pointer to the device structure 1405 * Description: 1406 * This function is a driver entry point which gets called by the kernel 1407 * whenever multicast addresses must be enabled/disabled. 1408 * Return value: 1409 * void. 1410 */ 1411static void stmmac_set_rx_mode(struct net_device *dev) 1412{ 1413 struct stmmac_priv *priv = netdev_priv(dev); 1414 1415 spin_lock(&priv->lock); 1416 priv->hw->mac->set_filter(dev); 1417 spin_unlock(&priv->lock); 1418} 1419 1420/** 1421 * stmmac_change_mtu - entry point to change MTU size for the device. 1422 * @dev : device pointer. 1423 * @new_mtu : the new MTU size for the device. 1424 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 1425 * to drive packet transmission. Ethernet has an MTU of 1500 octets 1426 * (ETH_DATA_LEN). This value can be changed with ifconfig. 1427 * Return value: 1428 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1429 * file on failure. 1430 */ 1431static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 1432{ 1433 struct stmmac_priv *priv = netdev_priv(dev); 1434 int max_mtu; 1435 1436 if (netif_running(dev)) { 1437 pr_err("%s: must be stopped to change its MTU\n", dev->name); 1438 return -EBUSY; 1439 } 1440 1441 if (priv->plat->enh_desc) 1442 max_mtu = JUMBO_LEN; 1443 else 1444 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 1445 1446 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 1447 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 1448 return -EINVAL; 1449 } 1450 1451 dev->mtu = new_mtu; 1452 netdev_update_features(dev); 1453 1454 return 0; 1455} 1456 1457static netdev_features_t stmmac_fix_features(struct net_device *dev, 1458 netdev_features_t features) 1459{ 1460 struct stmmac_priv *priv = netdev_priv(dev); 1461 1462 if (!priv->rx_coe) 1463 features &= ~NETIF_F_RXCSUM; 1464 if (!priv->plat->tx_coe) 1465 features &= ~NETIF_F_ALL_CSUM; 1466 1467 /* Some GMAC devices have a bugged Jumbo frame support that 1468 * needs to have the Tx COE disabled for oversized frames 1469 * (due to limited buffer sizes). In this case we disable 1470 * the TX csum insertionin the TDES and not use SF. */ 1471 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 1472 features &= ~NETIF_F_ALL_CSUM; 1473 1474 return features; 1475} 1476 1477static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 1478{ 1479 struct net_device *dev = (struct net_device *)dev_id; 1480 struct stmmac_priv *priv = netdev_priv(dev); 1481 1482 if (unlikely(!dev)) { 1483 pr_err("%s: invalid dev pointer\n", __func__); 1484 return IRQ_NONE; 1485 } 1486 1487 if (priv->plat->has_gmac) 1488 /* To handle GMAC own interrupts */ 1489 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr); 1490 1491 stmmac_dma_interrupt(priv); 1492 1493 return IRQ_HANDLED; 1494} 1495 1496#ifdef CONFIG_NET_POLL_CONTROLLER 1497/* Polling receive - used by NETCONSOLE and other diagnostic tools 1498 * to allow network I/O with interrupts disabled. */ 1499static void stmmac_poll_controller(struct net_device *dev) 1500{ 1501 disable_irq(dev->irq); 1502 stmmac_interrupt(dev->irq, dev); 1503 enable_irq(dev->irq); 1504} 1505#endif 1506 1507/** 1508 * stmmac_ioctl - Entry point for the Ioctl 1509 * @dev: Device pointer. 1510 * @rq: An IOCTL specefic structure, that can contain a pointer to 1511 * a proprietary structure used to pass information to the driver. 1512 * @cmd: IOCTL command 1513 * Description: 1514 * Currently there are no special functionality supported in IOCTL, just the 1515 * phy_mii_ioctl(...) can be invoked. 1516 */ 1517static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1518{ 1519 struct stmmac_priv *priv = netdev_priv(dev); 1520 int ret; 1521 1522 if (!netif_running(dev)) 1523 return -EINVAL; 1524 1525 if (!priv->phydev) 1526 return -EINVAL; 1527 1528 ret = phy_mii_ioctl(priv->phydev, rq, cmd); 1529 1530 return ret; 1531} 1532 1533#ifdef CONFIG_STMMAC_DEBUG_FS 1534static struct dentry *stmmac_fs_dir; 1535static struct dentry *stmmac_rings_status; 1536static struct dentry *stmmac_dma_cap; 1537 1538static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 1539{ 1540 struct tmp_s { 1541 u64 a; 1542 unsigned int b; 1543 unsigned int c; 1544 }; 1545 int i; 1546 struct net_device *dev = seq->private; 1547 struct stmmac_priv *priv = netdev_priv(dev); 1548 1549 seq_printf(seq, "=======================\n"); 1550 seq_printf(seq, " RX descriptor ring\n"); 1551 seq_printf(seq, "=======================\n"); 1552 1553 for (i = 0; i < priv->dma_rx_size; i++) { 1554 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i); 1555 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", 1556 i, (unsigned int)(x->a), 1557 (unsigned int)((x->a) >> 32), x->b, x->c); 1558 seq_printf(seq, "\n"); 1559 } 1560 1561 seq_printf(seq, "\n"); 1562 seq_printf(seq, "=======================\n"); 1563 seq_printf(seq, " TX descriptor ring\n"); 1564 seq_printf(seq, "=======================\n"); 1565 1566 for (i = 0; i < priv->dma_tx_size; i++) { 1567 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i); 1568 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", 1569 i, (unsigned int)(x->a), 1570 (unsigned int)((x->a) >> 32), x->b, x->c); 1571 seq_printf(seq, "\n"); 1572 } 1573 1574 return 0; 1575} 1576 1577static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 1578{ 1579 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 1580} 1581 1582static const struct file_operations stmmac_rings_status_fops = { 1583 .owner = THIS_MODULE, 1584 .open = stmmac_sysfs_ring_open, 1585 .read = seq_read, 1586 .llseek = seq_lseek, 1587 .release = seq_release, 1588}; 1589 1590static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 1591{ 1592 struct net_device *dev = seq->private; 1593 struct stmmac_priv *priv = netdev_priv(dev); 1594 1595 if (!priv->hw_cap_support) { 1596 seq_printf(seq, "DMA HW features not supported\n"); 1597 return 0; 1598 } 1599 1600 seq_printf(seq, "==============================\n"); 1601 seq_printf(seq, "\tDMA HW features\n"); 1602 seq_printf(seq, "==============================\n"); 1603 1604 seq_printf(seq, "\t10/100 Mbps %s\n", 1605 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 1606 seq_printf(seq, "\t1000 Mbps %s\n", 1607 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 1608 seq_printf(seq, "\tHalf duple %s\n", 1609 (priv->dma_cap.half_duplex) ? "Y" : "N"); 1610 seq_printf(seq, "\tHash Filter: %s\n", 1611 (priv->dma_cap.hash_filter) ? "Y" : "N"); 1612 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 1613 (priv->dma_cap.multi_addr) ? "Y" : "N"); 1614 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 1615 (priv->dma_cap.pcs) ? "Y" : "N"); 1616 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 1617 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 1618 seq_printf(seq, "\tPMT Remote wake up: %s\n", 1619 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 1620 seq_printf(seq, "\tPMT Magic Frame: %s\n", 1621 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 1622 seq_printf(seq, "\tRMON module: %s\n", 1623 (priv->dma_cap.rmon) ? "Y" : "N"); 1624 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 1625 (priv->dma_cap.time_stamp) ? "Y" : "N"); 1626 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 1627 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 1628 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 1629 (priv->dma_cap.eee) ? "Y" : "N"); 1630 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 1631 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 1632 (priv->dma_cap.tx_coe) ? "Y" : "N"); 1633 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 1634 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 1635 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 1636 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 1637 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 1638 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 1639 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 1640 priv->dma_cap.number_rx_channel); 1641 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 1642 priv->dma_cap.number_tx_channel); 1643 seq_printf(seq, "\tEnhanced descriptors: %s\n", 1644 (priv->dma_cap.enh_desc) ? "Y" : "N"); 1645 1646 return 0; 1647} 1648 1649static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 1650{ 1651 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 1652} 1653 1654static const struct file_operations stmmac_dma_cap_fops = { 1655 .owner = THIS_MODULE, 1656 .open = stmmac_sysfs_dma_cap_open, 1657 .read = seq_read, 1658 .llseek = seq_lseek, 1659 .release = seq_release, 1660}; 1661 1662static int stmmac_init_fs(struct net_device *dev) 1663{ 1664 /* Create debugfs entries */ 1665 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 1666 1667 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 1668 pr_err("ERROR %s, debugfs create directory failed\n", 1669 STMMAC_RESOURCE_NAME); 1670 1671 return -ENOMEM; 1672 } 1673 1674 /* Entry to report DMA RX/TX rings */ 1675 stmmac_rings_status = debugfs_create_file("descriptors_status", 1676 S_IRUGO, stmmac_fs_dir, dev, 1677 &stmmac_rings_status_fops); 1678 1679 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { 1680 pr_info("ERROR creating stmmac ring debugfs file\n"); 1681 debugfs_remove(stmmac_fs_dir); 1682 1683 return -ENOMEM; 1684 } 1685 1686 /* Entry to report the DMA HW features */ 1687 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, 1688 dev, &stmmac_dma_cap_fops); 1689 1690 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { 1691 pr_info("ERROR creating stmmac MMC debugfs file\n"); 1692 debugfs_remove(stmmac_rings_status); 1693 debugfs_remove(stmmac_fs_dir); 1694 1695 return -ENOMEM; 1696 } 1697 1698 return 0; 1699} 1700 1701static void stmmac_exit_fs(void) 1702{ 1703 debugfs_remove(stmmac_rings_status); 1704 debugfs_remove(stmmac_dma_cap); 1705 debugfs_remove(stmmac_fs_dir); 1706} 1707#endif /* CONFIG_STMMAC_DEBUG_FS */ 1708 1709static const struct net_device_ops stmmac_netdev_ops = { 1710 .ndo_open = stmmac_open, 1711 .ndo_start_xmit = stmmac_xmit, 1712 .ndo_stop = stmmac_release, 1713 .ndo_change_mtu = stmmac_change_mtu, 1714 .ndo_fix_features = stmmac_fix_features, 1715 .ndo_set_rx_mode = stmmac_set_rx_mode, 1716 .ndo_tx_timeout = stmmac_tx_timeout, 1717 .ndo_do_ioctl = stmmac_ioctl, 1718 .ndo_set_config = stmmac_config, 1719#ifdef CONFIG_NET_POLL_CONTROLLER 1720 .ndo_poll_controller = stmmac_poll_controller, 1721#endif 1722 .ndo_set_mac_address = eth_mac_addr, 1723}; 1724 1725/** 1726 * stmmac_hw_init - Init the MAC device 1727 * @priv : pointer to the private device structure. 1728 * Description: this function detects which MAC device 1729 * (GMAC/MAC10-100) has to attached, checks the HW capability 1730 * (if supported) and sets the driver's features (for example 1731 * to use the ring or chaine mode or support the normal/enh 1732 * descriptor structure). 1733 */ 1734static int stmmac_hw_init(struct stmmac_priv *priv) 1735{ 1736 int ret = 0; 1737 struct mac_device_info *mac; 1738 1739 /* Identify the MAC HW device */ 1740 if (priv->plat->has_gmac) { 1741 priv->dev->priv_flags |= IFF_UNICAST_FLT; 1742 mac = dwmac1000_setup(priv->ioaddr); 1743 } else { 1744 mac = dwmac100_setup(priv->ioaddr); 1745 } 1746 if (!mac) 1747 return -ENOMEM; 1748 1749 priv->hw = mac; 1750 1751 /* To use the chained or ring mode */ 1752 priv->hw->ring = &ring_mode_ops; 1753 1754 /* Get and dump the chip ID */ 1755 stmmac_get_synopsys_id(priv); 1756 1757 /* Get the HW capability (new GMAC newer than 3.50a) */ 1758 priv->hw_cap_support = stmmac_get_hw_features(priv); 1759 if (priv->hw_cap_support) { 1760 pr_info(" DMA HW capability register supported"); 1761 1762 /* We can override some gmac/dma configuration fields: e.g. 1763 * enh_desc, tx_coe (e.g. that are passed through the 1764 * platform) with the values from the HW capability 1765 * register (if supported). 1766 */ 1767 priv->plat->enh_desc = priv->dma_cap.enh_desc; 1768 priv->plat->tx_coe = priv->dma_cap.tx_coe; 1769 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 1770 } else 1771 pr_info(" No HW DMA feature register supported"); 1772 1773 /* Select the enhnaced/normal descriptor structures */ 1774 stmmac_selec_desc_mode(priv); 1775 1776 priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr); 1777 if (priv->rx_coe) 1778 pr_info(" RX Checksum Offload Engine supported\n"); 1779 if (priv->plat->tx_coe) 1780 pr_info(" TX Checksum insertion supported\n"); 1781 1782 if (priv->plat->pmt) { 1783 pr_info(" Wake-Up On Lan supported\n"); 1784 device_set_wakeup_capable(priv->device, 1); 1785 } 1786 1787 return ret; 1788} 1789 1790/** 1791 * stmmac_dvr_probe 1792 * @device: device pointer 1793 * Description: this is the main probe function used to 1794 * call the alloc_etherdev, allocate the priv structure. 1795 */ 1796struct stmmac_priv *stmmac_dvr_probe(struct device *device, 1797 struct plat_stmmacenet_data *plat_dat, 1798 void __iomem *addr) 1799{ 1800 int ret = 0; 1801 struct net_device *ndev = NULL; 1802 struct stmmac_priv *priv; 1803 1804 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 1805 if (!ndev) 1806 return NULL; 1807 1808 SET_NETDEV_DEV(ndev, device); 1809 1810 priv = netdev_priv(ndev); 1811 priv->device = device; 1812 priv->dev = ndev; 1813 1814 ether_setup(ndev); 1815 1816 stmmac_set_ethtool_ops(ndev); 1817 priv->pause = pause; 1818 priv->plat = plat_dat; 1819 priv->ioaddr = addr; 1820 priv->dev->base_addr = (unsigned long)addr; 1821 1822 /* Verify driver arguments */ 1823 stmmac_verify_args(); 1824 1825 /* Override with kernel parameters if supplied XXX CRS XXX 1826 * this needs to have multiple instances */ 1827 if ((phyaddr >= 0) && (phyaddr <= 31)) 1828 priv->plat->phy_addr = phyaddr; 1829 1830 /* Init MAC and get the capabilities */ 1831 stmmac_hw_init(priv); 1832 1833 ndev->netdev_ops = &stmmac_netdev_ops; 1834 1835 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1836 NETIF_F_RXCSUM; 1837 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 1838 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 1839#ifdef STMMAC_VLAN_TAG_USED 1840 /* Both mac100 and gmac support receive VLAN tag detection */ 1841 ndev->features |= NETIF_F_HW_VLAN_RX; 1842#endif 1843 priv->msg_enable = netif_msg_init(debug, default_msg_level); 1844 1845 if (flow_ctrl) 1846 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 1847 1848 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 1849 1850 spin_lock_init(&priv->lock); 1851 spin_lock_init(&priv->tx_lock); 1852 1853 ret = register_netdev(ndev); 1854 if (ret) { 1855 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 1856 goto error; 1857 } 1858 1859 return priv; 1860 1861error: 1862 netif_napi_del(&priv->napi); 1863 1864 unregister_netdev(ndev); 1865 free_netdev(ndev); 1866 1867 return NULL; 1868} 1869 1870/** 1871 * stmmac_dvr_remove 1872 * @ndev: net device pointer 1873 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 1874 * changes the link status, releases the DMA descriptor rings. 1875 */ 1876int stmmac_dvr_remove(struct net_device *ndev) 1877{ 1878 struct stmmac_priv *priv = netdev_priv(ndev); 1879 1880 pr_info("%s:\n\tremoving driver", __func__); 1881 1882 priv->hw->dma->stop_rx(priv->ioaddr); 1883 priv->hw->dma->stop_tx(priv->ioaddr); 1884 1885 stmmac_set_mac(priv->ioaddr, false); 1886 netif_carrier_off(ndev); 1887 unregister_netdev(ndev); 1888 free_netdev(ndev); 1889 1890 return 0; 1891} 1892 1893#ifdef CONFIG_PM 1894int stmmac_suspend(struct net_device *ndev) 1895{ 1896 struct stmmac_priv *priv = netdev_priv(ndev); 1897 int dis_ic = 0; 1898 1899 if (!ndev || !netif_running(ndev)) 1900 return 0; 1901 1902 if (priv->phydev) 1903 phy_stop(priv->phydev); 1904 1905 spin_lock(&priv->lock); 1906 1907 netif_device_detach(ndev); 1908 netif_stop_queue(ndev); 1909 1910#ifdef CONFIG_STMMAC_TIMER 1911 priv->tm->timer_stop(); 1912 if (likely(priv->tm->enable)) 1913 dis_ic = 1; 1914#endif 1915 napi_disable(&priv->napi); 1916 1917 /* Stop TX/RX DMA */ 1918 priv->hw->dma->stop_tx(priv->ioaddr); 1919 priv->hw->dma->stop_rx(priv->ioaddr); 1920 /* Clear the Rx/Tx descriptors */ 1921 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, 1922 dis_ic); 1923 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); 1924 1925 /* Enable Power down mode by programming the PMT regs */ 1926 if (device_may_wakeup(priv->device)) 1927 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); 1928 else 1929 stmmac_set_mac(priv->ioaddr, false); 1930 1931 spin_unlock(&priv->lock); 1932 return 0; 1933} 1934 1935int stmmac_resume(struct net_device *ndev) 1936{ 1937 struct stmmac_priv *priv = netdev_priv(ndev); 1938 1939 if (!netif_running(ndev)) 1940 return 0; 1941 1942 spin_lock(&priv->lock); 1943 1944 /* Power Down bit, into the PM register, is cleared 1945 * automatically as soon as a magic packet or a Wake-up frame 1946 * is received. Anyway, it's better to manually clear 1947 * this bit because it can generate problems while resuming 1948 * from another devices (e.g. serial console). */ 1949 if (device_may_wakeup(priv->device)) 1950 priv->hw->mac->pmt(priv->ioaddr, 0); 1951 1952 netif_device_attach(ndev); 1953 1954 /* Enable the MAC and DMA */ 1955 stmmac_set_mac(priv->ioaddr, true); 1956 priv->hw->dma->start_tx(priv->ioaddr); 1957 priv->hw->dma->start_rx(priv->ioaddr); 1958 1959#ifdef CONFIG_STMMAC_TIMER 1960 if (likely(priv->tm->enable)) 1961 priv->tm->timer_start(tmrate); 1962#endif 1963 napi_enable(&priv->napi); 1964 1965 netif_start_queue(ndev); 1966 1967 spin_unlock(&priv->lock); 1968 1969 if (priv->phydev) 1970 phy_start(priv->phydev); 1971 1972 return 0; 1973} 1974 1975int stmmac_freeze(struct net_device *ndev) 1976{ 1977 if (!ndev || !netif_running(ndev)) 1978 return 0; 1979 1980 return stmmac_release(ndev); 1981} 1982 1983int stmmac_restore(struct net_device *ndev) 1984{ 1985 if (!ndev || !netif_running(ndev)) 1986 return 0; 1987 1988 return stmmac_open(ndev); 1989} 1990#endif /* CONFIG_PM */ 1991 1992#ifndef MODULE 1993static int __init stmmac_cmdline_opt(char *str) 1994{ 1995 char *opt; 1996 1997 if (!str || !*str) 1998 return -EINVAL; 1999 while ((opt = strsep(&str, ",")) != NULL) { 2000 if (!strncmp(opt, "debug:", 6)) { 2001 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug)) 2002 goto err; 2003 } else if (!strncmp(opt, "phyaddr:", 8)) { 2004 if (strict_strtoul(opt + 8, 0, 2005 (unsigned long *)&phyaddr)) 2006 goto err; 2007 } else if (!strncmp(opt, "dma_txsize:", 11)) { 2008 if (strict_strtoul(opt + 11, 0, 2009 (unsigned long *)&dma_txsize)) 2010 goto err; 2011 } else if (!strncmp(opt, "dma_rxsize:", 11)) { 2012 if (strict_strtoul(opt + 11, 0, 2013 (unsigned long *)&dma_rxsize)) 2014 goto err; 2015 } else if (!strncmp(opt, "buf_sz:", 7)) { 2016 if (strict_strtoul(opt + 7, 0, 2017 (unsigned long *)&buf_sz)) 2018 goto err; 2019 } else if (!strncmp(opt, "tc:", 3)) { 2020 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc)) 2021 goto err; 2022 } else if (!strncmp(opt, "watchdog:", 9)) { 2023 if (strict_strtoul(opt + 9, 0, 2024 (unsigned long *)&watchdog)) 2025 goto err; 2026 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 2027 if (strict_strtoul(opt + 10, 0, 2028 (unsigned long *)&flow_ctrl)) 2029 goto err; 2030 } else if (!strncmp(opt, "pause:", 6)) { 2031 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause)) 2032 goto err; 2033#ifdef CONFIG_STMMAC_TIMER 2034 } else if (!strncmp(opt, "tmrate:", 7)) { 2035 if (strict_strtoul(opt + 7, 0, 2036 (unsigned long *)&tmrate)) 2037 goto err; 2038#endif 2039 } 2040 } 2041 return 0; 2042 2043err: 2044 pr_err("%s: ERROR broken module parameter conversion", __func__); 2045 return -EINVAL; 2046} 2047 2048__setup("stmmaceth=", stmmac_cmdline_opt); 2049#endif 2050 2051MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 2052MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 2053MODULE_LICENSE("GPL"); 2054