1/* 2 * Hitachi (now Renesas) SCA-II HD64572 driver for Linux 3 * 4 * Copyright (C) 1998-2008 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 * 10 * Source of information: HD64572 SCA-II User's Manual 11 * 12 * We use the following SCA memory map: 13 * 14 * Packet buffer descriptor rings - starting from card->rambase: 15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring 16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring 17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used) 18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used) 19 * 20 * Packet data buffers - starting from card->rambase + buff_offset: 21 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers 22 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers 23 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used) 24 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used) 25 */ 26 27#include <linux/bitops.h> 28#include <linux/errno.h> 29#include <linux/fcntl.h> 30#include <linux/hdlc.h> 31#include <linux/in.h> 32#include <linux/init.h> 33#include <linux/interrupt.h> 34#include <linux/ioport.h> 35#include <linux/jiffies.h> 36#include <linux/kernel.h> 37#include <linux/module.h> 38#include <linux/netdevice.h> 39#include <linux/skbuff.h> 40#include <linux/string.h> 41#include <linux/types.h> 42#include <asm/io.h> 43#include <asm/uaccess.h> 44#include "hd64572.h" 45 46#define NAPI_WEIGHT 16 47 48#define get_msci(port) (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) 49#define get_dmac_rx(port) (port->chan ? DMAC1RX_OFFSET : DMAC0RX_OFFSET) 50#define get_dmac_tx(port) (port->chan ? DMAC1TX_OFFSET : DMAC0TX_OFFSET) 51 52#define sca_in(reg, card) readb(card->scabase + (reg)) 53#define sca_out(value, reg, card) writeb(value, card->scabase + (reg)) 54#define sca_inw(reg, card) readw(card->scabase + (reg)) 55#define sca_outw(value, reg, card) writew(value, card->scabase + (reg)) 56#define sca_inl(reg, card) readl(card->scabase + (reg)) 57#define sca_outl(value, reg, card) writel(value, card->scabase + (reg)) 58 59static int sca_poll(struct napi_struct *napi, int budget); 60 61static inline port_t* dev_to_port(struct net_device *dev) 62{ 63 return dev_to_hdlc(dev)->priv; 64} 65 66static inline void enable_intr(port_t *port) 67{ 68 /* enable DMIB and MSCI RXINTA interrupts */ 69 sca_outl(sca_inl(IER0, port->card) | 70 (port->chan ? 0x08002200 : 0x00080022), IER0, port->card); 71} 72 73static inline void disable_intr(port_t *port) 74{ 75 sca_outl(sca_inl(IER0, port->card) & 76 (port->chan ? 0x00FF00FF : 0xFF00FF00), IER0, port->card); 77} 78 79static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit) 80{ 81 u16 rx_buffs = port->card->rx_ring_buffers; 82 u16 tx_buffs = port->card->tx_ring_buffers; 83 84 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc. 85 return port->chan * (rx_buffs + tx_buffs) + transmit * rx_buffs + desc; 86} 87 88 89static inline u16 desc_offset(port_t *port, u16 desc, int transmit) 90{ 91 /* Descriptor offset always fits in 16 bits */ 92 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc); 93} 94 95 96static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc, 97 int transmit) 98{ 99 return (pkt_desc __iomem *)(port->card->rambase + 100 desc_offset(port, desc, transmit)); 101} 102 103 104static inline u32 buffer_offset(port_t *port, u16 desc, int transmit) 105{ 106 return port->card->buff_offset + 107 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU; 108} 109 110 111static inline void sca_set_carrier(port_t *port) 112{ 113 if (!(sca_in(get_msci(port) + ST3, port->card) & ST3_DCD)) { 114#ifdef DEBUG_LINK 115 printk(KERN_DEBUG "%s: sca_set_carrier on\n", 116 port->netdev.name); 117#endif 118 netif_carrier_on(port->netdev); 119 } else { 120#ifdef DEBUG_LINK 121 printk(KERN_DEBUG "%s: sca_set_carrier off\n", 122 port->netdev.name); 123#endif 124 netif_carrier_off(port->netdev); 125 } 126} 127 128 129static void sca_init_port(port_t *port) 130{ 131 card_t *card = port->card; 132 u16 dmac_rx = get_dmac_rx(port), dmac_tx = get_dmac_tx(port); 133 int transmit, i; 134 135 port->rxin = 0; 136 port->txin = 0; 137 port->txlast = 0; 138 139 for (transmit = 0; transmit < 2; transmit++) { 140 u16 buffs = transmit ? card->tx_ring_buffers 141 : card->rx_ring_buffers; 142 143 for (i = 0; i < buffs; i++) { 144 pkt_desc __iomem *desc = desc_address(port, i, transmit); 145 u16 chain_off = desc_offset(port, i + 1, transmit); 146 u32 buff_off = buffer_offset(port, i, transmit); 147 148 writel(chain_off, &desc->cp); 149 writel(buff_off, &desc->bp); 150 writew(0, &desc->len); 151 writeb(0, &desc->stat); 152 } 153 } 154 155 /* DMA disable - to halt state */ 156 sca_out(0, DSR_RX(port->chan), card); 157 sca_out(0, DSR_TX(port->chan), card); 158 159 /* software ABORT - to initial state */ 160 sca_out(DCR_ABORT, DCR_RX(port->chan), card); 161 sca_out(DCR_ABORT, DCR_TX(port->chan), card); 162 163 /* current desc addr */ 164 sca_outl(desc_offset(port, 0, 0), dmac_rx + CDAL, card); 165 sca_outl(desc_offset(port, card->tx_ring_buffers - 1, 0), 166 dmac_rx + EDAL, card); 167 sca_outl(desc_offset(port, 0, 1), dmac_tx + CDAL, card); 168 sca_outl(desc_offset(port, 0, 1), dmac_tx + EDAL, card); 169 170 /* clear frame end interrupt counter */ 171 sca_out(DCR_CLEAR_EOF, DCR_RX(port->chan), card); 172 sca_out(DCR_CLEAR_EOF, DCR_TX(port->chan), card); 173 174 /* Receive */ 175 sca_outw(HDLC_MAX_MRU, dmac_rx + BFLL, card); /* set buffer length */ 176 sca_out(0x14, DMR_RX(port->chan), card); /* Chain mode, Multi-frame */ 177 sca_out(DIR_EOME, DIR_RX(port->chan), card); /* enable interrupts */ 178 sca_out(DSR_DE, DSR_RX(port->chan), card); /* DMA enable */ 179 180 /* Transmit */ 181 sca_out(0x14, DMR_TX(port->chan), card); /* Chain mode, Multi-frame */ 182 sca_out(DIR_EOME, DIR_TX(port->chan), card); /* enable interrupts */ 183 184 sca_set_carrier(port); 185 netif_napi_add(port->netdev, &port->napi, sca_poll, NAPI_WEIGHT); 186} 187 188 189/* MSCI interrupt service */ 190static inline void sca_msci_intr(port_t *port) 191{ 192 u16 msci = get_msci(port); 193 card_t* card = port->card; 194 195 if (sca_in(msci + ST1, card) & ST1_CDCD) { 196 /* Reset MSCI CDCD status bit */ 197 sca_out(ST1_CDCD, msci + ST1, card); 198 sca_set_carrier(port); 199 } 200} 201 202 203static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, 204 u16 rxin) 205{ 206 struct net_device *dev = port->netdev; 207 struct sk_buff *skb; 208 u16 len; 209 u32 buff; 210 211 len = readw(&desc->len); 212 skb = dev_alloc_skb(len); 213 if (!skb) { 214 dev->stats.rx_dropped++; 215 return; 216 } 217 218 buff = buffer_offset(port, rxin, 0); 219 memcpy_fromio(skb->data, card->rambase + buff, len); 220 221 skb_put(skb, len); 222#ifdef DEBUG_PKT 223 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len); 224 debug_frame(skb); 225#endif 226 dev->stats.rx_packets++; 227 dev->stats.rx_bytes += skb->len; 228 skb->protocol = hdlc_type_trans(skb, dev); 229 netif_receive_skb(skb); 230} 231 232 233/* Receive DMA service */ 234static inline int sca_rx_done(port_t *port, int budget) 235{ 236 struct net_device *dev = port->netdev; 237 u16 dmac = get_dmac_rx(port); 238 card_t *card = port->card; 239 u8 stat = sca_in(DSR_RX(port->chan), card); /* read DMA Status */ 240 int received = 0; 241 242 /* Reset DSR status bits */ 243 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 244 DSR_RX(port->chan), card); 245 246 if (stat & DSR_BOF) 247 /* Dropped one or more frames */ 248 dev->stats.rx_over_errors++; 249 250 while (received < budget) { 251 u32 desc_off = desc_offset(port, port->rxin, 0); 252 pkt_desc __iomem *desc; 253 u32 cda = sca_inl(dmac + CDAL, card); 254 255 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) 256 break; /* No frame received */ 257 258 desc = desc_address(port, port->rxin, 0); 259 stat = readb(&desc->stat); 260 if (!(stat & ST_RX_EOM)) 261 port->rxpart = 1; /* partial frame received */ 262 else if ((stat & ST_ERROR_MASK) || port->rxpart) { 263 dev->stats.rx_errors++; 264 if (stat & ST_RX_OVERRUN) 265 dev->stats.rx_fifo_errors++; 266 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | 267 ST_RX_RESBIT)) || port->rxpart) 268 dev->stats.rx_frame_errors++; 269 else if (stat & ST_RX_CRC) 270 dev->stats.rx_crc_errors++; 271 if (stat & ST_RX_EOM) 272 port->rxpart = 0; /* received last fragment */ 273 } else { 274 sca_rx(card, port, desc, port->rxin); 275 received++; 276 } 277 278 /* Set new error descriptor address */ 279 sca_outl(desc_off, dmac + EDAL, card); 280 port->rxin = (port->rxin + 1) % card->rx_ring_buffers; 281 } 282 283 /* make sure RX DMA is enabled */ 284 sca_out(DSR_DE, DSR_RX(port->chan), card); 285 return received; 286} 287 288 289/* Transmit DMA service */ 290static inline void sca_tx_done(port_t *port) 291{ 292 struct net_device *dev = port->netdev; 293 card_t* card = port->card; 294 u8 stat; 295 unsigned count = 0; 296 297 spin_lock(&port->lock); 298 299 stat = sca_in(DSR_TX(port->chan), card); /* read DMA Status */ 300 301 /* Reset DSR status bits */ 302 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 303 DSR_TX(port->chan), card); 304 305 while (1) { 306 pkt_desc __iomem *desc = desc_address(port, port->txlast, 1); 307 u8 stat = readb(&desc->stat); 308 309 if (!(stat & ST_TX_OWNRSHP)) 310 break; /* not yet transmitted */ 311 if (stat & ST_TX_UNDRRUN) { 312 dev->stats.tx_errors++; 313 dev->stats.tx_fifo_errors++; 314 } else { 315 dev->stats.tx_packets++; 316 dev->stats.tx_bytes += readw(&desc->len); 317 } 318 writeb(0, &desc->stat); /* Free descriptor */ 319 count++; 320 port->txlast = (port->txlast + 1) % card->tx_ring_buffers; 321 } 322 323 if (count) 324 netif_wake_queue(dev); 325 spin_unlock(&port->lock); 326} 327 328 329static int sca_poll(struct napi_struct *napi, int budget) 330{ 331 port_t *port = container_of(napi, port_t, napi); 332 u32 isr0 = sca_inl(ISR0, port->card); 333 int received = 0; 334 335 if (isr0 & (port->chan ? 0x08000000 : 0x00080000)) 336 sca_msci_intr(port); 337 338 if (isr0 & (port->chan ? 0x00002000 : 0x00000020)) 339 sca_tx_done(port); 340 341 if (isr0 & (port->chan ? 0x00000200 : 0x00000002)) 342 received = sca_rx_done(port, budget); 343 344 if (received < budget) { 345 napi_complete(napi); 346 enable_intr(port); 347 } 348 349 return received; 350} 351 352static irqreturn_t sca_intr(int irq, void *dev_id) 353{ 354 card_t *card = dev_id; 355 u32 isr0 = sca_inl(ISR0, card); 356 int i, handled = 0; 357 358 for (i = 0; i < 2; i++) { 359 port_t *port = get_port(card, i); 360 if (port && (isr0 & (i ? 0x08002200 : 0x00080022))) { 361 handled = 1; 362 disable_intr(port); 363 napi_schedule(&port->napi); 364 } 365 } 366 367 return IRQ_RETVAL(handled); 368} 369 370 371static void sca_set_port(port_t *port) 372{ 373 card_t* card = port->card; 374 u16 msci = get_msci(port); 375 u8 md2 = sca_in(msci + MD2, card); 376 unsigned int tmc, br = 10, brv = 1024; 377 378 379 if (port->settings.clock_rate > 0) { 380 /* Try lower br for better accuracy*/ 381 do { 382 br--; 383 brv >>= 1; /* brv = 2^9 = 512 max in specs */ 384 385 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ 386 tmc = CLOCK_BASE / brv / port->settings.clock_rate; 387 }while (br > 1 && tmc <= 128); 388 389 if (tmc < 1) { 390 tmc = 1; 391 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ 392 brv = 1; 393 } else if (tmc > 255) 394 tmc = 256; /* tmc=0 means 256 - low baud rates */ 395 396 port->settings.clock_rate = CLOCK_BASE / brv / tmc; 397 } else { 398 br = 9; /* Minimum clock rate */ 399 tmc = 256; /* 8bit = 0 */ 400 port->settings.clock_rate = CLOCK_BASE / (256 * 512); 401 } 402 403 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br; 404 port->txs = (port->txs & ~CLK_BRG_MASK) | br; 405 port->tmc = tmc; 406 407 /* baud divisor - time constant*/ 408 sca_out(port->tmc, msci + TMCR, card); 409 sca_out(port->tmc, msci + TMCT, card); 410 411 /* Set BRG bits */ 412 sca_out(port->rxs, msci + RXS, card); 413 sca_out(port->txs, msci + TXS, card); 414 415 if (port->settings.loopback) 416 md2 |= MD2_LOOPBACK; 417 else 418 md2 &= ~MD2_LOOPBACK; 419 420 sca_out(md2, msci + MD2, card); 421 422} 423 424 425static void sca_open(struct net_device *dev) 426{ 427 port_t *port = dev_to_port(dev); 428 card_t* card = port->card; 429 u16 msci = get_msci(port); 430 u8 md0, md2; 431 432 switch(port->encoding) { 433 case ENCODING_NRZ: md2 = MD2_NRZ; break; 434 case ENCODING_NRZI: md2 = MD2_NRZI; break; 435 case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break; 436 case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break; 437 default: md2 = MD2_MANCHESTER; 438 } 439 440 if (port->settings.loopback) 441 md2 |= MD2_LOOPBACK; 442 443 switch(port->parity) { 444 case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break; 445 case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break; 446 case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break; 447 case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break; 448 default: md0 = MD0_HDLC | MD0_CRC_NONE; 449 } 450 451 sca_out(CMD_RESET, msci + CMD, card); 452 sca_out(md0, msci + MD0, card); 453 sca_out(0x00, msci + MD1, card); /* no address field check */ 454 sca_out(md2, msci + MD2, card); 455 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */ 456 /* Skip the rest of underrun frame */ 457 sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card); 458 sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */ 459 sca_out(0x3C, msci + TFS, card); /* +1 = TX start */ 460 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */ 461 sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */ 462 sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/ 463 464/* We're using the following interrupts: 465 - RXINTA (DCD changes only) 466 - DMIB (EOM - single frame transfer complete) 467*/ 468 sca_outl(IE0_RXINTA | IE0_CDCD, msci + IE0, card); 469 470 sca_out(port->tmc, msci + TMCR, card); 471 sca_out(port->tmc, msci + TMCT, card); 472 sca_out(port->rxs, msci + RXS, card); 473 sca_out(port->txs, msci + TXS, card); 474 sca_out(CMD_TX_ENABLE, msci + CMD, card); 475 sca_out(CMD_RX_ENABLE, msci + CMD, card); 476 477 sca_set_carrier(port); 478 enable_intr(port); 479 napi_enable(&port->napi); 480 netif_start_queue(dev); 481} 482 483 484static void sca_close(struct net_device *dev) 485{ 486 port_t *port = dev_to_port(dev); 487 488 /* reset channel */ 489 sca_out(CMD_RESET, get_msci(port) + CMD, port->card); 490 disable_intr(port); 491 napi_disable(&port->napi); 492 netif_stop_queue(dev); 493} 494 495 496static int sca_attach(struct net_device *dev, unsigned short encoding, 497 unsigned short parity) 498{ 499 if (encoding != ENCODING_NRZ && 500 encoding != ENCODING_NRZI && 501 encoding != ENCODING_FM_MARK && 502 encoding != ENCODING_FM_SPACE && 503 encoding != ENCODING_MANCHESTER) 504 return -EINVAL; 505 506 if (parity != PARITY_NONE && 507 parity != PARITY_CRC16_PR0 && 508 parity != PARITY_CRC16_PR1 && 509 parity != PARITY_CRC32_PR1_CCITT && 510 parity != PARITY_CRC16_PR1_CCITT) 511 return -EINVAL; 512 513 dev_to_port(dev)->encoding = encoding; 514 dev_to_port(dev)->parity = parity; 515 return 0; 516} 517 518 519#ifdef DEBUG_RINGS 520static void sca_dump_rings(struct net_device *dev) 521{ 522 port_t *port = dev_to_port(dev); 523 card_t *card = port->card; 524 u16 cnt; 525 526 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive", 527 sca_inl(get_dmac_rx(port) + CDAL, card), 528 sca_inl(get_dmac_rx(port) + EDAL, card), 529 sca_in(DSR_RX(port->chan), card), port->rxin, 530 sca_in(DSR_RX(port->chan), card) & DSR_DE ? "" : "in"); 531 for (cnt = 0; cnt < port->card->rx_ring_buffers; cnt++) 532 pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat))); 533 pr_cont("\n"); 534 535 printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u " 536 "last=%u %sactive", 537 sca_inl(get_dmac_tx(port) + CDAL, card), 538 sca_inl(get_dmac_tx(port) + EDAL, card), 539 sca_in(DSR_TX(port->chan), card), port->txin, port->txlast, 540 sca_in(DSR_TX(port->chan), card) & DSR_DE ? "" : "in"); 541 542 for (cnt = 0; cnt < port->card->tx_ring_buffers; cnt++) 543 pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat))); 544 pr_cont("\n"); 545 546 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x," 547 " ST: %02x %02x %02x %02x %02x, FST: %02x CST: %02x %02x\n", 548 sca_in(get_msci(port) + MD0, card), 549 sca_in(get_msci(port) + MD1, card), 550 sca_in(get_msci(port) + MD2, card), 551 sca_in(get_msci(port) + ST0, card), 552 sca_in(get_msci(port) + ST1, card), 553 sca_in(get_msci(port) + ST2, card), 554 sca_in(get_msci(port) + ST3, card), 555 sca_in(get_msci(port) + ST4, card), 556 sca_in(get_msci(port) + FST, card), 557 sca_in(get_msci(port) + CST0, card), 558 sca_in(get_msci(port) + CST1, card)); 559 560 printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card), 561 sca_inl(ISR0, card), sca_inl(ISR1, card)); 562} 563#endif /* DEBUG_RINGS */ 564 565 566static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev) 567{ 568 port_t *port = dev_to_port(dev); 569 card_t *card = port->card; 570 pkt_desc __iomem *desc; 571 u32 buff, len; 572 573 spin_lock_irq(&port->lock); 574 575 desc = desc_address(port, port->txin + 1, 1); 576 BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */ 577 578#ifdef DEBUG_PKT 579 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len); 580 debug_frame(skb); 581#endif 582 583 desc = desc_address(port, port->txin, 1); 584 buff = buffer_offset(port, port->txin, 1); 585 len = skb->len; 586 memcpy_toio(card->rambase + buff, skb->data, len); 587 588 writew(len, &desc->len); 589 writeb(ST_TX_EOM, &desc->stat); 590 591 port->txin = (port->txin + 1) % card->tx_ring_buffers; 592 sca_outl(desc_offset(port, port->txin, 1), 593 get_dmac_tx(port) + EDAL, card); 594 595 sca_out(DSR_DE, DSR_TX(port->chan), card); /* Enable TX DMA */ 596 597 desc = desc_address(port, port->txin + 1, 1); 598 if (readb(&desc->stat)) /* allow 1 packet gap */ 599 netif_stop_queue(dev); 600 601 spin_unlock_irq(&port->lock); 602 603 dev_kfree_skb(skb); 604 return NETDEV_TX_OK; 605} 606 607 608static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase, 609 u32 ramsize) 610{ 611 /* Round RAM size to 32 bits, fill from end to start */ 612 u32 i = ramsize &= ~3; 613 614 do { 615 i -= 4; 616 writel(i ^ 0x12345678, rambase + i); 617 } while (i > 0); 618 619 for (i = 0; i < ramsize ; i += 4) { 620 if (readl(rambase + i) != (i ^ 0x12345678)) 621 break; 622 } 623 624 return i; 625} 626 627 628static void __devinit sca_init(card_t *card, int wait_states) 629{ 630 sca_out(wait_states, WCRL, card); /* Wait Control */ 631 sca_out(wait_states, WCRM, card); 632 sca_out(wait_states, WCRH, card); 633 634 sca_out(0, DMER, card); /* DMA Master disable */ 635 sca_out(0x03, PCR, card); /* DMA priority */ 636 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */ 637 sca_out(0, DSR_TX(0), card); 638 sca_out(0, DSR_RX(1), card); 639 sca_out(0, DSR_TX(1), card); 640 sca_out(DMER_DME, DMER, card); /* DMA Master enable */ 641} 642