1/* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org> 5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> 6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> 7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23/*********************************\ 24* Protocol Control Unit Functions * 25\*********************************/ 26 27#include <asm/unaligned.h> 28 29#include "ath5k.h" 30#include "reg.h" 31#include "debug.h" 32 33/** 34 * DOC: Protocol Control Unit (PCU) functions 35 * 36 * Protocol control unit is responsible to maintain various protocol 37 * properties before a frame is send and after a frame is received to/from 38 * baseband. To be more specific, PCU handles: 39 * 40 * - Buffering of RX and TX frames (after QCU/DCUs) 41 * 42 * - Encrypting and decrypting (using the built-in engine) 43 * 44 * - Generating ACKs, RTS/CTS frames 45 * 46 * - Maintaining TSF 47 * 48 * - FCS 49 * 50 * - Updating beacon data (with TSF etc) 51 * 52 * - Generating virtual CCA 53 * 54 * - RX/Multicast filtering 55 * 56 * - BSSID filtering 57 * 58 * - Various statistics 59 * 60 * -Different operating modes: AP, STA, IBSS 61 * 62 * Note: Most of these functions can be tweaked/bypassed so you can do 63 * them on sw above for debugging or research. For more infos check out PCU 64 * registers on reg.h. 65 */ 66 67/** 68 * DOC: ACK rates 69 * 70 * AR5212+ can use higher rates for ack transmission 71 * based on current tx rate instead of the base rate. 72 * It does this to better utilize channel usage. 73 * There is a mapping between G rates (that cover both 74 * CCK and OFDM) and ack rates that we use when setting 75 * rate -> duration table. This mapping is hw-based so 76 * don't change anything. 77 * 78 * To enable this functionality we must set 79 * ah->ah_ack_bitrate_high to true else base rate is 80 * used (1Mb for CCK, 6Mb for OFDM). 81 */ 82static const unsigned int ack_rates_high[] = 83/* Tx -> ACK */ 84/* 1Mb -> 1Mb */ { 0, 85/* 2MB -> 2Mb */ 1, 86/* 5.5Mb -> 2Mb */ 1, 87/* 11Mb -> 2Mb */ 1, 88/* 6Mb -> 6Mb */ 4, 89/* 9Mb -> 6Mb */ 4, 90/* 12Mb -> 12Mb */ 6, 91/* 18Mb -> 12Mb */ 6, 92/* 24Mb -> 24Mb */ 8, 93/* 36Mb -> 24Mb */ 8, 94/* 48Mb -> 24Mb */ 8, 95/* 54Mb -> 24Mb */ 8 }; 96 97/*******************\ 98* Helper functions * 99\*******************/ 100 101/** 102 * ath5k_hw_get_frame_duration() - Get tx time of a frame 103 * @ah: The &struct ath5k_hw 104 * @len: Frame's length in bytes 105 * @rate: The @struct ieee80211_rate 106 * @shortpre: Indicate short preample 107 * 108 * Calculate tx duration of a frame given it's rate and length 109 * It extends ieee80211_generic_frame_duration for non standard 110 * bwmodes. 111 */ 112int 113ath5k_hw_get_frame_duration(struct ath5k_hw *ah, 114 int len, struct ieee80211_rate *rate, bool shortpre) 115{ 116 int sifs, preamble, plcp_bits, sym_time; 117 int bitrate, bits, symbols, symbol_bits; 118 int dur; 119 120 /* Fallback */ 121 if (!ah->ah_bwmode) { 122 __le16 raw_dur = ieee80211_generic_frame_duration(ah->hw, 123 NULL, len, rate); 124 125 /* subtract difference between long and short preamble */ 126 dur = le16_to_cpu(raw_dur); 127 if (shortpre) 128 dur -= 96; 129 130 return dur; 131 } 132 133 bitrate = rate->bitrate; 134 preamble = AR5K_INIT_OFDM_PREAMPLE_TIME; 135 plcp_bits = AR5K_INIT_OFDM_PLCP_BITS; 136 sym_time = AR5K_INIT_OFDM_SYMBOL_TIME; 137 138 switch (ah->ah_bwmode) { 139 case AR5K_BWMODE_40MHZ: 140 sifs = AR5K_INIT_SIFS_TURBO; 141 preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN; 142 break; 143 case AR5K_BWMODE_10MHZ: 144 sifs = AR5K_INIT_SIFS_HALF_RATE; 145 preamble *= 2; 146 sym_time *= 2; 147 break; 148 case AR5K_BWMODE_5MHZ: 149 sifs = AR5K_INIT_SIFS_QUARTER_RATE; 150 preamble *= 4; 151 sym_time *= 4; 152 break; 153 default: 154 sifs = AR5K_INIT_SIFS_DEFAULT_BG; 155 break; 156 } 157 158 bits = plcp_bits + (len << 3); 159 /* Bit rate is in 100Kbits */ 160 symbol_bits = bitrate * sym_time; 161 symbols = DIV_ROUND_UP(bits * 10, symbol_bits); 162 163 dur = sifs + preamble + (sym_time * symbols); 164 165 return dur; 166} 167 168/** 169 * ath5k_hw_get_default_slottime() - Get the default slot time for current mode 170 * @ah: The &struct ath5k_hw 171 */ 172unsigned int 173ath5k_hw_get_default_slottime(struct ath5k_hw *ah) 174{ 175 struct ieee80211_channel *channel = ah->ah_current_channel; 176 unsigned int slot_time; 177 178 switch (ah->ah_bwmode) { 179 case AR5K_BWMODE_40MHZ: 180 slot_time = AR5K_INIT_SLOT_TIME_TURBO; 181 break; 182 case AR5K_BWMODE_10MHZ: 183 slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE; 184 break; 185 case AR5K_BWMODE_5MHZ: 186 slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE; 187 break; 188 case AR5K_BWMODE_DEFAULT: 189 default: 190 slot_time = AR5K_INIT_SLOT_TIME_DEFAULT; 191 if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot) 192 slot_time = AR5K_INIT_SLOT_TIME_B; 193 break; 194 } 195 196 return slot_time; 197} 198 199/** 200 * ath5k_hw_get_default_sifs() - Get the default SIFS for current mode 201 * @ah: The &struct ath5k_hw 202 */ 203unsigned int 204ath5k_hw_get_default_sifs(struct ath5k_hw *ah) 205{ 206 struct ieee80211_channel *channel = ah->ah_current_channel; 207 unsigned int sifs; 208 209 switch (ah->ah_bwmode) { 210 case AR5K_BWMODE_40MHZ: 211 sifs = AR5K_INIT_SIFS_TURBO; 212 break; 213 case AR5K_BWMODE_10MHZ: 214 sifs = AR5K_INIT_SIFS_HALF_RATE; 215 break; 216 case AR5K_BWMODE_5MHZ: 217 sifs = AR5K_INIT_SIFS_QUARTER_RATE; 218 break; 219 case AR5K_BWMODE_DEFAULT: 220 sifs = AR5K_INIT_SIFS_DEFAULT_BG; 221 default: 222 if (channel->band == IEEE80211_BAND_5GHZ) 223 sifs = AR5K_INIT_SIFS_DEFAULT_A; 224 break; 225 } 226 227 return sifs; 228} 229 230/** 231 * ath5k_hw_update_mib_counters() - Update MIB counters (mac layer statistics) 232 * @ah: The &struct ath5k_hw 233 * 234 * Reads MIB counters from PCU and updates sw statistics. Is called after a 235 * MIB interrupt, because one of these counters might have reached their maximum 236 * and triggered the MIB interrupt, to let us read and clear the counter. 237 * 238 * NOTE: Is called in interrupt context! 239 */ 240void 241ath5k_hw_update_mib_counters(struct ath5k_hw *ah) 242{ 243 struct ath5k_statistics *stats = &ah->stats; 244 245 /* Read-And-Clear */ 246 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); 247 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); 248 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK); 249 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); 250 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); 251} 252 253 254/******************\ 255* ACK/CTS Timeouts * 256\******************/ 257 258/** 259 * ath5k_hw_write_rate_duration() - Fill rate code to duration table 260 * @ah: The &struct ath5k_hw 261 * 262 * Write the rate code to duration table upon hw reset. This is a helper for 263 * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on 264 * the hardware, based on current mode, for each rate. The rates which are 265 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have 266 * different rate code so we write their value twice (one for long preamble 267 * and one for short). 268 * 269 * Note: Band doesn't matter here, if we set the values for OFDM it works 270 * on both a and g modes. So all we have to do is set values for all g rates 271 * that include all OFDM and CCK rates. 272 * 273 */ 274static inline void 275ath5k_hw_write_rate_duration(struct ath5k_hw *ah) 276{ 277 struct ieee80211_rate *rate; 278 unsigned int i; 279 /* 802.11g covers both OFDM and CCK */ 280 u8 band = IEEE80211_BAND_2GHZ; 281 282 /* Write rate duration table */ 283 for (i = 0; i < ah->sbands[band].n_bitrates; i++) { 284 u32 reg; 285 u16 tx_time; 286 287 if (ah->ah_ack_bitrate_high) 288 rate = &ah->sbands[band].bitrates[ack_rates_high[i]]; 289 /* CCK -> 1Mb */ 290 else if (i < 4) 291 rate = &ah->sbands[band].bitrates[0]; 292 /* OFDM -> 6Mb */ 293 else 294 rate = &ah->sbands[band].bitrates[4]; 295 296 /* Set ACK timeout */ 297 reg = AR5K_RATE_DUR(rate->hw_value); 298 299 /* An ACK frame consists of 10 bytes. If you add the FCS, 300 * which ieee80211_generic_frame_duration() adds, 301 * its 14 bytes. Note we use the control rate and not the 302 * actual rate for this rate. See mac80211 tx.c 303 * ieee80211_duration() for a brief description of 304 * what rate we should choose to TX ACKs. */ 305 tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, false); 306 307 ath5k_hw_reg_write(ah, tx_time, reg); 308 309 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) 310 continue; 311 312 tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, true); 313 ath5k_hw_reg_write(ah, tx_time, 314 reg + (AR5K_SET_SHORT_PREAMBLE << 2)); 315 } 316} 317 318/** 319 * ath5k_hw_set_ack_timeout() - Set ACK timeout on PCU 320 * @ah: The &struct ath5k_hw 321 * @timeout: Timeout in usec 322 */ 323static int 324ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) 325{ 326 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) 327 <= timeout) 328 return -EINVAL; 329 330 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, 331 ath5k_hw_htoclock(ah, timeout)); 332 333 return 0; 334} 335 336/** 337 * ath5k_hw_set_cts_timeout() - Set CTS timeout on PCU 338 * @ah: The &struct ath5k_hw 339 * @timeout: Timeout in usec 340 */ 341static int 342ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) 343{ 344 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) 345 <= timeout) 346 return -EINVAL; 347 348 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, 349 ath5k_hw_htoclock(ah, timeout)); 350 351 return 0; 352} 353 354 355/*******************\ 356* RX filter Control * 357\*******************/ 358 359/** 360 * ath5k_hw_set_lladdr() - Set station id 361 * @ah: The &struct ath5k_hw 362 * @mac: The card's mac address (array of octets) 363 * 364 * Set station id on hw using the provided mac address 365 */ 366int 367ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) 368{ 369 struct ath_common *common = ath5k_hw_common(ah); 370 u32 low_id, high_id; 371 u32 pcu_reg; 372 373 /* Set new station ID */ 374 memcpy(common->macaddr, mac, ETH_ALEN); 375 376 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 377 378 low_id = get_unaligned_le32(mac); 379 high_id = get_unaligned_le16(mac + 4); 380 381 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 382 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 383 384 return 0; 385} 386 387/** 388 * ath5k_hw_set_bssid() - Set current BSSID on hw 389 * @ah: The &struct ath5k_hw 390 * 391 * Sets the current BSSID and BSSID mask we have from the 392 * common struct into the hardware 393 */ 394void 395ath5k_hw_set_bssid(struct ath5k_hw *ah) 396{ 397 struct ath_common *common = ath5k_hw_common(ah); 398 u16 tim_offset = 0; 399 400 /* 401 * Set BSSID mask on 5212 402 */ 403 if (ah->ah_version == AR5K_AR5212) 404 ath_hw_setbssidmask(common); 405 406 /* 407 * Set BSSID 408 */ 409 ath5k_hw_reg_write(ah, 410 get_unaligned_le32(common->curbssid), 411 AR5K_BSS_ID0); 412 ath5k_hw_reg_write(ah, 413 get_unaligned_le16(common->curbssid + 4) | 414 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S), 415 AR5K_BSS_ID1); 416 417 if (common->curaid == 0) { 418 ath5k_hw_disable_pspoll(ah); 419 return; 420 } 421 422 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, 423 tim_offset ? tim_offset + 4 : 0); 424 425 ath5k_hw_enable_pspoll(ah, NULL, 0); 426} 427 428/** 429 * ath5k_hw_set_bssid_mask() - Filter out bssids we listen 430 * @ah: The &struct ath5k_hw 431 * @mask: The BSSID mask to set (array of octets) 432 * 433 * BSSID masking is a method used by AR5212 and newer hardware to inform PCU 434 * which bits of the interface's MAC address should be looked at when trying 435 * to decide which packets to ACK. In station mode and AP mode with a single 436 * BSS every bit matters since we lock to only one BSS. In AP mode with 437 * multiple BSSes (virtual interfaces) not every bit matters because hw must 438 * accept frames for all BSSes and so we tweak some bits of our mac address 439 * in order to have multiple BSSes. 440 * 441 * For more information check out ../hw.c of the common ath module. 442 */ 443void 444ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) 445{ 446 struct ath_common *common = ath5k_hw_common(ah); 447 448 /* Cache bssid mask so that we can restore it 449 * on reset */ 450 memcpy(common->bssidmask, mask, ETH_ALEN); 451 if (ah->ah_version == AR5K_AR5212) 452 ath_hw_setbssidmask(common); 453} 454 455/** 456 * ath5k_hw_set_mcast_filter() - Set multicast filter 457 * @ah: The &struct ath5k_hw 458 * @filter0: Lower 32bits of muticast filter 459 * @filter1: Higher 16bits of multicast filter 460 */ 461void 462ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) 463{ 464 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); 465 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); 466} 467 468/** 469 * ath5k_hw_get_rx_filter() - Get current rx filter 470 * @ah: The &struct ath5k_hw 471 * 472 * Returns the RX filter by reading rx filter and 473 * phy error filter registers. RX filter is used 474 * to set the allowed frame types that PCU will accept 475 * and pass to the driver. For a list of frame types 476 * check out reg.h. 477 */ 478u32 479ath5k_hw_get_rx_filter(struct ath5k_hw *ah) 480{ 481 u32 data, filter = 0; 482 483 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); 484 485 /*Radar detection for 5212*/ 486 if (ah->ah_version == AR5K_AR5212) { 487 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); 488 489 if (data & AR5K_PHY_ERR_FIL_RADAR) 490 filter |= AR5K_RX_FILTER_RADARERR; 491 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) 492 filter |= AR5K_RX_FILTER_PHYERR; 493 } 494 495 return filter; 496} 497 498/** 499 * ath5k_hw_set_rx_filter() - Set rx filter 500 * @ah: The &struct ath5k_hw 501 * @filter: RX filter mask (see reg.h) 502 * 503 * Sets RX filter register and also handles PHY error filter 504 * register on 5212 and newer chips so that we have proper PHY 505 * error reporting. 506 */ 507void 508ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) 509{ 510 u32 data = 0; 511 512 /* Set PHY error filter register on 5212*/ 513 if (ah->ah_version == AR5K_AR5212) { 514 if (filter & AR5K_RX_FILTER_RADARERR) 515 data |= AR5K_PHY_ERR_FIL_RADAR; 516 if (filter & AR5K_RX_FILTER_PHYERR) 517 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; 518 } 519 520 /* 521 * The AR5210 uses promiscuous mode to detect radar activity 522 */ 523 if (ah->ah_version == AR5K_AR5210 && 524 (filter & AR5K_RX_FILTER_RADARERR)) { 525 filter &= ~AR5K_RX_FILTER_RADARERR; 526 filter |= AR5K_RX_FILTER_PROM; 527 } 528 529 /*Zero length DMA (phy error reporting) */ 530 if (data) 531 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 532 else 533 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 534 535 /*Write RX Filter register*/ 536 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); 537 538 /*Write PHY error filter register on 5212*/ 539 if (ah->ah_version == AR5K_AR5212) 540 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); 541 542} 543 544 545/****************\ 546* Beacon control * 547\****************/ 548 549#define ATH5K_MAX_TSF_READ 10 550 551/** 552 * ath5k_hw_get_tsf64() - Get the full 64bit TSF 553 * @ah: The &struct ath5k_hw 554 * 555 * Returns the current TSF 556 */ 557u64 558ath5k_hw_get_tsf64(struct ath5k_hw *ah) 559{ 560 u32 tsf_lower, tsf_upper1, tsf_upper2; 561 int i; 562 unsigned long flags; 563 564 /* This code is time critical - we don't want to be interrupted here */ 565 local_irq_save(flags); 566 567 /* 568 * While reading TSF upper and then lower part, the clock is still 569 * counting (or jumping in case of IBSS merge) so we might get 570 * inconsistent values. To avoid this, we read the upper part again 571 * and check it has not been changed. We make the hypothesis that a 572 * maximum of 3 changes can happens in a row (we use 10 as a safe 573 * value). 574 * 575 * Impact on performance is pretty small, since in most cases, only 576 * 3 register reads are needed. 577 */ 578 579 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 580 for (i = 0; i < ATH5K_MAX_TSF_READ; i++) { 581 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32); 582 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 583 if (tsf_upper2 == tsf_upper1) 584 break; 585 tsf_upper1 = tsf_upper2; 586 } 587 588 local_irq_restore(flags); 589 590 WARN_ON(i == ATH5K_MAX_TSF_READ); 591 592 return ((u64)tsf_upper1 << 32) | tsf_lower; 593} 594 595#undef ATH5K_MAX_TSF_READ 596 597/** 598 * ath5k_hw_set_tsf64() - Set a new 64bit TSF 599 * @ah: The &struct ath5k_hw 600 * @tsf64: The new 64bit TSF 601 * 602 * Sets the new TSF 603 */ 604void 605ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) 606{ 607 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); 608 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); 609} 610 611/** 612 * ath5k_hw_reset_tsf() - Force a TSF reset 613 * @ah: The &struct ath5k_hw 614 * 615 * Forces a TSF reset on PCU 616 */ 617void 618ath5k_hw_reset_tsf(struct ath5k_hw *ah) 619{ 620 u32 val; 621 622 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; 623 624 /* 625 * Each write to the RESET_TSF bit toggles a hardware internal 626 * signal to reset TSF, but if left high it will cause a TSF reset 627 * on the next chip reset as well. Thus we always write the value 628 * twice to clear the signal. 629 */ 630 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 631 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 632} 633 634/** 635 * ath5k_hw_init_beacon_timers() - Initialize beacon timers 636 * @ah: The &struct ath5k_hw 637 * @next_beacon: Next TBTT 638 * @interval: Current beacon interval 639 * 640 * This function is used to initialize beacon timers based on current 641 * operation mode and settings. 642 */ 643void 644ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval) 645{ 646 u32 timer1, timer2, timer3; 647 648 /* 649 * Set the additional timers by mode 650 */ 651 switch (ah->opmode) { 652 case NL80211_IFTYPE_MONITOR: 653 case NL80211_IFTYPE_STATION: 654 /* In STA mode timer1 is used as next wakeup 655 * timer and timer2 as next CFP duration start 656 * timer. Both in 1/8TUs. */ 657 /* TODO: PCF handling */ 658 if (ah->ah_version == AR5K_AR5210) { 659 timer1 = 0xffffffff; 660 timer2 = 0xffffffff; 661 } else { 662 timer1 = 0x0000ffff; 663 timer2 = 0x0007ffff; 664 } 665 /* Mark associated AP as PCF incapable for now */ 666 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF); 667 break; 668 case NL80211_IFTYPE_ADHOC: 669 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); 670 default: 671 /* On non-STA modes timer1 is used as next DMA 672 * beacon alert (DBA) timer and timer2 as next 673 * software beacon alert. Both in 1/8TUs. */ 674 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; 675 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; 676 break; 677 } 678 679 /* Timer3 marks the end of our ATIM window 680 * a zero length window is not allowed because 681 * we 'll get no beacons */ 682 timer3 = next_beacon + 1; 683 684 /* 685 * Set the beacon register and enable all timers. 686 */ 687 /* When in AP or Mesh Point mode zero timer0 to start TSF */ 688 if (ah->opmode == NL80211_IFTYPE_AP || 689 ah->opmode == NL80211_IFTYPE_MESH_POINT) 690 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); 691 692 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); 693 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); 694 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); 695 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); 696 697 /* Force a TSF reset if requested and enable beacons */ 698 if (interval & AR5K_BEACON_RESET_TSF) 699 ath5k_hw_reset_tsf(ah); 700 701 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | 702 AR5K_BEACON_ENABLE), 703 AR5K_BEACON); 704 705 /* Flush any pending BMISS interrupts on ISR by 706 * performing a clear-on-write operation on PISR 707 * register for the BMISS bit (writing a bit on 708 * ISR toggles a reset for that bit and leaves 709 * the remaining bits intact) */ 710 if (ah->ah_version == AR5K_AR5210) 711 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); 712 else 713 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); 714 715 /* TODO: Set enhanced sleep registers on AR5212 716 * based on vif->bss_conf params, until then 717 * disable power save reporting.*/ 718 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); 719 720} 721 722/** 723 * ath5k_check_timer_win() - Check if timer B is timer A + window 724 * @a: timer a (before b) 725 * @b: timer b (after a) 726 * @window: difference between a and b 727 * @intval: timers are increased by this interval 728 * 729 * This helper function checks if timer B is timer A + window and covers 730 * cases where timer A or B might have already been updated or wrapped 731 * around (Timers are 16 bit). 732 * 733 * Returns true if O.K. 734 */ 735static inline bool 736ath5k_check_timer_win(int a, int b, int window, int intval) 737{ 738 /* 739 * 1.) usually B should be A + window 740 * 2.) A already updated, B not updated yet 741 * 3.) A already updated and has wrapped around 742 * 4.) B has wrapped around 743 */ 744 if ((b - a == window) || /* 1.) */ 745 (a - b == intval - window) || /* 2.) */ 746 ((a | 0x10000) - b == intval - window) || /* 3.) */ 747 ((b | 0x10000) - a == window)) /* 4.) */ 748 return true; /* O.K. */ 749 return false; 750} 751 752/** 753 * ath5k_hw_check_beacon_timers() - Check if the beacon timers are correct 754 * @ah: The &struct ath5k_hw 755 * @intval: beacon interval 756 * 757 * This is a workaround for IBSS mode 758 * 759 * The need for this function arises from the fact that we have 4 separate 760 * HW timer registers (TIMER0 - TIMER3), which are closely related to the 761 * next beacon target time (NBTT), and that the HW updates these timers 762 * separately based on the current TSF value. The hardware increments each 763 * timer by the beacon interval, when the local TSF converted to TU is equal 764 * to the value stored in the timer. 765 * 766 * The reception of a beacon with the same BSSID can update the local HW TSF 767 * at any time - this is something we can't avoid. If the TSF jumps to a 768 * time which is later than the time stored in a timer, this timer will not 769 * be updated until the TSF in TU wraps around at 16 bit (the size of the 770 * timers) and reaches the time which is stored in the timer. 771 * 772 * The problem is that these timers are closely related to TIMER0 (NBTT) and 773 * that they define a time "window". When the TSF jumps between two timers 774 * (e.g. ATIM and NBTT), the one in the past will be left behind (not 775 * updated), while the one in the future will be updated every beacon 776 * interval. This causes the window to get larger, until the TSF wraps 777 * around as described above and the timer which was left behind gets 778 * updated again. But - because the beacon interval is usually not an exact 779 * divisor of the size of the timers (16 bit), an unwanted "window" between 780 * these timers has developed! 781 * 782 * This is especially important with the ATIM window, because during 783 * the ATIM window only ATIM frames and no data frames are allowed to be 784 * sent, which creates transmission pauses after each beacon. This symptom 785 * has been described as "ramping ping" because ping times increase linearly 786 * for some time and then drop down again. A wrong window on the DMA beacon 787 * timer has the same effect, so we check for these two conditions. 788 * 789 * Returns true if O.K. 790 */ 791bool 792ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval) 793{ 794 unsigned int nbtt, atim, dma; 795 796 nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0); 797 atim = ath5k_hw_reg_read(ah, AR5K_TIMER3); 798 dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3; 799 800 /* NOTE: SWBA is different. Having a wrong window there does not 801 * stop us from sending data and this condition is caught by 802 * other means (SWBA interrupt) */ 803 804 if (ath5k_check_timer_win(nbtt, atim, 1, intval) && 805 ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP, 806 intval)) 807 return true; /* O.K. */ 808 return false; 809} 810 811/** 812 * ath5k_hw_set_coverage_class() - Set IEEE 802.11 coverage class 813 * @ah: The &struct ath5k_hw 814 * @coverage_class: IEEE 802.11 coverage class number 815 * 816 * Sets IFS intervals and ACK/CTS timeouts for given coverage class. 817 */ 818void 819ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class) 820{ 821 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 822 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class; 823 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time; 824 int cts_timeout = ack_timeout; 825 826 ath5k_hw_set_ifs_intervals(ah, slot_time); 827 ath5k_hw_set_ack_timeout(ah, ack_timeout); 828 ath5k_hw_set_cts_timeout(ah, cts_timeout); 829 830 ah->ah_coverage_class = coverage_class; 831} 832 833/***************************\ 834* Init/Start/Stop functions * 835\***************************/ 836 837/** 838 * ath5k_hw_start_rx_pcu() - Start RX engine 839 * @ah: The &struct ath5k_hw 840 * 841 * Starts RX engine on PCU so that hw can process RXed frames 842 * (ACK etc). 843 * 844 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma 845 */ 846void 847ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) 848{ 849 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 850} 851 852/** 853 * at5k_hw_stop_rx_pcu() - Stop RX engine 854 * @ah: The &struct ath5k_hw 855 * 856 * Stops RX engine on PCU 857 */ 858void 859ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) 860{ 861 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 862} 863 864/** 865 * ath5k_hw_set_opmode() - Set PCU operating mode 866 * @ah: The &struct ath5k_hw 867 * @op_mode: One of enum nl80211_iftype 868 * 869 * Configure PCU for the various operating modes (AP/STA etc) 870 */ 871int 872ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode) 873{ 874 struct ath_common *common = ath5k_hw_common(ah); 875 u32 pcu_reg, beacon_reg, low_id, high_id; 876 877 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode); 878 879 /* Preserve rest settings */ 880 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 881 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP 882 | AR5K_STA_ID1_KEYSRCH_MODE 883 | (ah->ah_version == AR5K_AR5210 ? 884 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); 885 886 beacon_reg = 0; 887 888 switch (op_mode) { 889 case NL80211_IFTYPE_ADHOC: 890 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE; 891 beacon_reg |= AR5K_BCR_ADHOC; 892 if (ah->ah_version == AR5K_AR5210) 893 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 894 else 895 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 896 break; 897 898 case NL80211_IFTYPE_AP: 899 case NL80211_IFTYPE_MESH_POINT: 900 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE; 901 beacon_reg |= AR5K_BCR_AP; 902 if (ah->ah_version == AR5K_AR5210) 903 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 904 else 905 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 906 break; 907 908 case NL80211_IFTYPE_STATION: 909 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 910 | (ah->ah_version == AR5K_AR5210 ? 911 AR5K_STA_ID1_PWR_SV : 0); 912 case NL80211_IFTYPE_MONITOR: 913 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 914 | (ah->ah_version == AR5K_AR5210 ? 915 AR5K_STA_ID1_NO_PSPOLL : 0); 916 break; 917 918 default: 919 return -EINVAL; 920 } 921 922 /* 923 * Set PCU registers 924 */ 925 low_id = get_unaligned_le32(common->macaddr); 926 high_id = get_unaligned_le16(common->macaddr + 4); 927 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 928 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 929 930 /* 931 * Set Beacon Control Register on 5210 932 */ 933 if (ah->ah_version == AR5K_AR5210) 934 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); 935 936 return 0; 937} 938 939/** 940 * ath5k_hw_pcu_init() - Initialize PCU 941 * @ah: The &struct ath5k_hw 942 * @op_mode: One of enum nl80211_iftype 943 * @mode: One of enum ath5k_driver_mode 944 * 945 * This function is used to initialize PCU by setting current 946 * operation mode and various other settings. 947 */ 948void 949ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode) 950{ 951 /* Set bssid and bssid mask */ 952 ath5k_hw_set_bssid(ah); 953 954 /* Set PCU config */ 955 ath5k_hw_set_opmode(ah, op_mode); 956 957 /* Write rate duration table only on AR5212 and if 958 * virtual interface has already been brought up 959 * XXX: rethink this after new mode changes to 960 * mac80211 are integrated */ 961 if (ah->ah_version == AR5K_AR5212 && 962 ah->nvifs) 963 ath5k_hw_write_rate_duration(ah); 964 965 /* Set RSSI/BRSSI thresholds 966 * 967 * Note: If we decide to set this value 968 * dynamically, have in mind that when AR5K_RSSI_THR 969 * register is read it might return 0x40 if we haven't 970 * wrote anything to it plus BMISS RSSI threshold is zeroed. 971 * So doing a save/restore procedure here isn't the right 972 * choice. Instead store it on ath5k_hw */ 973 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | 974 AR5K_TUNE_BMISS_THRES << 975 AR5K_RSSI_THR_BMISS_S), 976 AR5K_RSSI_THR); 977 978 /* MIC QoS support */ 979 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { 980 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); 981 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); 982 } 983 984 /* QoS NOACK Policy */ 985 if (ah->ah_version == AR5K_AR5212) { 986 ath5k_hw_reg_write(ah, 987 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | 988 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | 989 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), 990 AR5K_QOS_NOACK); 991 } 992 993 /* Restore slot time and ACK timeouts */ 994 if (ah->ah_coverage_class > 0) 995 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class); 996 997 /* Set ACK bitrate mode (see ack_rates_high) */ 998 if (ah->ah_version == AR5K_AR5212) { 999 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; 1000 if (ah->ah_ack_bitrate_high) 1001 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); 1002 else 1003 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); 1004 } 1005 return; 1006} 1007