1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef EEPROM_H 18#define EEPROM_H 19 20#define AR_EEPROM_MODAL_SPURS 5 21 22#include "../ath.h" 23#include <net/cfg80211.h> 24#include "ar9003_eeprom.h" 25 26#ifdef __BIG_ENDIAN 27#define AR5416_EEPROM_MAGIC 0x5aa5 28#else 29#define AR5416_EEPROM_MAGIC 0xa55a 30#endif 31 32#define CTRY_DEBUG 0x1ff 33#define CTRY_DEFAULT 0 34 35#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 36#define AR_EEPROM_EEPCAP_AES_DIS 0x0002 37#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 38#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 39#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 40#define AR_EEPROM_EEPCAP_MAXQCU_S 4 41#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 42#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 43#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 44 45#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 46#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 47#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 48#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 49#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 50#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 51 52#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 53#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 54 55#define AR5416_EEPROM_MAGIC_OFFSET 0x0 56#define AR5416_EEPROM_S 2 57#define AR5416_EEPROM_OFFSET 0x2000 58#define AR5416_EEPROM_MAX 0xae0 59 60#define AR5416_EEPROM_START_ADDR \ 61 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 62 63#define SD_NO_CTL 0xE0 64#define NO_CTL 0xff 65#define CTL_MODE_M 0xf 66#define CTL_11A 0 67#define CTL_11B 1 68#define CTL_11G 2 69#define CTL_2GHT20 5 70#define CTL_5GHT20 6 71#define CTL_2GHT40 7 72#define CTL_5GHT40 8 73 74#define EXT_ADDITIVE (0x8000) 75#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 76#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 77#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 78 79#define SUB_NUM_CTL_MODES_AT_5G_40 2 80#define SUB_NUM_CTL_MODES_AT_2G_40 3 81 82#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ 83#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ 84 85/* 86 * For AR9285 and later chipsets, the following bits are not being programmed 87 * in EEPROM and so need to be enabled always. 88 * 89 * Bit 0: en_fcc_mid 90 * Bit 1: en_jap_mid 91 * Bit 2: en_fcc_dfs_ht40 92 * Bit 3: en_jap_ht40 93 * Bit 4: en_jap_dfs_ht40 94 */ 95#define AR9285_RDEXT_DEFAULT 0x1F 96 97#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 98#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 99#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) 100 101#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) 102#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ 103 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 104#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \ 105 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 106 107#define EEP_RFSILENT_ENABLED 0x0001 108#define EEP_RFSILENT_ENABLED_S 0 109#define EEP_RFSILENT_POLARITY 0x0002 110#define EEP_RFSILENT_POLARITY_S 1 111#define EEP_RFSILENT_GPIO_SEL (AR_SREV_9462(ah) ? 0x00fc : 0x001c) 112#define EEP_RFSILENT_GPIO_SEL_S 2 113 114#define AR5416_OPFLAGS_11A 0x01 115#define AR5416_OPFLAGS_11G 0x02 116#define AR5416_OPFLAGS_N_5G_HT40 0x04 117#define AR5416_OPFLAGS_N_2G_HT40 0x08 118#define AR5416_OPFLAGS_N_5G_HT20 0x10 119#define AR5416_OPFLAGS_N_2G_HT20 0x20 120 121#define AR5416_EEP_NO_BACK_VER 0x1 122#define AR5416_EEP_VER 0xE 123#define AR5416_EEP_VER_MINOR_MASK 0x0FFF 124#define AR5416_EEP_MINOR_VER_2 0x2 125#define AR5416_EEP_MINOR_VER_3 0x3 126#define AR5416_EEP_MINOR_VER_7 0x7 127#define AR5416_EEP_MINOR_VER_9 0x9 128#define AR5416_EEP_MINOR_VER_16 0x10 129#define AR5416_EEP_MINOR_VER_17 0x11 130#define AR5416_EEP_MINOR_VER_19 0x13 131#define AR5416_EEP_MINOR_VER_20 0x14 132#define AR5416_EEP_MINOR_VER_21 0x15 133#define AR5416_EEP_MINOR_VER_22 0x16 134 135#define AR5416_NUM_5G_CAL_PIERS 8 136#define AR5416_NUM_2G_CAL_PIERS 4 137#define AR5416_NUM_5G_20_TARGET_POWERS 8 138#define AR5416_NUM_5G_40_TARGET_POWERS 8 139#define AR5416_NUM_2G_CCK_TARGET_POWERS 3 140#define AR5416_NUM_2G_20_TARGET_POWERS 4 141#define AR5416_NUM_2G_40_TARGET_POWERS 4 142#define AR5416_NUM_CTLS 24 143#define AR5416_NUM_BAND_EDGES 8 144#define AR5416_NUM_PD_GAINS 4 145#define AR5416_PD_GAINS_IN_MASK 4 146#define AR5416_PD_GAIN_ICEPTS 5 147#define AR5416_NUM_PDADC_VALUES 128 148#define AR5416_BCHAN_UNUSED 0xFF 149#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 150#define AR5416_MAX_CHAINS 3 151#define AR9300_MAX_CHAINS 3 152#define AR5416_PWR_TABLE_OFFSET_DB -5 153 154/* Rx gain type values */ 155#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 156#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 157#define AR5416_EEP_RXGAIN_ORIG 2 158 159/* Tx gain type values */ 160#define AR5416_EEP_TXGAIN_ORIGINAL 0 161#define AR5416_EEP_TXGAIN_HIGH_POWER 1 162 163#define AR5416_EEP4K_START_LOC 64 164#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 165#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 166#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 167#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 168#define AR5416_EEP4K_NUM_CTLS 12 169#define AR5416_EEP4K_NUM_BAND_EDGES 4 170#define AR5416_EEP4K_NUM_PD_GAINS 2 171#define AR5416_EEP4K_MAX_CHAINS 1 172 173#define AR9280_TX_GAIN_TABLE_SIZE 22 174 175#define AR9287_EEP_VER 0xE 176#define AR9287_EEP_VER_MINOR_MASK 0xFFF 177#define AR9287_EEP_MINOR_VER_1 0x1 178#define AR9287_EEP_MINOR_VER_2 0x2 179#define AR9287_EEP_MINOR_VER_3 0x3 180#define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3 181#define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER 182#define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1 183 184#define AR9287_EEP_START_LOC 128 185#define AR9287_HTC_EEP_START_LOC 256 186#define AR9287_NUM_2G_CAL_PIERS 3 187#define AR9287_NUM_2G_CCK_TARGET_POWERS 3 188#define AR9287_NUM_2G_20_TARGET_POWERS 3 189#define AR9287_NUM_2G_40_TARGET_POWERS 3 190#define AR9287_NUM_CTLS 12 191#define AR9287_NUM_BAND_EDGES 4 192#define AR9287_PD_GAIN_ICEPTS 1 193#define AR9287_EEPMISC_BIG_ENDIAN 0x01 194#define AR9287_EEPMISC_WOW 0x02 195#define AR9287_MAX_CHAINS 2 196#define AR9287_ANT_16S 32 197 198#define AR9287_DATA_SZ 32 199 200#define AR9287_PWR_TABLE_OFFSET_DB -5 201 202#define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1) 203 204#define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f) 205#define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03) 206 207#define LNA_CTL_BUF_MODE BIT(0) 208#define LNA_CTL_ISEL_LO BIT(1) 209#define LNA_CTL_ISEL_HI BIT(2) 210#define LNA_CTL_BUF_IN BIT(3) 211#define LNA_CTL_FEM_BAND BIT(4) 212#define LNA_CTL_LOCAL_BIAS BIT(5) 213#define LNA_CTL_FORCE_XPA BIT(6) 214#define LNA_CTL_USE_ANT1 BIT(7) 215 216enum eeprom_param { 217 EEP_NFTHRESH_5, 218 EEP_NFTHRESH_2, 219 EEP_MAC_MSW, 220 EEP_MAC_MID, 221 EEP_MAC_LSW, 222 EEP_REG_0, 223 EEP_OP_CAP, 224 EEP_OP_MODE, 225 EEP_RF_SILENT, 226 EEP_OB_5, 227 EEP_DB_5, 228 EEP_OB_2, 229 EEP_DB_2, 230 EEP_MINOR_REV, 231 EEP_TX_MASK, 232 EEP_RX_MASK, 233 EEP_FSTCLK_5G, 234 EEP_RXGAIN_TYPE, 235 EEP_OL_PWRCTRL, 236 EEP_TXGAIN_TYPE, 237 EEP_RC_CHAIN_MASK, 238 EEP_DAC_HPWR_5G, 239 EEP_FRAC_N_5G, 240 EEP_DEV_TYPE, 241 EEP_TEMPSENSE_SLOPE, 242 EEP_TEMPSENSE_SLOPE_PAL_ON, 243 EEP_PWR_TABLE_OFFSET, 244 EEP_DRIVE_STRENGTH, 245 EEP_INTERNAL_REGULATOR, 246 EEP_SWREG, 247 EEP_PAPRD, 248 EEP_MODAL_VER, 249 EEP_ANT_DIV_CTL1, 250 EEP_CHAIN_MASK_REDUCE, 251 EEP_ANTENNA_GAIN_2G, 252 EEP_ANTENNA_GAIN_5G, 253 EEP_QUICK_DROP 254}; 255 256enum ar5416_rates { 257 rate6mb, rate9mb, rate12mb, rate18mb, 258 rate24mb, rate36mb, rate48mb, rate54mb, 259 rate1l, rate2l, rate2s, rate5_5l, 260 rate5_5s, rate11l, rate11s, rateXr, 261 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 262 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 263 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 264 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 265 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 266 Ar5416RateSize 267}; 268 269enum ath9k_hal_freq_band { 270 ATH9K_HAL_FREQ_BAND_5GHZ = 0, 271 ATH9K_HAL_FREQ_BAND_2GHZ = 1 272}; 273 274struct base_eep_header { 275 u16 length; 276 u16 checksum; 277 u16 version; 278 u8 opCapFlags; 279 u8 eepMisc; 280 u16 regDmn[2]; 281 u8 macAddr[6]; 282 u8 rxMask; 283 u8 txMask; 284 u16 rfSilent; 285 u16 blueToothOptions; 286 u16 deviceCap; 287 u32 binBuildNumber; 288 u8 deviceType; 289 u8 pwdclkind; 290 u8 fastClk5g; 291 u8 divChain; 292 u8 rxGainType; 293 u8 dacHiPwrMode_5G; 294 u8 openLoopPwrCntl; 295 u8 dacLpMode; 296 u8 txGainType; 297 u8 rcChainMask; 298 u8 desiredScaleCCK; 299 u8 pwr_table_offset; 300 u8 frac_n_5g; 301 u8 futureBase_3[21]; 302} __packed; 303 304struct base_eep_header_4k { 305 u16 length; 306 u16 checksum; 307 u16 version; 308 u8 opCapFlags; 309 u8 eepMisc; 310 u16 regDmn[2]; 311 u8 macAddr[6]; 312 u8 rxMask; 313 u8 txMask; 314 u16 rfSilent; 315 u16 blueToothOptions; 316 u16 deviceCap; 317 u32 binBuildNumber; 318 u8 deviceType; 319 u8 txGainType; 320} __packed; 321 322 323struct spur_chan { 324 u16 spurChan; 325 u8 spurRangeLow; 326 u8 spurRangeHigh; 327} __packed; 328 329struct modal_eep_header { 330 u32 antCtrlChain[AR5416_MAX_CHAINS]; 331 u32 antCtrlCommon; 332 u8 antennaGainCh[AR5416_MAX_CHAINS]; 333 u8 switchSettling; 334 u8 txRxAttenCh[AR5416_MAX_CHAINS]; 335 u8 rxTxMarginCh[AR5416_MAX_CHAINS]; 336 u8 adcDesiredSize; 337 u8 pgaDesiredSize; 338 u8 xlnaGainCh[AR5416_MAX_CHAINS]; 339 u8 txEndToXpaOff; 340 u8 txEndToRxOn; 341 u8 txFrameToXpaOn; 342 u8 thresh62; 343 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; 344 u8 xpdGain; 345 u8 xpd; 346 u8 iqCalICh[AR5416_MAX_CHAINS]; 347 u8 iqCalQCh[AR5416_MAX_CHAINS]; 348 u8 pdGainOverlap; 349 u8 ob; 350 u8 db; 351 u8 xpaBiasLvl; 352 u8 pwrDecreaseFor2Chain; 353 u8 pwrDecreaseFor3Chain; 354 u8 txFrameToDataStart; 355 u8 txFrameToPaOn; 356 u8 ht40PowerIncForPdadc; 357 u8 bswAtten[AR5416_MAX_CHAINS]; 358 u8 bswMargin[AR5416_MAX_CHAINS]; 359 u8 swSettleHt40; 360 u8 xatten2Db[AR5416_MAX_CHAINS]; 361 u8 xatten2Margin[AR5416_MAX_CHAINS]; 362 u8 ob_ch1; 363 u8 db_ch1; 364 u8 lna_ctl; 365 u8 miscBits; 366 u16 xpaBiasLvlFreq[3]; 367 u8 futureModal[6]; 368 369 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 370} __packed; 371 372struct calDataPerFreqOpLoop { 373 u8 pwrPdg[2][5]; 374 u8 vpdPdg[2][5]; 375 u8 pcdac[2][5]; 376 u8 empty[2][5]; 377} __packed; 378 379struct modal_eep_4k_header { 380 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; 381 u32 antCtrlCommon; 382 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; 383 u8 switchSettling; 384 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; 385 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; 386 u8 adcDesiredSize; 387 u8 pgaDesiredSize; 388 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; 389 u8 txEndToXpaOff; 390 u8 txEndToRxOn; 391 u8 txFrameToXpaOn; 392 u8 thresh62; 393 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; 394 u8 xpdGain; 395 u8 xpd; 396 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; 397 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; 398 u8 pdGainOverlap; 399#ifdef __BIG_ENDIAN_BITFIELD 400 u8 ob_1:4, ob_0:4; 401 u8 db1_1:4, db1_0:4; 402#else 403 u8 ob_0:4, ob_1:4; 404 u8 db1_0:4, db1_1:4; 405#endif 406 u8 xpaBiasLvl; 407 u8 txFrameToDataStart; 408 u8 txFrameToPaOn; 409 u8 ht40PowerIncForPdadc; 410 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; 411 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; 412 u8 swSettleHt40; 413 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; 414 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; 415#ifdef __BIG_ENDIAN_BITFIELD 416 u8 db2_1:4, db2_0:4; 417#else 418 u8 db2_0:4, db2_1:4; 419#endif 420 u8 version; 421#ifdef __BIG_ENDIAN_BITFIELD 422 u8 ob_3:4, ob_2:4; 423 u8 antdiv_ctl1:4, ob_4:4; 424 u8 db1_3:4, db1_2:4; 425 u8 antdiv_ctl2:4, db1_4:4; 426 u8 db2_2:4, db2_3:4; 427 u8 reserved:4, db2_4:4; 428#else 429 u8 ob_2:4, ob_3:4; 430 u8 ob_4:4, antdiv_ctl1:4; 431 u8 db1_2:4, db1_3:4; 432 u8 db1_4:4, antdiv_ctl2:4; 433 u8 db2_2:4, db2_3:4; 434 u8 db2_4:4, reserved:4; 435#endif 436 u8 tx_diversity; 437 u8 flc_pwr_thresh; 438 u8 bb_scale_smrt_antenna; 439#define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f 440 u8 futureModal[1]; 441 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 442} __packed; 443 444struct base_eep_ar9287_header { 445 u16 length; 446 u16 checksum; 447 u16 version; 448 u8 opCapFlags; 449 u8 eepMisc; 450 u16 regDmn[2]; 451 u8 macAddr[6]; 452 u8 rxMask; 453 u8 txMask; 454 u16 rfSilent; 455 u16 blueToothOptions; 456 u16 deviceCap; 457 u32 binBuildNumber; 458 u8 deviceType; 459 u8 openLoopPwrCntl; 460 int8_t pwrTableOffset; 461 int8_t tempSensSlope; 462 int8_t tempSensSlopePalOn; 463 u8 futureBase[29]; 464} __packed; 465 466struct modal_eep_ar9287_header { 467 u32 antCtrlChain[AR9287_MAX_CHAINS]; 468 u32 antCtrlCommon; 469 int8_t antennaGainCh[AR9287_MAX_CHAINS]; 470 u8 switchSettling; 471 u8 txRxAttenCh[AR9287_MAX_CHAINS]; 472 u8 rxTxMarginCh[AR9287_MAX_CHAINS]; 473 int8_t adcDesiredSize; 474 u8 txEndToXpaOff; 475 u8 txEndToRxOn; 476 u8 txFrameToXpaOn; 477 u8 thresh62; 478 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; 479 u8 xpdGain; 480 u8 xpd; 481 int8_t iqCalICh[AR9287_MAX_CHAINS]; 482 int8_t iqCalQCh[AR9287_MAX_CHAINS]; 483 u8 pdGainOverlap; 484 u8 xpaBiasLvl; 485 u8 txFrameToDataStart; 486 u8 txFrameToPaOn; 487 u8 ht40PowerIncForPdadc; 488 u8 bswAtten[AR9287_MAX_CHAINS]; 489 u8 bswMargin[AR9287_MAX_CHAINS]; 490 u8 swSettleHt40; 491 u8 version; 492 u8 db1; 493 u8 db2; 494 u8 ob_cck; 495 u8 ob_psk; 496 u8 ob_qam; 497 u8 ob_pal_off; 498 u8 futureModal[30]; 499 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 500} __packed; 501 502struct cal_data_per_freq { 503 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 504 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 505} __packed; 506 507struct cal_data_per_freq_4k { 508 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 509 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 510} __packed; 511 512struct cal_target_power_leg { 513 u8 bChannel; 514 u8 tPow2x[4]; 515} __packed; 516 517struct cal_target_power_ht { 518 u8 bChannel; 519 u8 tPow2x[8]; 520} __packed; 521 522struct cal_ctl_edges { 523 u8 bChannel; 524 u8 ctl; 525} __packed; 526 527struct cal_data_op_loop_ar9287 { 528 u8 pwrPdg[2][5]; 529 u8 vpdPdg[2][5]; 530 u8 pcdac[2][5]; 531 u8 empty[2][5]; 532} __packed; 533 534struct cal_data_per_freq_ar9287 { 535 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 536 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 537} __packed; 538 539union cal_data_per_freq_ar9287_u { 540 struct cal_data_op_loop_ar9287 calDataOpen; 541 struct cal_data_per_freq_ar9287 calDataClose; 542} __packed; 543 544struct cal_ctl_data_ar9287 { 545 struct cal_ctl_edges 546 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES]; 547} __packed; 548 549struct cal_ctl_data { 550 struct cal_ctl_edges 551 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 552} __packed; 553 554struct cal_ctl_data_4k { 555 struct cal_ctl_edges 556 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]; 557} __packed; 558 559struct ar5416_eeprom_def { 560 struct base_eep_header baseEepHeader; 561 u8 custData[64]; 562 struct modal_eep_header modalHeader[2]; 563 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 564 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 565 struct cal_data_per_freq 566 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; 567 struct cal_data_per_freq 568 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; 569 struct cal_target_power_leg 570 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; 571 struct cal_target_power_ht 572 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 573 struct cal_target_power_ht 574 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 575 struct cal_target_power_leg 576 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 577 struct cal_target_power_leg 578 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; 579 struct cal_target_power_ht 580 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 581 struct cal_target_power_ht 582 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 583 u8 ctlIndex[AR5416_NUM_CTLS]; 584 struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; 585 u8 padding; 586} __packed; 587 588struct ar5416_eeprom_4k { 589 struct base_eep_header_4k baseEepHeader; 590 u8 custData[20]; 591 struct modal_eep_4k_header modalHeader; 592 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]; 593 struct cal_data_per_freq_4k 594 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]; 595 struct cal_target_power_leg 596 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]; 597 struct cal_target_power_leg 598 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 599 struct cal_target_power_ht 600 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 601 struct cal_target_power_ht 602 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]; 603 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]; 604 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]; 605 u8 padding; 606} __packed; 607 608struct ar9287_eeprom { 609 struct base_eep_ar9287_header baseEepHeader; 610 u8 custData[AR9287_DATA_SZ]; 611 struct modal_eep_ar9287_header modalHeader; 612 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; 613 union cal_data_per_freq_ar9287_u 614 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; 615 struct cal_target_power_leg 616 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; 617 struct cal_target_power_leg 618 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; 619 struct cal_target_power_ht 620 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; 621 struct cal_target_power_ht 622 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; 623 u8 ctlIndex[AR9287_NUM_CTLS]; 624 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; 625 u8 padding; 626} __packed; 627 628enum reg_ext_bitmap { 629 REG_EXT_FCC_MIDBAND = 0, 630 REG_EXT_JAPAN_MIDBAND = 1, 631 REG_EXT_FCC_DFS_HT40 = 2, 632 REG_EXT_JAPAN_NONDFS_HT40 = 3, 633 REG_EXT_JAPAN_DFS_HT40 = 4 634}; 635 636struct ath9k_country_entry { 637 u16 countryCode; 638 u16 regDmnEnum; 639 u16 regDmn5G; 640 u16 regDmn2G; 641 u8 isMultidomain; 642 u8 iso[3]; 643}; 644 645struct eeprom_ops { 646 int (*check_eeprom)(struct ath_hw *hw); 647 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param); 648 bool (*fill_eeprom)(struct ath_hw *hw); 649 u32 (*dump_eeprom)(struct ath_hw *hw, bool dump_base_hdr, u8 *buf, 650 u32 len, u32 size); 651 int (*get_eeprom_ver)(struct ath_hw *hw); 652 int (*get_eeprom_rev)(struct ath_hw *hw); 653 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); 654 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); 655 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, 656 u16 cfgCtl, u8 twiceAntennaReduction, 657 u8 powerLimit, bool test); 658 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); 659}; 660 661void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val); 662void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, 663 u32 shift, u32 val); 664int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, 665 int16_t targetLeft, 666 int16_t targetRight); 667bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, 668 u16 *indexL, u16 *indexR); 669bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data); 670void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data, 671 int eep_start_loc, int size); 672void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 673 u8 *pVpdList, u16 numIntercepts, 674 u8 *pRetVpdList); 675void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, 676 struct ath9k_channel *chan, 677 struct cal_target_power_leg *powInfo, 678 u16 numChannels, 679 struct cal_target_power_leg *pNewPower, 680 u16 numRates, bool isExtTarget); 681void ath9k_hw_get_target_powers(struct ath_hw *ah, 682 struct ath9k_channel *chan, 683 struct cal_target_power_ht *powInfo, 684 u16 numChannels, 685 struct cal_target_power_ht *pNewPower, 686 u16 numRates, bool isHt40Target); 687u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, 688 bool is2GHz, int num_band_edges); 689void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah); 690int ath9k_hw_eeprom_init(struct ath_hw *ah); 691 692void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, 693 struct ath9k_channel *chan, 694 void *pRawDataSet, 695 u8 *bChans, u16 availPiers, 696 u16 tPdGainOverlap, 697 u16 *pPdGainBoundaries, u8 *pPDADCValues, 698 u16 numXpdGains); 699 700#define ar5416_get_ntxchains(_txchainmask) \ 701 (((_txchainmask >> 2) & 1) + \ 702 ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 703 704extern const struct eeprom_ops eep_def_ops; 705extern const struct eeprom_ops eep_4k_ops; 706extern const struct eeprom_ops eep_ar9287_ops; 707extern const struct eeprom_ops eep_ar9287_ops; 708extern const struct eeprom_ops eep_ar9300_ops; 709 710#endif /* EEPROM_H */ 711