1/* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/dma-mapping.h> 18#include <linux/slab.h> 19 20#include "ath9k.h" 21#include "mci.h" 22 23static const u8 ath_mci_duty_cycle[] = { 0, 50, 60, 70, 80, 85, 90, 95, 98 }; 24 25static struct ath_mci_profile_info* 26ath_mci_find_profile(struct ath_mci_profile *mci, 27 struct ath_mci_profile_info *info) 28{ 29 struct ath_mci_profile_info *entry; 30 31 list_for_each_entry(entry, &mci->info, list) { 32 if (entry->conn_handle == info->conn_handle) 33 break; 34 } 35 return entry; 36} 37 38static bool ath_mci_add_profile(struct ath_common *common, 39 struct ath_mci_profile *mci, 40 struct ath_mci_profile_info *info) 41{ 42 struct ath_mci_profile_info *entry; 43 44 if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) && 45 (info->type == MCI_GPM_COEX_PROFILE_VOICE)) 46 return false; 47 48 if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) && 49 (info->type != MCI_GPM_COEX_PROFILE_VOICE)) 50 return false; 51 52 entry = ath_mci_find_profile(mci, info); 53 54 if (entry) { 55 memcpy(entry, info, 10); 56 } else { 57 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 58 if (!entry) 59 return false; 60 61 memcpy(entry, info, 10); 62 INC_PROF(mci, info); 63 list_add_tail(&info->list, &mci->info); 64 } 65 66 return true; 67} 68 69static void ath_mci_del_profile(struct ath_common *common, 70 struct ath_mci_profile *mci, 71 struct ath_mci_profile_info *info) 72{ 73 struct ath_mci_profile_info *entry; 74 75 entry = ath_mci_find_profile(mci, info); 76 77 if (!entry) 78 return; 79 80 DEC_PROF(mci, entry); 81 list_del(&entry->list); 82 kfree(entry); 83} 84 85void ath_mci_flush_profile(struct ath_mci_profile *mci) 86{ 87 struct ath_mci_profile_info *info, *tinfo; 88 89 list_for_each_entry_safe(info, tinfo, &mci->info, list) { 90 list_del(&info->list); 91 DEC_PROF(mci, info); 92 kfree(info); 93 } 94 mci->aggr_limit = 0; 95} 96 97static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex) 98{ 99 struct ath_mci_profile *mci = &btcoex->mci; 100 u32 wlan_airtime = btcoex->btcoex_period * 101 (100 - btcoex->duty_cycle) / 100; 102 103 /* 104 * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms. 105 * When wlan_airtime is less than 4ms, aggregation limit has to be 106 * adjusted half of wlan_airtime to ensure that the aggregation can fit 107 * without collision with BT traffic. 108 */ 109 if ((wlan_airtime <= 4) && 110 (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime)))) 111 mci->aggr_limit = 2 * wlan_airtime; 112} 113 114static void ath_mci_update_scheme(struct ath_softc *sc) 115{ 116 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 117 struct ath_btcoex *btcoex = &sc->btcoex; 118 struct ath_mci_profile *mci = &btcoex->mci; 119 struct ath_mci_profile_info *info; 120 u32 num_profile = NUM_PROF(mci); 121 122 if (num_profile == 1) { 123 info = list_first_entry(&mci->info, 124 struct ath_mci_profile_info, 125 list); 126 if (mci->num_sco && info->T == 12) { 127 mci->aggr_limit = 8; 128 ath_dbg(common, MCI, 129 "Single SCO, aggregation limit 2 ms\n"); 130 } else if ((info->type == MCI_GPM_COEX_PROFILE_BNEP) && 131 !info->master) { 132 btcoex->btcoex_period = 60; 133 ath_dbg(common, MCI, 134 "Single slave PAN/FTP, bt period 60 ms\n"); 135 } else if ((info->type == MCI_GPM_COEX_PROFILE_HID) && 136 (info->T > 0 && info->T < 50) && 137 (info->A > 1 || info->W > 1)) { 138 btcoex->duty_cycle = 30; 139 mci->aggr_limit = 8; 140 ath_dbg(common, MCI, 141 "Multiple attempt/timeout single HID " 142 "aggregation limit 2 ms dutycycle 30%%\n"); 143 } 144 } else if ((num_profile == 2) && (mci->num_hid == 2)) { 145 btcoex->duty_cycle = 30; 146 mci->aggr_limit = 8; 147 ath_dbg(common, MCI, 148 "Two HIDs aggregation limit 2 ms dutycycle 30%%\n"); 149 } else if (num_profile > 3) { 150 mci->aggr_limit = 6; 151 ath_dbg(common, MCI, 152 "Three or more profiles aggregation limit 1.5 ms\n"); 153 } 154 155 if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) { 156 if (IS_CHAN_HT(sc->sc_ah->curchan)) 157 ath_mci_adjust_aggr_limit(btcoex); 158 else 159 btcoex->btcoex_period >>= 1; 160 } 161 162 ath9k_hw_btcoex_disable(sc->sc_ah); 163 ath9k_btcoex_timer_pause(sc); 164 165 if (IS_CHAN_5GHZ(sc->sc_ah->curchan)) 166 return; 167 168 btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_MAX_DUTY_CYCLE : 0); 169 if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE) 170 btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE; 171 172 btcoex->btcoex_period *= 1000; 173 btcoex->btcoex_no_stomp = btcoex->btcoex_period * 174 (100 - btcoex->duty_cycle) / 100; 175 176 ath9k_hw_btcoex_enable(sc->sc_ah); 177 ath9k_btcoex_timer_resume(sc); 178} 179 180static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) 181{ 182 struct ath_hw *ah = sc->sc_ah; 183 struct ath_common *common = ath9k_hw_common(ah); 184 u32 payload[4] = {0, 0, 0, 0}; 185 186 switch (opcode) { 187 case MCI_GPM_BT_CAL_REQ: 188 if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) { 189 ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START, NULL); 190 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 191 } else { 192 ath_dbg(common, MCI, "MCI State mismatch: %d\n", 193 ar9003_mci_state(ah, MCI_STATE_BT, NULL)); 194 } 195 break; 196 case MCI_GPM_BT_CAL_DONE: 197 ar9003_mci_state(ah, MCI_STATE_BT, NULL); 198 break; 199 case MCI_GPM_BT_CAL_GRANT: 200 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE); 201 ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload, 202 16, false, true); 203 break; 204 default: 205 ath_dbg(common, MCI, "Unknown GPM CAL message\n"); 206 break; 207 } 208} 209 210static void ath_mci_process_profile(struct ath_softc *sc, 211 struct ath_mci_profile_info *info) 212{ 213 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 214 struct ath_btcoex *btcoex = &sc->btcoex; 215 struct ath_mci_profile *mci = &btcoex->mci; 216 217 if (info->start) { 218 if (!ath_mci_add_profile(common, mci, info)) 219 return; 220 } else 221 ath_mci_del_profile(common, mci, info); 222 223 btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD; 224 mci->aggr_limit = mci->num_sco ? 6 : 0; 225 226 if (NUM_PROF(mci)) { 227 btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW; 228 btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)]; 229 } else { 230 btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL : 231 ATH_BTCOEX_STOMP_LOW; 232 btcoex->duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE; 233 } 234 235 ath_mci_update_scheme(sc); 236} 237 238static void ath_mci_process_status(struct ath_softc *sc, 239 struct ath_mci_profile_status *status) 240{ 241 struct ath_btcoex *btcoex = &sc->btcoex; 242 struct ath_mci_profile *mci = &btcoex->mci; 243 struct ath_mci_profile_info info; 244 int i = 0, old_num_mgmt = mci->num_mgmt; 245 246 /* Link status type are not handled */ 247 if (status->is_link) 248 return; 249 250 memset(&info, 0, sizeof(struct ath_mci_profile_info)); 251 252 info.conn_handle = status->conn_handle; 253 if (ath_mci_find_profile(mci, &info)) 254 return; 255 256 if (status->conn_handle >= ATH_MCI_MAX_PROFILE) 257 return; 258 259 if (status->is_critical) 260 __set_bit(status->conn_handle, mci->status); 261 else 262 __clear_bit(status->conn_handle, mci->status); 263 264 mci->num_mgmt = 0; 265 do { 266 if (test_bit(i, mci->status)) 267 mci->num_mgmt++; 268 } while (++i < ATH_MCI_MAX_PROFILE); 269 270 if (old_num_mgmt != mci->num_mgmt) 271 ath_mci_update_scheme(sc); 272} 273 274static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) 275{ 276 struct ath_hw *ah = sc->sc_ah; 277 struct ath_mci_profile_info profile_info; 278 struct ath_mci_profile_status profile_status; 279 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 280 u32 version; 281 u8 major; 282 u8 minor; 283 u32 seq_num; 284 285 switch (opcode) { 286 case MCI_GPM_COEX_VERSION_QUERY: 287 version = ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION, 288 NULL); 289 break; 290 case MCI_GPM_COEX_VERSION_RESPONSE: 291 major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION); 292 minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION); 293 version = (major << 8) + minor; 294 version = ar9003_mci_state(ah, MCI_STATE_SET_BT_COEX_VERSION, 295 &version); 296 break; 297 case MCI_GPM_COEX_STATUS_QUERY: 298 ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_CHANNELS, NULL); 299 break; 300 case MCI_GPM_COEX_BT_PROFILE_INFO: 301 memcpy(&profile_info, 302 (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10); 303 304 if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) || 305 (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) { 306 ath_dbg(common, MCI, 307 "Illegal profile type = %d, state = %d\n", 308 profile_info.type, 309 profile_info.start); 310 break; 311 } 312 313 ath_mci_process_profile(sc, &profile_info); 314 break; 315 case MCI_GPM_COEX_BT_STATUS_UPDATE: 316 profile_status.is_link = *(rx_payload + 317 MCI_GPM_COEX_B_STATUS_TYPE); 318 profile_status.conn_handle = *(rx_payload + 319 MCI_GPM_COEX_B_STATUS_LINKID); 320 profile_status.is_critical = *(rx_payload + 321 MCI_GPM_COEX_B_STATUS_STATE); 322 323 seq_num = *((u32 *)(rx_payload + 12)); 324 ath_dbg(common, MCI, 325 "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n", 326 profile_status.is_link, profile_status.conn_handle, 327 profile_status.is_critical, seq_num); 328 329 ath_mci_process_status(sc, &profile_status); 330 break; 331 default: 332 ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode); 333 break; 334 } 335} 336 337int ath_mci_setup(struct ath_softc *sc) 338{ 339 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 340 struct ath_mci_coex *mci = &sc->mci_coex; 341 struct ath_mci_buf *buf = &mci->sched_buf; 342 343 buf->bf_addr = dma_alloc_coherent(sc->dev, 344 ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE, 345 &buf->bf_paddr, GFP_KERNEL); 346 347 if (buf->bf_addr == NULL) { 348 ath_dbg(common, FATAL, "MCI buffer alloc failed\n"); 349 return -ENOMEM; 350 } 351 352 memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN, 353 ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE); 354 355 mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE; 356 357 mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE; 358 mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len; 359 mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len; 360 361 ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr, 362 mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4), 363 mci->sched_buf.bf_paddr); 364 365 ath_dbg(common, MCI, "MCI Initialized\n"); 366 367 return 0; 368} 369 370void ath_mci_cleanup(struct ath_softc *sc) 371{ 372 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 373 struct ath_hw *ah = sc->sc_ah; 374 struct ath_mci_coex *mci = &sc->mci_coex; 375 struct ath_mci_buf *buf = &mci->sched_buf; 376 377 if (buf->bf_addr) 378 dma_free_coherent(sc->dev, 379 ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE, 380 buf->bf_addr, buf->bf_paddr); 381 382 ar9003_mci_cleanup(ah); 383 384 ath_dbg(common, MCI, "MCI De-Initialized\n"); 385} 386 387void ath_mci_intr(struct ath_softc *sc) 388{ 389 struct ath_mci_coex *mci = &sc->mci_coex; 390 struct ath_hw *ah = sc->sc_ah; 391 struct ath_common *common = ath9k_hw_common(ah); 392 u32 mci_int, mci_int_rxmsg; 393 u32 offset, subtype, opcode; 394 u32 *pgpm; 395 u32 more_data = MCI_GPM_MORE; 396 bool skip_gpm = false; 397 398 ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg); 399 400 if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) == 0) { 401 ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL); 402 return; 403 } 404 405 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) { 406 u32 payload[4] = { 0xffffffff, 0xffffffff, 407 0xffffffff, 0xffffff00}; 408 409 /* 410 * The following REMOTE_RESET and SYS_WAKING used to sent 411 * only when BT wake up. Now they are always sent, as a 412 * recovery method to reset BT MCI's RX alignment. 413 */ 414 ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, 415 payload, 16, true, false); 416 ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0, 417 NULL, 0, true, false); 418 419 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE; 420 ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE, NULL); 421 422 /* 423 * always do this for recovery and 2G/5G toggling and LNA_TRANS 424 */ 425 ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, NULL); 426 } 427 428 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) { 429 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING; 430 431 if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_SLEEP) { 432 if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) != 433 MCI_BT_SLEEP) 434 ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, 435 NULL); 436 } 437 } 438 439 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) { 440 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING; 441 442 if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) { 443 if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) != 444 MCI_BT_AWAKE) 445 ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP, 446 NULL); 447 } 448 } 449 450 if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) || 451 (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) { 452 ar9003_mci_state(ah, MCI_STATE_RECOVER_RX, NULL); 453 skip_gpm = true; 454 } 455 456 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) { 457 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO; 458 offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET, 459 NULL); 460 } 461 462 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) { 463 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM; 464 465 while (more_data == MCI_GPM_MORE) { 466 467 pgpm = mci->gpm_buf.bf_addr; 468 offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET, 469 &more_data); 470 471 if (offset == MCI_GPM_INVALID) 472 break; 473 474 pgpm += (offset >> 2); 475 476 /* 477 * The first dword is timer. 478 * The real data starts from 2nd dword. 479 */ 480 subtype = MCI_GPM_TYPE(pgpm); 481 opcode = MCI_GPM_OPCODE(pgpm); 482 483 if (skip_gpm) 484 goto recycle; 485 486 if (MCI_GPM_IS_CAL_TYPE(subtype)) { 487 ath_mci_cal_msg(sc, subtype, (u8 *)pgpm); 488 } else { 489 switch (subtype) { 490 case MCI_GPM_COEX_AGENT: 491 ath_mci_msg(sc, opcode, (u8 *)pgpm); 492 break; 493 default: 494 break; 495 } 496 } 497 recycle: 498 MCI_GPM_RECYCLE(pgpm); 499 } 500 } 501 502 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) { 503 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL) 504 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL; 505 506 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO) 507 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO; 508 509 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) { 510 int value_dbm = ar9003_mci_state(ah, 511 MCI_STATE_CONT_RSSI_POWER, NULL); 512 513 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO; 514 515 if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX, NULL)) 516 ath_dbg(common, MCI, 517 "MCI CONT_INFO: (tx) pri = %d, pwr = %d dBm\n", 518 ar9003_mci_state(ah, 519 MCI_STATE_CONT_PRIORITY, NULL), 520 value_dbm); 521 else 522 ath_dbg(common, MCI, 523 "MCI CONT_INFO: (rx) pri = %d,pwr = %d dBm\n", 524 ar9003_mci_state(ah, 525 MCI_STATE_CONT_PRIORITY, NULL), 526 value_dbm); 527 } 528 529 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK) 530 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK; 531 532 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST) 533 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST; 534 } 535 536 if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) || 537 (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) 538 mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR | 539 AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT); 540} 541