1#ifndef B43_XMIT_H_ 2#define B43_XMIT_H_ 3 4#include "main.h" 5#include <net/mac80211.h> 6 7 8#define _b43_declare_plcp_hdr(size) \ 9 struct b43_plcp_hdr##size { \ 10 union { \ 11 __le32 data; \ 12 __u8 raw[size]; \ 13 } __packed; \ 14 } __packed 15 16/* struct b43_plcp_hdr4 */ 17_b43_declare_plcp_hdr(4); 18/* struct b43_plcp_hdr6 */ 19_b43_declare_plcp_hdr(6); 20 21#undef _b43_declare_plcp_hdr 22 23/* TX header for v4 firmware */ 24struct b43_txhdr { 25 __le32 mac_ctl; /* MAC TX control */ 26 __le16 mac_frame_ctl; /* Copy of the FrameControl field */ 27 __le16 tx_fes_time_norm; /* TX FES Time Normal */ 28 __le16 phy_ctl; /* PHY TX control */ 29 __le16 phy_ctl1; /* PHY TX control word 1 */ 30 __le16 phy_ctl1_fb; /* PHY TX control word 1 for fallback rates */ 31 __le16 phy_ctl1_rts; /* PHY TX control word 1 RTS */ 32 __le16 phy_ctl1_rts_fb; /* PHY TX control word 1 RTS for fallback rates */ 33 __u8 phy_rate; /* PHY rate */ 34 __u8 phy_rate_rts; /* PHY rate for RTS/CTS */ 35 __u8 extra_ft; /* Extra Frame Types */ 36 __u8 chan_radio_code; /* Channel Radio Code */ 37 __u8 iv[16]; /* Encryption IV */ 38 __u8 tx_receiver[6]; /* TX Frame Receiver address */ 39 __le16 tx_fes_time_fb; /* TX FES Time Fallback */ 40 struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */ 41 __le16 rts_dur_fb; /* RTS fallback duration */ 42 struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP header */ 43 __le16 dur_fb; /* Fallback duration */ 44 __le16 mimo_modelen; /* MIMO mode length */ 45 __le16 mimo_ratelen_fb; /* MIMO fallback rate length */ 46 __le32 timeout; /* Timeout */ 47 48 union { 49 /* Tested with 598.314, 644.1001 and 666.2 */ 50 struct { 51 __le16 mimo_antenna; /* MIMO antenna select */ 52 __le16 preload_size; /* Preload size */ 53 PAD_BYTES(2); 54 __le16 cookie; /* TX frame cookie */ 55 __le16 tx_status; /* TX status */ 56 __le16 max_n_mpdus; 57 __le16 max_a_bytes_mrt; 58 __le16 max_a_bytes_fbr; 59 __le16 min_m_bytes; 60 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ 61 __u8 rts_frame[16]; /* The RTS frame (if used) */ 62 PAD_BYTES(2); 63 struct b43_plcp_hdr6 plcp; /* Main PLCP header */ 64 } format_598 __packed; 65 66 /* Tested with 410.2160, 478.104 and 508.* */ 67 struct { 68 __le16 mimo_antenna; /* MIMO antenna select */ 69 __le16 preload_size; /* Preload size */ 70 PAD_BYTES(2); 71 __le16 cookie; /* TX frame cookie */ 72 __le16 tx_status; /* TX status */ 73 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ 74 __u8 rts_frame[16]; /* The RTS frame (if used) */ 75 PAD_BYTES(2); 76 struct b43_plcp_hdr6 plcp; /* Main PLCP header */ 77 } format_410 __packed; 78 79 /* Tested with 351.126 */ 80 struct { 81 PAD_BYTES(2); 82 __le16 cookie; /* TX frame cookie */ 83 __le16 tx_status; /* TX status */ 84 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ 85 __u8 rts_frame[16]; /* The RTS frame (if used) */ 86 PAD_BYTES(2); 87 struct b43_plcp_hdr6 plcp; /* Main PLCP header */ 88 } format_351 __packed; 89 90 } __packed; 91} __packed; 92 93struct b43_tx_legacy_rate_phy_ctl_entry { 94 u8 bitrate; 95 u16 coding_rate; 96 u16 modulation; 97}; 98 99/* MAC TX control */ 100#define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */ 101#define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */ 102#define B43_TXH_MAC_KEYIDX_SHIFT 20 103#define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */ 104#define B43_TXH_MAC_KEYALG_SHIFT 16 105#define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */ 106#define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */ 107#define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */ 108#define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */ 109#define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */ 110#define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */ 111#define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */ 112#define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */ 113#define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */ 114#define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */ 115#define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */ 116#define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */ 117#define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */ 118#define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */ 119#define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */ 120#define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */ 121#define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */ 122#define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */ 123#define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */ 124 125/* Extra Frame Types */ 126#define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */ 127#define B43_TXH_EFT_FB_CCK 0x00 /* CCK */ 128#define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */ 129#define B43_TXH_EFT_FB_EWC 0x02 /* EWC */ 130#define B43_TXH_EFT_FB_N 0x03 /* N */ 131#define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */ 132#define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */ 133#define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */ 134#define B43_TXH_EFT_RTS_EWC 0x08 /* EWC */ 135#define B43_TXH_EFT_RTS_N 0x0C /* N */ 136#define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */ 137#define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */ 138#define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */ 139#define B43_TXH_EFT_RTSFB_EWC 0x20 /* EWC */ 140#define B43_TXH_EFT_RTSFB_N 0x30 /* N */ 141 142/* PHY TX control word */ 143#define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */ 144#define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */ 145#define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */ 146#define B43_TXH_PHY_ENC_EWC 0x0002 /* EWC */ 147#define B43_TXH_PHY_ENC_N 0x0003 /* N */ 148#define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */ 149#define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */ 150#define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */ 151#define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */ 152#define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */ 153#define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */ 154#define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */ 155#define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */ 156#define B43_TXH_PHY_TXPWR_SHIFT 10 157 158/* PHY TX control word 1 */ 159#define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */ 160#define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */ 161#define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */ 162#define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */ 163#define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */ 164#define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */ 165#define B43_TXH_PHY1_BW_40DUP 0x0005 /* 50 MHz duplicate */ 166#define B43_TXH_PHY1_MODE 0x0038 /* Mode */ 167#define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */ 168#define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */ 169#define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */ 170#define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */ 171#define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */ 172#define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */ 173#define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */ 174#define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */ 175#define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */ 176#define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */ 177#define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */ 178#define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */ 179#define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */ 180#define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */ 181#define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */ 182#define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */ 183#define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */ 184 185 186static inline 187size_t b43_txhdr_size(struct b43_wldev *dev) 188{ 189 switch (dev->fw.hdr_format) { 190 case B43_FW_HDR_598: 191 return 112 + sizeof(struct b43_plcp_hdr6); 192 case B43_FW_HDR_410: 193 return 104 + sizeof(struct b43_plcp_hdr6); 194 case B43_FW_HDR_351: 195 return 100 + sizeof(struct b43_plcp_hdr6); 196 } 197 return 0; 198} 199 200 201int b43_generate_txhdr(struct b43_wldev *dev, 202 u8 * txhdr, 203 struct sk_buff *skb_frag, 204 struct ieee80211_tx_info *txctl, u16 cookie); 205 206/* Transmit Status */ 207struct b43_txstatus { 208 u16 cookie; /* The cookie from the txhdr */ 209 u16 seq; /* Sequence number */ 210 u8 phy_stat; /* PHY TX status */ 211 u8 frame_count; /* Frame transmit count */ 212 u8 rts_count; /* RTS transmit count */ 213 u8 supp_reason; /* Suppression reason */ 214 /* flags */ 215 u8 pm_indicated; /* PM mode indicated to AP */ 216 u8 intermediate; /* Intermediate status notification (not final) */ 217 u8 for_ampdu; /* Status is for an AMPDU (afterburner) */ 218 u8 acked; /* Wireless ACK received */ 219}; 220 221/* txstatus supp_reason values */ 222enum { 223 B43_TXST_SUPP_NONE, /* Not suppressed */ 224 B43_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */ 225 B43_TXST_SUPP_FLUSH, /* Suppressed due to flush request */ 226 B43_TXST_SUPP_PREV, /* Previous fragment failed */ 227 B43_TXST_SUPP_CHAN, /* Channel mismatch */ 228 B43_TXST_SUPP_LIFE, /* Lifetime expired */ 229 B43_TXST_SUPP_UNDER, /* Buffer underflow */ 230 B43_TXST_SUPP_ABNACK, /* Afterburner NACK */ 231}; 232 233/* Receive header for v4 firmware. */ 234struct b43_rxhdr_fw4 { 235 __le16 frame_len; /* Frame length */ 236 PAD_BYTES(2); 237 __le16 phy_status0; /* PHY RX Status 0 */ 238 union { 239 /* RSSI for A/B/G-PHYs */ 240 struct { 241 __u8 jssi; /* PHY RX Status 1: JSSI */ 242 __u8 sig_qual; /* PHY RX Status 1: Signal Quality */ 243 } __packed; 244 245 /* RSSI for N-PHYs */ 246 struct { 247 __s8 power0; /* PHY RX Status 1: Power 0 */ 248 __s8 power1; /* PHY RX Status 1: Power 1 */ 249 } __packed; 250 } __packed; 251 union { 252 /* HT-PHY */ 253 struct { 254 PAD_BYTES(1); 255 __s8 phy_ht_power0; 256 } __packed; 257 258 /* RSSI for N-PHYs */ 259 struct { 260 __s8 power2; 261 PAD_BYTES(1); 262 } __packed; 263 264 __le16 phy_status2; /* PHY RX Status 2 */ 265 } __packed; 266 union { 267 /* HT-PHY */ 268 struct { 269 __s8 phy_ht_power1; 270 __s8 phy_ht_power2; 271 } __packed; 272 273 __le16 phy_status3; /* PHY RX Status 3 */ 274 } __packed; 275 union { 276 /* Tested with 598.314, 644.1001 and 666.2 */ 277 struct { 278 __le16 phy_status4; /* PHY RX Status 4 */ 279 __le16 phy_status5; /* PHY RX Status 5 */ 280 __le32 mac_status; /* MAC RX status */ 281 __le16 mac_time; 282 __le16 channel; 283 } format_598 __packed; 284 285 /* Tested with 351.126, 410.2160, 478.104 and 508.* */ 286 struct { 287 __le32 mac_status; /* MAC RX status */ 288 __le16 mac_time; 289 __le16 channel; 290 } format_351 __packed; 291 } __packed; 292} __packed; 293 294/* PHY RX Status 0 */ 295#define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */ 296#define B43_RX_PHYST0_PLCPHCF 0x0200 297#define B43_RX_PHYST0_PLCPFV 0x0100 298#define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */ 299#define B43_RX_PHYST0_LCRS 0x0040 300#define B43_RX_PHYST0_ANT 0x0020 /* Antenna */ 301#define B43_RX_PHYST0_UNSRATE 0x0010 302#define B43_RX_PHYST0_CLIP 0x000C 303#define B43_RX_PHYST0_CLIP_SHIFT 2 304#define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */ 305#define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */ 306#define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */ 307#define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */ 308#define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */ 309 310/* PHY RX Status 2 */ 311#define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */ 312#define B43_RX_PHYST2_LNAG_SHIFT 14 313#define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */ 314#define B43_RX_PHYST2_PNAG_SHIFT 10 315#define B43_RX_PHYST2_FOFF 0x03FF /* F offset */ 316 317/* PHY RX Status 3 */ 318#define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */ 319#define B43_RX_PHYST3_DIGG_SHIFT 11 320#define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */ 321 322/* MAC RX Status */ 323#define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */ 324#define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */ 325#define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */ 326#define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */ 327#define B43_RX_MAC_AGGTYPE_SHIFT 17 328#define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */ 329#define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */ 330#define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */ 331#define B43_RX_MAC_KEYIDX_SHIFT 5 332#define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */ 333#define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */ 334#define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */ 335#define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */ 336#define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */ 337 338/* RX channel */ 339#define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */ 340#define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */ 341#define B43_RX_CHAN_ID 0x07F8 /* Channel ID */ 342#define B43_RX_CHAN_ID_SHIFT 3 343#define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */ 344 345 346u8 b43_plcp_get_ratecode_cck(const u8 bitrate); 347u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate); 348 349void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp, 350 const u16 octets, const u8 bitrate); 351 352void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr); 353 354void b43_handle_txstatus(struct b43_wldev *dev, 355 const struct b43_txstatus *status); 356bool b43_fill_txstatus_report(struct b43_wldev *dev, 357 struct ieee80211_tx_info *report, 358 const struct b43_txstatus *status); 359 360void b43_tx_suspend(struct b43_wldev *dev); 361void b43_tx_resume(struct b43_wldev *dev); 362 363 364/* Helper functions for converting the key-table index from "firmware-format" 365 * to "raw-format" and back. The firmware API changed for this at some revision. 366 * We need to account for that here. */ 367static inline int b43_new_kidx_api(struct b43_wldev *dev) 368{ 369 /* FIXME: Not sure the change was at rev 351 */ 370 return (dev->fw.rev >= 351); 371} 372static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx) 373{ 374 u8 firmware_kidx; 375 if (b43_new_kidx_api(dev)) { 376 firmware_kidx = raw_kidx; 377 } else { 378 if (raw_kidx >= 4) /* Is per STA key? */ 379 firmware_kidx = raw_kidx - 4; 380 else 381 firmware_kidx = raw_kidx; /* TX default key */ 382 } 383 return firmware_kidx; 384} 385static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx) 386{ 387 u8 raw_kidx; 388 if (b43_new_kidx_api(dev)) 389 raw_kidx = firmware_kidx; 390 else 391 raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */ 392 return raw_kidx; 393} 394 395/* struct b43_private_tx_info - TX info private to b43. 396 * The structure is placed in (struct ieee80211_tx_info *)->rate_driver_data 397 * 398 * @bouncebuffer: DMA Bouncebuffer (if used) 399 */ 400struct b43_private_tx_info { 401 void *bouncebuffer; 402}; 403 404static inline struct b43_private_tx_info * 405b43_get_priv_tx_info(struct ieee80211_tx_info *info) 406{ 407 BUILD_BUG_ON(sizeof(struct b43_private_tx_info) > 408 sizeof(info->rate_driver_data)); 409 return (struct b43_private_tx_info *)info->rate_driver_data; 410} 411 412#endif /* B43_XMIT_H_ */ 413