1/* 2 * Misc utility routines for accessing the SOC Interconnects 3 * of Broadcom HNBU chips. 4 * 5 * Copyright (C) 1999-2012, Broadcom Corporation 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * $Id: siutils.h 347614 2012-07-27 10:24:51Z $ 26 */ 27 28#ifndef _siutils_h_ 29#define _siutils_h_ 30 31 32struct si_pub { 33 uint socitype; 34 35 uint bustype; 36 uint buscoretype; 37 uint buscorerev; 38 uint buscoreidx; 39 int ccrev; 40 uint32 cccaps; 41 uint32 cccaps_ext; 42 int pmurev; 43 uint32 pmucaps; 44 uint boardtype; 45 uint boardrev; 46 uint boardvendor; 47 uint boardflags; 48 uint boardflags2; 49 uint chip; 50 uint chiprev; 51 uint chippkg; 52 uint32 chipst; 53 bool issim; 54 uint socirev; 55 bool pci_pr32414; 56 57}; 58 59 60typedef const struct si_pub si_t; 61 62 63 64#define SI_OSH NULL 65 66#define BADIDX (SI_MAXCORES + 1) 67 68 69#define XTAL 0x1 70#define PLL 0x2 71 72 73#define CLK_FAST 0 74#define CLK_DYNAMIC 2 75 76 77#define GPIO_DRV_PRIORITY 0 78#define GPIO_APP_PRIORITY 1 79#define GPIO_HI_PRIORITY 2 80 81 82#define GPIO_PULLUP 0 83#define GPIO_PULLDN 1 84 85 86#define GPIO_REGEVT 0 87#define GPIO_REGEVT_INTMSK 1 88#define GPIO_REGEVT_INTPOL 2 89 90 91#define SI_DEVPATH_BUFSZ 16 92 93 94#define SI_DOATTACH 1 95#define SI_PCIDOWN 2 96#define SI_PCIUP 3 97 98#define ISSIM_ENAB(sih) 0 99 100 101#if defined(BCMPMUCTL) 102#define PMUCTL_ENAB(sih) (BCMPMUCTL) 103#else 104#define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU) 105#endif 106 107 108#if defined(BCMPMUCTL) && BCMPMUCTL 109#define CCCTL_ENAB(sih) (0) 110#define CCPLL_ENAB(sih) (0) 111#else 112#define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL) 113#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK) 114#endif 115 116typedef void (*gpio_handler_t)(uint32 stat, void *arg); 117 118#define CC_BTCOEX_EN_MASK 0x01 119 120#define GPIO_CTRL_EPA_EN_MASK 0x40 121 122#define GPIO_CTRL_5_6_EN_MASK 0x60 123#define GPIO_CTRL_7_6_EN_MASK 0xC0 124#define GPIO_OUT_7_EN_MASK 0x80 125 126 127 128#define SI_CR4_CAP (0x04) 129#define SI_CR4_BANKIDX (0x40) 130#define SI_CR4_BANKINFO (0x44) 131 132#define ARMCR4_TCBBNB_MASK 0xf0 133#define ARMCR4_TCBBNB_SHIFT 4 134#define ARMCR4_TCBANB_MASK 0xf 135#define ARMCR4_TCBANB_SHIFT 0 136 137#define SICF_CPUHALT (0x0020) 138#define ARMCR4_BSZ_MASK 0x3f 139#define ARMCR4_BSZ_MULT 8192 140 141 142 143extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, 144 void *sdh, char **vars, uint *varsz); 145extern si_t *si_kattach(osl_t *osh); 146extern void si_detach(si_t *sih); 147extern bool si_pci_war16165(si_t *sih); 148 149extern uint si_corelist(si_t *sih, uint coreid[]); 150extern uint si_coreid(si_t *sih); 151extern uint si_flag(si_t *sih); 152extern uint si_intflag(si_t *sih); 153extern uint si_coreidx(si_t *sih); 154extern uint si_coreunit(si_t *sih); 155extern uint si_corevendor(si_t *sih); 156extern uint si_corerev(si_t *sih); 157extern void *si_osh(si_t *sih); 158extern void si_setosh(si_t *sih, osl_t *osh); 159extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 160extern void *si_coreregs(si_t *sih); 161extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 162extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val); 163extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 164extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val); 165extern bool si_iscoreup(si_t *sih); 166extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit); 167extern void *si_setcoreidx(si_t *sih, uint coreidx); 168extern void *si_setcore(si_t *sih, uint coreid, uint coreunit); 169extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val); 170extern void si_restore_core(si_t *sih, uint coreid, uint intr_val); 171extern int si_numaddrspaces(si_t *sih); 172extern uint32 si_addrspace(si_t *sih, uint asidx); 173extern uint32 si_addrspacesize(si_t *sih, uint asidx); 174extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size); 175extern int si_corebist(si_t *sih); 176extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 177extern void si_core_disable(si_t *sih, uint32 bits); 178extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m); 179extern bool si_read_pmu_autopll(si_t *sih); 180extern uint32 si_clock(si_t *sih); 181extern uint32 si_alp_clock(si_t *sih); 182extern uint32 si_ilp_clock(si_t *sih); 183extern void si_pci_setup(si_t *sih, uint coremask); 184extern void si_pcmcia_init(si_t *sih); 185extern void si_setint(si_t *sih, int siflag); 186extern bool si_backplane64(si_t *sih); 187extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, 188 void *intrsenabled_fn, void *intr_arg); 189extern void si_deregister_intr_callback(si_t *sih); 190extern void si_clkctl_init(si_t *sih); 191extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih); 192extern bool si_clkctl_cc(si_t *sih, uint mode); 193extern int si_clkctl_xtal(si_t *sih, uint what, bool on); 194extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val); 195extern void si_btcgpiowar(si_t *sih); 196extern bool si_deviceremoved(si_t *sih); 197extern uint32 si_socram_size(si_t *sih); 198extern uint32 si_socdevram_size(si_t *sih); 199extern uint32 si_socram_srmem_size(si_t *sih); 200extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect, uint8 *remap); 201extern bool si_socdevram_pkg(si_t *sih); 202extern bool si_socdevram_remap_isenb(si_t *sih); 203extern uint32 si_socdevram_remap_size(si_t *sih); 204 205extern void si_watchdog(si_t *sih, uint ticks); 206extern void si_watchdog_ms(si_t *sih, uint32 ms); 207extern uint32 si_watchdog_msticks(void); 208extern void *si_gpiosetcore(si_t *sih); 209extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority); 210extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority); 211extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority); 212extern uint32 si_gpioin(si_t *sih); 213extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority); 214extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority); 215extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val); 216extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority); 217extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority); 218extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val); 219extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val); 220extern uint32 si_gpio_int_enable(si_t *sih, bool enable); 221 222 223extern void *si_gpio_handler_register(si_t *sih, uint32 e, bool lev, gpio_handler_t cb, void *arg); 224extern void si_gpio_handler_unregister(si_t *sih, void* gpioh); 225extern void si_gpio_handler_process(si_t *sih); 226 227 228extern bool si_pci_pmecap(si_t *sih); 229struct osl_info; 230extern bool si_pci_fastpmecap(struct osl_info *osh); 231extern bool si_pci_pmestat(si_t *sih); 232extern void si_pci_pmeclr(si_t *sih); 233extern void si_pci_pmeen(si_t *sih); 234extern void si_pci_pmestatclr(si_t *sih); 235extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset); 236 237extern void si_sdio_init(si_t *sih); 238 239extern uint16 si_d11_devid(si_t *sih); 240extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice, 241 uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader); 242 243#define si_eci(sih) 0 244static INLINE void * si_eci_init(si_t *sih) {return NULL;} 245#define si_eci_notify_bt(sih, type, val) (0) 246#define si_seci(sih) 0 247#define si_seci_upd(sih, a) do {} while (0) 248static INLINE void * si_seci_init(si_t *sih, uint8 use_seci) {return NULL;} 249#define si_seci_down(sih) do {} while (0) 250 251 252extern bool si_is_otp_disabled(si_t *sih); 253extern bool si_is_otp_powered(si_t *sih); 254extern void si_otp_power(si_t *sih, bool on); 255 256 257extern bool si_is_sprom_available(si_t *sih); 258extern bool si_is_sprom_enabled(si_t *sih); 259extern void si_sprom_enable(si_t *sih, bool enable); 260 261 262extern int si_cis_source(si_t *sih); 263#define CIS_DEFAULT 0 264#define CIS_SROM 1 265#define CIS_OTP 2 266 267 268#define DEFAULT_FAB 0x0 269#define CSM_FAB7 0x1 270#define TSMC_FAB12 0x2 271#define SMIC_FAB4 0x3 272extern int si_otp_fabid(si_t *sih, uint16 *fabid, bool rw); 273extern uint16 si_fabid(si_t *sih); 274 275 276extern int si_devpath(si_t *sih, char *path, int size); 277 278extern char *si_getdevpathvar(si_t *sih, const char *name); 279extern int si_getdevpathintvar(si_t *sih, const char *name); 280extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len, const char *name); 281 282 283extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val); 284extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val); 285extern void si_war42780_clkreq(si_t *sih, bool clkreq); 286extern void si_pci_down(si_t *sih); 287extern void si_pci_up(si_t *sih); 288extern void si_pci_sleep(si_t *sih); 289extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm); 290extern void si_pcie_power_save_enable(si_t *sih, bool enable); 291extern void si_pcie_extendL1timer(si_t *sih, bool extend); 292extern int si_pci_fixcfg(si_t *sih); 293extern void si_chippkg_set(si_t *sih, uint); 294 295extern void si_chipcontrl_btshd0_4331(si_t *sih, bool on); 296extern void si_chipcontrl_restore(si_t *sih, uint32 val); 297extern uint32 si_chipcontrl_read(si_t *sih); 298extern void si_chipcontrl_epa4331(si_t *sih, bool on); 299extern void si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl); 300extern void si_chipcontrl_srom4360(si_t *sih, bool on); 301 302extern void si_epa_4313war(si_t *sih); 303extern void si_btc_enable_chipcontrol(si_t *sih); 304 305extern void si_btcombo_p250_4313_war(si_t *sih); 306extern void si_btcombo_43228_war(si_t *sih); 307extern void si_clk_pmu_htavail_set(si_t *sih, bool set_clear); 308extern uint si_pll_reset(si_t *sih); 309 310 311extern bool si_taclear(si_t *sih, bool details); 312 313 314 315extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type); 316extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val); 317extern void si_pcie_set_request_size(si_t *sih, uint16 size); 318extern uint16 si_pcie_get_request_size(si_t *sih); 319extern uint16 si_pcie_get_ssid(si_t *sih); 320extern uint32 si_pcie_get_bar0(si_t *sih); 321extern int si_pcie_configspace_cache(si_t *sih); 322extern int si_pcie_configspace_restore(si_t *sih); 323extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size); 324 325char *si_getnvramflvar(si_t *sih, const char *name); 326 327 328extern uint32 si_tcm_size(si_t *sih); 329 330extern int si_set_sromctl(si_t *sih, uint32 value); 331extern uint32 si_get_sromctl(si_t *sih); 332#endif 333