1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#include "../wifi.h" 31#include "../core.h" 32#include "../pci.h" 33#include "reg.h" 34#include "def.h" 35#include "phy.h" 36#include "dm.h" 37#include "hw.h" 38#include "rf.h" 39#include "sw.h" 40#include "trx.h" 41#include "led.h" 42 43#include <linux/module.h> 44 45static void rtl92c_init_aspm_vars(struct ieee80211_hw *hw) 46{ 47 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 48 49 /*close ASPM for AMD defaultly */ 50 rtlpci->const_amdpci_aspm = 0; 51 52 /* 53 * ASPM PS mode. 54 * 0 - Disable ASPM, 55 * 1 - Enable ASPM without Clock Req, 56 * 2 - Enable ASPM with Clock Req, 57 * 3 - Alwyas Enable ASPM with Clock Req, 58 * 4 - Always Enable ASPM without Clock Req. 59 * set defult to RTL8192CE:3 RTL8192E:2 60 * */ 61 rtlpci->const_pci_aspm = 3; 62 63 /*Setting for PCI-E device */ 64 rtlpci->const_devicepci_aspm_setting = 0x03; 65 66 /*Setting for PCI-E bridge */ 67 rtlpci->const_hostpci_aspm_setting = 0x02; 68 69 /* 70 * In Hw/Sw Radio Off situation. 71 * 0 - Default, 72 * 1 - From ASPM setting without low Mac Pwr, 73 * 2 - From ASPM setting with low Mac Pwr, 74 * 3 - Bus D3 75 * set default to RTL8192CE:0 RTL8192SE:2 76 */ 77 rtlpci->const_hwsw_rfoff_d3 = 0; 78 79 /* 80 * This setting works for those device with 81 * backdoor ASPM setting such as EPHY setting. 82 * 0 - Not support ASPM, 83 * 1 - Support ASPM, 84 * 2 - According to chipset. 85 */ 86 rtlpci->const_support_pciaspm = 1; 87} 88 89int rtl92c_init_sw_vars(struct ieee80211_hw *hw) 90{ 91 int err; 92 struct rtl_priv *rtlpriv = rtl_priv(hw); 93 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 94 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 95 96 rtl8192ce_bt_reg_init(hw); 97 98 rtlpriv->dm.dm_initialgain_enable = true; 99 rtlpriv->dm.dm_flag = 0; 100 rtlpriv->dm.disable_framebursting = false; 101 rtlpriv->dm.thermalvalue = 0; 102 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); 103 104 /* compatible 5G band 88ce just 2.4G band & smsp */ 105 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G; 106 rtlpriv->rtlhal.bandset = BAND_ON_2_4G; 107 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY; 108 109 rtlpci->receive_config = (RCR_APPFCS | 110 RCR_AMF | 111 RCR_ADF | 112 RCR_APP_MIC | 113 RCR_APP_ICV | 114 RCR_AICV | 115 RCR_ACRC32 | 116 RCR_AB | 117 RCR_AM | 118 RCR_APM | 119 RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0); 120 121 rtlpci->irq_mask[0] = 122 (u32) (IMR_ROK | 123 IMR_VODOK | 124 IMR_VIDOK | 125 IMR_BEDOK | 126 IMR_BKDOK | 127 IMR_MGNTDOK | 128 IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0); 129 130 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0); 131 132 /* for debug level */ 133 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug; 134 /* for LPS & IPS */ 135 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 136 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 137 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 138 if (!rtlpriv->psc.inactiveps) 139 pr_info("rtl8192ce: Power Save off (module option)\n"); 140 if (!rtlpriv->psc.fwctrl_lps) 141 pr_info("rtl8192ce: FW Power Save off (module option)\n"); 142 rtlpriv->psc.reg_fwctrl_lps = 3; 143 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 144 /* for ASPM, you can close aspm through 145 * set const_support_pciaspm = 0 */ 146 rtl92c_init_aspm_vars(hw); 147 148 if (rtlpriv->psc.reg_fwctrl_lps == 1) 149 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 150 else if (rtlpriv->psc.reg_fwctrl_lps == 2) 151 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; 152 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 153 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 154 155 /* for firmware buf */ 156 rtlpriv->rtlhal.pfirmware = vzalloc(0x4000); 157 if (!rtlpriv->rtlhal.pfirmware) { 158 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 159 "Can't alloc buffer for fw\n"); 160 return 1; 161 } 162 163 /* request fw */ 164 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && 165 !IS_92C_SERIAL(rtlhal->version)) 166 rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cfwU.bin"; 167 else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) 168 rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cfwU_B.bin"; 169 170 rtlpriv->max_fw_size = 0x4000; 171 pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name); 172 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name, 173 rtlpriv->io.dev, GFP_KERNEL, hw, 174 rtl_fw_cb); 175 if (err) { 176 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 177 "Failed to request firmware!\n"); 178 return 1; 179 } 180 181 return 0; 182} 183 184void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw) 185{ 186 struct rtl_priv *rtlpriv = rtl_priv(hw); 187 188 if (rtlpriv->rtlhal.pfirmware) { 189 vfree(rtlpriv->rtlhal.pfirmware); 190 rtlpriv->rtlhal.pfirmware = NULL; 191 } 192} 193 194static struct rtl_hal_ops rtl8192ce_hal_ops = { 195 .init_sw_vars = rtl92c_init_sw_vars, 196 .deinit_sw_vars = rtl92c_deinit_sw_vars, 197 .read_eeprom_info = rtl92ce_read_eeprom_info, 198 .interrupt_recognized = rtl92ce_interrupt_recognized, 199 .hw_init = rtl92ce_hw_init, 200 .hw_disable = rtl92ce_card_disable, 201 .hw_suspend = rtl92ce_suspend, 202 .hw_resume = rtl92ce_resume, 203 .enable_interrupt = rtl92ce_enable_interrupt, 204 .disable_interrupt = rtl92ce_disable_interrupt, 205 .set_network_type = rtl92ce_set_network_type, 206 .set_chk_bssid = rtl92ce_set_check_bssid, 207 .set_qos = rtl92ce_set_qos, 208 .set_bcn_reg = rtl92ce_set_beacon_related_registers, 209 .set_bcn_intv = rtl92ce_set_beacon_interval, 210 .update_interrupt_mask = rtl92ce_update_interrupt_mask, 211 .get_hw_reg = rtl92ce_get_hw_reg, 212 .set_hw_reg = rtl92ce_set_hw_reg, 213 .update_rate_tbl = rtl92ce_update_hal_rate_tbl, 214 .fill_tx_desc = rtl92ce_tx_fill_desc, 215 .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc, 216 .query_rx_desc = rtl92ce_rx_query_desc, 217 .set_channel_access = rtl92ce_update_channel_access_setting, 218 .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking, 219 .set_bw_mode = rtl92c_phy_set_bw_mode, 220 .switch_channel = rtl92c_phy_sw_chnl, 221 .dm_watchdog = rtl92c_dm_watchdog, 222 .scan_operation_backup = rtl92c_phy_scan_operation_backup, 223 .set_rf_power_state = rtl92c_phy_set_rf_power_state, 224 .led_control = rtl92ce_led_control, 225 .set_desc = rtl92ce_set_desc, 226 .get_desc = rtl92ce_get_desc, 227 .tx_polling = rtl92ce_tx_polling, 228 .enable_hw_sec = rtl92ce_enable_hw_security_config, 229 .set_key = rtl92ce_set_key, 230 .init_sw_leds = rtl92ce_init_sw_leds, 231 .get_bbreg = rtl92c_phy_query_bb_reg, 232 .set_bbreg = rtl92c_phy_set_bb_reg, 233 .set_rfreg = rtl92ce_phy_set_rf_reg, 234 .get_rfreg = rtl92c_phy_query_rf_reg, 235 .phy_rf6052_config = rtl92ce_phy_rf6052_config, 236 .phy_rf6052_set_cck_txpower = rtl92ce_phy_rf6052_set_cck_txpower, 237 .phy_rf6052_set_ofdm_txpower = rtl92ce_phy_rf6052_set_ofdm_txpower, 238 .config_bb_with_headerfile = _rtl92ce_phy_config_bb_with_headerfile, 239 .config_bb_with_pgheaderfile = _rtl92ce_phy_config_bb_with_pgheaderfile, 240 .phy_lc_calibrate = _rtl92ce_phy_lc_calibrate, 241 .phy_set_bw_mode_callback = rtl92ce_phy_set_bw_mode_callback, 242 .dm_dynamic_txpower = rtl92ce_dm_dynamic_txpower, 243}; 244 245static struct rtl_mod_params rtl92ce_mod_params = { 246 .sw_crypto = false, 247 .inactiveps = true, 248 .swctrl_lps = false, 249 .fwctrl_lps = true, 250 .debug = DBG_EMERG, 251}; 252 253static struct rtl_hal_cfg rtl92ce_hal_cfg = { 254 .bar_id = 2, 255 .write_readback = true, 256 .name = "rtl92c_pci", 257 .fw_name = "rtlwifi/rtl8192cfw.bin", 258 .ops = &rtl8192ce_hal_ops, 259 .mod_params = &rtl92ce_mod_params, 260 261 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 262 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 263 .maps[SYS_CLK] = REG_SYS_CLKR, 264 .maps[MAC_RCR_AM] = AM, 265 .maps[MAC_RCR_AB] = AB, 266 .maps[MAC_RCR_ACRC32] = ACRC32, 267 .maps[MAC_RCR_ACF] = ACF, 268 .maps[MAC_RCR_AAP] = AAP, 269 270 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 271 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 272 .maps[EFUSE_CLK] = 0, 273 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, 274 .maps[EFUSE_PWC_EV12V] = PWC_EV12V, 275 .maps[EFUSE_FEN_ELDR] = FEN_ELDR, 276 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, 277 .maps[EFUSE_ANA8M] = EFUSE_ANA8M, 278 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, 279 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, 280 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, 281 282 .maps[RWCAM] = REG_CAMCMD, 283 .maps[WCAMI] = REG_CAMWRITE, 284 .maps[RCAMO] = REG_CAMREAD, 285 .maps[CAMDBG] = REG_CAMDBG, 286 .maps[SECR] = REG_SECCFG, 287 .maps[SEC_CAM_NONE] = CAM_NONE, 288 .maps[SEC_CAM_WEP40] = CAM_WEP40, 289 .maps[SEC_CAM_TKIP] = CAM_TKIP, 290 .maps[SEC_CAM_AES] = CAM_AES, 291 .maps[SEC_CAM_WEP104] = CAM_WEP104, 292 293 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, 294 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, 295 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, 296 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 297 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 298 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 299 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, 300 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 301 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 302 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 303 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, 304 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 305 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 306 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 307 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, 308 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, 309 310 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, 311 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, 312 .maps[RTL_IMR_BcnInt] = IMR_BCNINT, 313 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, 314 .maps[RTL_IMR_RDU] = IMR_RDU, 315 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, 316 .maps[RTL_IMR_BDOK] = IMR_BDOK, 317 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, 318 .maps[RTL_IMR_TBDER] = IMR_TBDER, 319 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, 320 .maps[RTL_IMR_TBDOK] = IMR_TBDOK, 321 .maps[RTL_IMR_BKDOK] = IMR_BKDOK, 322 .maps[RTL_IMR_BEDOK] = IMR_BEDOK, 323 .maps[RTL_IMR_VIDOK] = IMR_VIDOK, 324 .maps[RTL_IMR_VODOK] = IMR_VODOK, 325 .maps[RTL_IMR_ROK] = IMR_ROK, 326 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER), 327 328 .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M, 329 .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M, 330 .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M, 331 .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M, 332 .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M, 333 .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M, 334 .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M, 335 .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M, 336 .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M, 337 .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M, 338 .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M, 339 .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M, 340 341 .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7, 342 .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15, 343}; 344 345DEFINE_PCI_DEVICE_TABLE(rtl92ce_pci_ids) = { 346 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)}, 347 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)}, 348 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)}, 349 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)}, 350 {}, 351}; 352 353MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids); 354 355MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 356MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 357MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); 358MODULE_LICENSE("GPL"); 359MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless"); 360MODULE_FIRMWARE("rtlwifi/rtl8192cfw.bin"); 361MODULE_FIRMWARE("rtlwifi/rtl8192cfwU.bin"); 362MODULE_FIRMWARE("rtlwifi/rtl8192cfwU_B.bin"); 363 364module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444); 365module_param_named(debug, rtl92ce_mod_params.debug, int, 0444); 366module_param_named(ips, rtl92ce_mod_params.inactiveps, bool, 0444); 367module_param_named(swlps, rtl92ce_mod_params.swctrl_lps, bool, 0444); 368module_param_named(fwlps, rtl92ce_mod_params.fwctrl_lps, bool, 0444); 369MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 370MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 371MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); 372MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); 373MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)"); 374 375static const struct dev_pm_ops rtlwifi_pm_ops = { 376 .suspend = rtl_pci_suspend, 377 .resume = rtl_pci_resume, 378 .freeze = rtl_pci_suspend, 379 .thaw = rtl_pci_resume, 380 .poweroff = rtl_pci_suspend, 381 .restore = rtl_pci_resume, 382}; 383 384static struct pci_driver rtl92ce_driver = { 385 .name = KBUILD_MODNAME, 386 .id_table = rtl92ce_pci_ids, 387 .probe = rtl_pci_probe, 388 .remove = rtl_pci_disconnect, 389 .driver.pm = &rtlwifi_pm_ops, 390}; 391 392static int __init rtl92ce_module_init(void) 393{ 394 int ret; 395 396 ret = pci_register_driver(&rtl92ce_driver); 397 if (ret) 398 RT_ASSERT(false, "No device found\n"); 399 400 return ret; 401} 402 403static void __exit rtl92ce_module_exit(void) 404{ 405 pci_unregister_driver(&rtl92ce_driver); 406} 407 408module_init(rtl92ce_module_init); 409module_exit(rtl92ce_module_exit); 410