1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#include "../wifi.h" 31#include "../core.h" 32#include "../pci.h" 33#include "../base.h" 34#include "../pci.h" 35#include "reg.h" 36#include "def.h" 37#include "phy.h" 38#include "dm.h" 39#include "fw.h" 40#include "hw.h" 41#include "sw.h" 42#include "trx.h" 43#include "led.h" 44 45#include <linux/module.h> 46 47static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw) 48{ 49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 50 51 /*close ASPM for AMD defaultly */ 52 rtlpci->const_amdpci_aspm = 0; 53 54 /* 55 * ASPM PS mode. 56 * 0 - Disable ASPM, 57 * 1 - Enable ASPM without Clock Req, 58 * 2 - Enable ASPM with Clock Req, 59 * 3 - Alwyas Enable ASPM with Clock Req, 60 * 4 - Always Enable ASPM without Clock Req. 61 * set defult to RTL8192CE:3 RTL8192E:2 62 * */ 63 rtlpci->const_pci_aspm = 2; 64 65 /*Setting for PCI-E device */ 66 rtlpci->const_devicepci_aspm_setting = 0x03; 67 68 /*Setting for PCI-E bridge */ 69 rtlpci->const_hostpci_aspm_setting = 0x02; 70 71 /* 72 * In Hw/Sw Radio Off situation. 73 * 0 - Default, 74 * 1 - From ASPM setting without low Mac Pwr, 75 * 2 - From ASPM setting with low Mac Pwr, 76 * 3 - Bus D3 77 * set default to RTL8192CE:0 RTL8192SE:2 78 */ 79 rtlpci->const_hwsw_rfoff_d3 = 2; 80 81 /* 82 * This setting works for those device with 83 * backdoor ASPM setting such as EPHY setting. 84 * 0 - Not support ASPM, 85 * 1 - Support ASPM, 86 * 2 - According to chipset. 87 */ 88 rtlpci->const_support_pciaspm = 2; 89} 90 91static void rtl92se_fw_cb(const struct firmware *firmware, void *context) 92{ 93 struct ieee80211_hw *hw = context; 94 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 95 struct rtl_priv *rtlpriv = rtl_priv(hw); 96 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 97 struct rt_firmware *pfirmware = NULL; 98 int err; 99 100 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 101 "Firmware callback routine entered!\n"); 102 complete(&rtlpriv->firmware_loading_complete); 103 if (!firmware) { 104 pr_err("Firmware %s not available\n", rtlpriv->cfg->fw_name); 105 rtlpriv->max_fw_size = 0; 106 return; 107 } 108 if (firmware->size > rtlpriv->max_fw_size) { 109 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 110 "Firmware is too big!\n"); 111 rtlpriv->max_fw_size = 0; 112 release_firmware(firmware); 113 return; 114 } 115 pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware; 116 memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size); 117 pfirmware->sz_fw_tmpbufferlen = firmware->size; 118 release_firmware(firmware); 119 120 err = ieee80211_register_hw(hw); 121 if (err) { 122 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 123 "Can't register mac80211 hw\n"); 124 return; 125 } else { 126 rtlpriv->mac80211.mac80211_registered = 1; 127 } 128 rtlpci->irq_alloc = 1; 129 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 130 131 /*init rfkill */ 132 rtl_init_rfkill(hw); 133} 134 135static int rtl92s_init_sw_vars(struct ieee80211_hw *hw) 136{ 137 struct rtl_priv *rtlpriv = rtl_priv(hw); 138 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 139 int err = 0; 140 u16 earlyrxthreshold = 7; 141 142 rtlpriv->dm.dm_initialgain_enable = true; 143 rtlpriv->dm.dm_flag = 0; 144 rtlpriv->dm.disable_framebursting = false; 145 rtlpriv->dm.thermalvalue = 0; 146 rtlpriv->dm.useramask = true; 147 148 /* compatible 5G band 91se just 2.4G band & smsp */ 149 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G; 150 rtlpriv->rtlhal.bandset = BAND_ON_2_4G; 151 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY; 152 153 rtlpci->transmit_config = 0; 154 155 rtlpci->receive_config = 156 RCR_APPFCS | 157 RCR_APWRMGT | 158 /*RCR_ADD3 |*/ 159 RCR_AMF | 160 RCR_ADF | 161 RCR_APP_MIC | 162 RCR_APP_ICV | 163 RCR_AICV | 164 /* Accept ICV error, CRC32 Error */ 165 RCR_ACRC32 | 166 RCR_AB | 167 /* Accept Broadcast, Multicast */ 168 RCR_AM | 169 /* Accept Physical match */ 170 RCR_APM | 171 /* Accept Destination Address packets */ 172 /*RCR_AAP |*/ 173 RCR_APP_PHYST_STAFF | 174 /* Accept PHY status */ 175 RCR_APP_PHYST_RXFF | 176 (earlyrxthreshold << RCR_FIFO_OFFSET); 177 178 rtlpci->irq_mask[0] = (u32) 179 (IMR_ROK | 180 IMR_VODOK | 181 IMR_VIDOK | 182 IMR_BEDOK | 183 IMR_BKDOK | 184 IMR_HCCADOK | 185 IMR_MGNTDOK | 186 IMR_COMDOK | 187 IMR_HIGHDOK | 188 IMR_BDOK | 189 IMR_RXCMDOK | 190 /*IMR_TIMEOUT0 |*/ 191 IMR_RDU | 192 IMR_RXFOVW | 193 IMR_BCNINT 194 /*| IMR_TXFOVW*/ 195 /*| IMR_TBDOK | 196 IMR_TBDER*/); 197 198 rtlpci->irq_mask[1] = (u32) 0; 199 200 rtlpci->shortretry_limit = 0x30; 201 rtlpci->longretry_limit = 0x30; 202 203 rtlpci->first_init = true; 204 205 /* for debug level */ 206 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug; 207 /* for LPS & IPS */ 208 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 209 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 210 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 211 if (!rtlpriv->psc.inactiveps) 212 pr_info("Power Save off (module option)\n"); 213 if (!rtlpriv->psc.fwctrl_lps) 214 pr_info("FW Power Save off (module option)\n"); 215 rtlpriv->psc.reg_fwctrl_lps = 3; 216 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 217 /* for ASPM, you can close aspm through 218 * set const_support_pciaspm = 0 */ 219 rtl92s_init_aspm_vars(hw); 220 221 if (rtlpriv->psc.reg_fwctrl_lps == 1) 222 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 223 else if (rtlpriv->psc.reg_fwctrl_lps == 2) 224 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; 225 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 226 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 227 228 /* for firmware buf */ 229 rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware)); 230 if (!rtlpriv->rtlhal.pfirmware) 231 return 1; 232 233 rtlpriv->max_fw_size = RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE; 234 235 pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n" 236 "Loading firmware %s\n", rtlpriv->cfg->fw_name); 237 /* request fw */ 238 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name, 239 rtlpriv->io.dev, GFP_KERNEL, hw, 240 rtl92se_fw_cb); 241 if (err) { 242 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 243 "Failed to request firmware!\n"); 244 return 1; 245 } 246 247 return err; 248} 249 250static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw) 251{ 252 struct rtl_priv *rtlpriv = rtl_priv(hw); 253 254 if (rtlpriv->rtlhal.pfirmware) { 255 vfree(rtlpriv->rtlhal.pfirmware); 256 rtlpriv->rtlhal.pfirmware = NULL; 257 } 258} 259 260static struct rtl_hal_ops rtl8192se_hal_ops = { 261 .init_sw_vars = rtl92s_init_sw_vars, 262 .deinit_sw_vars = rtl92s_deinit_sw_vars, 263 .read_eeprom_info = rtl92se_read_eeprom_info, 264 .interrupt_recognized = rtl92se_interrupt_recognized, 265 .hw_init = rtl92se_hw_init, 266 .hw_disable = rtl92se_card_disable, 267 .hw_suspend = rtl92se_suspend, 268 .hw_resume = rtl92se_resume, 269 .enable_interrupt = rtl92se_enable_interrupt, 270 .disable_interrupt = rtl92se_disable_interrupt, 271 .set_network_type = rtl92se_set_network_type, 272 .set_chk_bssid = rtl92se_set_check_bssid, 273 .set_qos = rtl92se_set_qos, 274 .set_bcn_reg = rtl92se_set_beacon_related_registers, 275 .set_bcn_intv = rtl92se_set_beacon_interval, 276 .update_interrupt_mask = rtl92se_update_interrupt_mask, 277 .get_hw_reg = rtl92se_get_hw_reg, 278 .set_hw_reg = rtl92se_set_hw_reg, 279 .update_rate_tbl = rtl92se_update_hal_rate_tbl, 280 .fill_tx_desc = rtl92se_tx_fill_desc, 281 .fill_tx_cmddesc = rtl92se_tx_fill_cmddesc, 282 .query_rx_desc = rtl92se_rx_query_desc, 283 .set_channel_access = rtl92se_update_channel_access_setting, 284 .radio_onoff_checking = rtl92se_gpio_radio_on_off_checking, 285 .set_bw_mode = rtl92s_phy_set_bw_mode, 286 .switch_channel = rtl92s_phy_sw_chnl, 287 .dm_watchdog = rtl92s_dm_watchdog, 288 .scan_operation_backup = rtl92s_phy_scan_operation_backup, 289 .set_rf_power_state = rtl92s_phy_set_rf_power_state, 290 .led_control = rtl92se_led_control, 291 .set_desc = rtl92se_set_desc, 292 .get_desc = rtl92se_get_desc, 293 .tx_polling = rtl92se_tx_polling, 294 .enable_hw_sec = rtl92se_enable_hw_security_config, 295 .set_key = rtl92se_set_key, 296 .init_sw_leds = rtl92se_init_sw_leds, 297 .get_bbreg = rtl92s_phy_query_bb_reg, 298 .set_bbreg = rtl92s_phy_set_bb_reg, 299 .get_rfreg = rtl92s_phy_query_rf_reg, 300 .set_rfreg = rtl92s_phy_set_rf_reg, 301}; 302 303static struct rtl_mod_params rtl92se_mod_params = { 304 .sw_crypto = false, 305 .inactiveps = true, 306 .swctrl_lps = true, 307 .fwctrl_lps = false, 308 .debug = DBG_EMERG, 309}; 310 311/* Because memory R/W bursting will cause system hang/crash 312 * for 92se, so we don't read back after every write action */ 313static struct rtl_hal_cfg rtl92se_hal_cfg = { 314 .bar_id = 1, 315 .write_readback = false, 316 .name = "rtl92s_pci", 317 .fw_name = "rtlwifi/rtl8192sefw.bin", 318 .ops = &rtl8192se_hal_ops, 319 .mod_params = &rtl92se_mod_params, 320 321 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 322 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 323 .maps[SYS_CLK] = SYS_CLKR, 324 .maps[MAC_RCR_AM] = RCR_AM, 325 .maps[MAC_RCR_AB] = RCR_AB, 326 .maps[MAC_RCR_ACRC32] = RCR_ACRC32, 327 .maps[MAC_RCR_ACF] = RCR_ACF, 328 .maps[MAC_RCR_AAP] = RCR_AAP, 329 330 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 331 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 332 .maps[EFUSE_CLK] = REG_EFUSE_CLK, 333 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, 334 .maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */ 335 .maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */ 336 .maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */ 337 .maps[EFUSE_ANA8M] = EFUSE_ANA8M, 338 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S, 339 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, 340 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, 341 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES, 342 343 .maps[RWCAM] = REG_RWCAM, 344 .maps[WCAMI] = REG_WCAMI, 345 .maps[RCAMO] = REG_RCAMO, 346 .maps[CAMDBG] = REG_CAMDBG, 347 .maps[SECR] = REG_SECR, 348 .maps[SEC_CAM_NONE] = CAM_NONE, 349 .maps[SEC_CAM_WEP40] = CAM_WEP40, 350 .maps[SEC_CAM_TKIP] = CAM_TKIP, 351 .maps[SEC_CAM_AES] = CAM_AES, 352 .maps[SEC_CAM_WEP104] = CAM_WEP104, 353 354 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, 355 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, 356 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, 357 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 358 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 359 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 360 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, 361 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 362 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 363 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 364 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, 365 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 366 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 367 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 368 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, 369 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, 370 371 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, 372 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, 373 .maps[RTL_IMR_BcnInt] = IMR_BCNINT, 374 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, 375 .maps[RTL_IMR_RDU] = IMR_RDU, 376 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, 377 .maps[RTL_IMR_BDOK] = IMR_BDOK, 378 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, 379 .maps[RTL_IMR_TBDER] = IMR_TBDER, 380 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, 381 .maps[RTL_IMR_COMDOK] = IMR_COMDOK, 382 .maps[RTL_IMR_TBDOK] = IMR_TBDOK, 383 .maps[RTL_IMR_BKDOK] = IMR_BKDOK, 384 .maps[RTL_IMR_BEDOK] = IMR_BEDOK, 385 .maps[RTL_IMR_VIDOK] = IMR_VIDOK, 386 .maps[RTL_IMR_VODOK] = IMR_VODOK, 387 .maps[RTL_IMR_ROK] = IMR_ROK, 388 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER), 389 390 .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M, 391 .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M, 392 .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M, 393 .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M, 394 .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M, 395 .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M, 396 .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M, 397 .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M, 398 .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M, 399 .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M, 400 .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M, 401 .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M, 402 403 .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7, 404 .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15, 405}; 406 407static struct pci_device_id rtl92se_pci_ids[] __devinitdata = { 408 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)}, 409 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)}, 410 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)}, 411 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)}, 412 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)}, 413 {}, 414}; 415 416MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids); 417 418MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 419MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 420MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); 421MODULE_LICENSE("GPL"); 422MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless"); 423MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin"); 424 425module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444); 426module_param_named(debug, rtl92se_mod_params.debug, int, 0444); 427module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444); 428module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444); 429module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444); 430MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 431MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 432MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); 433MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); 434MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)"); 435 436static const struct dev_pm_ops rtlwifi_pm_ops = { 437 .suspend = rtl_pci_suspend, 438 .resume = rtl_pci_resume, 439 .freeze = rtl_pci_suspend, 440 .thaw = rtl_pci_resume, 441 .poweroff = rtl_pci_suspend, 442 .restore = rtl_pci_resume, 443}; 444 445static struct pci_driver rtl92se_driver = { 446 .name = KBUILD_MODNAME, 447 .id_table = rtl92se_pci_ids, 448 .probe = rtl_pci_probe, 449 .remove = rtl_pci_disconnect, 450 .driver.pm = &rtlwifi_pm_ops, 451}; 452 453static int __init rtl92se_module_init(void) 454{ 455 int ret = 0; 456 457 ret = pci_register_driver(&rtl92se_driver); 458 if (ret) 459 RT_ASSERT(false, "No device found\n"); 460 461 return ret; 462} 463 464static void __exit rtl92se_module_exit(void) 465{ 466 pci_unregister_driver(&rtl92se_driver); 467} 468 469module_init(rtl92se_module_init); 470module_exit(rtl92se_module_exit); 471