1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#ifndef __RTL_WIFI_H__ 31#define __RTL_WIFI_H__ 32 33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 34 35#include <linux/sched.h> 36#include <linux/firmware.h> 37#include <linux/etherdevice.h> 38#include <linux/vmalloc.h> 39#include <linux/usb.h> 40#include <net/mac80211.h> 41#include <linux/completion.h> 42#include "debug.h" 43 44#define RF_CHANGE_BY_INIT 0 45#define RF_CHANGE_BY_IPS BIT(28) 46#define RF_CHANGE_BY_PS BIT(29) 47#define RF_CHANGE_BY_HW BIT(30) 48#define RF_CHANGE_BY_SW BIT(31) 49 50#define IQK_ADDA_REG_NUM 16 51#define IQK_MAC_REG_NUM 4 52 53#define MAX_KEY_LEN 61 54#define KEY_BUF_SIZE 5 55 56/* QoS related. */ 57/*aci: 0x00 Best Effort*/ 58/*aci: 0x01 Background*/ 59/*aci: 0x10 Video*/ 60/*aci: 0x11 Voice*/ 61/*Max: define total number.*/ 62#define AC0_BE 0 63#define AC1_BK 1 64#define AC2_VI 2 65#define AC3_VO 3 66#define AC_MAX 4 67#define QOS_QUEUE_NUM 4 68#define RTL_MAC80211_NUM_QUEUE 5 69#define REALTEK_USB_VENQT_MAX_BUF_SIZE 254 70#define RTL_USB_MAX_RX_COUNT 100 71#define QBSS_LOAD_SIZE 5 72#define MAX_WMMELE_LENGTH 64 73 74#define TOTAL_CAM_ENTRY 32 75 76/*slot time for 11g. */ 77#define RTL_SLOT_TIME_9 9 78#define RTL_SLOT_TIME_20 20 79 80/*related with tcp/ip. */ 81/*if_ehther.h*/ 82#define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */ 83#define ETH_P_IP 0x0800 /*Internet Protocol packet */ 84#define ETH_P_ARP 0x0806 /*Address Resolution packet */ 85#define SNAP_SIZE 6 86#define PROTOC_TYPE_SIZE 2 87 88/*related with 802.11 frame*/ 89#define MAC80211_3ADDR_LEN 24 90#define MAC80211_4ADDR_LEN 30 91 92#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ 93#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ 94#define MAX_PG_GROUP 13 95#define CHANNEL_GROUP_MAX_2G 3 96#define CHANNEL_GROUP_IDX_5GL 3 97#define CHANNEL_GROUP_IDX_5GM 6 98#define CHANNEL_GROUP_IDX_5GH 9 99#define CHANNEL_GROUP_MAX_5G 9 100#define CHANNEL_MAX_NUMBER_2G 14 101#define AVG_THERMAL_NUM 8 102#define MAX_TID_COUNT 9 103 104/* for early mode */ 105#define FCS_LEN 4 106#define EM_HDR_LEN 8 107enum intf_type { 108 INTF_PCI = 0, 109 INTF_USB = 1, 110}; 111 112enum radio_path { 113 RF90_PATH_A = 0, 114 RF90_PATH_B = 1, 115 RF90_PATH_C = 2, 116 RF90_PATH_D = 3, 117}; 118 119enum rt_eeprom_type { 120 EEPROM_93C46, 121 EEPROM_93C56, 122 EEPROM_BOOT_EFUSE, 123}; 124 125enum rtl_status { 126 RTL_STATUS_INTERFACE_START = 0, 127}; 128 129enum hardware_type { 130 HARDWARE_TYPE_RTL8192E, 131 HARDWARE_TYPE_RTL8192U, 132 HARDWARE_TYPE_RTL8192SE, 133 HARDWARE_TYPE_RTL8192SU, 134 HARDWARE_TYPE_RTL8192CE, 135 HARDWARE_TYPE_RTL8192CU, 136 HARDWARE_TYPE_RTL8192DE, 137 HARDWARE_TYPE_RTL8192DU, 138 HARDWARE_TYPE_RTL8723E, 139 HARDWARE_TYPE_RTL8723U, 140 141 /* keep it last */ 142 HARDWARE_TYPE_NUM 143}; 144 145#define IS_HARDWARE_TYPE_8192SU(rtlhal) \ 146 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU) 147#define IS_HARDWARE_TYPE_8192SE(rtlhal) \ 148 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 149#define IS_HARDWARE_TYPE_8192CE(rtlhal) \ 150 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE) 151#define IS_HARDWARE_TYPE_8192CU(rtlhal) \ 152 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU) 153#define IS_HARDWARE_TYPE_8192DE(rtlhal) \ 154 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) 155#define IS_HARDWARE_TYPE_8192DU(rtlhal) \ 156 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU) 157#define IS_HARDWARE_TYPE_8723E(rtlhal) \ 158 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E) 159#define IS_HARDWARE_TYPE_8723U(rtlhal) \ 160 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U) 161#define IS_HARDWARE_TYPE_8192S(rtlhal) \ 162(IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal)) 163#define IS_HARDWARE_TYPE_8192C(rtlhal) \ 164(IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal)) 165#define IS_HARDWARE_TYPE_8192D(rtlhal) \ 166(IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal)) 167#define IS_HARDWARE_TYPE_8723(rtlhal) \ 168(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal)) 169#define IS_HARDWARE_TYPE_8723U(rtlhal) \ 170 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U) 171 172#define RX_HAL_IS_CCK_RATE(_pdesc)\ 173 (_pdesc->rxmcs == DESC92_RATE1M || \ 174 _pdesc->rxmcs == DESC92_RATE2M || \ 175 _pdesc->rxmcs == DESC92_RATE5_5M || \ 176 _pdesc->rxmcs == DESC92_RATE11M) 177 178enum scan_operation_backup_opt { 179 SCAN_OPT_BACKUP = 0, 180 SCAN_OPT_RESTORE, 181 SCAN_OPT_MAX 182}; 183 184/*RF state.*/ 185enum rf_pwrstate { 186 ERFON, 187 ERFSLEEP, 188 ERFOFF 189}; 190 191struct bb_reg_def { 192 u32 rfintfs; 193 u32 rfintfi; 194 u32 rfintfo; 195 u32 rfintfe; 196 u32 rf3wire_offset; 197 u32 rflssi_select; 198 u32 rftxgain_stage; 199 u32 rfhssi_para1; 200 u32 rfhssi_para2; 201 u32 rfswitch_control; 202 u32 rfagc_control1; 203 u32 rfagc_control2; 204 u32 rfrxiq_imbalance; 205 u32 rfrx_afe; 206 u32 rftxiq_imbalance; 207 u32 rftx_afe; 208 u32 rflssi_readback; 209 u32 rflssi_readbackpi; 210}; 211 212enum io_type { 213 IO_CMD_PAUSE_DM_BY_SCAN = 0, 214 IO_CMD_RESUME_DM_BY_SCAN = 1, 215}; 216 217enum hw_variables { 218 HW_VAR_ETHER_ADDR, 219 HW_VAR_MULTICAST_REG, 220 HW_VAR_BASIC_RATE, 221 HW_VAR_BSSID, 222 HW_VAR_MEDIA_STATUS, 223 HW_VAR_SECURITY_CONF, 224 HW_VAR_BEACON_INTERVAL, 225 HW_VAR_ATIM_WINDOW, 226 HW_VAR_LISTEN_INTERVAL, 227 HW_VAR_CS_COUNTER, 228 HW_VAR_DEFAULTKEY0, 229 HW_VAR_DEFAULTKEY1, 230 HW_VAR_DEFAULTKEY2, 231 HW_VAR_DEFAULTKEY3, 232 HW_VAR_SIFS, 233 HW_VAR_DIFS, 234 HW_VAR_EIFS, 235 HW_VAR_SLOT_TIME, 236 HW_VAR_ACK_PREAMBLE, 237 HW_VAR_CW_CONFIG, 238 HW_VAR_CW_VALUES, 239 HW_VAR_RATE_FALLBACK_CONTROL, 240 HW_VAR_CONTENTION_WINDOW, 241 HW_VAR_RETRY_COUNT, 242 HW_VAR_TR_SWITCH, 243 HW_VAR_COMMAND, 244 HW_VAR_WPA_CONFIG, 245 HW_VAR_AMPDU_MIN_SPACE, 246 HW_VAR_SHORTGI_DENSITY, 247 HW_VAR_AMPDU_FACTOR, 248 HW_VAR_MCS_RATE_AVAILABLE, 249 HW_VAR_AC_PARAM, 250 HW_VAR_ACM_CTRL, 251 HW_VAR_DIS_Req_Qsize, 252 HW_VAR_CCX_CHNL_LOAD, 253 HW_VAR_CCX_NOISE_HISTOGRAM, 254 HW_VAR_CCX_CLM_NHM, 255 HW_VAR_TxOPLimit, 256 HW_VAR_TURBO_MODE, 257 HW_VAR_RF_STATE, 258 HW_VAR_RF_OFF_BY_HW, 259 HW_VAR_BUS_SPEED, 260 HW_VAR_SET_DEV_POWER, 261 262 HW_VAR_RCR, 263 HW_VAR_RATR_0, 264 HW_VAR_RRSR, 265 HW_VAR_CPU_RST, 266 HW_VAR_CECHK_BSSID, 267 HW_VAR_LBK_MODE, 268 HW_VAR_AES_11N_FIX, 269 HW_VAR_USB_RX_AGGR, 270 HW_VAR_USER_CONTROL_TURBO_MODE, 271 HW_VAR_RETRY_LIMIT, 272 HW_VAR_INIT_TX_RATE, 273 HW_VAR_TX_RATE_REG, 274 HW_VAR_EFUSE_USAGE, 275 HW_VAR_EFUSE_BYTES, 276 HW_VAR_AUTOLOAD_STATUS, 277 HW_VAR_RF_2R_DISABLE, 278 HW_VAR_SET_RPWM, 279 HW_VAR_H2C_FW_PWRMODE, 280 HW_VAR_H2C_FW_JOINBSSRPT, 281 HW_VAR_FW_PSMODE_STATUS, 282 HW_VAR_1X1_RECV_COMBINE, 283 HW_VAR_STOP_SEND_BEACON, 284 HW_VAR_TSF_TIMER, 285 HW_VAR_IO_CMD, 286 287 HW_VAR_RF_RECOVERY, 288 HW_VAR_H2C_FW_UPDATE_GTK, 289 HW_VAR_WF_MASK, 290 HW_VAR_WF_CRC, 291 HW_VAR_WF_IS_MAC_ADDR, 292 HW_VAR_H2C_FW_OFFLOAD, 293 HW_VAR_RESET_WFCRC, 294 295 HW_VAR_HANDLE_FW_C2H, 296 HW_VAR_DL_FW_RSVD_PAGE, 297 HW_VAR_AID, 298 HW_VAR_HW_SEQ_ENABLE, 299 HW_VAR_CORRECT_TSF, 300 HW_VAR_BCN_VALID, 301 HW_VAR_FWLPS_RF_ON, 302 HW_VAR_DUAL_TSF_RST, 303 HW_VAR_SWITCH_EPHY_WoWLAN, 304 HW_VAR_INT_MIGRATION, 305 HW_VAR_INT_AC, 306 HW_VAR_RF_TIMING, 307 308 HW_VAR_MRC, 309 310 HW_VAR_MGT_FILTER, 311 HW_VAR_CTRL_FILTER, 312 HW_VAR_DATA_FILTER, 313}; 314 315enum _RT_MEDIA_STATUS { 316 RT_MEDIA_DISCONNECT = 0, 317 RT_MEDIA_CONNECT = 1 318}; 319 320enum rt_oem_id { 321 RT_CID_DEFAULT = 0, 322 RT_CID_8187_ALPHA0 = 1, 323 RT_CID_8187_SERCOMM_PS = 2, 324 RT_CID_8187_HW_LED = 3, 325 RT_CID_8187_NETGEAR = 4, 326 RT_CID_WHQL = 5, 327 RT_CID_819x_CAMEO = 6, 328 RT_CID_819x_RUNTOP = 7, 329 RT_CID_819x_Senao = 8, 330 RT_CID_TOSHIBA = 9, 331 RT_CID_819x_Netcore = 10, 332 RT_CID_Nettronix = 11, 333 RT_CID_DLINK = 12, 334 RT_CID_PRONET = 13, 335 RT_CID_COREGA = 14, 336 RT_CID_819x_ALPHA = 15, 337 RT_CID_819x_Sitecom = 16, 338 RT_CID_CCX = 17, 339 RT_CID_819x_Lenovo = 18, 340 RT_CID_819x_QMI = 19, 341 RT_CID_819x_Edimax_Belkin = 20, 342 RT_CID_819x_Sercomm_Belkin = 21, 343 RT_CID_819x_CAMEO1 = 22, 344 RT_CID_819x_MSI = 23, 345 RT_CID_819x_Acer = 24, 346 RT_CID_819x_HP = 27, 347 RT_CID_819x_CLEVO = 28, 348 RT_CID_819x_Arcadyan_Belkin = 29, 349 RT_CID_819x_SAMSUNG = 30, 350 RT_CID_819x_WNC_COREGA = 31, 351 RT_CID_819x_Foxcoon = 32, 352 RT_CID_819x_DELL = 33, 353}; 354 355enum hw_descs { 356 HW_DESC_OWN, 357 HW_DESC_RXOWN, 358 HW_DESC_TX_NEXTDESC_ADDR, 359 HW_DESC_TXBUFF_ADDR, 360 HW_DESC_RXBUFF_ADDR, 361 HW_DESC_RXPKT_LEN, 362 HW_DESC_RXERO, 363}; 364 365enum prime_sc { 366 PRIME_CHNL_OFFSET_DONT_CARE = 0, 367 PRIME_CHNL_OFFSET_LOWER = 1, 368 PRIME_CHNL_OFFSET_UPPER = 2, 369}; 370 371enum rf_type { 372 RF_1T1R = 0, 373 RF_1T2R = 1, 374 RF_2T2R = 2, 375 RF_2T2R_GREEN = 3, 376}; 377 378enum ht_channel_width { 379 HT_CHANNEL_WIDTH_20 = 0, 380 HT_CHANNEL_WIDTH_20_40 = 1, 381}; 382 383/* Ref: 802.11i sepc D10.0 7.3.2.25.1 384Cipher Suites Encryption Algorithms */ 385enum rt_enc_alg { 386 NO_ENCRYPTION = 0, 387 WEP40_ENCRYPTION = 1, 388 TKIP_ENCRYPTION = 2, 389 RSERVED_ENCRYPTION = 3, 390 AESCCMP_ENCRYPTION = 4, 391 WEP104_ENCRYPTION = 5, 392}; 393 394enum rtl_hal_state { 395 _HAL_STATE_STOP = 0, 396 _HAL_STATE_START = 1, 397}; 398 399enum rtl_desc92_rate { 400 DESC92_RATE1M = 0x00, 401 DESC92_RATE2M = 0x01, 402 DESC92_RATE5_5M = 0x02, 403 DESC92_RATE11M = 0x03, 404 405 DESC92_RATE6M = 0x04, 406 DESC92_RATE9M = 0x05, 407 DESC92_RATE12M = 0x06, 408 DESC92_RATE18M = 0x07, 409 DESC92_RATE24M = 0x08, 410 DESC92_RATE36M = 0x09, 411 DESC92_RATE48M = 0x0a, 412 DESC92_RATE54M = 0x0b, 413 414 DESC92_RATEMCS0 = 0x0c, 415 DESC92_RATEMCS1 = 0x0d, 416 DESC92_RATEMCS2 = 0x0e, 417 DESC92_RATEMCS3 = 0x0f, 418 DESC92_RATEMCS4 = 0x10, 419 DESC92_RATEMCS5 = 0x11, 420 DESC92_RATEMCS6 = 0x12, 421 DESC92_RATEMCS7 = 0x13, 422 DESC92_RATEMCS8 = 0x14, 423 DESC92_RATEMCS9 = 0x15, 424 DESC92_RATEMCS10 = 0x16, 425 DESC92_RATEMCS11 = 0x17, 426 DESC92_RATEMCS12 = 0x18, 427 DESC92_RATEMCS13 = 0x19, 428 DESC92_RATEMCS14 = 0x1a, 429 DESC92_RATEMCS15 = 0x1b, 430 DESC92_RATEMCS15_SG = 0x1c, 431 DESC92_RATEMCS32 = 0x20, 432}; 433 434enum rtl_var_map { 435 /*reg map */ 436 SYS_ISO_CTRL = 0, 437 SYS_FUNC_EN, 438 SYS_CLK, 439 MAC_RCR_AM, 440 MAC_RCR_AB, 441 MAC_RCR_ACRC32, 442 MAC_RCR_ACF, 443 MAC_RCR_AAP, 444 445 /*efuse map */ 446 EFUSE_TEST, 447 EFUSE_CTRL, 448 EFUSE_CLK, 449 EFUSE_CLK_CTRL, 450 EFUSE_PWC_EV12V, 451 EFUSE_FEN_ELDR, 452 EFUSE_LOADER_CLK_EN, 453 EFUSE_ANA8M, 454 EFUSE_HWSET_MAX_SIZE, 455 EFUSE_MAX_SECTION_MAP, 456 EFUSE_REAL_CONTENT_SIZE, 457 EFUSE_OOB_PROTECT_BYTES_LEN, 458 459 /*CAM map */ 460 RWCAM, 461 WCAMI, 462 RCAMO, 463 CAMDBG, 464 SECR, 465 SEC_CAM_NONE, 466 SEC_CAM_WEP40, 467 SEC_CAM_TKIP, 468 SEC_CAM_AES, 469 SEC_CAM_WEP104, 470 471 /*IMR map */ 472 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ 473 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ 474 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ 475 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ 476 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ 477 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ 478 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ 479 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ 480 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ 481 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ 482 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ 483 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ 484 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ 485 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ 486 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ 487 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ 488 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ 489 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ 490 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */ 491 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ 492 RTL_IMR_RDU, /*Receive Descriptor Unavailable */ 493 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ 494 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ 495 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ 496 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ 497 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ 498 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ 499 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ 500 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ 501 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ 502 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ 503 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ 504 RTL_IMR_ROK, /*Receive DMA OK Interrupt */ 505 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK | 506 * RTL_IMR_TBDER) */ 507 508 /*CCK Rates, TxHT = 0 */ 509 RTL_RC_CCK_RATE1M, 510 RTL_RC_CCK_RATE2M, 511 RTL_RC_CCK_RATE5_5M, 512 RTL_RC_CCK_RATE11M, 513 514 /*OFDM Rates, TxHT = 0 */ 515 RTL_RC_OFDM_RATE6M, 516 RTL_RC_OFDM_RATE9M, 517 RTL_RC_OFDM_RATE12M, 518 RTL_RC_OFDM_RATE18M, 519 RTL_RC_OFDM_RATE24M, 520 RTL_RC_OFDM_RATE36M, 521 RTL_RC_OFDM_RATE48M, 522 RTL_RC_OFDM_RATE54M, 523 524 RTL_RC_HT_RATEMCS7, 525 RTL_RC_HT_RATEMCS15, 526 527 /*keep it last */ 528 RTL_VAR_MAP_MAX, 529}; 530 531/*Firmware PS mode for control LPS.*/ 532enum _fw_ps_mode { 533 FW_PS_ACTIVE_MODE = 0, 534 FW_PS_MIN_MODE = 1, 535 FW_PS_MAX_MODE = 2, 536 FW_PS_DTIM_MODE = 3, 537 FW_PS_VOIP_MODE = 4, 538 FW_PS_UAPSD_WMM_MODE = 5, 539 FW_PS_UAPSD_MODE = 6, 540 FW_PS_IBSS_MODE = 7, 541 FW_PS_WWLAN_MODE = 8, 542 FW_PS_PM_Radio_Off = 9, 543 FW_PS_PM_Card_Disable = 10, 544}; 545 546enum rt_psmode { 547 EACTIVE, /*Active/Continuous access. */ 548 EMAXPS, /*Max power save mode. */ 549 EFASTPS, /*Fast power save mode. */ 550 EAUTOPS, /*Auto power save mode. */ 551}; 552 553/*LED related.*/ 554enum led_ctl_mode { 555 LED_CTL_POWER_ON = 1, 556 LED_CTL_LINK = 2, 557 LED_CTL_NO_LINK = 3, 558 LED_CTL_TX = 4, 559 LED_CTL_RX = 5, 560 LED_CTL_SITE_SURVEY = 6, 561 LED_CTL_POWER_OFF = 7, 562 LED_CTL_START_TO_LINK = 8, 563 LED_CTL_START_WPS = 9, 564 LED_CTL_STOP_WPS = 10, 565}; 566 567enum rtl_led_pin { 568 LED_PIN_GPIO0, 569 LED_PIN_LED0, 570 LED_PIN_LED1, 571 LED_PIN_LED2 572}; 573 574/*QoS related.*/ 575/*acm implementation method.*/ 576enum acm_method { 577 eAcmWay0_SwAndHw = 0, 578 eAcmWay1_HW = 1, 579 eAcmWay2_SW = 2, 580}; 581 582enum macphy_mode { 583 SINGLEMAC_SINGLEPHY = 0, 584 DUALMAC_DUALPHY, 585 DUALMAC_SINGLEPHY, 586}; 587 588enum band_type { 589 BAND_ON_2_4G = 0, 590 BAND_ON_5G, 591 BAND_ON_BOTH, 592 BANDMAX 593}; 594 595/*aci/aifsn Field. 596Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ 597union aci_aifsn { 598 u8 char_data; 599 600 struct { 601 u8 aifsn:4; 602 u8 acm:1; 603 u8 aci:2; 604 u8 reserved:1; 605 } f; /* Field */ 606}; 607 608/*mlme related.*/ 609enum wireless_mode { 610 WIRELESS_MODE_UNKNOWN = 0x00, 611 WIRELESS_MODE_A = 0x01, 612 WIRELESS_MODE_B = 0x02, 613 WIRELESS_MODE_G = 0x04, 614 WIRELESS_MODE_AUTO = 0x08, 615 WIRELESS_MODE_N_24G = 0x10, 616 WIRELESS_MODE_N_5G = 0x20 617}; 618 619#define IS_WIRELESS_MODE_A(wirelessmode) \ 620 (wirelessmode == WIRELESS_MODE_A) 621#define IS_WIRELESS_MODE_B(wirelessmode) \ 622 (wirelessmode == WIRELESS_MODE_B) 623#define IS_WIRELESS_MODE_G(wirelessmode) \ 624 (wirelessmode == WIRELESS_MODE_G) 625#define IS_WIRELESS_MODE_N_24G(wirelessmode) \ 626 (wirelessmode == WIRELESS_MODE_N_24G) 627#define IS_WIRELESS_MODE_N_5G(wirelessmode) \ 628 (wirelessmode == WIRELESS_MODE_N_5G) 629 630enum ratr_table_mode { 631 RATR_INX_WIRELESS_NGB = 0, 632 RATR_INX_WIRELESS_NG = 1, 633 RATR_INX_WIRELESS_NB = 2, 634 RATR_INX_WIRELESS_N = 3, 635 RATR_INX_WIRELESS_GB = 4, 636 RATR_INX_WIRELESS_G = 5, 637 RATR_INX_WIRELESS_B = 6, 638 RATR_INX_WIRELESS_MC = 7, 639 RATR_INX_WIRELESS_A = 8, 640}; 641 642enum rtl_link_state { 643 MAC80211_NOLINK = 0, 644 MAC80211_LINKING = 1, 645 MAC80211_LINKED = 2, 646 MAC80211_LINKED_SCANNING = 3, 647}; 648 649enum act_category { 650 ACT_CAT_QOS = 1, 651 ACT_CAT_DLS = 2, 652 ACT_CAT_BA = 3, 653 ACT_CAT_HT = 7, 654 ACT_CAT_WMM = 17, 655}; 656 657enum ba_action { 658 ACT_ADDBAREQ = 0, 659 ACT_ADDBARSP = 1, 660 ACT_DELBA = 2, 661}; 662 663struct octet_string { 664 u8 *octet; 665 u16 length; 666}; 667 668struct rtl_hdr_3addr { 669 __le16 frame_ctl; 670 __le16 duration_id; 671 u8 addr1[ETH_ALEN]; 672 u8 addr2[ETH_ALEN]; 673 u8 addr3[ETH_ALEN]; 674 __le16 seq_ctl; 675 u8 payload[0]; 676} __packed; 677 678struct rtl_info_element { 679 u8 id; 680 u8 len; 681 u8 data[0]; 682} __packed; 683 684struct rtl_probe_rsp { 685 struct rtl_hdr_3addr header; 686 u32 time_stamp[2]; 687 __le16 beacon_interval; 688 __le16 capability; 689 /*SSID, supported rates, FH params, DS params, 690 CF params, IBSS params, TIM (if beacon), RSN */ 691 struct rtl_info_element info_element[0]; 692} __packed; 693 694/*LED related.*/ 695/*ledpin Identify how to implement this SW led.*/ 696struct rtl_led { 697 void *hw; 698 enum rtl_led_pin ledpin; 699 bool ledon; 700}; 701 702struct rtl_led_ctl { 703 bool led_opendrain; 704 struct rtl_led sw_led0; 705 struct rtl_led sw_led1; 706}; 707 708struct rtl_qos_parameters { 709 __le16 cw_min; 710 __le16 cw_max; 711 u8 aifs; 712 u8 flag; 713 __le16 tx_op; 714} __packed; 715 716struct rt_smooth_data { 717 u32 elements[100]; /*array to store values */ 718 u32 index; /*index to current array to store */ 719 u32 total_num; /*num of valid elements */ 720 u32 total_val; /*sum of valid elements */ 721}; 722 723struct false_alarm_statistics { 724 u32 cnt_parity_fail; 725 u32 cnt_rate_illegal; 726 u32 cnt_crc8_fail; 727 u32 cnt_mcs_fail; 728 u32 cnt_fast_fsync_fail; 729 u32 cnt_sb_search_fail; 730 u32 cnt_ofdm_fail; 731 u32 cnt_cck_fail; 732 u32 cnt_all; 733}; 734 735struct init_gain { 736 u8 xaagccore1; 737 u8 xbagccore1; 738 u8 xcagccore1; 739 u8 xdagccore1; 740 u8 cca; 741 742}; 743 744struct wireless_stats { 745 unsigned long txbytesunicast; 746 unsigned long txbytesmulticast; 747 unsigned long txbytesbroadcast; 748 unsigned long rxbytesunicast; 749 750 long rx_snr_db[4]; 751 /*Correct smoothed ss in Dbm, only used 752 in driver to report real power now. */ 753 long recv_signal_power; 754 long signal_quality; 755 long last_sigstrength_inpercent; 756 757 u32 rssi_calculate_cnt; 758 759 /*Transformed, in dbm. Beautified signal 760 strength for UI, not correct. */ 761 long signal_strength; 762 763 u8 rx_rssi_percentage[4]; 764 u8 rx_evm_percentage[2]; 765 766 struct rt_smooth_data ui_rssi; 767 struct rt_smooth_data ui_link_quality; 768}; 769 770struct rate_adaptive { 771 u8 rate_adaptive_disabled; 772 u8 ratr_state; 773 u16 reserve; 774 775 u32 high_rssi_thresh_for_ra; 776 u32 high2low_rssi_thresh_for_ra; 777 u8 low2high_rssi_thresh_for_ra40m; 778 u32 low_rssi_thresh_for_ra40M; 779 u8 low2high_rssi_thresh_for_ra20m; 780 u32 low_rssi_thresh_for_ra20M; 781 u32 upper_rssi_threshold_ratr; 782 u32 middleupper_rssi_threshold_ratr; 783 u32 middle_rssi_threshold_ratr; 784 u32 middlelow_rssi_threshold_ratr; 785 u32 low_rssi_threshold_ratr; 786 u32 ultralow_rssi_threshold_ratr; 787 u32 low_rssi_threshold_ratr_40m; 788 u32 low_rssi_threshold_ratr_20m; 789 u8 ping_rssi_enable; 790 u32 ping_rssi_ratr; 791 u32 ping_rssi_thresh_for_ra; 792 u32 last_ratr; 793 u8 pre_ratr_state; 794}; 795 796struct regd_pair_mapping { 797 u16 reg_dmnenum; 798 u16 reg_5ghz_ctl; 799 u16 reg_2ghz_ctl; 800}; 801 802struct rtl_regulatory { 803 char alpha2[2]; 804 u16 country_code; 805 u16 max_power_level; 806 u32 tp_scale; 807 u16 current_rd; 808 u16 current_rd_ext; 809 int16_t power_limit; 810 struct regd_pair_mapping *regpair; 811}; 812 813struct rtl_rfkill { 814 bool rfkill_state; /*0 is off, 1 is on */ 815}; 816 817#define IQK_MATRIX_REG_NUM 8 818#define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) 819struct iqk_matrix_regs { 820 bool iqk_done; 821 long value[1][IQK_MATRIX_REG_NUM]; 822}; 823 824struct phy_parameters { 825 u16 length; 826 u32 *pdata; 827}; 828 829enum hw_param_tab_index { 830 PHY_REG_2T, 831 PHY_REG_1T, 832 PHY_REG_PG, 833 RADIOA_2T, 834 RADIOB_2T, 835 RADIOA_1T, 836 RADIOB_1T, 837 MAC_REG, 838 AGCTAB_2T, 839 AGCTAB_1T, 840 MAX_TAB 841}; 842 843struct rtl_phy { 844 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ 845 struct init_gain initgain_backup; 846 enum io_type current_io_type; 847 848 u8 rf_mode; 849 u8 rf_type; 850 u8 current_chan_bw; 851 u8 set_bwmode_inprogress; 852 u8 sw_chnl_inprogress; 853 u8 sw_chnl_stage; 854 u8 sw_chnl_step; 855 u8 current_channel; 856 u8 h2c_box_num; 857 u8 set_io_inprogress; 858 u8 lck_inprogress; 859 860 /* record for power tracking */ 861 s32 reg_e94; 862 s32 reg_e9c; 863 s32 reg_ea4; 864 s32 reg_eac; 865 s32 reg_eb4; 866 s32 reg_ebc; 867 s32 reg_ec4; 868 s32 reg_ecc; 869 u8 rfpienable; 870 u8 reserve_0; 871 u16 reserve_1; 872 u32 reg_c04, reg_c08, reg_874; 873 u32 adda_backup[16]; 874 u32 iqk_mac_backup[IQK_MAC_REG_NUM]; 875 u32 iqk_bb_backup[10]; 876 877 /* Dual mac */ 878 bool need_iqk; 879 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM]; 880 881 bool rfpi_enable; 882 883 u8 pwrgroup_cnt; 884 u8 cck_high_power; 885 /* MAX_PG_GROUP groups of pwr diff by rates */ 886 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16]; 887 u8 default_initialgain[4]; 888 889 /* the current Tx power level */ 890 u8 cur_cck_txpwridx; 891 u8 cur_ofdm24g_txpwridx; 892 893 u32 rfreg_chnlval[2]; 894 bool apk_done; 895 u32 reg_rf3c[2]; /* pathA / pathB */ 896 897 /* bfsync */ 898 u8 framesync; 899 u32 framesync_c34; 900 901 u8 num_total_rfpath; 902 struct phy_parameters hwparam_tables[MAX_TAB]; 903 u16 rf_pathmap; 904}; 905 906#define MAX_TID_COUNT 9 907#define RTL_AGG_STOP 0 908#define RTL_AGG_PROGRESS 1 909#define RTL_AGG_START 2 910#define RTL_AGG_OPERATIONAL 3 911#define RTL_AGG_OFF 0 912#define RTL_AGG_ON 1 913#define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 914#define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 915 916struct rtl_ht_agg { 917 u16 txq_id; 918 u16 wait_for_ba; 919 u16 start_idx; 920 u64 bitmap; 921 u32 rate_n_flags; 922 u8 agg_state; 923}; 924 925struct rtl_tid_data { 926 u16 seq_number; 927 struct rtl_ht_agg agg; 928}; 929 930struct rtl_sta_info { 931 u8 ratr_index; 932 u8 wireless_mode; 933 u8 mimo_ps; 934 struct rtl_tid_data tids[MAX_TID_COUNT]; 935} __packed; 936 937struct rtl_priv; 938struct rtl_io { 939 struct device *dev; 940 struct mutex bb_mutex; 941 942 /*PCI MEM map */ 943 unsigned long pci_mem_end; /*shared mem end */ 944 unsigned long pci_mem_start; /*shared mem start */ 945 946 /*PCI IO map */ 947 unsigned long pci_base_addr; /*device I/O address */ 948 949 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val); 950 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val); 951 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val); 952 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf, 953 u16 len); 954 955 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr); 956 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr); 957 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr); 958 959}; 960 961struct rtl_mac { 962 u8 mac_addr[ETH_ALEN]; 963 u8 mac80211_registered; 964 u8 beacon_enabled; 965 966 u32 tx_ss_num; 967 u32 rx_ss_num; 968 969 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; 970 struct ieee80211_hw *hw; 971 struct ieee80211_vif *vif; 972 enum nl80211_iftype opmode; 973 974 /*Probe Beacon management */ 975 struct rtl_tid_data tids[MAX_TID_COUNT]; 976 enum rtl_link_state link_state; 977 978 int n_channels; 979 int n_bitrates; 980 981 bool offchan_delay; 982 983 /*filters */ 984 u32 rx_conf; 985 u16 rx_mgt_filter; 986 u16 rx_ctrl_filter; 987 u16 rx_data_filter; 988 989 bool act_scanning; 990 u8 cnt_after_linked; 991 992 /* early mode */ 993 /* skb wait queue */ 994 struct sk_buff_head skb_waitq[MAX_TID_COUNT]; 995 u8 earlymode_threshold; 996 997 /*RDG*/ 998 bool rdg_en; 999 1000 /*AP*/ 1001 u8 bssid[6]; 1002 u32 vendor; 1003 u8 mcs[16]; /* 16 bytes mcs for HT rates. */ 1004 u32 basic_rates; /* b/g rates */ 1005 u8 ht_enable; 1006 u8 sgi_40; 1007 u8 sgi_20; 1008 u8 bw_40; 1009 u8 mode; /* wireless mode */ 1010 u8 slot_time; 1011 u8 short_preamble; 1012 u8 use_cts_protect; 1013 u8 cur_40_prime_sc; 1014 u8 cur_40_prime_sc_bk; 1015 u64 tsf; 1016 u8 retry_short; 1017 u8 retry_long; 1018 u16 assoc_id; 1019 1020 /*IBSS*/ 1021 int beacon_interval; 1022 1023 /*AMPDU*/ 1024 u8 min_space_cfg; /*For Min spacing configurations */ 1025 u8 max_mss_density; 1026 u8 current_ampdu_factor; 1027 u8 current_ampdu_density; 1028 1029 /*QOS & EDCA */ 1030 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; 1031 struct rtl_qos_parameters ac[AC_MAX]; 1032}; 1033 1034struct rtl_hal { 1035 struct ieee80211_hw *hw; 1036 1037 enum intf_type interface; 1038 u16 hw_type; /*92c or 92d or 92s and so on */ 1039 u8 ic_class; 1040 u8 oem_id; 1041 u32 version; /*version of chip */ 1042 u8 state; /*stop 0, start 1 */ 1043 1044 /*firmware */ 1045 u32 fwsize; 1046 u8 *pfirmware; 1047 u16 fw_version; 1048 u16 fw_subversion; 1049 bool h2c_setinprogress; 1050 u8 last_hmeboxnum; 1051 /*Reserve page start offset except beacon in TxQ. */ 1052 u8 fw_rsvdpage_startoffset; 1053 u8 h2c_txcmd_seq; 1054 1055 /* FW Cmd IO related */ 1056 u16 fwcmd_iomap; 1057 u32 fwcmd_ioparam; 1058 bool set_fwcmd_inprogress; 1059 u8 current_fwcmd_io; 1060 1061 /**/ 1062 bool driver_going2unload; 1063 1064 /*AMPDU init min space*/ 1065 u8 minspace_cfg; /*For Min spacing configurations */ 1066 1067 /* Dual mac */ 1068 enum macphy_mode macphymode; 1069 enum band_type current_bandtype; /* 0:2.4G, 1:5G */ 1070 enum band_type current_bandtypebackup; 1071 enum band_type bandset; 1072 /* dual MAC 0--Mac0 1--Mac1 */ 1073 u32 interfaceindex; 1074 /* just for DualMac S3S4 */ 1075 u8 macphyctl_reg; 1076 bool earlymode_enable; 1077 /* Dual mac*/ 1078 bool during_mac0init_radiob; 1079 bool during_mac1init_radioa; 1080 bool reloadtxpowerindex; 1081 /* True if IMR or IQK have done 1082 for 2.4G in scan progress */ 1083 bool load_imrandiqk_setting_for2g; 1084 1085 bool disable_amsdu_8k; 1086}; 1087 1088struct rtl_security { 1089 /*default 0 */ 1090 bool use_sw_sec; 1091 1092 bool being_setkey; 1093 bool use_defaultkey; 1094 /*Encryption Algorithm for Unicast Packet */ 1095 enum rt_enc_alg pairwise_enc_algorithm; 1096 /*Encryption Algorithm for Brocast/Multicast */ 1097 enum rt_enc_alg group_enc_algorithm; 1098 /*Cam Entry Bitmap */ 1099 u32 hwsec_cam_bitmap; 1100 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN]; 1101 /*local Key buffer, indx 0 is for 1102 pairwise key 1-4 is for agoup key. */ 1103 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; 1104 u8 key_len[KEY_BUF_SIZE]; 1105 1106 /*The pointer of Pairwise Key, 1107 it always points to KeyBuf[4] */ 1108 u8 *pairwise_key; 1109}; 1110 1111struct rtl_dm { 1112 /*PHY status for Dynamic Management */ 1113 long entry_min_undecoratedsmoothed_pwdb; 1114 long undecorated_smoothed_pwdb; /*out dm */ 1115 long entry_max_undecoratedsmoothed_pwdb; 1116 bool dm_initialgain_enable; 1117 bool dynamic_txpower_enable; 1118 bool current_turbo_edca; 1119 bool is_any_nonbepkts; /*out dm */ 1120 bool is_cur_rdlstate; 1121 bool txpower_trackinginit; 1122 bool disable_framebursting; 1123 bool cck_inch14; 1124 bool txpower_tracking; 1125 bool useramask; 1126 bool rfpath_rxenable[4]; 1127 bool inform_fw_driverctrldm; 1128 bool current_mrc_switch; 1129 u8 txpowercount; 1130 1131 u8 thermalvalue_rxgain; 1132 u8 thermalvalue_iqk; 1133 u8 thermalvalue_lck; 1134 u8 thermalvalue; 1135 u8 last_dtp_lvl; 1136 u8 thermalvalue_avg[AVG_THERMAL_NUM]; 1137 u8 thermalvalue_avg_index; 1138 bool done_txpower; 1139 u8 dynamic_txhighpower_lvl; /*Tx high power level */ 1140 u8 dm_flag; /*Indicate each dynamic mechanism's status. */ 1141 u8 dm_type; 1142 u8 txpower_track_control; 1143 bool interrupt_migration; 1144 bool disable_tx_int; 1145 char ofdm_index[2]; 1146 char cck_index; 1147}; 1148 1149#define EFUSE_MAX_LOGICAL_SIZE 256 1150 1151struct rtl_efuse { 1152 bool autoLoad_ok; 1153 bool bootfromefuse; 1154 u16 max_physical_size; 1155 1156 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; 1157 u16 efuse_usedbytes; 1158 u8 efuse_usedpercentage; 1159#ifdef EFUSE_REPG_WORKAROUND 1160 bool efuse_re_pg_sec1flag; 1161 u8 efuse_re_pg_data[8]; 1162#endif 1163 1164 u8 autoload_failflag; 1165 u8 autoload_status; 1166 1167 short epromtype; 1168 u16 eeprom_vid; 1169 u16 eeprom_did; 1170 u16 eeprom_svid; 1171 u16 eeprom_smid; 1172 u8 eeprom_oemid; 1173 u16 eeprom_channelplan; 1174 u8 eeprom_version; 1175 u8 board_type; 1176 u8 external_pa; 1177 1178 u8 dev_addr[6]; 1179 1180 bool txpwr_fromeprom; 1181 u8 eeprom_crystalcap; 1182 u8 eeprom_tssi[2]; 1183 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ 1184 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; 1185 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; 1186 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G]; 1187 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX]; 1188 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX]; 1189 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G]; 1190 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */ 1191 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */ 1192 1193 u8 internal_pa_5g[2]; /* pathA / pathB */ 1194 u8 eeprom_c9; 1195 u8 eeprom_cc; 1196 1197 /*For power group */ 1198 u8 eeprom_pwrgroup[2][3]; 1199 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; 1200 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; 1201 1202 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */ 1203 /*For HT<->legacy pwr diff*/ 1204 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER]; 1205 u8 txpwr_safetyflag; /* Band edge enable flag */ 1206 u16 eeprom_txpowerdiff; 1207 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ 1208 u8 antenna_txpwdiff[3]; 1209 1210 u8 eeprom_regulatory; 1211 u8 eeprom_thermalmeter; 1212 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */ 1213 u16 tssi_13dbm; 1214 u8 crystalcap; /* CrystalCap. */ 1215 u8 delta_iqk; 1216 u8 delta_lck; 1217 1218 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ 1219 bool apk_thermalmeterignore; 1220 1221 bool b1x1_recvcombine; 1222 bool b1ss_support; 1223 1224 /*channel plan */ 1225 u8 channel_plan; 1226}; 1227 1228struct rtl_ps_ctl { 1229 bool pwrdomain_protect; 1230 bool in_powersavemode; 1231 bool rfchange_inprogress; 1232 bool swrf_processing; 1233 bool hwradiooff; 1234 1235 /* 1236 * just for PCIE ASPM 1237 * If it supports ASPM, Offset[560h] = 0x40, 1238 * otherwise Offset[560h] = 0x00. 1239 * */ 1240 bool support_aspm; 1241 1242 bool support_backdoor; 1243 1244 /*for LPS */ 1245 enum rt_psmode dot11_psmode; /*Power save mode configured. */ 1246 bool swctrl_lps; 1247 bool leisure_ps; 1248 bool fwctrl_lps; 1249 u8 fwctrl_psmode; 1250 /*For Fw control LPS mode */ 1251 u8 reg_fwctrl_lps; 1252 /*Record Fw PS mode status. */ 1253 bool fw_current_inpsmode; 1254 u8 reg_max_lps_awakeintvl; 1255 bool report_linked; 1256 1257 /*for IPS */ 1258 bool inactiveps; 1259 1260 u32 rfoff_reason; 1261 1262 /*RF OFF Level */ 1263 u32 cur_ps_level; 1264 u32 reg_rfps_level; 1265 1266 /*just for PCIE ASPM */ 1267 u8 const_amdpci_aspm; 1268 bool pwrdown_mode; 1269 1270 enum rf_pwrstate inactive_pwrstate; 1271 enum rf_pwrstate rfpwr_state; /*cur power state */ 1272 1273 /* for SW LPS*/ 1274 bool sw_ps_enabled; 1275 bool state; 1276 bool state_inap; 1277 bool multi_buffered; 1278 u16 nullfunc_seq; 1279 unsigned int dtim_counter; 1280 unsigned int sleep_ms; 1281 unsigned long last_sleep_jiffies; 1282 unsigned long last_awake_jiffies; 1283 unsigned long last_delaylps_stamp_jiffies; 1284 unsigned long last_dtim; 1285 unsigned long last_beacon; 1286 unsigned long last_action; 1287 unsigned long last_slept; 1288}; 1289 1290struct rtl_stats { 1291 u32 mac_time[2]; 1292 s8 rssi; 1293 u8 signal; 1294 u8 noise; 1295 u16 rate; /*in 100 kbps */ 1296 u8 received_channel; 1297 u8 control; 1298 u8 mask; 1299 u8 freq; 1300 u16 len; 1301 u64 tsf; 1302 u32 beacon_time; 1303 u8 nic_type; 1304 u16 length; 1305 u8 signalquality; /*in 0-100 index. */ 1306 /* 1307 * Real power in dBm for this packet, 1308 * no beautification and aggregation. 1309 * */ 1310 s32 recvsignalpower; 1311 s8 rxpower; /*in dBm Translate from PWdB */ 1312 u8 signalstrength; /*in 0-100 index. */ 1313 u16 hwerror:1; 1314 u16 crc:1; 1315 u16 icv:1; 1316 u16 shortpreamble:1; 1317 u16 antenna:1; 1318 u16 decrypted:1; 1319 u16 wakeup:1; 1320 u32 timestamp_low; 1321 u32 timestamp_high; 1322 1323 u8 rx_drvinfo_size; 1324 u8 rx_bufshift; 1325 bool isampdu; 1326 bool isfirst_ampdu; 1327 bool rx_is40Mhzpacket; 1328 u32 rx_pwdb_all; 1329 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ 1330 s8 rx_mimo_signalquality[2]; 1331 bool packet_matchbssid; 1332 bool is_cck; 1333 bool is_ht; 1334 bool packet_toself; 1335 bool packet_beacon; /*for rssi */ 1336 char cck_adc_pwdb[4]; /*for rx path selection */ 1337}; 1338 1339struct rt_link_detect { 1340 u32 num_tx_in4period[4]; 1341 u32 num_rx_in4period[4]; 1342 1343 u32 num_tx_inperiod; 1344 u32 num_rx_inperiod; 1345 1346 bool busytraffic; 1347 bool higher_busytraffic; 1348 bool higher_busyrxtraffic; 1349 1350 u32 tidtx_in4period[MAX_TID_COUNT][4]; 1351 u32 tidtx_inperiod[MAX_TID_COUNT]; 1352 bool higher_busytxtraffic[MAX_TID_COUNT]; 1353}; 1354 1355struct rtl_tcb_desc { 1356 u8 packet_bw:1; 1357 u8 multicast:1; 1358 u8 broadcast:1; 1359 1360 u8 rts_stbc:1; 1361 u8 rts_enable:1; 1362 u8 cts_enable:1; 1363 u8 rts_use_shortpreamble:1; 1364 u8 rts_use_shortgi:1; 1365 u8 rts_sc:1; 1366 u8 rts_bw:1; 1367 u8 rts_rate; 1368 1369 u8 use_shortgi:1; 1370 u8 use_shortpreamble:1; 1371 u8 use_driver_rate:1; 1372 u8 disable_ratefallback:1; 1373 1374 u8 ratr_index; 1375 u8 mac_id; 1376 u8 hw_rate; 1377 1378 u8 last_inipkt:1; 1379 u8 cmd_or_init:1; 1380 u8 queue_index; 1381 1382 /* early mode */ 1383 u8 empkt_num; 1384 /* The max value by HW */ 1385 u32 empkt_len[5]; 1386}; 1387 1388struct rtl_hal_ops { 1389 int (*init_sw_vars) (struct ieee80211_hw *hw); 1390 void (*deinit_sw_vars) (struct ieee80211_hw *hw); 1391 void (*read_chip_version)(struct ieee80211_hw *hw); 1392 void (*read_eeprom_info) (struct ieee80211_hw *hw); 1393 void (*interrupt_recognized) (struct ieee80211_hw *hw, 1394 u32 *p_inta, u32 *p_intb); 1395 int (*hw_init) (struct ieee80211_hw *hw); 1396 void (*hw_disable) (struct ieee80211_hw *hw); 1397 void (*hw_suspend) (struct ieee80211_hw *hw); 1398 void (*hw_resume) (struct ieee80211_hw *hw); 1399 void (*enable_interrupt) (struct ieee80211_hw *hw); 1400 void (*disable_interrupt) (struct ieee80211_hw *hw); 1401 int (*set_network_type) (struct ieee80211_hw *hw, 1402 enum nl80211_iftype type); 1403 void (*set_chk_bssid)(struct ieee80211_hw *hw, 1404 bool check_bssid); 1405 void (*set_bw_mode) (struct ieee80211_hw *hw, 1406 enum nl80211_channel_type ch_type); 1407 u8(*switch_channel) (struct ieee80211_hw *hw); 1408 void (*set_qos) (struct ieee80211_hw *hw, int aci); 1409 void (*set_bcn_reg) (struct ieee80211_hw *hw); 1410 void (*set_bcn_intv) (struct ieee80211_hw *hw); 1411 void (*update_interrupt_mask) (struct ieee80211_hw *hw, 1412 u32 add_msr, u32 rm_msr); 1413 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 1414 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 1415 void (*update_rate_tbl) (struct ieee80211_hw *hw, 1416 struct ieee80211_sta *sta, u8 rssi_level); 1417 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level); 1418 void (*fill_tx_desc) (struct ieee80211_hw *hw, 1419 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 1420 struct ieee80211_tx_info *info, 1421 struct sk_buff *skb, u8 hw_queue, 1422 struct rtl_tcb_desc *ptcb_desc); 1423 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc, 1424 u32 buffer_len, bool bIsPsPoll); 1425 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc, 1426 bool firstseg, bool lastseg, 1427 struct sk_buff *skb); 1428 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb); 1429 bool (*query_rx_desc) (struct ieee80211_hw *hw, 1430 struct rtl_stats *stats, 1431 struct ieee80211_rx_status *rx_status, 1432 u8 *pdesc, struct sk_buff *skb); 1433 void (*set_channel_access) (struct ieee80211_hw *hw); 1434 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid); 1435 void (*dm_watchdog) (struct ieee80211_hw *hw); 1436 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation); 1437 bool (*set_rf_power_state) (struct ieee80211_hw *hw, 1438 enum rf_pwrstate rfpwr_state); 1439 void (*led_control) (struct ieee80211_hw *hw, 1440 enum led_ctl_mode ledaction); 1441 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val); 1442 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name); 1443 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue); 1444 void (*enable_hw_sec) (struct ieee80211_hw *hw); 1445 void (*set_key) (struct ieee80211_hw *hw, u32 key_index, 1446 u8 *macaddr, bool is_group, u8 enc_algo, 1447 bool is_wepkey, bool clear_all); 1448 void (*init_sw_leds) (struct ieee80211_hw *hw); 1449 void (*deinit_sw_leds) (struct ieee80211_hw *hw); 1450 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); 1451 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 1452 u32 data); 1453 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 1454 u32 regaddr, u32 bitmask); 1455 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 1456 u32 regaddr, u32 bitmask, u32 data); 1457 void (*linked_set_reg) (struct ieee80211_hw *hw); 1458 bool (*phy_rf6052_config) (struct ieee80211_hw *hw); 1459 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw, 1460 u8 *powerlevel); 1461 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw, 1462 u8 *ppowerlevel, u8 channel); 1463 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw, 1464 u8 configtype); 1465 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw, 1466 u8 configtype); 1467 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t); 1468 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw); 1469 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw); 1470}; 1471 1472struct rtl_intf_ops { 1473 /*com */ 1474 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); 1475 int (*adapter_start) (struct ieee80211_hw *hw); 1476 void (*adapter_stop) (struct ieee80211_hw *hw); 1477 1478 int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb, 1479 struct rtl_tcb_desc *ptcb_desc); 1480 void (*flush)(struct ieee80211_hw *hw, bool drop); 1481 int (*reset_trx_ring) (struct ieee80211_hw *hw); 1482 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb); 1483 1484 /*pci */ 1485 void (*disable_aspm) (struct ieee80211_hw *hw); 1486 void (*enable_aspm) (struct ieee80211_hw *hw); 1487 1488 /*usb */ 1489}; 1490 1491struct rtl_mod_params { 1492 /* default: 0 = using hardware encryption */ 1493 bool sw_crypto; 1494 1495 /* default: 0 = DBG_EMERG (0)*/ 1496 int debug; 1497 1498 /* default: 1 = using no linked power save */ 1499 bool inactiveps; 1500 1501 /* default: 1 = using linked sw power save */ 1502 bool swctrl_lps; 1503 1504 /* default: 1 = using linked fw power save */ 1505 bool fwctrl_lps; 1506}; 1507 1508struct rtl_hal_usbint_cfg { 1509 /* data - rx */ 1510 u32 in_ep_num; 1511 u32 rx_urb_num; 1512 u32 rx_max_size; 1513 1514 /* op - rx */ 1515 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *); 1516 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *, 1517 struct sk_buff_head *); 1518 1519 /* tx */ 1520 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *); 1521 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *, 1522 struct sk_buff *); 1523 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *, 1524 struct sk_buff_head *); 1525 1526 /* endpoint mapping */ 1527 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw); 1528 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index); 1529}; 1530 1531struct rtl_hal_cfg { 1532 u8 bar_id; 1533 bool write_readback; 1534 char *name; 1535 char *fw_name; 1536 struct rtl_hal_ops *ops; 1537 struct rtl_mod_params *mod_params; 1538 struct rtl_hal_usbint_cfg *usb_interface_cfg; 1539 1540 /*this map used for some registers or vars 1541 defined int HAL but used in MAIN */ 1542 u32 maps[RTL_VAR_MAP_MAX]; 1543 1544}; 1545 1546struct rtl_locks { 1547 /* mutex */ 1548 struct mutex conf_mutex; 1549 struct mutex ps_mutex; 1550 1551 /*spin lock */ 1552 spinlock_t ips_lock; 1553 spinlock_t irq_th_lock; 1554 spinlock_t h2c_lock; 1555 spinlock_t rf_ps_lock; 1556 spinlock_t rf_lock; 1557 spinlock_t waitq_lock; 1558 1559 /*Dual mac*/ 1560 spinlock_t cck_and_rw_pagea_lock; 1561}; 1562 1563struct rtl_works { 1564 struct ieee80211_hw *hw; 1565 1566 /*timer */ 1567 struct timer_list watchdog_timer; 1568 1569 /*task */ 1570 struct tasklet_struct irq_tasklet; 1571 struct tasklet_struct irq_prepare_bcn_tasklet; 1572 1573 /*work queue */ 1574 struct workqueue_struct *rtl_wq; 1575 struct delayed_work watchdog_wq; 1576 struct delayed_work ips_nic_off_wq; 1577 1578 /* For SW LPS */ 1579 struct delayed_work ps_work; 1580 struct delayed_work ps_rfon_wq; 1581 1582 struct work_struct lps_leave_work; 1583}; 1584 1585struct rtl_debug { 1586 u32 dbgp_type[DBGP_TYPE_MAX]; 1587 u32 global_debuglevel; 1588 u64 global_debugcomponents; 1589 1590 /* add for proc debug */ 1591 struct proc_dir_entry *proc_dir; 1592 char proc_name[20]; 1593}; 1594 1595struct rtl_priv { 1596 struct completion firmware_loading_complete; 1597 struct rtl_locks locks; 1598 struct rtl_works works; 1599 struct rtl_mac mac80211; 1600 struct rtl_hal rtlhal; 1601 struct rtl_regulatory regd; 1602 struct rtl_rfkill rfkill; 1603 struct rtl_io io; 1604 struct rtl_phy phy; 1605 struct rtl_dm dm; 1606 struct rtl_security sec; 1607 struct rtl_efuse efuse; 1608 1609 struct rtl_ps_ctl psc; 1610 struct rate_adaptive ra; 1611 struct wireless_stats stats; 1612 struct rt_link_detect link_info; 1613 struct false_alarm_statistics falsealm_cnt; 1614 1615 struct rtl_rate_priv *rate_priv; 1616 1617 struct rtl_debug dbg; 1618 int max_fw_size; 1619 1620 /* 1621 *hal_cfg : for diff cards 1622 *intf_ops : for diff interrface usb/pcie 1623 */ 1624 struct rtl_hal_cfg *cfg; 1625 struct rtl_intf_ops *intf_ops; 1626 1627 /*this var will be set by set_bit, 1628 and was used to indicate status of 1629 interface or hardware */ 1630 unsigned long status; 1631 1632 /* data buffer pointer for USB reads */ 1633 __le32 *usb_data; 1634 int usb_data_index; 1635 1636 /*This must be the last item so 1637 that it points to the data allocated 1638 beyond this structure like: 1639 rtl_pci_priv or rtl_usb_priv */ 1640 u8 priv[0]; 1641}; 1642 1643#define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) 1644#define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) 1645#define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) 1646#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) 1647#define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) 1648 1649 1650/*************************************** 1651 Bluetooth Co-existence Related 1652****************************************/ 1653 1654enum bt_ant_num { 1655 ANT_X2 = 0, 1656 ANT_X1 = 1, 1657}; 1658 1659enum bt_co_type { 1660 BT_2WIRE = 0, 1661 BT_ISSC_3WIRE = 1, 1662 BT_ACCEL = 2, 1663 BT_CSR_BC4 = 3, 1664 BT_CSR_BC8 = 4, 1665 BT_RTL8756 = 5, 1666}; 1667 1668enum bt_cur_state { 1669 BT_OFF = 0, 1670 BT_ON = 1, 1671}; 1672 1673enum bt_service_type { 1674 BT_SCO = 0, 1675 BT_A2DP = 1, 1676 BT_HID = 2, 1677 BT_HID_IDLE = 3, 1678 BT_SCAN = 4, 1679 BT_IDLE = 5, 1680 BT_OTHER_ACTION = 6, 1681 BT_BUSY = 7, 1682 BT_OTHERBUSY = 8, 1683 BT_PAN = 9, 1684}; 1685 1686enum bt_radio_shared { 1687 BT_RADIO_SHARED = 0, 1688 BT_RADIO_INDIVIDUAL = 1, 1689}; 1690 1691struct bt_coexist_info { 1692 1693 /* EEPROM BT info. */ 1694 u8 eeprom_bt_coexist; 1695 u8 eeprom_bt_type; 1696 u8 eeprom_bt_ant_num; 1697 u8 eeprom_bt_ant_isolation; 1698 u8 eeprom_bt_radio_shared; 1699 1700 u8 bt_coexistence; 1701 u8 bt_ant_num; 1702 u8 bt_coexist_type; 1703 u8 bt_state; 1704 u8 bt_cur_state; /* 0:on, 1:off */ 1705 u8 bt_ant_isolation; /* 0:good, 1:bad */ 1706 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ 1707 u8 bt_service; 1708 u8 bt_radio_shared_type; 1709 u8 bt_rfreg_origin_1e; 1710 u8 bt_rfreg_origin_1f; 1711 u8 bt_rssi_state; 1712 u32 ratio_tx; 1713 u32 ratio_pri; 1714 u32 bt_edca_ul; 1715 u32 bt_edca_dl; 1716 1717 bool init_set; 1718 bool bt_busy_traffic; 1719 bool bt_traffic_mode_set; 1720 bool bt_non_traffic_mode_set; 1721 1722 bool fw_coexist_all_off; 1723 bool sw_coexist_all_off; 1724 u32 current_state; 1725 u32 previous_state; 1726 u8 bt_pre_rssi_state; 1727 1728 u8 reg_bt_iso; 1729 u8 reg_bt_sco; 1730 1731}; 1732 1733 1734/**************************************** 1735 mem access macro define start 1736 Call endian free function when 1737 1. Read/write packet content. 1738 2. Before write integer to IO. 1739 3. After read integer from IO. 1740****************************************/ 1741/* Convert little data endian to host ordering */ 1742#define EF1BYTE(_val) \ 1743 ((u8)(_val)) 1744#define EF2BYTE(_val) \ 1745 (le16_to_cpu(_val)) 1746#define EF4BYTE(_val) \ 1747 (le32_to_cpu(_val)) 1748 1749/* Read data from memory */ 1750#define READEF1BYTE(_ptr) \ 1751 EF1BYTE(*((u8 *)(_ptr))) 1752/* Read le16 data from memory and convert to host ordering */ 1753#define READEF2BYTE(_ptr) \ 1754 EF2BYTE(*((u16 *)(_ptr))) 1755#define READEF4BYTE(_ptr) \ 1756 EF4BYTE(*((u32 *)(_ptr))) 1757 1758/* Write data to memory */ 1759#define WRITEEF1BYTE(_ptr, _val) \ 1760 (*((u8 *)(_ptr))) = EF1BYTE(_val) 1761/* Write le16 data to memory in host ordering */ 1762#define WRITEEF2BYTE(_ptr, _val) \ 1763 (*((u16 *)(_ptr))) = EF2BYTE(_val) 1764#define WRITEEF4BYTE(_ptr, _val) \ 1765 (*((u16 *)(_ptr))) = EF2BYTE(_val) 1766 1767/* Create a bit mask 1768 * Examples: 1769 * BIT_LEN_MASK_32(0) => 0x00000000 1770 * BIT_LEN_MASK_32(1) => 0x00000001 1771 * BIT_LEN_MASK_32(2) => 0x00000003 1772 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF 1773 */ 1774#define BIT_LEN_MASK_32(__bitlen) \ 1775 (0xFFFFFFFF >> (32 - (__bitlen))) 1776#define BIT_LEN_MASK_16(__bitlen) \ 1777 (0xFFFF >> (16 - (__bitlen))) 1778#define BIT_LEN_MASK_8(__bitlen) \ 1779 (0xFF >> (8 - (__bitlen))) 1780 1781/* Create an offset bit mask 1782 * Examples: 1783 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 1784 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 1785 */ 1786#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ 1787 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) 1788#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ 1789 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) 1790#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ 1791 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) 1792 1793/*Description: 1794 * Return 4-byte value in host byte ordering from 1795 * 4-byte pointer in little-endian system. 1796 */ 1797#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ 1798 (EF4BYTE(*((u32 *)(__pstart)))) 1799#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ 1800 (EF2BYTE(*((u16 *)(__pstart)))) 1801#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ 1802 (EF1BYTE(*((u8 *)(__pstart)))) 1803 1804/*Description: 1805Translate subfield (continuous bits in little-endian) of 4-byte 1806value to host byte ordering.*/ 1807#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 1808 ( \ 1809 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ 1810 BIT_LEN_MASK_32(__bitlen) \ 1811 ) 1812#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 1813 ( \ 1814 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ 1815 BIT_LEN_MASK_16(__bitlen) \ 1816 ) 1817#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 1818 ( \ 1819 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ 1820 BIT_LEN_MASK_8(__bitlen) \ 1821 ) 1822 1823/* Description: 1824 * Mask subfield (continuous bits in little-endian) of 4-byte value 1825 * and return the result in 4-byte value in host byte ordering. 1826 */ 1827#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 1828 ( \ 1829 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ 1830 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ 1831 ) 1832#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 1833 ( \ 1834 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ 1835 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ 1836 ) 1837#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 1838 ( \ 1839 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ 1840 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ 1841 ) 1842 1843/* Description: 1844 * Set subfield of little-endian 4-byte value to specified value. 1845 */ 1846#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ 1847 *((u32 *)(__pstart)) = EF4BYTE \ 1848 ( \ 1849 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ 1850 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ 1851 ); 1852#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ 1853 *((u16 *)(__pstart)) = EF2BYTE \ 1854 ( \ 1855 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ 1856 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ 1857 ); 1858#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ 1859 *((u8 *)(__pstart)) = EF1BYTE \ 1860 ( \ 1861 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ 1862 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ 1863 ); 1864 1865#define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ 1866 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment)) 1867 1868/**************************************** 1869 mem access macro define end 1870****************************************/ 1871 1872#define byte(x, n) ((x >> (8 * n)) & 0xff) 1873 1874#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) 1875#define RTL_WATCH_DOG_TIME 2000 1876#define MSECS(t) msecs_to_jiffies(t) 1877#define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) 1878#define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) 1879#define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) 1880#define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) 1881#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) 1882#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) 1883#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) 1884 1885#define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ 1886#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ 1887#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ 1888/*NIC halt, re-initialize hw parameters*/ 1889#define RT_RF_OFF_LEVL_HALT_NIC BIT(3) 1890#define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ 1891#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ 1892/*Always enable ASPM and Clock Req in initialization.*/ 1893#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) 1894/* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ 1895#define RT_PS_LEVEL_ASPM BIT(7) 1896/*When LPS is on, disable 2R if no packet is received or transmittd.*/ 1897#define RT_RF_LPS_DISALBE_2R BIT(30) 1898#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ 1899#define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ 1900 ((ppsc->cur_ps_level & _ps_flg) ? true : false) 1901#define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ 1902 (ppsc->cur_ps_level &= (~(_ps_flg))) 1903#define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ 1904 (ppsc->cur_ps_level |= _ps_flg) 1905 1906#define container_of_dwork_rtl(x, y, z) \ 1907 container_of(container_of(x, struct delayed_work, work), y, z) 1908 1909#define FILL_OCTET_STRING(_os, _octet, _len) \ 1910 (_os).octet = (u8 *)(_octet); \ 1911 (_os).length = (_len); 1912 1913#define CP_MACADDR(des, src) \ 1914 ((des)[0] = (src)[0], (des)[1] = (src)[1],\ 1915 (des)[2] = (src)[2], (des)[3] = (src)[3],\ 1916 (des)[4] = (src)[4], (des)[5] = (src)[5]) 1917 1918static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) 1919{ 1920 return rtlpriv->io.read8_sync(rtlpriv, addr); 1921} 1922 1923static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) 1924{ 1925 return rtlpriv->io.read16_sync(rtlpriv, addr); 1926} 1927 1928static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) 1929{ 1930 return rtlpriv->io.read32_sync(rtlpriv, addr); 1931} 1932 1933static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) 1934{ 1935 rtlpriv->io.write8_async(rtlpriv, addr, val8); 1936 1937 if (rtlpriv->cfg->write_readback) 1938 rtlpriv->io.read8_sync(rtlpriv, addr); 1939} 1940 1941static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) 1942{ 1943 rtlpriv->io.write16_async(rtlpriv, addr, val16); 1944 1945 if (rtlpriv->cfg->write_readback) 1946 rtlpriv->io.read16_sync(rtlpriv, addr); 1947} 1948 1949static inline void rtl_write_dword(struct rtl_priv *rtlpriv, 1950 u32 addr, u32 val32) 1951{ 1952 rtlpriv->io.write32_async(rtlpriv, addr, val32); 1953 1954 if (rtlpriv->cfg->write_readback) 1955 rtlpriv->io.read32_sync(rtlpriv, addr); 1956} 1957 1958static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, 1959 u32 regaddr, u32 bitmask) 1960{ 1961 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw, 1962 regaddr, 1963 bitmask); 1964} 1965 1966static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, 1967 u32 bitmask, u32 data) 1968{ 1969 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw, 1970 regaddr, bitmask, 1971 data); 1972 1973} 1974 1975static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, 1976 enum radio_path rfpath, u32 regaddr, 1977 u32 bitmask) 1978{ 1979 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw, 1980 rfpath, 1981 regaddr, 1982 bitmask); 1983} 1984 1985static inline void rtl_set_rfreg(struct ieee80211_hw *hw, 1986 enum radio_path rfpath, u32 regaddr, 1987 u32 bitmask, u32 data) 1988{ 1989 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw, 1990 rfpath, regaddr, 1991 bitmask, data); 1992} 1993 1994static inline bool is_hal_stop(struct rtl_hal *rtlhal) 1995{ 1996 return (_HAL_STATE_STOP == rtlhal->state); 1997} 1998 1999static inline void set_hal_start(struct rtl_hal *rtlhal) 2000{ 2001 rtlhal->state = _HAL_STATE_START; 2002} 2003 2004static inline void set_hal_stop(struct rtl_hal *rtlhal) 2005{ 2006 rtlhal->state = _HAL_STATE_STOP; 2007} 2008 2009static inline u8 get_rf_type(struct rtl_phy *rtlphy) 2010{ 2011 return rtlphy->rf_type; 2012} 2013 2014static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb) 2015{ 2016 return (struct ieee80211_hdr *)(skb->data); 2017} 2018 2019static inline __le16 rtl_get_fc(struct sk_buff *skb) 2020{ 2021 return rtl_get_hdr(skb)->frame_control; 2022} 2023 2024static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr) 2025{ 2026 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK; 2027} 2028 2029static inline u16 rtl_get_tid(struct sk_buff *skb) 2030{ 2031 return rtl_get_tid_h(rtl_get_hdr(skb)); 2032} 2033 2034static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw, 2035 struct ieee80211_vif *vif, 2036 const u8 *bssid) 2037{ 2038 return ieee80211_find_sta(vif, bssid); 2039} 2040 2041#endif 2042