1/* 2 * This file is part of wl1271 3 * 4 * Copyright (C) 2008-2010 Nokia Corporation 5 * 6 * Contact: Luciano Coelho <luciano.coelho@nokia.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 */ 23 24#include <linux/slab.h> 25#include <linux/wl12xx.h> 26#include <linux/export.h> 27 28#include "debug.h" 29#include "acx.h" 30#include "reg.h" 31#include "boot.h" 32#include "io.h" 33#include "event.h" 34#include "rx.h" 35 36static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag) 37{ 38 u32 cpu_ctrl; 39 40 /* 10.5.0 run the firmware (I) */ 41 cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL); 42 43 /* 10.5.1 run the firmware (II) */ 44 cpu_ctrl |= flag; 45 wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl); 46} 47 48static unsigned int wl12xx_get_fw_ver_quirks(struct wl1271 *wl) 49{ 50 unsigned int quirks = 0; 51 unsigned int *fw_ver = wl->chip.fw_ver; 52 53 /* Only new station firmwares support routing fw logs to the host */ 54 if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) && 55 (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN)) 56 quirks |= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED; 57 58 /* This feature is not yet supported for AP mode */ 59 if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP) 60 quirks |= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED; 61 62 return quirks; 63} 64 65static void wl1271_parse_fw_ver(struct wl1271 *wl) 66{ 67 int ret; 68 69 ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u", 70 &wl->chip.fw_ver[0], &wl->chip.fw_ver[1], 71 &wl->chip.fw_ver[2], &wl->chip.fw_ver[3], 72 &wl->chip.fw_ver[4]); 73 74 if (ret != 5) { 75 wl1271_warning("fw version incorrect value"); 76 memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver)); 77 return; 78 } 79 80 /* Check if any quirks are needed with older fw versions */ 81 wl->quirks |= wl12xx_get_fw_ver_quirks(wl); 82} 83 84static void wl1271_boot_fw_version(struct wl1271 *wl) 85{ 86 struct wl1271_static_data static_data; 87 88 wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data), 89 false); 90 91 strncpy(wl->chip.fw_ver_str, static_data.fw_version, 92 sizeof(wl->chip.fw_ver_str)); 93 94 /* make sure the string is NULL-terminated */ 95 wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0'; 96 97 wl1271_parse_fw_ver(wl); 98} 99 100static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf, 101 size_t fw_data_len, u32 dest) 102{ 103 struct wl1271_partition_set partition; 104 int addr, chunk_num, partition_limit; 105 u8 *p, *chunk; 106 107 /* whal_FwCtrl_LoadFwImageSm() */ 108 109 wl1271_debug(DEBUG_BOOT, "starting firmware upload"); 110 111 wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d", 112 fw_data_len, CHUNK_SIZE); 113 114 if ((fw_data_len % 4) != 0) { 115 wl1271_error("firmware length not multiple of four"); 116 return -EIO; 117 } 118 119 chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL); 120 if (!chunk) { 121 wl1271_error("allocation for firmware upload chunk failed"); 122 return -ENOMEM; 123 } 124 125 memcpy(&partition, &wl12xx_part_table[PART_DOWN], sizeof(partition)); 126 partition.mem.start = dest; 127 wl1271_set_partition(wl, &partition); 128 129 /* 10.1 set partition limit and chunk num */ 130 chunk_num = 0; 131 partition_limit = wl12xx_part_table[PART_DOWN].mem.size; 132 133 while (chunk_num < fw_data_len / CHUNK_SIZE) { 134 /* 10.2 update partition, if needed */ 135 addr = dest + (chunk_num + 2) * CHUNK_SIZE; 136 if (addr > partition_limit) { 137 addr = dest + chunk_num * CHUNK_SIZE; 138 partition_limit = chunk_num * CHUNK_SIZE + 139 wl12xx_part_table[PART_DOWN].mem.size; 140 partition.mem.start = addr; 141 wl1271_set_partition(wl, &partition); 142 } 143 144 /* 10.3 upload the chunk */ 145 addr = dest + chunk_num * CHUNK_SIZE; 146 p = buf + chunk_num * CHUNK_SIZE; 147 memcpy(chunk, p, CHUNK_SIZE); 148 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x", 149 p, addr); 150 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false); 151 152 chunk_num++; 153 } 154 155 /* 10.4 upload the last chunk */ 156 addr = dest + chunk_num * CHUNK_SIZE; 157 p = buf + chunk_num * CHUNK_SIZE; 158 memcpy(chunk, p, fw_data_len % CHUNK_SIZE); 159 wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x", 160 fw_data_len % CHUNK_SIZE, p, addr); 161 wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false); 162 163 kfree(chunk); 164 return 0; 165} 166 167static int wl1271_boot_upload_firmware(struct wl1271 *wl) 168{ 169 u32 chunks, addr, len; 170 int ret = 0; 171 u8 *fw; 172 173 fw = wl->fw; 174 chunks = be32_to_cpup((__be32 *) fw); 175 fw += sizeof(u32); 176 177 wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks); 178 179 while (chunks--) { 180 addr = be32_to_cpup((__be32 *) fw); 181 fw += sizeof(u32); 182 len = be32_to_cpup((__be32 *) fw); 183 fw += sizeof(u32); 184 185 if (len > 300000) { 186 wl1271_info("firmware chunk too long: %u", len); 187 return -EINVAL; 188 } 189 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u", 190 chunks, addr, len); 191 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr); 192 if (ret != 0) 193 break; 194 fw += len; 195 } 196 197 return ret; 198} 199 200static int wl1271_boot_upload_nvs(struct wl1271 *wl) 201{ 202 size_t nvs_len, burst_len; 203 int i; 204 u32 dest_addr, val; 205 u8 *nvs_ptr, *nvs_aligned; 206 207 if (wl->nvs == NULL) 208 return -ENODEV; 209 210 if (wl->chip.id == CHIP_ID_1283_PG20) { 211 struct wl128x_nvs_file *nvs = (struct wl128x_nvs_file *)wl->nvs; 212 213 if (wl->nvs_len == sizeof(struct wl128x_nvs_file)) { 214 if (nvs->general_params.dual_mode_select) 215 wl->enable_11a = true; 216 } else { 217 wl1271_error("nvs size is not as expected: %zu != %zu", 218 wl->nvs_len, 219 sizeof(struct wl128x_nvs_file)); 220 kfree(wl->nvs); 221 wl->nvs = NULL; 222 wl->nvs_len = 0; 223 return -EILSEQ; 224 } 225 226 /* only the first part of the NVS needs to be uploaded */ 227 nvs_len = sizeof(nvs->nvs); 228 nvs_ptr = (u8 *)nvs->nvs; 229 230 } else { 231 struct wl1271_nvs_file *nvs = 232 (struct wl1271_nvs_file *)wl->nvs; 233 /* 234 * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz 235 * band configurations) can be removed when those NVS files stop 236 * floating around. 237 */ 238 if (wl->nvs_len == sizeof(struct wl1271_nvs_file) || 239 wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) { 240 if (nvs->general_params.dual_mode_select) 241 wl->enable_11a = true; 242 } 243 244 if (wl->nvs_len != sizeof(struct wl1271_nvs_file) && 245 (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE || 246 wl->enable_11a)) { 247 wl1271_error("nvs size is not as expected: %zu != %zu", 248 wl->nvs_len, sizeof(struct wl1271_nvs_file)); 249 kfree(wl->nvs); 250 wl->nvs = NULL; 251 wl->nvs_len = 0; 252 return -EILSEQ; 253 } 254 255 /* only the first part of the NVS needs to be uploaded */ 256 nvs_len = sizeof(nvs->nvs); 257 nvs_ptr = (u8 *) nvs->nvs; 258 } 259 260 /* update current MAC address to NVS */ 261 nvs_ptr[11] = wl->addresses[0].addr[0]; 262 nvs_ptr[10] = wl->addresses[0].addr[1]; 263 nvs_ptr[6] = wl->addresses[0].addr[2]; 264 nvs_ptr[5] = wl->addresses[0].addr[3]; 265 nvs_ptr[4] = wl->addresses[0].addr[4]; 266 nvs_ptr[3] = wl->addresses[0].addr[5]; 267 268 /* 269 * Layout before the actual NVS tables: 270 * 1 byte : burst length. 271 * 2 bytes: destination address. 272 * n bytes: data to burst copy. 273 * 274 * This is ended by a 0 length, then the NVS tables. 275 */ 276 277 /* FIXME: Do we need to check here whether the LSB is 1? */ 278 while (nvs_ptr[0]) { 279 burst_len = nvs_ptr[0]; 280 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8)); 281 282 /* 283 * Due to our new wl1271_translate_reg_addr function, 284 * we need to add the REGISTER_BASE to the destination 285 */ 286 dest_addr += REGISTERS_BASE; 287 288 /* We move our pointer to the data */ 289 nvs_ptr += 3; 290 291 for (i = 0; i < burst_len; i++) { 292 if (nvs_ptr + 3 >= (u8 *) wl->nvs + nvs_len) 293 goto out_badnvs; 294 295 val = (nvs_ptr[0] | (nvs_ptr[1] << 8) 296 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24)); 297 298 wl1271_debug(DEBUG_BOOT, 299 "nvs burst write 0x%x: 0x%x", 300 dest_addr, val); 301 wl1271_write32(wl, dest_addr, val); 302 303 nvs_ptr += 4; 304 dest_addr += 4; 305 } 306 307 if (nvs_ptr >= (u8 *) wl->nvs + nvs_len) 308 goto out_badnvs; 309 } 310 311 /* 312 * We've reached the first zero length, the first NVS table 313 * is located at an aligned offset which is at least 7 bytes further. 314 * NOTE: The wl->nvs->nvs element must be first, in order to 315 * simplify the casting, we assume it is at the beginning of 316 * the wl->nvs structure. 317 */ 318 nvs_ptr = (u8 *)wl->nvs + 319 ALIGN(nvs_ptr - (u8 *)wl->nvs + 7, 4); 320 321 if (nvs_ptr >= (u8 *) wl->nvs + nvs_len) 322 goto out_badnvs; 323 324 nvs_len -= nvs_ptr - (u8 *)wl->nvs; 325 326 /* Now we must set the partition correctly */ 327 wl1271_set_partition(wl, &wl12xx_part_table[PART_WORK]); 328 329 /* Copy the NVS tables to a new block to ensure alignment */ 330 nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL); 331 if (!nvs_aligned) 332 return -ENOMEM; 333 334 /* And finally we upload the NVS tables */ 335 wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false); 336 337 kfree(nvs_aligned); 338 return 0; 339 340out_badnvs: 341 wl1271_error("nvs data is malformed"); 342 return -EILSEQ; 343} 344 345static void wl1271_boot_enable_interrupts(struct wl1271 *wl) 346{ 347 wl1271_enable_interrupts(wl); 348 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, 349 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK)); 350 wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL); 351} 352 353static int wl1271_boot_soft_reset(struct wl1271 *wl) 354{ 355 unsigned long timeout; 356 u32 boot_data; 357 358 /* perform soft reset */ 359 wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT); 360 361 /* SOFT_RESET is self clearing */ 362 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME); 363 while (1) { 364 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET); 365 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data); 366 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0) 367 break; 368 369 if (time_after(jiffies, timeout)) { 370 /* 1.2 check pWhalBus->uSelfClearTime if the 371 * timeout was reached */ 372 wl1271_error("soft reset timeout"); 373 return -1; 374 } 375 376 udelay(SOFT_RESET_STALL_TIME); 377 } 378 379 /* disable Rx/Tx */ 380 wl1271_write32(wl, ENABLE, 0x0); 381 382 /* disable auto calibration on start*/ 383 wl1271_write32(wl, SPARE_A2, 0xffff); 384 385 return 0; 386} 387 388static int wl1271_boot_run_firmware(struct wl1271 *wl) 389{ 390 int loop, ret; 391 u32 chip_id, intr; 392 393 wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT); 394 395 chip_id = wl1271_read32(wl, CHIP_ID_B); 396 397 wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id); 398 399 if (chip_id != wl->chip.id) { 400 wl1271_error("chip id doesn't match after firmware boot"); 401 return -EIO; 402 } 403 404 /* wait for init to complete */ 405 loop = 0; 406 while (loop++ < INIT_LOOP) { 407 udelay(INIT_LOOP_DELAY); 408 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); 409 410 if (intr == 0xffffffff) { 411 wl1271_error("error reading hardware complete " 412 "init indication"); 413 return -EIO; 414 } 415 /* check that ACX_INTR_INIT_COMPLETE is enabled */ 416 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) { 417 wl1271_write32(wl, ACX_REG_INTERRUPT_ACK, 418 WL1271_ACX_INTR_INIT_COMPLETE); 419 break; 420 } 421 } 422 423 if (loop > INIT_LOOP) { 424 wl1271_error("timeout waiting for the hardware to " 425 "complete initialization"); 426 return -EIO; 427 } 428 429 /* get hardware config command mail box */ 430 wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR); 431 432 /* get hardware config event mail box */ 433 wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR); 434 435 /* set the working partition to its "running" mode offset */ 436 wl1271_set_partition(wl, &wl12xx_part_table[PART_WORK]); 437 438 wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x", 439 wl->cmd_box_addr, wl->event_box_addr); 440 441 wl1271_boot_fw_version(wl); 442 443 /* 444 * in case of full asynchronous mode the firmware event must be 445 * ready to receive event from the command mailbox 446 */ 447 448 /* unmask required mbox events */ 449 wl->event_mask = BSS_LOSE_EVENT_ID | 450 SCAN_COMPLETE_EVENT_ID | 451 ROLE_STOP_COMPLETE_EVENT_ID | 452 RSSI_SNR_TRIGGER_0_EVENT_ID | 453 PSPOLL_DELIVERY_FAILURE_EVENT_ID | 454 SOFT_GEMINI_SENSE_EVENT_ID | 455 PERIODIC_SCAN_REPORT_EVENT_ID | 456 PERIODIC_SCAN_COMPLETE_EVENT_ID | 457 DUMMY_PACKET_EVENT_ID | 458 PEER_REMOVE_COMPLETE_EVENT_ID | 459 BA_SESSION_RX_CONSTRAINT_EVENT_ID | 460 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID | 461 INACTIVE_STA_EVENT_ID | 462 MAX_TX_RETRY_EVENT_ID | 463 CHANNEL_SWITCH_COMPLETE_EVENT_ID; 464 465 ret = wl1271_event_unmask(wl); 466 if (ret < 0) { 467 wl1271_error("EVENT mask setting failed"); 468 return ret; 469 } 470 471 wl1271_event_mbox_config(wl); 472 473 /* firmware startup completed */ 474 return 0; 475} 476 477static int wl1271_boot_write_irq_polarity(struct wl1271 *wl) 478{ 479 u32 polarity; 480 481 polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY); 482 483 /* We use HIGH polarity, so unset the LOW bit */ 484 polarity &= ~POLARITY_LOW; 485 wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity); 486 487 return 0; 488} 489 490static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl) 491{ 492 u16 spare_reg; 493 494 /* Mask bits [2] & [8:4] in the sys_clk_cfg register */ 495 spare_reg = wl1271_top_reg_read(wl, WL_SPARE_REG); 496 if (spare_reg == 0xFFFF) 497 return -EFAULT; 498 spare_reg |= (BIT(3) | BIT(5) | BIT(6)); 499 wl1271_top_reg_write(wl, WL_SPARE_REG, spare_reg); 500 501 /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */ 502 wl1271_top_reg_write(wl, SYS_CLK_CFG_REG, 503 WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF); 504 505 /* Delay execution for 15msec, to let the HW settle */ 506 mdelay(15); 507 508 return 0; 509} 510 511static bool wl128x_is_tcxo_valid(struct wl1271 *wl) 512{ 513 u16 tcxo_detection; 514 515 tcxo_detection = wl1271_top_reg_read(wl, TCXO_CLK_DETECT_REG); 516 if (tcxo_detection & TCXO_DET_FAILED) 517 return false; 518 519 return true; 520} 521 522static bool wl128x_is_fref_valid(struct wl1271 *wl) 523{ 524 u16 fref_detection; 525 526 fref_detection = wl1271_top_reg_read(wl, FREF_CLK_DETECT_REG); 527 if (fref_detection & FREF_CLK_DETECT_FAIL) 528 return false; 529 530 return true; 531} 532 533static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl) 534{ 535 wl1271_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL); 536 wl1271_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL); 537 wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG, MCS_PLL_CONFIG_REG_VAL); 538 539 return 0; 540} 541 542static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk) 543{ 544 u16 spare_reg; 545 u16 pll_config; 546 u8 input_freq; 547 548 /* Mask bits [3:1] in the sys_clk_cfg register */ 549 spare_reg = wl1271_top_reg_read(wl, WL_SPARE_REG); 550 if (spare_reg == 0xFFFF) 551 return -EFAULT; 552 spare_reg |= BIT(2); 553 wl1271_top_reg_write(wl, WL_SPARE_REG, spare_reg); 554 555 /* Handle special cases of the TCXO clock */ 556 if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_8 || 557 wl->tcxo_clock == WL12XX_TCXOCLOCK_33_6) 558 return wl128x_manually_configure_mcs_pll(wl); 559 560 /* Set the input frequency according to the selected clock source */ 561 input_freq = (clk & 1) + 1; 562 563 pll_config = wl1271_top_reg_read(wl, MCS_PLL_CONFIG_REG); 564 if (pll_config == 0xFFFF) 565 return -EFAULT; 566 pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT); 567 pll_config |= MCS_PLL_ENABLE_HP; 568 wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config); 569 570 return 0; 571} 572 573/* 574 * WL128x has two clocks input - TCXO and FREF. 575 * TCXO is the main clock of the device, while FREF is used to sync 576 * between the GPS and the cellular modem. 577 * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used 578 * as the WLAN/BT main clock. 579 */ 580static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock) 581{ 582 u16 sys_clk_cfg; 583 584 /* For XTAL-only modes, FREF will be used after switching from TCXO */ 585 if (wl->ref_clock == WL12XX_REFCLOCK_26_XTAL || 586 wl->ref_clock == WL12XX_REFCLOCK_38_XTAL) { 587 if (!wl128x_switch_tcxo_to_fref(wl)) 588 return -EINVAL; 589 goto fref_clk; 590 } 591 592 /* Query the HW, to determine which clock source we should use */ 593 sys_clk_cfg = wl1271_top_reg_read(wl, SYS_CLK_CFG_REG); 594 if (sys_clk_cfg == 0xFFFF) 595 return -EINVAL; 596 if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF) 597 goto fref_clk; 598 599 /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */ 600 if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_368 || 601 wl->tcxo_clock == WL12XX_TCXOCLOCK_32_736) { 602 if (!wl128x_switch_tcxo_to_fref(wl)) 603 return -EINVAL; 604 goto fref_clk; 605 } 606 607 /* TCXO clock is selected */ 608 if (!wl128x_is_tcxo_valid(wl)) 609 return -EINVAL; 610 *selected_clock = wl->tcxo_clock; 611 goto config_mcs_pll; 612 613fref_clk: 614 /* FREF clock is selected */ 615 if (!wl128x_is_fref_valid(wl)) 616 return -EINVAL; 617 *selected_clock = wl->ref_clock; 618 619config_mcs_pll: 620 return wl128x_configure_mcs_pll(wl, *selected_clock); 621} 622 623static int wl127x_boot_clk(struct wl1271 *wl) 624{ 625 u32 pause; 626 u32 clk; 627 628 if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3) 629 wl->quirks |= WL12XX_QUIRK_END_OF_TRANSACTION; 630 631 if (wl->ref_clock == CONF_REF_CLK_19_2_E || 632 wl->ref_clock == CONF_REF_CLK_38_4_E || 633 wl->ref_clock == CONF_REF_CLK_38_4_M_XTAL) 634 /* ref clk: 19.2/38.4/38.4-XTAL */ 635 clk = 0x3; 636 else if (wl->ref_clock == CONF_REF_CLK_26_E || 637 wl->ref_clock == CONF_REF_CLK_52_E) 638 /* ref clk: 26/52 */ 639 clk = 0x5; 640 else 641 return -EINVAL; 642 643 if (wl->ref_clock != CONF_REF_CLK_19_2_E) { 644 u16 val; 645 /* Set clock type (open drain) */ 646 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE); 647 val &= FREF_CLK_TYPE_BITS; 648 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val); 649 650 /* Set clock pull mode (no pull) */ 651 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL); 652 val |= NO_PULL; 653 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val); 654 } else { 655 u16 val; 656 /* Set clock polarity */ 657 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY); 658 val &= FREF_CLK_POLARITY_BITS; 659 val |= CLK_REQ_OUTN_SEL; 660 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val); 661 } 662 663 wl1271_write32(wl, PLL_PARAMETERS, clk); 664 665 pause = wl1271_read32(wl, PLL_PARAMETERS); 666 667 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause); 668 669 pause &= ~(WU_COUNTER_PAUSE_VAL); 670 pause |= WU_COUNTER_PAUSE_VAL; 671 wl1271_write32(wl, WU_COUNTER_PAUSE, pause); 672 673 return 0; 674} 675 676/* uploads NVS and firmware */ 677int wl1271_load_firmware(struct wl1271 *wl) 678{ 679 int ret = 0; 680 u32 tmp, clk; 681 int selected_clock = -1; 682 683 if (wl->chip.id == CHIP_ID_1283_PG20) { 684 ret = wl128x_boot_clk(wl, &selected_clock); 685 if (ret < 0) 686 goto out; 687 } else { 688 ret = wl127x_boot_clk(wl); 689 if (ret < 0) 690 goto out; 691 } 692 693 /* Continue the ELP wake up sequence */ 694 wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); 695 udelay(500); 696 697 wl1271_set_partition(wl, &wl12xx_part_table[PART_DRPW]); 698 699 /* Read-modify-write DRPW_SCRATCH_START register (see next state) 700 to be used by DRPw FW. The RTRIM value will be added by the FW 701 before taking DRPw out of reset */ 702 703 wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START); 704 clk = wl1271_read32(wl, DRPW_SCRATCH_START); 705 706 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk); 707 708 if (wl->chip.id == CHIP_ID_1283_PG20) { 709 clk |= ((selected_clock & 0x3) << 1) << 4; 710 } else { 711 clk |= (wl->ref_clock << 1) << 4; 712 } 713 714 wl1271_write32(wl, DRPW_SCRATCH_START, clk); 715 716 wl1271_set_partition(wl, &wl12xx_part_table[PART_WORK]); 717 718 /* Disable interrupts */ 719 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); 720 721 ret = wl1271_boot_soft_reset(wl); 722 if (ret < 0) 723 goto out; 724 725 /* 2. start processing NVS file */ 726 ret = wl1271_boot_upload_nvs(wl); 727 if (ret < 0) 728 goto out; 729 730 /* write firmware's last address (ie. it's length) to 731 * ACX_EEPROMLESS_IND_REG */ 732 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG"); 733 734 wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG); 735 736 tmp = wl1271_read32(wl, CHIP_ID_B); 737 738 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp); 739 740 /* 6. read the EEPROM parameters */ 741 tmp = wl1271_read32(wl, SCR_PAD2); 742 743 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly 744 * to upload_fw) */ 745 746 if (wl->chip.id == CHIP_ID_1283_PG20) 747 wl1271_top_reg_write(wl, SDIO_IO_DS, wl->conf.hci_io_ds); 748 749 ret = wl1271_boot_upload_firmware(wl); 750 if (ret < 0) 751 goto out; 752 753out: 754 return ret; 755} 756EXPORT_SYMBOL_GPL(wl1271_load_firmware); 757 758int wl1271_boot(struct wl1271 *wl) 759{ 760 int ret; 761 762 /* upload NVS and firmware */ 763 ret = wl1271_load_firmware(wl); 764 if (ret) 765 return ret; 766 767 /* 10.5 start firmware */ 768 ret = wl1271_boot_run_firmware(wl); 769 if (ret < 0) 770 goto out; 771 772 ret = wl1271_boot_write_irq_polarity(wl); 773 if (ret < 0) 774 goto out; 775 776 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, 777 WL1271_ACX_ALL_EVENTS_VECTOR); 778 779 /* Enable firmware interrupts now */ 780 wl1271_boot_enable_interrupts(wl); 781 782 wl1271_event_mbox_config(wl); 783 784out: 785 return ret; 786} 787