1/* 2 * Copyright (c) 2009-2010 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 17 * The full GNU General Public License is included in this distribution in 18 * the file called "COPYING". 19 * 20 * Authors: 21 * Jesse Barnes <jbarnes@virtuousgeek.org> 22 */ 23 24/* 25 * Some Intel Ibex Peak based platforms support so-called "intelligent 26 * power sharing", which allows the CPU and GPU to cooperate to maximize 27 * performance within a given TDP (thermal design point). This driver 28 * performs the coordination between the CPU and GPU, monitors thermal and 29 * power statistics in the platform, and initializes power monitoring 30 * hardware. It also provides a few tunables to control behavior. Its 31 * primary purpose is to safely allow CPU and GPU turbo modes to be enabled 32 * by tracking power and thermal budget; secondarily it can boost turbo 33 * performance by allocating more power or thermal budget to the CPU or GPU 34 * based on available headroom and activity. 35 * 36 * The basic algorithm is driven by a 5s moving average of tempurature. If 37 * thermal headroom is available, the CPU and/or GPU power clamps may be 38 * adjusted upwards. If we hit the thermal ceiling or a thermal trigger, 39 * we scale back the clamp. Aside from trigger events (when we're critically 40 * close or over our TDP) we don't adjust the clamps more than once every 41 * five seconds. 42 * 43 * The thermal device (device 31, function 6) has a set of registers that 44 * are updated by the ME firmware. The ME should also take the clamp values 45 * written to those registers and write them to the CPU, but we currently 46 * bypass that functionality and write the CPU MSR directly. 47 * 48 * UNSUPPORTED: 49 * - dual MCP configs 50 * 51 * TODO: 52 * - handle CPU hotplug 53 * - provide turbo enable/disable api 54 * 55 * Related documents: 56 * - CDI 403777, 403778 - Auburndale EDS vol 1 & 2 57 * - CDI 401376 - Ibex Peak EDS 58 * - ref 26037, 26641 - IPS BIOS spec 59 * - ref 26489 - Nehalem BIOS writer's guide 60 * - ref 26921 - Ibex Peak BIOS Specification 61 */ 62 63#include <linux/debugfs.h> 64#include <linux/delay.h> 65#include <linux/interrupt.h> 66#include <linux/kernel.h> 67#include <linux/kthread.h> 68#include <linux/module.h> 69#include <linux/pci.h> 70#include <linux/sched.h> 71#include <linux/seq_file.h> 72#include <linux/string.h> 73#include <linux/tick.h> 74#include <linux/timer.h> 75#include <drm/i915_drm.h> 76#include <asm/msr.h> 77#include <asm/processor.h> 78#include "intel_ips.h" 79 80#include <asm-generic/io-64-nonatomic-lo-hi.h> 81 82#define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32 83 84/* 85 * Package level MSRs for monitor/control 86 */ 87#define PLATFORM_INFO 0xce 88#define PLATFORM_TDP (1<<29) 89#define PLATFORM_RATIO (1<<28) 90 91#define IA32_MISC_ENABLE 0x1a0 92#define IA32_MISC_TURBO_EN (1ULL<<38) 93 94#define TURBO_POWER_CURRENT_LIMIT 0x1ac 95#define TURBO_TDC_OVR_EN (1UL<<31) 96#define TURBO_TDC_MASK (0x000000007fff0000UL) 97#define TURBO_TDC_SHIFT (16) 98#define TURBO_TDP_OVR_EN (1UL<<15) 99#define TURBO_TDP_MASK (0x0000000000003fffUL) 100 101/* 102 * Core/thread MSRs for monitoring 103 */ 104#define IA32_PERF_CTL 0x199 105#define IA32_PERF_TURBO_DIS (1ULL<<32) 106 107/* 108 * Thermal PCI device regs 109 */ 110#define THM_CFG_TBAR 0x10 111#define THM_CFG_TBAR_HI 0x14 112 113#define THM_TSIU 0x00 114#define THM_TSE 0x01 115#define TSE_EN 0xb8 116#define THM_TSS 0x02 117#define THM_TSTR 0x03 118#define THM_TSTTP 0x04 119#define THM_TSCO 0x08 120#define THM_TSES 0x0c 121#define THM_TSGPEN 0x0d 122#define TSGPEN_HOT_LOHI (1<<1) 123#define TSGPEN_CRIT_LOHI (1<<2) 124#define THM_TSPC 0x0e 125#define THM_PPEC 0x10 126#define THM_CTA 0x12 127#define THM_PTA 0x14 128#define PTA_SLOPE_MASK (0xff00) 129#define PTA_SLOPE_SHIFT 8 130#define PTA_OFFSET_MASK (0x00ff) 131#define THM_MGTA 0x16 132#define MGTA_SLOPE_MASK (0xff00) 133#define MGTA_SLOPE_SHIFT 8 134#define MGTA_OFFSET_MASK (0x00ff) 135#define THM_TRC 0x1a 136#define TRC_CORE2_EN (1<<15) 137#define TRC_THM_EN (1<<12) 138#define TRC_C6_WAR (1<<8) 139#define TRC_CORE1_EN (1<<7) 140#define TRC_CORE_PWR (1<<6) 141#define TRC_PCH_EN (1<<5) 142#define TRC_MCH_EN (1<<4) 143#define TRC_DIMM4 (1<<3) 144#define TRC_DIMM3 (1<<2) 145#define TRC_DIMM2 (1<<1) 146#define TRC_DIMM1 (1<<0) 147#define THM_TES 0x20 148#define THM_TEN 0x21 149#define TEN_UPDATE_EN 1 150#define THM_PSC 0x24 151#define PSC_NTG (1<<0) /* No GFX turbo support */ 152#define PSC_NTPC (1<<1) /* No CPU turbo support */ 153#define PSC_PP_DEF (0<<2) /* Perf policy up to driver */ 154#define PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */ 155#define PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */ 156#define PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */ 157#define PSP_PBRT (1<<4) /* BIOS run time support */ 158#define THM_CTV1 0x30 159#define CTV_TEMP_ERROR (1<<15) 160#define CTV_TEMP_MASK 0x3f 161#define CTV_ 162#define THM_CTV2 0x32 163#define THM_CEC 0x34 /* undocumented power accumulator in joules */ 164#define THM_AE 0x3f 165#define THM_HTS 0x50 /* 32 bits */ 166#define HTS_PCPL_MASK (0x7fe00000) 167#define HTS_PCPL_SHIFT 21 168#define HTS_GPL_MASK (0x001ff000) 169#define HTS_GPL_SHIFT 12 170#define HTS_PP_MASK (0x00000c00) 171#define HTS_PP_SHIFT 10 172#define HTS_PP_DEF 0 173#define HTS_PP_PROC 1 174#define HTS_PP_BAL 2 175#define HTS_PP_GFX 3 176#define HTS_PCTD_DIS (1<<9) 177#define HTS_GTD_DIS (1<<8) 178#define HTS_PTL_MASK (0x000000fe) 179#define HTS_PTL_SHIFT 1 180#define HTS_NVV (1<<0) 181#define THM_HTSHI 0x54 /* 16 bits */ 182#define HTS2_PPL_MASK (0x03ff) 183#define HTS2_PRST_MASK (0x3c00) 184#define HTS2_PRST_SHIFT 10 185#define HTS2_PRST_UNLOADED 0 186#define HTS2_PRST_RUNNING 1 187#define HTS2_PRST_TDISOP 2 /* turbo disabled due to power */ 188#define HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */ 189#define HTS2_PRST_TDISUSR 4 /* user disabled turbo */ 190#define HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */ 191#define HTS2_PRST_TDISPM 6 /* power management disabled turbo */ 192#define HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */ 193#define THM_PTL 0x56 194#define THM_MGTV 0x58 195#define TV_MASK 0x000000000000ff00 196#define TV_SHIFT 8 197#define THM_PTV 0x60 198#define PTV_MASK 0x00ff 199#define THM_MMGPC 0x64 200#define THM_MPPC 0x66 201#define THM_MPCPC 0x68 202#define THM_TSPIEN 0x82 203#define TSPIEN_AUX_LOHI (1<<0) 204#define TSPIEN_HOT_LOHI (1<<1) 205#define TSPIEN_CRIT_LOHI (1<<2) 206#define TSPIEN_AUX2_LOHI (1<<3) 207#define THM_TSLOCK 0x83 208#define THM_ATR 0x84 209#define THM_TOF 0x87 210#define THM_STS 0x98 211#define STS_PCPL_MASK (0x7fe00000) 212#define STS_PCPL_SHIFT 21 213#define STS_GPL_MASK (0x001ff000) 214#define STS_GPL_SHIFT 12 215#define STS_PP_MASK (0x00000c00) 216#define STS_PP_SHIFT 10 217#define STS_PP_DEF 0 218#define STS_PP_PROC 1 219#define STS_PP_BAL 2 220#define STS_PP_GFX 3 221#define STS_PCTD_DIS (1<<9) 222#define STS_GTD_DIS (1<<8) 223#define STS_PTL_MASK (0x000000fe) 224#define STS_PTL_SHIFT 1 225#define STS_NVV (1<<0) 226#define THM_SEC 0x9c 227#define SEC_ACK (1<<0) 228#define THM_TC3 0xa4 229#define THM_TC1 0xa8 230#define STS_PPL_MASK (0x0003ff00) 231#define STS_PPL_SHIFT 16 232#define THM_TC2 0xac 233#define THM_DTV 0xb0 234#define THM_ITV 0xd8 235#define ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */ 236#define ITV_ME_SEQNO_SHIFT (16) 237#define ITV_MCH_TEMP_MASK 0x0000ff00 238#define ITV_MCH_TEMP_SHIFT (8) 239#define ITV_PCH_TEMP_MASK 0x000000ff 240 241#define thm_readb(off) readb(ips->regmap + (off)) 242#define thm_readw(off) readw(ips->regmap + (off)) 243#define thm_readl(off) readl(ips->regmap + (off)) 244#define thm_readq(off) readq(ips->regmap + (off)) 245 246#define thm_writeb(off, val) writeb((val), ips->regmap + (off)) 247#define thm_writew(off, val) writew((val), ips->regmap + (off)) 248#define thm_writel(off, val) writel((val), ips->regmap + (off)) 249 250static const int IPS_ADJUST_PERIOD = 5000; /* ms */ 251static bool late_i915_load = false; 252 253/* For initial average collection */ 254static const int IPS_SAMPLE_PERIOD = 200; /* ms */ 255static const int IPS_SAMPLE_WINDOW = 5000; /* 5s moving window of samples */ 256#define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD) 257 258/* Per-SKU limits */ 259struct ips_mcp_limits { 260 int cpu_family; 261 int cpu_model; /* includes extended model... */ 262 int mcp_power_limit; /* mW units */ 263 int core_power_limit; 264 int mch_power_limit; 265 int core_temp_limit; /* degrees C */ 266 int mch_temp_limit; 267}; 268 269/* Max temps are -10 degrees C to avoid PROCHOT# */ 270 271struct ips_mcp_limits ips_sv_limits = { 272 .mcp_power_limit = 35000, 273 .core_power_limit = 29000, 274 .mch_power_limit = 20000, 275 .core_temp_limit = 95, 276 .mch_temp_limit = 90 277}; 278 279struct ips_mcp_limits ips_lv_limits = { 280 .mcp_power_limit = 25000, 281 .core_power_limit = 21000, 282 .mch_power_limit = 13000, 283 .core_temp_limit = 95, 284 .mch_temp_limit = 90 285}; 286 287struct ips_mcp_limits ips_ulv_limits = { 288 .mcp_power_limit = 18000, 289 .core_power_limit = 14000, 290 .mch_power_limit = 11000, 291 .core_temp_limit = 95, 292 .mch_temp_limit = 90 293}; 294 295struct ips_driver { 296 struct pci_dev *dev; 297 void *regmap; 298 struct task_struct *monitor; 299 struct task_struct *adjust; 300 struct dentry *debug_root; 301 302 /* Average CPU core temps (all averages in .01 degrees C for precision) */ 303 u16 ctv1_avg_temp; 304 u16 ctv2_avg_temp; 305 /* GMCH average */ 306 u16 mch_avg_temp; 307 /* Average for the CPU (both cores?) */ 308 u16 mcp_avg_temp; 309 /* Average power consumption (in mW) */ 310 u32 cpu_avg_power; 311 u32 mch_avg_power; 312 313 /* Offset values */ 314 u16 cta_val; 315 u16 pta_val; 316 u16 mgta_val; 317 318 /* Maximums & prefs, protected by turbo status lock */ 319 spinlock_t turbo_status_lock; 320 u16 mcp_temp_limit; 321 u16 mcp_power_limit; 322 u16 core_power_limit; 323 u16 mch_power_limit; 324 bool cpu_turbo_enabled; 325 bool __cpu_turbo_on; 326 bool gpu_turbo_enabled; 327 bool __gpu_turbo_on; 328 bool gpu_preferred; 329 bool poll_turbo_status; 330 bool second_cpu; 331 bool turbo_toggle_allowed; 332 struct ips_mcp_limits *limits; 333 334 /* Optional MCH interfaces for if i915 is in use */ 335 unsigned long (*read_mch_val)(void); 336 bool (*gpu_raise)(void); 337 bool (*gpu_lower)(void); 338 bool (*gpu_busy)(void); 339 bool (*gpu_turbo_disable)(void); 340 341 /* For restoration at unload */ 342 u64 orig_turbo_limit; 343 u64 orig_turbo_ratios; 344}; 345 346static bool 347ips_gpu_turbo_enabled(struct ips_driver *ips); 348 349/** 350 * ips_cpu_busy - is CPU busy? 351 * @ips: IPS driver struct 352 * 353 * Check CPU for load to see whether we should increase its thermal budget. 354 * 355 * RETURNS: 356 * True if the CPU could use more power, false otherwise. 357 */ 358static bool ips_cpu_busy(struct ips_driver *ips) 359{ 360 if ((avenrun[0] >> FSHIFT) > 1) 361 return true; 362 363 return false; 364} 365 366/** 367 * ips_cpu_raise - raise CPU power clamp 368 * @ips: IPS driver struct 369 * 370 * Raise the CPU power clamp by %IPS_CPU_STEP, in accordance with TDP for 371 * this platform. 372 * 373 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR upwards (as 374 * long as we haven't hit the TDP limit for the SKU). 375 */ 376static void ips_cpu_raise(struct ips_driver *ips) 377{ 378 u64 turbo_override; 379 u16 cur_tdp_limit, new_tdp_limit; 380 381 if (!ips->cpu_turbo_enabled) 382 return; 383 384 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 385 386 cur_tdp_limit = turbo_override & TURBO_TDP_MASK; 387 new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */ 388 389 /* Clamp to SKU TDP limit */ 390 if (((new_tdp_limit * 10) / 8) > ips->core_power_limit) 391 new_tdp_limit = cur_tdp_limit; 392 393 thm_writew(THM_MPCPC, (new_tdp_limit * 10) / 8); 394 395 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN; 396 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 397 398 turbo_override &= ~TURBO_TDP_MASK; 399 turbo_override |= new_tdp_limit; 400 401 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 402} 403 404/** 405 * ips_cpu_lower - lower CPU power clamp 406 * @ips: IPS driver struct 407 * 408 * Lower CPU power clamp b %IPS_CPU_STEP if possible. 409 * 410 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR down, going 411 * as low as the platform limits will allow (though we could go lower there 412 * wouldn't be much point). 413 */ 414static void ips_cpu_lower(struct ips_driver *ips) 415{ 416 u64 turbo_override; 417 u16 cur_limit, new_limit; 418 419 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 420 421 cur_limit = turbo_override & TURBO_TDP_MASK; 422 new_limit = cur_limit - 8; /* 1W decrease */ 423 424 /* Clamp to SKU TDP limit */ 425 if (new_limit < (ips->orig_turbo_limit & TURBO_TDP_MASK)) 426 new_limit = ips->orig_turbo_limit & TURBO_TDP_MASK; 427 428 thm_writew(THM_MPCPC, (new_limit * 10) / 8); 429 430 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN; 431 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 432 433 turbo_override &= ~TURBO_TDP_MASK; 434 turbo_override |= new_limit; 435 436 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 437} 438 439/** 440 * do_enable_cpu_turbo - internal turbo enable function 441 * @data: unused 442 * 443 * Internal function for actually updating MSRs. When we enable/disable 444 * turbo, we need to do it on each CPU; this function is the one called 445 * by on_each_cpu() when needed. 446 */ 447static void do_enable_cpu_turbo(void *data) 448{ 449 u64 perf_ctl; 450 451 rdmsrl(IA32_PERF_CTL, perf_ctl); 452 if (perf_ctl & IA32_PERF_TURBO_DIS) { 453 perf_ctl &= ~IA32_PERF_TURBO_DIS; 454 wrmsrl(IA32_PERF_CTL, perf_ctl); 455 } 456} 457 458/** 459 * ips_enable_cpu_turbo - enable turbo mode on all CPUs 460 * @ips: IPS driver struct 461 * 462 * Enable turbo mode by clearing the disable bit in IA32_PERF_CTL on 463 * all logical threads. 464 */ 465static void ips_enable_cpu_turbo(struct ips_driver *ips) 466{ 467 /* Already on, no need to mess with MSRs */ 468 if (ips->__cpu_turbo_on) 469 return; 470 471 if (ips->turbo_toggle_allowed) 472 on_each_cpu(do_enable_cpu_turbo, ips, 1); 473 474 ips->__cpu_turbo_on = true; 475} 476 477/** 478 * do_disable_cpu_turbo - internal turbo disable function 479 * @data: unused 480 * 481 * Internal function for actually updating MSRs. When we enable/disable 482 * turbo, we need to do it on each CPU; this function is the one called 483 * by on_each_cpu() when needed. 484 */ 485static void do_disable_cpu_turbo(void *data) 486{ 487 u64 perf_ctl; 488 489 rdmsrl(IA32_PERF_CTL, perf_ctl); 490 if (!(perf_ctl & IA32_PERF_TURBO_DIS)) { 491 perf_ctl |= IA32_PERF_TURBO_DIS; 492 wrmsrl(IA32_PERF_CTL, perf_ctl); 493 } 494} 495 496/** 497 * ips_disable_cpu_turbo - disable turbo mode on all CPUs 498 * @ips: IPS driver struct 499 * 500 * Disable turbo mode by setting the disable bit in IA32_PERF_CTL on 501 * all logical threads. 502 */ 503static void ips_disable_cpu_turbo(struct ips_driver *ips) 504{ 505 /* Already off, leave it */ 506 if (!ips->__cpu_turbo_on) 507 return; 508 509 if (ips->turbo_toggle_allowed) 510 on_each_cpu(do_disable_cpu_turbo, ips, 1); 511 512 ips->__cpu_turbo_on = false; 513} 514 515/** 516 * ips_gpu_busy - is GPU busy? 517 * @ips: IPS driver struct 518 * 519 * Check GPU for load to see whether we should increase its thermal budget. 520 * We need to call into the i915 driver in this case. 521 * 522 * RETURNS: 523 * True if the GPU could use more power, false otherwise. 524 */ 525static bool ips_gpu_busy(struct ips_driver *ips) 526{ 527 if (!ips_gpu_turbo_enabled(ips)) 528 return false; 529 530 return ips->gpu_busy(); 531} 532 533/** 534 * ips_gpu_raise - raise GPU power clamp 535 * @ips: IPS driver struct 536 * 537 * Raise the GPU frequency/power if possible. We need to call into the 538 * i915 driver in this case. 539 */ 540static void ips_gpu_raise(struct ips_driver *ips) 541{ 542 if (!ips_gpu_turbo_enabled(ips)) 543 return; 544 545 if (!ips->gpu_raise()) 546 ips->gpu_turbo_enabled = false; 547 548 return; 549} 550 551/** 552 * ips_gpu_lower - lower GPU power clamp 553 * @ips: IPS driver struct 554 * 555 * Lower GPU frequency/power if possible. Need to call i915. 556 */ 557static void ips_gpu_lower(struct ips_driver *ips) 558{ 559 if (!ips_gpu_turbo_enabled(ips)) 560 return; 561 562 if (!ips->gpu_lower()) 563 ips->gpu_turbo_enabled = false; 564 565 return; 566} 567 568/** 569 * ips_enable_gpu_turbo - notify the gfx driver turbo is available 570 * @ips: IPS driver struct 571 * 572 * Call into the graphics driver indicating that it can safely use 573 * turbo mode. 574 */ 575static void ips_enable_gpu_turbo(struct ips_driver *ips) 576{ 577 if (ips->__gpu_turbo_on) 578 return; 579 ips->__gpu_turbo_on = true; 580} 581 582/** 583 * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode 584 * @ips: IPS driver struct 585 * 586 * Request that the graphics driver disable turbo mode. 587 */ 588static void ips_disable_gpu_turbo(struct ips_driver *ips) 589{ 590 /* Avoid calling i915 if turbo is already disabled */ 591 if (!ips->__gpu_turbo_on) 592 return; 593 594 if (!ips->gpu_turbo_disable()) 595 dev_err(&ips->dev->dev, "failed to disable graphis turbo\n"); 596 else 597 ips->__gpu_turbo_on = false; 598} 599 600/** 601 * mcp_exceeded - check whether we're outside our thermal & power limits 602 * @ips: IPS driver struct 603 * 604 * Check whether the MCP is over its thermal or power budget. 605 */ 606static bool mcp_exceeded(struct ips_driver *ips) 607{ 608 unsigned long flags; 609 bool ret = false; 610 u32 temp_limit; 611 u32 avg_power; 612 613 spin_lock_irqsave(&ips->turbo_status_lock, flags); 614 615 temp_limit = ips->mcp_temp_limit * 100; 616 if (ips->mcp_avg_temp > temp_limit) 617 ret = true; 618 619 avg_power = ips->cpu_avg_power + ips->mch_avg_power; 620 if (avg_power > ips->mcp_power_limit) 621 ret = true; 622 623 spin_unlock_irqrestore(&ips->turbo_status_lock, flags); 624 625 return ret; 626} 627 628/** 629 * cpu_exceeded - check whether a CPU core is outside its limits 630 * @ips: IPS driver struct 631 * @cpu: CPU number to check 632 * 633 * Check a given CPU's average temp or power is over its limit. 634 */ 635static bool cpu_exceeded(struct ips_driver *ips, int cpu) 636{ 637 unsigned long flags; 638 int avg; 639 bool ret = false; 640 641 spin_lock_irqsave(&ips->turbo_status_lock, flags); 642 avg = cpu ? ips->ctv2_avg_temp : ips->ctv1_avg_temp; 643 if (avg > (ips->limits->core_temp_limit * 100)) 644 ret = true; 645 if (ips->cpu_avg_power > ips->core_power_limit * 100) 646 ret = true; 647 spin_unlock_irqrestore(&ips->turbo_status_lock, flags); 648 649 if (ret) 650 dev_info(&ips->dev->dev, 651 "CPU power or thermal limit exceeded\n"); 652 653 return ret; 654} 655 656/** 657 * mch_exceeded - check whether the GPU is over budget 658 * @ips: IPS driver struct 659 * 660 * Check the MCH temp & power against their maximums. 661 */ 662static bool mch_exceeded(struct ips_driver *ips) 663{ 664 unsigned long flags; 665 bool ret = false; 666 667 spin_lock_irqsave(&ips->turbo_status_lock, flags); 668 if (ips->mch_avg_temp > (ips->limits->mch_temp_limit * 100)) 669 ret = true; 670 if (ips->mch_avg_power > ips->mch_power_limit) 671 ret = true; 672 spin_unlock_irqrestore(&ips->turbo_status_lock, flags); 673 674 return ret; 675} 676 677/** 678 * verify_limits - verify BIOS provided limits 679 * @ips: IPS structure 680 * 681 * BIOS can optionally provide non-default limits for power and temp. Check 682 * them here and use the defaults if the BIOS values are not provided or 683 * are otherwise unusable. 684 */ 685static void verify_limits(struct ips_driver *ips) 686{ 687 if (ips->mcp_power_limit < ips->limits->mcp_power_limit || 688 ips->mcp_power_limit > 35000) 689 ips->mcp_power_limit = ips->limits->mcp_power_limit; 690 691 if (ips->mcp_temp_limit < ips->limits->core_temp_limit || 692 ips->mcp_temp_limit < ips->limits->mch_temp_limit || 693 ips->mcp_temp_limit > 150) 694 ips->mcp_temp_limit = min(ips->limits->core_temp_limit, 695 ips->limits->mch_temp_limit); 696} 697 698/** 699 * update_turbo_limits - get various limits & settings from regs 700 * @ips: IPS driver struct 701 * 702 * Update the IPS power & temp limits, along with turbo enable flags, 703 * based on latest register contents. 704 * 705 * Used at init time and for runtime BIOS support, which requires polling 706 * the regs for updates (as a result of AC->DC transition for example). 707 * 708 * LOCKING: 709 * Caller must hold turbo_status_lock (outside of init) 710 */ 711static void update_turbo_limits(struct ips_driver *ips) 712{ 713 u32 hts = thm_readl(THM_HTS); 714 715 ips->cpu_turbo_enabled = !(hts & HTS_PCTD_DIS); 716 /* 717 * Disable turbo for now, until we can figure out why the power figures 718 * are wrong 719 */ 720 ips->cpu_turbo_enabled = false; 721 722 if (ips->gpu_busy) 723 ips->gpu_turbo_enabled = !(hts & HTS_GTD_DIS); 724 725 ips->core_power_limit = thm_readw(THM_MPCPC); 726 ips->mch_power_limit = thm_readw(THM_MMGPC); 727 ips->mcp_temp_limit = thm_readw(THM_PTL); 728 ips->mcp_power_limit = thm_readw(THM_MPPC); 729 730 verify_limits(ips); 731 /* Ignore BIOS CPU vs GPU pref */ 732} 733 734/** 735 * ips_adjust - adjust power clamp based on thermal state 736 * @data: ips driver structure 737 * 738 * Wake up every 5s or so and check whether we should adjust the power clamp. 739 * Check CPU and GPU load to determine which needs adjustment. There are 740 * several things to consider here: 741 * - do we need to adjust up or down? 742 * - is CPU busy? 743 * - is GPU busy? 744 * - is CPU in turbo? 745 * - is GPU in turbo? 746 * - is CPU or GPU preferred? (CPU is default) 747 * 748 * So, given the above, we do the following: 749 * - up (TDP available) 750 * - CPU not busy, GPU not busy - nothing 751 * - CPU busy, GPU not busy - adjust CPU up 752 * - CPU not busy, GPU busy - adjust GPU up 753 * - CPU busy, GPU busy - adjust preferred unit up, taking headroom from 754 * non-preferred unit if necessary 755 * - down (at TDP limit) 756 * - adjust both CPU and GPU down if possible 757 * 758 cpu+ gpu+ cpu+gpu- cpu-gpu+ cpu-gpu- 759cpu < gpu < cpu+gpu+ cpu+ gpu+ nothing 760cpu < gpu >= cpu+gpu-(mcp<) cpu+gpu-(mcp<) gpu- gpu- 761cpu >= gpu < cpu-gpu+(mcp<) cpu- cpu-gpu+(mcp<) cpu- 762cpu >= gpu >= cpu-gpu- cpu-gpu- cpu-gpu- cpu-gpu- 763 * 764 */ 765static int ips_adjust(void *data) 766{ 767 struct ips_driver *ips = data; 768 unsigned long flags; 769 770 dev_dbg(&ips->dev->dev, "starting ips-adjust thread\n"); 771 772 /* 773 * Adjust CPU and GPU clamps every 5s if needed. Doing it more 774 * often isn't recommended due to ME interaction. 775 */ 776 do { 777 bool cpu_busy = ips_cpu_busy(ips); 778 bool gpu_busy = ips_gpu_busy(ips); 779 780 spin_lock_irqsave(&ips->turbo_status_lock, flags); 781 if (ips->poll_turbo_status) 782 update_turbo_limits(ips); 783 spin_unlock_irqrestore(&ips->turbo_status_lock, flags); 784 785 /* Update turbo status if necessary */ 786 if (ips->cpu_turbo_enabled) 787 ips_enable_cpu_turbo(ips); 788 else 789 ips_disable_cpu_turbo(ips); 790 791 if (ips->gpu_turbo_enabled) 792 ips_enable_gpu_turbo(ips); 793 else 794 ips_disable_gpu_turbo(ips); 795 796 /* We're outside our comfort zone, crank them down */ 797 if (mcp_exceeded(ips)) { 798 ips_cpu_lower(ips); 799 ips_gpu_lower(ips); 800 goto sleep; 801 } 802 803 if (!cpu_exceeded(ips, 0) && cpu_busy) 804 ips_cpu_raise(ips); 805 else 806 ips_cpu_lower(ips); 807 808 if (!mch_exceeded(ips) && gpu_busy) 809 ips_gpu_raise(ips); 810 else 811 ips_gpu_lower(ips); 812 813sleep: 814 schedule_timeout_interruptible(msecs_to_jiffies(IPS_ADJUST_PERIOD)); 815 } while (!kthread_should_stop()); 816 817 dev_dbg(&ips->dev->dev, "ips-adjust thread stopped\n"); 818 819 return 0; 820} 821 822/* 823 * Helpers for reading out temp/power values and calculating their 824 * averages for the decision making and monitoring functions. 825 */ 826 827static u16 calc_avg_temp(struct ips_driver *ips, u16 *array) 828{ 829 u64 total = 0; 830 int i; 831 u16 avg; 832 833 for (i = 0; i < IPS_SAMPLE_COUNT; i++) 834 total += (u64)(array[i] * 100); 835 836 do_div(total, IPS_SAMPLE_COUNT); 837 838 avg = (u16)total; 839 840 return avg; 841} 842 843static u16 read_mgtv(struct ips_driver *ips) 844{ 845 u16 ret; 846 u64 slope, offset; 847 u64 val; 848 849 val = thm_readq(THM_MGTV); 850 val = (val & TV_MASK) >> TV_SHIFT; 851 852 slope = offset = thm_readw(THM_MGTA); 853 slope = (slope & MGTA_SLOPE_MASK) >> MGTA_SLOPE_SHIFT; 854 offset = offset & MGTA_OFFSET_MASK; 855 856 ret = ((val * slope + 0x40) >> 7) + offset; 857 858 return 0; /* MCH temp reporting buggy */ 859} 860 861static u16 read_ptv(struct ips_driver *ips) 862{ 863 u16 val, slope, offset; 864 865 slope = (ips->pta_val & PTA_SLOPE_MASK) >> PTA_SLOPE_SHIFT; 866 offset = ips->pta_val & PTA_OFFSET_MASK; 867 868 val = thm_readw(THM_PTV) & PTV_MASK; 869 870 return val; 871} 872 873static u16 read_ctv(struct ips_driver *ips, int cpu) 874{ 875 int reg = cpu ? THM_CTV2 : THM_CTV1; 876 u16 val; 877 878 val = thm_readw(reg); 879 if (!(val & CTV_TEMP_ERROR)) 880 val = (val) >> 6; /* discard fractional component */ 881 else 882 val = 0; 883 884 return val; 885} 886 887static u32 get_cpu_power(struct ips_driver *ips, u32 *last, int period) 888{ 889 u32 val; 890 u32 ret; 891 892 /* 893 * CEC is in joules/65535. Take difference over time to 894 * get watts. 895 */ 896 val = thm_readl(THM_CEC); 897 898 /* period is in ms and we want mW */ 899 ret = (((val - *last) * 1000) / period); 900 ret = (ret * 1000) / 65535; 901 *last = val; 902 903 return 0; 904} 905 906static const u16 temp_decay_factor = 2; 907static u16 update_average_temp(u16 avg, u16 val) 908{ 909 u16 ret; 910 911 /* Multiply by 100 for extra precision */ 912 ret = (val * 100 / temp_decay_factor) + 913 (((temp_decay_factor - 1) * avg) / temp_decay_factor); 914 return ret; 915} 916 917static const u16 power_decay_factor = 2; 918static u16 update_average_power(u32 avg, u32 val) 919{ 920 u32 ret; 921 922 ret = (val / power_decay_factor) + 923 (((power_decay_factor - 1) * avg) / power_decay_factor); 924 925 return ret; 926} 927 928static u32 calc_avg_power(struct ips_driver *ips, u32 *array) 929{ 930 u64 total = 0; 931 u32 avg; 932 int i; 933 934 for (i = 0; i < IPS_SAMPLE_COUNT; i++) 935 total += array[i]; 936 937 do_div(total, IPS_SAMPLE_COUNT); 938 avg = (u32)total; 939 940 return avg; 941} 942 943static void monitor_timeout(unsigned long arg) 944{ 945 wake_up_process((struct task_struct *)arg); 946} 947 948/** 949 * ips_monitor - temp/power monitoring thread 950 * @data: ips driver structure 951 * 952 * This is the main function for the IPS driver. It monitors power and 953 * tempurature in the MCP and adjusts CPU and GPU power clams accordingly. 954 * 955 * We keep a 5s moving average of power consumption and tempurature. Using 956 * that data, along with CPU vs GPU preference, we adjust the power clamps 957 * up or down. 958 */ 959static int ips_monitor(void *data) 960{ 961 struct ips_driver *ips = data; 962 struct timer_list timer; 963 unsigned long seqno_timestamp, expire, last_msecs, last_sample_period; 964 int i; 965 u32 *cpu_samples, *mchp_samples, old_cpu_power; 966 u16 *mcp_samples, *ctv1_samples, *ctv2_samples, *mch_samples; 967 u8 cur_seqno, last_seqno; 968 969 mcp_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); 970 ctv1_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); 971 ctv2_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); 972 mch_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); 973 cpu_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL); 974 mchp_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL); 975 if (!mcp_samples || !ctv1_samples || !ctv2_samples || !mch_samples || 976 !cpu_samples || !mchp_samples) { 977 dev_err(&ips->dev->dev, 978 "failed to allocate sample array, ips disabled\n"); 979 kfree(mcp_samples); 980 kfree(ctv1_samples); 981 kfree(ctv2_samples); 982 kfree(mch_samples); 983 kfree(cpu_samples); 984 kfree(mchp_samples); 985 return -ENOMEM; 986 } 987 988 last_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >> 989 ITV_ME_SEQNO_SHIFT; 990 seqno_timestamp = get_jiffies_64(); 991 992 old_cpu_power = thm_readl(THM_CEC); 993 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD)); 994 995 /* Collect an initial average */ 996 for (i = 0; i < IPS_SAMPLE_COUNT; i++) { 997 u32 mchp, cpu_power; 998 u16 val; 999 1000 mcp_samples[i] = read_ptv(ips); 1001 1002 val = read_ctv(ips, 0); 1003 ctv1_samples[i] = val; 1004 1005 val = read_ctv(ips, 1); 1006 ctv2_samples[i] = val; 1007 1008 val = read_mgtv(ips); 1009 mch_samples[i] = val; 1010 1011 cpu_power = get_cpu_power(ips, &old_cpu_power, 1012 IPS_SAMPLE_PERIOD); 1013 cpu_samples[i] = cpu_power; 1014 1015 if (ips->read_mch_val) { 1016 mchp = ips->read_mch_val(); 1017 mchp_samples[i] = mchp; 1018 } 1019 1020 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD)); 1021 if (kthread_should_stop()) 1022 break; 1023 } 1024 1025 ips->mcp_avg_temp = calc_avg_temp(ips, mcp_samples); 1026 ips->ctv1_avg_temp = calc_avg_temp(ips, ctv1_samples); 1027 ips->ctv2_avg_temp = calc_avg_temp(ips, ctv2_samples); 1028 ips->mch_avg_temp = calc_avg_temp(ips, mch_samples); 1029 ips->cpu_avg_power = calc_avg_power(ips, cpu_samples); 1030 ips->mch_avg_power = calc_avg_power(ips, mchp_samples); 1031 kfree(mcp_samples); 1032 kfree(ctv1_samples); 1033 kfree(ctv2_samples); 1034 kfree(mch_samples); 1035 kfree(cpu_samples); 1036 kfree(mchp_samples); 1037 1038 /* Start the adjustment thread now that we have data */ 1039 wake_up_process(ips->adjust); 1040 1041 /* 1042 * Ok, now we have an initial avg. From here on out, we track the 1043 * running avg using a decaying average calculation. This allows 1044 * us to reduce the sample frequency if the CPU and GPU are idle. 1045 */ 1046 old_cpu_power = thm_readl(THM_CEC); 1047 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD)); 1048 last_sample_period = IPS_SAMPLE_PERIOD; 1049 1050 setup_deferrable_timer_on_stack(&timer, monitor_timeout, 1051 (unsigned long)current); 1052 do { 1053 u32 cpu_val, mch_val; 1054 u16 val; 1055 1056 /* MCP itself */ 1057 val = read_ptv(ips); 1058 ips->mcp_avg_temp = update_average_temp(ips->mcp_avg_temp, val); 1059 1060 /* Processor 0 */ 1061 val = read_ctv(ips, 0); 1062 ips->ctv1_avg_temp = 1063 update_average_temp(ips->ctv1_avg_temp, val); 1064 /* Power */ 1065 cpu_val = get_cpu_power(ips, &old_cpu_power, 1066 last_sample_period); 1067 ips->cpu_avg_power = 1068 update_average_power(ips->cpu_avg_power, cpu_val); 1069 1070 if (ips->second_cpu) { 1071 /* Processor 1 */ 1072 val = read_ctv(ips, 1); 1073 ips->ctv2_avg_temp = 1074 update_average_temp(ips->ctv2_avg_temp, val); 1075 } 1076 1077 /* MCH */ 1078 val = read_mgtv(ips); 1079 ips->mch_avg_temp = update_average_temp(ips->mch_avg_temp, val); 1080 /* Power */ 1081 if (ips->read_mch_val) { 1082 mch_val = ips->read_mch_val(); 1083 ips->mch_avg_power = 1084 update_average_power(ips->mch_avg_power, 1085 mch_val); 1086 } 1087 1088 /* 1089 * Make sure ME is updating thermal regs. 1090 * Note: 1091 * If it's been more than a second since the last update, 1092 * the ME is probably hung. 1093 */ 1094 cur_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >> 1095 ITV_ME_SEQNO_SHIFT; 1096 if (cur_seqno == last_seqno && 1097 time_after(jiffies, seqno_timestamp + HZ)) { 1098 dev_warn(&ips->dev->dev, "ME failed to update for more than 1s, likely hung\n"); 1099 } else { 1100 seqno_timestamp = get_jiffies_64(); 1101 last_seqno = cur_seqno; 1102 } 1103 1104 last_msecs = jiffies_to_msecs(jiffies); 1105 expire = jiffies + msecs_to_jiffies(IPS_SAMPLE_PERIOD); 1106 1107 __set_current_state(TASK_INTERRUPTIBLE); 1108 mod_timer(&timer, expire); 1109 schedule(); 1110 1111 /* Calculate actual sample period for power averaging */ 1112 last_sample_period = jiffies_to_msecs(jiffies) - last_msecs; 1113 if (!last_sample_period) 1114 last_sample_period = 1; 1115 } while (!kthread_should_stop()); 1116 1117 del_timer_sync(&timer); 1118 destroy_timer_on_stack(&timer); 1119 1120 dev_dbg(&ips->dev->dev, "ips-monitor thread stopped\n"); 1121 1122 return 0; 1123} 1124 1125#if 0 1126#define THM_DUMPW(reg) \ 1127 { \ 1128 u16 val = thm_readw(reg); \ 1129 dev_dbg(&ips->dev->dev, #reg ": 0x%04x\n", val); \ 1130 } 1131#define THM_DUMPL(reg) \ 1132 { \ 1133 u32 val = thm_readl(reg); \ 1134 dev_dbg(&ips->dev->dev, #reg ": 0x%08x\n", val); \ 1135 } 1136#define THM_DUMPQ(reg) \ 1137 { \ 1138 u64 val = thm_readq(reg); \ 1139 dev_dbg(&ips->dev->dev, #reg ": 0x%016x\n", val); \ 1140 } 1141 1142static void dump_thermal_info(struct ips_driver *ips) 1143{ 1144 u16 ptl; 1145 1146 ptl = thm_readw(THM_PTL); 1147 dev_dbg(&ips->dev->dev, "Processor temp limit: %d\n", ptl); 1148 1149 THM_DUMPW(THM_CTA); 1150 THM_DUMPW(THM_TRC); 1151 THM_DUMPW(THM_CTV1); 1152 THM_DUMPL(THM_STS); 1153 THM_DUMPW(THM_PTV); 1154 THM_DUMPQ(THM_MGTV); 1155} 1156#endif 1157 1158/** 1159 * ips_irq_handler - handle temperature triggers and other IPS events 1160 * @irq: irq number 1161 * @arg: unused 1162 * 1163 * Handle temperature limit trigger events, generally by lowering the clamps. 1164 * If we're at a critical limit, we clamp back to the lowest possible value 1165 * to prevent emergency shutdown. 1166 */ 1167static irqreturn_t ips_irq_handler(int irq, void *arg) 1168{ 1169 struct ips_driver *ips = arg; 1170 u8 tses = thm_readb(THM_TSES); 1171 u8 tes = thm_readb(THM_TES); 1172 1173 if (!tses && !tes) 1174 return IRQ_NONE; 1175 1176 dev_info(&ips->dev->dev, "TSES: 0x%02x\n", tses); 1177 dev_info(&ips->dev->dev, "TES: 0x%02x\n", tes); 1178 1179 /* STS update from EC? */ 1180 if (tes & 1) { 1181 u32 sts, tc1; 1182 1183 sts = thm_readl(THM_STS); 1184 tc1 = thm_readl(THM_TC1); 1185 1186 if (sts & STS_NVV) { 1187 spin_lock(&ips->turbo_status_lock); 1188 ips->core_power_limit = (sts & STS_PCPL_MASK) >> 1189 STS_PCPL_SHIFT; 1190 ips->mch_power_limit = (sts & STS_GPL_MASK) >> 1191 STS_GPL_SHIFT; 1192 /* ignore EC CPU vs GPU pref */ 1193 ips->cpu_turbo_enabled = !(sts & STS_PCTD_DIS); 1194 /* 1195 * Disable turbo for now, until we can figure 1196 * out why the power figures are wrong 1197 */ 1198 ips->cpu_turbo_enabled = false; 1199 if (ips->gpu_busy) 1200 ips->gpu_turbo_enabled = !(sts & STS_GTD_DIS); 1201 ips->mcp_temp_limit = (sts & STS_PTL_MASK) >> 1202 STS_PTL_SHIFT; 1203 ips->mcp_power_limit = (tc1 & STS_PPL_MASK) >> 1204 STS_PPL_SHIFT; 1205 verify_limits(ips); 1206 spin_unlock(&ips->turbo_status_lock); 1207 1208 thm_writeb(THM_SEC, SEC_ACK); 1209 } 1210 thm_writeb(THM_TES, tes); 1211 } 1212 1213 /* Thermal trip */ 1214 if (tses) { 1215 dev_warn(&ips->dev->dev, 1216 "thermal trip occurred, tses: 0x%04x\n", tses); 1217 thm_writeb(THM_TSES, tses); 1218 } 1219 1220 return IRQ_HANDLED; 1221} 1222 1223#ifndef CONFIG_DEBUG_FS 1224static void ips_debugfs_init(struct ips_driver *ips) { return; } 1225static void ips_debugfs_cleanup(struct ips_driver *ips) { return; } 1226#else 1227 1228/* Expose current state and limits in debugfs if possible */ 1229 1230struct ips_debugfs_node { 1231 struct ips_driver *ips; 1232 char *name; 1233 int (*show)(struct seq_file *m, void *data); 1234}; 1235 1236static int show_cpu_temp(struct seq_file *m, void *data) 1237{ 1238 struct ips_driver *ips = m->private; 1239 1240 seq_printf(m, "%d.%02d\n", ips->ctv1_avg_temp / 100, 1241 ips->ctv1_avg_temp % 100); 1242 1243 return 0; 1244} 1245 1246static int show_cpu_power(struct seq_file *m, void *data) 1247{ 1248 struct ips_driver *ips = m->private; 1249 1250 seq_printf(m, "%dmW\n", ips->cpu_avg_power); 1251 1252 return 0; 1253} 1254 1255static int show_cpu_clamp(struct seq_file *m, void *data) 1256{ 1257 u64 turbo_override; 1258 int tdp, tdc; 1259 1260 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1261 1262 tdp = (int)(turbo_override & TURBO_TDP_MASK); 1263 tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT); 1264 1265 /* Convert to .1W/A units */ 1266 tdp = tdp * 10 / 8; 1267 tdc = tdc * 10 / 8; 1268 1269 /* Watts Amperes */ 1270 seq_printf(m, "%d.%dW %d.%dA\n", tdp / 10, tdp % 10, 1271 tdc / 10, tdc % 10); 1272 1273 return 0; 1274} 1275 1276static int show_mch_temp(struct seq_file *m, void *data) 1277{ 1278 struct ips_driver *ips = m->private; 1279 1280 seq_printf(m, "%d.%02d\n", ips->mch_avg_temp / 100, 1281 ips->mch_avg_temp % 100); 1282 1283 return 0; 1284} 1285 1286static int show_mch_power(struct seq_file *m, void *data) 1287{ 1288 struct ips_driver *ips = m->private; 1289 1290 seq_printf(m, "%dmW\n", ips->mch_avg_power); 1291 1292 return 0; 1293} 1294 1295static struct ips_debugfs_node ips_debug_files[] = { 1296 { NULL, "cpu_temp", show_cpu_temp }, 1297 { NULL, "cpu_power", show_cpu_power }, 1298 { NULL, "cpu_clamp", show_cpu_clamp }, 1299 { NULL, "mch_temp", show_mch_temp }, 1300 { NULL, "mch_power", show_mch_power }, 1301}; 1302 1303static int ips_debugfs_open(struct inode *inode, struct file *file) 1304{ 1305 struct ips_debugfs_node *node = inode->i_private; 1306 1307 return single_open(file, node->show, node->ips); 1308} 1309 1310static const struct file_operations ips_debugfs_ops = { 1311 .owner = THIS_MODULE, 1312 .open = ips_debugfs_open, 1313 .read = seq_read, 1314 .llseek = seq_lseek, 1315 .release = single_release, 1316}; 1317 1318static void ips_debugfs_cleanup(struct ips_driver *ips) 1319{ 1320 if (ips->debug_root) 1321 debugfs_remove_recursive(ips->debug_root); 1322 return; 1323} 1324 1325static void ips_debugfs_init(struct ips_driver *ips) 1326{ 1327 int i; 1328 1329 ips->debug_root = debugfs_create_dir("ips", NULL); 1330 if (!ips->debug_root) { 1331 dev_err(&ips->dev->dev, 1332 "failed to create debugfs entries: %ld\n", 1333 PTR_ERR(ips->debug_root)); 1334 return; 1335 } 1336 1337 for (i = 0; i < ARRAY_SIZE(ips_debug_files); i++) { 1338 struct dentry *ent; 1339 struct ips_debugfs_node *node = &ips_debug_files[i]; 1340 1341 node->ips = ips; 1342 ent = debugfs_create_file(node->name, S_IFREG | S_IRUGO, 1343 ips->debug_root, node, 1344 &ips_debugfs_ops); 1345 if (!ent) { 1346 dev_err(&ips->dev->dev, 1347 "failed to create debug file: %ld\n", 1348 PTR_ERR(ent)); 1349 goto err_cleanup; 1350 } 1351 } 1352 1353 return; 1354 1355err_cleanup: 1356 ips_debugfs_cleanup(ips); 1357 return; 1358} 1359#endif /* CONFIG_DEBUG_FS */ 1360 1361/** 1362 * ips_detect_cpu - detect whether CPU supports IPS 1363 * 1364 * Walk our list and see if we're on a supported CPU. If we find one, 1365 * return the limits for it. 1366 */ 1367static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips) 1368{ 1369 u64 turbo_power, misc_en; 1370 struct ips_mcp_limits *limits = NULL; 1371 u16 tdp; 1372 1373 if (!(boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 37)) { 1374 dev_info(&ips->dev->dev, "Non-IPS CPU detected.\n"); 1375 goto out; 1376 } 1377 1378 rdmsrl(IA32_MISC_ENABLE, misc_en); 1379 /* 1380 * If the turbo enable bit isn't set, we shouldn't try to enable/disable 1381 * turbo manually or we'll get an illegal MSR access, even though 1382 * turbo will still be available. 1383 */ 1384 if (misc_en & IA32_MISC_TURBO_EN) 1385 ips->turbo_toggle_allowed = true; 1386 else 1387 ips->turbo_toggle_allowed = false; 1388 1389 if (strstr(boot_cpu_data.x86_model_id, "CPU M")) 1390 limits = &ips_sv_limits; 1391 else if (strstr(boot_cpu_data.x86_model_id, "CPU L")) 1392 limits = &ips_lv_limits; 1393 else if (strstr(boot_cpu_data.x86_model_id, "CPU U")) 1394 limits = &ips_ulv_limits; 1395 else { 1396 dev_info(&ips->dev->dev, "No CPUID match found.\n"); 1397 goto out; 1398 } 1399 1400 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_power); 1401 tdp = turbo_power & TURBO_TDP_MASK; 1402 1403 /* Sanity check TDP against CPU */ 1404 if (limits->core_power_limit != (tdp / 8) * 1000) { 1405 dev_info(&ips->dev->dev, "CPU TDP doesn't match expected value (found %d, expected %d)\n", 1406 tdp / 8, limits->core_power_limit / 1000); 1407 limits->core_power_limit = (tdp / 8) * 1000; 1408 } 1409 1410out: 1411 return limits; 1412} 1413 1414/** 1415 * ips_get_i915_syms - try to get GPU control methods from i915 driver 1416 * @ips: IPS driver 1417 * 1418 * The i915 driver exports several interfaces to allow the IPS driver to 1419 * monitor and control graphics turbo mode. If we can find them, we can 1420 * enable graphics turbo, otherwise we must disable it to avoid exceeding 1421 * thermal and power limits in the MCP. 1422 */ 1423static bool ips_get_i915_syms(struct ips_driver *ips) 1424{ 1425 ips->read_mch_val = symbol_get(i915_read_mch_val); 1426 if (!ips->read_mch_val) 1427 goto out_err; 1428 ips->gpu_raise = symbol_get(i915_gpu_raise); 1429 if (!ips->gpu_raise) 1430 goto out_put_mch; 1431 ips->gpu_lower = symbol_get(i915_gpu_lower); 1432 if (!ips->gpu_lower) 1433 goto out_put_raise; 1434 ips->gpu_busy = symbol_get(i915_gpu_busy); 1435 if (!ips->gpu_busy) 1436 goto out_put_lower; 1437 ips->gpu_turbo_disable = symbol_get(i915_gpu_turbo_disable); 1438 if (!ips->gpu_turbo_disable) 1439 goto out_put_busy; 1440 1441 return true; 1442 1443out_put_busy: 1444 symbol_put(i915_gpu_busy); 1445out_put_lower: 1446 symbol_put(i915_gpu_lower); 1447out_put_raise: 1448 symbol_put(i915_gpu_raise); 1449out_put_mch: 1450 symbol_put(i915_read_mch_val); 1451out_err: 1452 return false; 1453} 1454 1455static bool 1456ips_gpu_turbo_enabled(struct ips_driver *ips) 1457{ 1458 if (!ips->gpu_busy && late_i915_load) { 1459 if (ips_get_i915_syms(ips)) { 1460 dev_info(&ips->dev->dev, 1461 "i915 driver attached, reenabling gpu turbo\n"); 1462 ips->gpu_turbo_enabled = !(thm_readl(THM_HTS) & HTS_GTD_DIS); 1463 } 1464 } 1465 1466 return ips->gpu_turbo_enabled; 1467} 1468 1469void 1470ips_link_to_i915_driver(void) 1471{ 1472 /* We can't cleanly get at the various ips_driver structs from 1473 * this caller (the i915 driver), so just set a flag saying 1474 * that it's time to try getting the symbols again. 1475 */ 1476 late_i915_load = true; 1477} 1478EXPORT_SYMBOL_GPL(ips_link_to_i915_driver); 1479 1480static DEFINE_PCI_DEVICE_TABLE(ips_id_table) = { 1481 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 1482 PCI_DEVICE_ID_INTEL_THERMAL_SENSOR), }, 1483 { 0, } 1484}; 1485 1486MODULE_DEVICE_TABLE(pci, ips_id_table); 1487 1488static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id) 1489{ 1490 u64 platform_info; 1491 struct ips_driver *ips; 1492 u32 hts; 1493 int ret = 0; 1494 u16 htshi, trc, trc_required_mask; 1495 u8 tse; 1496 1497 ips = kzalloc(sizeof(struct ips_driver), GFP_KERNEL); 1498 if (!ips) 1499 return -ENOMEM; 1500 1501 pci_set_drvdata(dev, ips); 1502 ips->dev = dev; 1503 1504 ips->limits = ips_detect_cpu(ips); 1505 if (!ips->limits) { 1506 dev_info(&dev->dev, "IPS not supported on this CPU\n"); 1507 ret = -ENXIO; 1508 goto error_free; 1509 } 1510 1511 spin_lock_init(&ips->turbo_status_lock); 1512 1513 ret = pci_enable_device(dev); 1514 if (ret) { 1515 dev_err(&dev->dev, "can't enable PCI device, aborting\n"); 1516 goto error_free; 1517 } 1518 1519 if (!pci_resource_start(dev, 0)) { 1520 dev_err(&dev->dev, "TBAR not assigned, aborting\n"); 1521 ret = -ENXIO; 1522 goto error_free; 1523 } 1524 1525 ret = pci_request_regions(dev, "ips thermal sensor"); 1526 if (ret) { 1527 dev_err(&dev->dev, "thermal resource busy, aborting\n"); 1528 goto error_free; 1529 } 1530 1531 1532 ips->regmap = ioremap(pci_resource_start(dev, 0), 1533 pci_resource_len(dev, 0)); 1534 if (!ips->regmap) { 1535 dev_err(&dev->dev, "failed to map thermal regs, aborting\n"); 1536 ret = -EBUSY; 1537 goto error_release; 1538 } 1539 1540 tse = thm_readb(THM_TSE); 1541 if (tse != TSE_EN) { 1542 dev_err(&dev->dev, "thermal device not enabled (0x%02x), aborting\n", tse); 1543 ret = -ENXIO; 1544 goto error_unmap; 1545 } 1546 1547 trc = thm_readw(THM_TRC); 1548 trc_required_mask = TRC_CORE1_EN | TRC_CORE_PWR | TRC_MCH_EN; 1549 if ((trc & trc_required_mask) != trc_required_mask) { 1550 dev_err(&dev->dev, "thermal reporting for required devices not enabled, aborting\n"); 1551 ret = -ENXIO; 1552 goto error_unmap; 1553 } 1554 1555 if (trc & TRC_CORE2_EN) 1556 ips->second_cpu = true; 1557 1558 update_turbo_limits(ips); 1559 dev_dbg(&dev->dev, "max cpu power clamp: %dW\n", 1560 ips->mcp_power_limit / 10); 1561 dev_dbg(&dev->dev, "max core power clamp: %dW\n", 1562 ips->core_power_limit / 10); 1563 /* BIOS may update limits at runtime */ 1564 if (thm_readl(THM_PSC) & PSP_PBRT) 1565 ips->poll_turbo_status = true; 1566 1567 if (!ips_get_i915_syms(ips)) { 1568 dev_info(&dev->dev, "failed to get i915 symbols, graphics turbo disabled until i915 loads\n"); 1569 ips->gpu_turbo_enabled = false; 1570 } else { 1571 dev_dbg(&dev->dev, "graphics turbo enabled\n"); 1572 ips->gpu_turbo_enabled = true; 1573 } 1574 1575 /* 1576 * Check PLATFORM_INFO MSR to make sure this chip is 1577 * turbo capable. 1578 */ 1579 rdmsrl(PLATFORM_INFO, platform_info); 1580 if (!(platform_info & PLATFORM_TDP)) { 1581 dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n"); 1582 ret = -ENODEV; 1583 goto error_unmap; 1584 } 1585 1586 /* 1587 * IRQ handler for ME interaction 1588 * Note: don't use MSI here as the PCH has bugs. 1589 */ 1590 pci_disable_msi(dev); 1591 ret = request_irq(dev->irq, ips_irq_handler, IRQF_SHARED, "ips", 1592 ips); 1593 if (ret) { 1594 dev_err(&dev->dev, "request irq failed, aborting\n"); 1595 goto error_unmap; 1596 } 1597 1598 /* Enable aux, hot & critical interrupts */ 1599 thm_writeb(THM_TSPIEN, TSPIEN_AUX2_LOHI | TSPIEN_CRIT_LOHI | 1600 TSPIEN_HOT_LOHI | TSPIEN_AUX_LOHI); 1601 thm_writeb(THM_TEN, TEN_UPDATE_EN); 1602 1603 /* Collect adjustment values */ 1604 ips->cta_val = thm_readw(THM_CTA); 1605 ips->pta_val = thm_readw(THM_PTA); 1606 ips->mgta_val = thm_readw(THM_MGTA); 1607 1608 /* Save turbo limits & ratios */ 1609 rdmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); 1610 1611 ips_disable_cpu_turbo(ips); 1612 ips->cpu_turbo_enabled = false; 1613 1614 /* Create thermal adjust thread */ 1615 ips->adjust = kthread_create(ips_adjust, ips, "ips-adjust"); 1616 if (IS_ERR(ips->adjust)) { 1617 dev_err(&dev->dev, 1618 "failed to create thermal adjust thread, aborting\n"); 1619 ret = -ENOMEM; 1620 goto error_free_irq; 1621 1622 } 1623 1624 /* 1625 * Set up the work queue and monitor thread. The monitor thread 1626 * will wake up ips_adjust thread. 1627 */ 1628 ips->monitor = kthread_run(ips_monitor, ips, "ips-monitor"); 1629 if (IS_ERR(ips->monitor)) { 1630 dev_err(&dev->dev, 1631 "failed to create thermal monitor thread, aborting\n"); 1632 ret = -ENOMEM; 1633 goto error_thread_cleanup; 1634 } 1635 1636 hts = (ips->core_power_limit << HTS_PCPL_SHIFT) | 1637 (ips->mcp_temp_limit << HTS_PTL_SHIFT) | HTS_NVV; 1638 htshi = HTS2_PRST_RUNNING << HTS2_PRST_SHIFT; 1639 1640 thm_writew(THM_HTSHI, htshi); 1641 thm_writel(THM_HTS, hts); 1642 1643 ips_debugfs_init(ips); 1644 1645 dev_info(&dev->dev, "IPS driver initialized, MCP temp limit %d\n", 1646 ips->mcp_temp_limit); 1647 return ret; 1648 1649error_thread_cleanup: 1650 kthread_stop(ips->adjust); 1651error_free_irq: 1652 free_irq(ips->dev->irq, ips); 1653error_unmap: 1654 iounmap(ips->regmap); 1655error_release: 1656 pci_release_regions(dev); 1657error_free: 1658 kfree(ips); 1659 return ret; 1660} 1661 1662static void ips_remove(struct pci_dev *dev) 1663{ 1664 struct ips_driver *ips = pci_get_drvdata(dev); 1665 u64 turbo_override; 1666 1667 if (!ips) 1668 return; 1669 1670 ips_debugfs_cleanup(ips); 1671 1672 /* Release i915 driver */ 1673 if (ips->read_mch_val) 1674 symbol_put(i915_read_mch_val); 1675 if (ips->gpu_raise) 1676 symbol_put(i915_gpu_raise); 1677 if (ips->gpu_lower) 1678 symbol_put(i915_gpu_lower); 1679 if (ips->gpu_busy) 1680 symbol_put(i915_gpu_busy); 1681 if (ips->gpu_turbo_disable) 1682 symbol_put(i915_gpu_turbo_disable); 1683 1684 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1685 turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN); 1686 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1687 wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); 1688 1689 free_irq(ips->dev->irq, ips); 1690 if (ips->adjust) 1691 kthread_stop(ips->adjust); 1692 if (ips->monitor) 1693 kthread_stop(ips->monitor); 1694 iounmap(ips->regmap); 1695 pci_release_regions(dev); 1696 kfree(ips); 1697 dev_dbg(&dev->dev, "IPS driver removed\n"); 1698} 1699 1700#ifdef CONFIG_PM 1701static int ips_suspend(struct pci_dev *dev, pm_message_t state) 1702{ 1703 return 0; 1704} 1705 1706static int ips_resume(struct pci_dev *dev) 1707{ 1708 return 0; 1709} 1710#else 1711#define ips_suspend NULL 1712#define ips_resume NULL 1713#endif /* CONFIG_PM */ 1714 1715static void ips_shutdown(struct pci_dev *dev) 1716{ 1717} 1718 1719static struct pci_driver ips_pci_driver = { 1720 .name = "intel ips", 1721 .id_table = ips_id_table, 1722 .probe = ips_probe, 1723 .remove = ips_remove, 1724 .suspend = ips_suspend, 1725 .resume = ips_resume, 1726 .shutdown = ips_shutdown, 1727}; 1728 1729static int __init ips_init(void) 1730{ 1731 return pci_register_driver(&ips_pci_driver); 1732} 1733module_init(ips_init); 1734 1735static void ips_exit(void) 1736{ 1737 pci_unregister_driver(&ips_pci_driver); 1738 return; 1739} 1740module_exit(ips_exit); 1741 1742MODULE_LICENSE("GPL"); 1743MODULE_AUTHOR("Jesse Barnes <jbarnes@virtuousgeek.org>"); 1744MODULE_DESCRIPTION("Intelligent Power Sharing Driver"); 1745