be_main.c revision e528586079a20c3d28a490ec8e3271bb4348fc3e
1/** 2 * Copyright (C) 2005 - 2011 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com) 11 * 12 * Contact Information: 13 * linux-drivers@emulex.com 14 * 15 * Emulex 16 * 3333 Susan Street 17 * Costa Mesa, CA 92626 18 */ 19 20#include <linux/reboot.h> 21#include <linux/delay.h> 22#include <linux/slab.h> 23#include <linux/interrupt.h> 24#include <linux/blkdev.h> 25#include <linux/pci.h> 26#include <linux/string.h> 27#include <linux/kernel.h> 28#include <linux/semaphore.h> 29#include <linux/iscsi_boot_sysfs.h> 30 31#include <scsi/libiscsi.h> 32#include <scsi/scsi_transport_iscsi.h> 33#include <scsi/scsi_transport.h> 34#include <scsi/scsi_cmnd.h> 35#include <scsi/scsi_device.h> 36#include <scsi/scsi_host.h> 37#include <scsi/scsi.h> 38#include "be_main.h" 39#include "be_iscsi.h" 40#include "be_mgmt.h" 41 42static unsigned int be_iopoll_budget = 10; 43static unsigned int be_max_phys_size = 64; 44static unsigned int enable_msix = 1; 45static unsigned int gcrashmode = 0; 46static unsigned int num_hba = 0; 47 48MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table); 49MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR); 50MODULE_AUTHOR("ServerEngines Corporation"); 51MODULE_LICENSE("GPL"); 52module_param(be_iopoll_budget, int, 0); 53module_param(enable_msix, int, 0); 54module_param(be_max_phys_size, uint, S_IRUGO); 55MODULE_PARM_DESC(be_max_phys_size, "Maximum Size (In Kilobytes) of physically" 56 "contiguous memory that can be allocated." 57 "Range is 16 - 128"); 58 59static int beiscsi_slave_configure(struct scsi_device *sdev) 60{ 61 blk_queue_max_segment_size(sdev->request_queue, 65536); 62 return 0; 63} 64 65static int beiscsi_eh_abort(struct scsi_cmnd *sc) 66{ 67 struct iscsi_cls_session *cls_session; 68 struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr; 69 struct beiscsi_io_task *aborted_io_task; 70 struct iscsi_conn *conn; 71 struct beiscsi_conn *beiscsi_conn; 72 struct beiscsi_hba *phba; 73 struct iscsi_session *session; 74 struct invalidate_command_table *inv_tbl; 75 struct be_dma_mem nonemb_cmd; 76 unsigned int cid, tag, num_invalidate; 77 78 cls_session = starget_to_session(scsi_target(sc->device)); 79 session = cls_session->dd_data; 80 81 spin_lock_bh(&session->lock); 82 if (!aborted_task || !aborted_task->sc) { 83 /* we raced */ 84 spin_unlock_bh(&session->lock); 85 return SUCCESS; 86 } 87 88 aborted_io_task = aborted_task->dd_data; 89 if (!aborted_io_task->scsi_cmnd) { 90 /* raced or invalid command */ 91 spin_unlock_bh(&session->lock); 92 return SUCCESS; 93 } 94 spin_unlock_bh(&session->lock); 95 conn = aborted_task->conn; 96 beiscsi_conn = conn->dd_data; 97 phba = beiscsi_conn->phba; 98 99 /* invalidate iocb */ 100 cid = beiscsi_conn->beiscsi_conn_cid; 101 inv_tbl = phba->inv_tbl; 102 memset(inv_tbl, 0x0, sizeof(*inv_tbl)); 103 inv_tbl->cid = cid; 104 inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index; 105 num_invalidate = 1; 106 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, 107 sizeof(struct invalidate_commands_params_in), 108 &nonemb_cmd.dma); 109 if (nonemb_cmd.va == NULL) { 110 SE_DEBUG(DBG_LVL_1, 111 "Failed to allocate memory for" 112 "mgmt_invalidate_icds\n"); 113 return FAILED; 114 } 115 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in); 116 117 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate, 118 cid, &nonemb_cmd); 119 if (!tag) { 120 shost_printk(KERN_WARNING, phba->shost, 121 "mgmt_invalidate_icds could not be" 122 " submitted\n"); 123 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, 124 nonemb_cmd.va, nonemb_cmd.dma); 125 126 return FAILED; 127 } else { 128 wait_event_interruptible(phba->ctrl.mcc_wait[tag], 129 phba->ctrl.mcc_numtag[tag]); 130 free_mcc_tag(&phba->ctrl, tag); 131 } 132 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, 133 nonemb_cmd.va, nonemb_cmd.dma); 134 return iscsi_eh_abort(sc); 135} 136 137static int beiscsi_eh_device_reset(struct scsi_cmnd *sc) 138{ 139 struct iscsi_task *abrt_task; 140 struct beiscsi_io_task *abrt_io_task; 141 struct iscsi_conn *conn; 142 struct beiscsi_conn *beiscsi_conn; 143 struct beiscsi_hba *phba; 144 struct iscsi_session *session; 145 struct iscsi_cls_session *cls_session; 146 struct invalidate_command_table *inv_tbl; 147 struct be_dma_mem nonemb_cmd; 148 unsigned int cid, tag, i, num_invalidate; 149 int rc = FAILED; 150 151 /* invalidate iocbs */ 152 cls_session = starget_to_session(scsi_target(sc->device)); 153 session = cls_session->dd_data; 154 spin_lock_bh(&session->lock); 155 if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) 156 goto unlock; 157 158 conn = session->leadconn; 159 beiscsi_conn = conn->dd_data; 160 phba = beiscsi_conn->phba; 161 cid = beiscsi_conn->beiscsi_conn_cid; 162 inv_tbl = phba->inv_tbl; 163 memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN); 164 num_invalidate = 0; 165 for (i = 0; i < conn->session->cmds_max; i++) { 166 abrt_task = conn->session->cmds[i]; 167 abrt_io_task = abrt_task->dd_data; 168 if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE) 169 continue; 170 171 if (abrt_task->sc->device->lun != abrt_task->sc->device->lun) 172 continue; 173 174 inv_tbl->cid = cid; 175 inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index; 176 num_invalidate++; 177 inv_tbl++; 178 } 179 spin_unlock_bh(&session->lock); 180 inv_tbl = phba->inv_tbl; 181 182 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, 183 sizeof(struct invalidate_commands_params_in), 184 &nonemb_cmd.dma); 185 if (nonemb_cmd.va == NULL) { 186 SE_DEBUG(DBG_LVL_1, 187 "Failed to allocate memory for" 188 "mgmt_invalidate_icds\n"); 189 return FAILED; 190 } 191 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in); 192 memset(nonemb_cmd.va, 0, nonemb_cmd.size); 193 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate, 194 cid, &nonemb_cmd); 195 if (!tag) { 196 shost_printk(KERN_WARNING, phba->shost, 197 "mgmt_invalidate_icds could not be" 198 " submitted\n"); 199 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, 200 nonemb_cmd.va, nonemb_cmd.dma); 201 return FAILED; 202 } else { 203 wait_event_interruptible(phba->ctrl.mcc_wait[tag], 204 phba->ctrl.mcc_numtag[tag]); 205 free_mcc_tag(&phba->ctrl, tag); 206 } 207 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, 208 nonemb_cmd.va, nonemb_cmd.dma); 209 return iscsi_eh_device_reset(sc); 210unlock: 211 spin_unlock_bh(&session->lock); 212 return rc; 213} 214 215static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf) 216{ 217 struct beiscsi_hba *phba = data; 218 struct mgmt_session_info *boot_sess = &phba->boot_sess; 219 struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0]; 220 char *str = buf; 221 int rc; 222 223 switch (type) { 224 case ISCSI_BOOT_TGT_NAME: 225 rc = sprintf(buf, "%.*s\n", 226 (int)strlen(boot_sess->target_name), 227 (char *)&boot_sess->target_name); 228 break; 229 case ISCSI_BOOT_TGT_IP_ADDR: 230 if (boot_conn->dest_ipaddr.ip_type == 0x1) 231 rc = sprintf(buf, "%pI4\n", 232 (char *)&boot_conn->dest_ipaddr.ip_address); 233 else 234 rc = sprintf(str, "%pI6\n", 235 (char *)&boot_conn->dest_ipaddr.ip_address); 236 break; 237 case ISCSI_BOOT_TGT_PORT: 238 rc = sprintf(str, "%d\n", boot_conn->dest_port); 239 break; 240 241 case ISCSI_BOOT_TGT_CHAP_NAME: 242 rc = sprintf(str, "%.*s\n", 243 boot_conn->negotiated_login_options.auth_data.chap. 244 target_chap_name_length, 245 (char *)&boot_conn->negotiated_login_options. 246 auth_data.chap.target_chap_name); 247 break; 248 case ISCSI_BOOT_TGT_CHAP_SECRET: 249 rc = sprintf(str, "%.*s\n", 250 boot_conn->negotiated_login_options.auth_data.chap. 251 target_secret_length, 252 (char *)&boot_conn->negotiated_login_options. 253 auth_data.chap.target_secret); 254 break; 255 case ISCSI_BOOT_TGT_REV_CHAP_NAME: 256 rc = sprintf(str, "%.*s\n", 257 boot_conn->negotiated_login_options.auth_data.chap. 258 intr_chap_name_length, 259 (char *)&boot_conn->negotiated_login_options. 260 auth_data.chap.intr_chap_name); 261 break; 262 case ISCSI_BOOT_TGT_REV_CHAP_SECRET: 263 rc = sprintf(str, "%.*s\n", 264 boot_conn->negotiated_login_options.auth_data.chap. 265 intr_secret_length, 266 (char *)&boot_conn->negotiated_login_options. 267 auth_data.chap.intr_secret); 268 break; 269 case ISCSI_BOOT_TGT_FLAGS: 270 rc = sprintf(str, "2\n"); 271 break; 272 case ISCSI_BOOT_TGT_NIC_ASSOC: 273 rc = sprintf(str, "0\n"); 274 break; 275 default: 276 rc = -ENOSYS; 277 break; 278 } 279 return rc; 280} 281 282static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf) 283{ 284 struct beiscsi_hba *phba = data; 285 char *str = buf; 286 int rc; 287 288 switch (type) { 289 case ISCSI_BOOT_INI_INITIATOR_NAME: 290 rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname); 291 break; 292 default: 293 rc = -ENOSYS; 294 break; 295 } 296 return rc; 297} 298 299static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf) 300{ 301 struct beiscsi_hba *phba = data; 302 char *str = buf; 303 int rc; 304 305 switch (type) { 306 case ISCSI_BOOT_ETH_FLAGS: 307 rc = sprintf(str, "2\n"); 308 break; 309 case ISCSI_BOOT_ETH_INDEX: 310 rc = sprintf(str, "0\n"); 311 break; 312 case ISCSI_BOOT_ETH_MAC: 313 rc = beiscsi_get_macaddr(buf, phba); 314 if (rc < 0) { 315 SE_DEBUG(DBG_LVL_1, "beiscsi_get_macaddr Failed\n"); 316 return rc; 317 } 318 break; 319 default: 320 rc = -ENOSYS; 321 break; 322 } 323 return rc; 324} 325 326 327static mode_t beiscsi_tgt_get_attr_visibility(void *data, int type) 328{ 329 int rc; 330 331 switch (type) { 332 case ISCSI_BOOT_TGT_NAME: 333 case ISCSI_BOOT_TGT_IP_ADDR: 334 case ISCSI_BOOT_TGT_PORT: 335 case ISCSI_BOOT_TGT_CHAP_NAME: 336 case ISCSI_BOOT_TGT_CHAP_SECRET: 337 case ISCSI_BOOT_TGT_REV_CHAP_NAME: 338 case ISCSI_BOOT_TGT_REV_CHAP_SECRET: 339 case ISCSI_BOOT_TGT_NIC_ASSOC: 340 case ISCSI_BOOT_TGT_FLAGS: 341 rc = S_IRUGO; 342 break; 343 default: 344 rc = 0; 345 break; 346 } 347 return rc; 348} 349 350static mode_t beiscsi_ini_get_attr_visibility(void *data, int type) 351{ 352 int rc; 353 354 switch (type) { 355 case ISCSI_BOOT_INI_INITIATOR_NAME: 356 rc = S_IRUGO; 357 break; 358 default: 359 rc = 0; 360 break; 361 } 362 return rc; 363} 364 365 366static mode_t beiscsi_eth_get_attr_visibility(void *data, int type) 367{ 368 int rc; 369 370 switch (type) { 371 case ISCSI_BOOT_ETH_FLAGS: 372 case ISCSI_BOOT_ETH_MAC: 373 case ISCSI_BOOT_ETH_INDEX: 374 rc = S_IRUGO; 375 break; 376 default: 377 rc = 0; 378 break; 379 } 380 return rc; 381} 382 383/*------------------- PCI Driver operations and data ----------------- */ 384static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = { 385 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) }, 386 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) }, 387 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) }, 388 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) }, 389 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) }, 390 { 0 } 391}; 392MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table); 393 394static struct scsi_host_template beiscsi_sht = { 395 .module = THIS_MODULE, 396 .name = "ServerEngines 10Gbe open-iscsi Initiator Driver", 397 .proc_name = DRV_NAME, 398 .queuecommand = iscsi_queuecommand, 399 .change_queue_depth = iscsi_change_queue_depth, 400 .slave_configure = beiscsi_slave_configure, 401 .target_alloc = iscsi_target_alloc, 402 .eh_abort_handler = beiscsi_eh_abort, 403 .eh_device_reset_handler = beiscsi_eh_device_reset, 404 .eh_target_reset_handler = iscsi_eh_session_reset, 405 .sg_tablesize = BEISCSI_SGLIST_ELEMENTS, 406 .can_queue = BE2_IO_DEPTH, 407 .this_id = -1, 408 .max_sectors = BEISCSI_MAX_SECTORS, 409 .cmd_per_lun = BEISCSI_CMD_PER_LUN, 410 .use_clustering = ENABLE_CLUSTERING, 411}; 412 413static struct scsi_transport_template *beiscsi_scsi_transport; 414 415static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev) 416{ 417 struct beiscsi_hba *phba; 418 struct Scsi_Host *shost; 419 420 shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0); 421 if (!shost) { 422 dev_err(&pcidev->dev, "beiscsi_hba_alloc -" 423 "iscsi_host_alloc failed\n"); 424 return NULL; 425 } 426 shost->dma_boundary = pcidev->dma_mask; 427 shost->max_id = BE2_MAX_SESSIONS; 428 shost->max_channel = 0; 429 shost->max_cmd_len = BEISCSI_MAX_CMD_LEN; 430 shost->max_lun = BEISCSI_NUM_MAX_LUN; 431 shost->transportt = beiscsi_scsi_transport; 432 phba = iscsi_host_priv(shost); 433 memset(phba, 0, sizeof(*phba)); 434 phba->shost = shost; 435 phba->pcidev = pci_dev_get(pcidev); 436 pci_set_drvdata(pcidev, phba); 437 438 if (iscsi_host_add(shost, &phba->pcidev->dev)) 439 goto free_devices; 440 441 return phba; 442 443free_devices: 444 pci_dev_put(phba->pcidev); 445 iscsi_host_free(phba->shost); 446 return NULL; 447} 448 449static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba) 450{ 451 if (phba->csr_va) { 452 iounmap(phba->csr_va); 453 phba->csr_va = NULL; 454 } 455 if (phba->db_va) { 456 iounmap(phba->db_va); 457 phba->db_va = NULL; 458 } 459 if (phba->pci_va) { 460 iounmap(phba->pci_va); 461 phba->pci_va = NULL; 462 } 463} 464 465static int beiscsi_map_pci_bars(struct beiscsi_hba *phba, 466 struct pci_dev *pcidev) 467{ 468 u8 __iomem *addr; 469 int pcicfg_reg; 470 471 addr = ioremap_nocache(pci_resource_start(pcidev, 2), 472 pci_resource_len(pcidev, 2)); 473 if (addr == NULL) 474 return -ENOMEM; 475 phba->ctrl.csr = addr; 476 phba->csr_va = addr; 477 phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2); 478 479 addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024); 480 if (addr == NULL) 481 goto pci_map_err; 482 phba->ctrl.db = addr; 483 phba->db_va = addr; 484 phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4); 485 486 if (phba->generation == BE_GEN2) 487 pcicfg_reg = 1; 488 else 489 pcicfg_reg = 0; 490 491 addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg), 492 pci_resource_len(pcidev, pcicfg_reg)); 493 494 if (addr == NULL) 495 goto pci_map_err; 496 phba->ctrl.pcicfg = addr; 497 phba->pci_va = addr; 498 phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg); 499 return 0; 500 501pci_map_err: 502 beiscsi_unmap_pci_function(phba); 503 return -ENOMEM; 504} 505 506static int beiscsi_enable_pci(struct pci_dev *pcidev) 507{ 508 int ret; 509 510 ret = pci_enable_device(pcidev); 511 if (ret) { 512 dev_err(&pcidev->dev, "beiscsi_enable_pci - enable device " 513 "failed. Returning -ENODEV\n"); 514 return ret; 515 } 516 517 pci_set_master(pcidev); 518 if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) { 519 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32)); 520 if (ret) { 521 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n"); 522 pci_disable_device(pcidev); 523 return ret; 524 } 525 } 526 return 0; 527} 528 529static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev) 530{ 531 struct be_ctrl_info *ctrl = &phba->ctrl; 532 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced; 533 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem; 534 int status = 0; 535 536 ctrl->pdev = pdev; 537 status = beiscsi_map_pci_bars(phba, pdev); 538 if (status) 539 return status; 540 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16; 541 mbox_mem_alloc->va = pci_alloc_consistent(pdev, 542 mbox_mem_alloc->size, 543 &mbox_mem_alloc->dma); 544 if (!mbox_mem_alloc->va) { 545 beiscsi_unmap_pci_function(phba); 546 status = -ENOMEM; 547 return status; 548 } 549 550 mbox_mem_align->size = sizeof(struct be_mcc_mailbox); 551 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16); 552 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16); 553 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox)); 554 spin_lock_init(&ctrl->mbox_lock); 555 spin_lock_init(&phba->ctrl.mcc_lock); 556 spin_lock_init(&phba->ctrl.mcc_cq_lock); 557 558 return status; 559} 560 561static void beiscsi_get_params(struct beiscsi_hba *phba) 562{ 563 phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count 564 - (phba->fw_config.iscsi_cid_count 565 + BE2_TMFS 566 + BE2_NOPOUT_REQ)); 567 phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count; 568 phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2; 569 phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count; 570 phba->params.num_sge_per_io = BE2_SGE; 571 phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ; 572 phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ; 573 phba->params.eq_timer = 64; 574 phba->params.num_eq_entries = 575 (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2 576 + BE2_TMFS) / 512) + 1) * 512; 577 phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024) 578 ? 1024 : phba->params.num_eq_entries; 579 SE_DEBUG(DBG_LVL_8, "phba->params.num_eq_entries=%d\n", 580 phba->params.num_eq_entries); 581 phba->params.num_cq_entries = 582 (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2 583 + BE2_TMFS) / 512) + 1) * 512; 584 phba->params.wrbs_per_cxn = 256; 585} 586 587static void hwi_ring_eq_db(struct beiscsi_hba *phba, 588 unsigned int id, unsigned int clr_interrupt, 589 unsigned int num_processed, 590 unsigned char rearm, unsigned char event) 591{ 592 u32 val = 0; 593 val |= id & DB_EQ_RING_ID_MASK; 594 if (rearm) 595 val |= 1 << DB_EQ_REARM_SHIFT; 596 if (clr_interrupt) 597 val |= 1 << DB_EQ_CLR_SHIFT; 598 if (event) 599 val |= 1 << DB_EQ_EVNT_SHIFT; 600 val |= num_processed << DB_EQ_NUM_POPPED_SHIFT; 601 iowrite32(val, phba->db_va + DB_EQ_OFFSET); 602} 603 604/** 605 * be_isr_mcc - The isr routine of the driver. 606 * @irq: Not used 607 * @dev_id: Pointer to host adapter structure 608 */ 609static irqreturn_t be_isr_mcc(int irq, void *dev_id) 610{ 611 struct beiscsi_hba *phba; 612 struct be_eq_entry *eqe = NULL; 613 struct be_queue_info *eq; 614 struct be_queue_info *mcc; 615 unsigned int num_eq_processed; 616 struct be_eq_obj *pbe_eq; 617 unsigned long flags; 618 619 pbe_eq = dev_id; 620 eq = &pbe_eq->q; 621 phba = pbe_eq->phba; 622 mcc = &phba->ctrl.mcc_obj.cq; 623 eqe = queue_tail_node(eq); 624 if (!eqe) 625 SE_DEBUG(DBG_LVL_1, "eqe is NULL\n"); 626 627 num_eq_processed = 0; 628 629 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 630 & EQE_VALID_MASK) { 631 if (((eqe->dw[offsetof(struct amap_eq_entry, 632 resource_id) / 32] & 633 EQE_RESID_MASK) >> 16) == mcc->id) { 634 spin_lock_irqsave(&phba->isr_lock, flags); 635 phba->todo_mcc_cq = 1; 636 spin_unlock_irqrestore(&phba->isr_lock, flags); 637 } 638 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 639 queue_tail_inc(eq); 640 eqe = queue_tail_node(eq); 641 num_eq_processed++; 642 } 643 if (phba->todo_mcc_cq) 644 queue_work(phba->wq, &phba->work_cqs); 645 if (num_eq_processed) 646 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1); 647 648 return IRQ_HANDLED; 649} 650 651/** 652 * be_isr_msix - The isr routine of the driver. 653 * @irq: Not used 654 * @dev_id: Pointer to host adapter structure 655 */ 656static irqreturn_t be_isr_msix(int irq, void *dev_id) 657{ 658 struct beiscsi_hba *phba; 659 struct be_eq_entry *eqe = NULL; 660 struct be_queue_info *eq; 661 struct be_queue_info *cq; 662 unsigned int num_eq_processed; 663 struct be_eq_obj *pbe_eq; 664 unsigned long flags; 665 666 pbe_eq = dev_id; 667 eq = &pbe_eq->q; 668 cq = pbe_eq->cq; 669 eqe = queue_tail_node(eq); 670 if (!eqe) 671 SE_DEBUG(DBG_LVL_1, "eqe is NULL\n"); 672 673 phba = pbe_eq->phba; 674 num_eq_processed = 0; 675 if (blk_iopoll_enabled) { 676 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 677 & EQE_VALID_MASK) { 678 if (!blk_iopoll_sched_prep(&pbe_eq->iopoll)) 679 blk_iopoll_sched(&pbe_eq->iopoll); 680 681 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 682 queue_tail_inc(eq); 683 eqe = queue_tail_node(eq); 684 num_eq_processed++; 685 } 686 if (num_eq_processed) 687 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1); 688 689 return IRQ_HANDLED; 690 } else { 691 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 692 & EQE_VALID_MASK) { 693 spin_lock_irqsave(&phba->isr_lock, flags); 694 phba->todo_cq = 1; 695 spin_unlock_irqrestore(&phba->isr_lock, flags); 696 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 697 queue_tail_inc(eq); 698 eqe = queue_tail_node(eq); 699 num_eq_processed++; 700 } 701 if (phba->todo_cq) 702 queue_work(phba->wq, &phba->work_cqs); 703 704 if (num_eq_processed) 705 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1); 706 707 return IRQ_HANDLED; 708 } 709} 710 711/** 712 * be_isr - The isr routine of the driver. 713 * @irq: Not used 714 * @dev_id: Pointer to host adapter structure 715 */ 716static irqreturn_t be_isr(int irq, void *dev_id) 717{ 718 struct beiscsi_hba *phba; 719 struct hwi_controller *phwi_ctrlr; 720 struct hwi_context_memory *phwi_context; 721 struct be_eq_entry *eqe = NULL; 722 struct be_queue_info *eq; 723 struct be_queue_info *cq; 724 struct be_queue_info *mcc; 725 unsigned long flags, index; 726 unsigned int num_mcceq_processed, num_ioeq_processed; 727 struct be_ctrl_info *ctrl; 728 struct be_eq_obj *pbe_eq; 729 int isr; 730 731 phba = dev_id; 732 ctrl = &phba->ctrl; 733 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET + 734 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE)); 735 if (!isr) 736 return IRQ_NONE; 737 738 phwi_ctrlr = phba->phwi_ctrlr; 739 phwi_context = phwi_ctrlr->phwi_ctxt; 740 pbe_eq = &phwi_context->be_eq[0]; 741 742 eq = &phwi_context->be_eq[0].q; 743 mcc = &phba->ctrl.mcc_obj.cq; 744 index = 0; 745 eqe = queue_tail_node(eq); 746 if (!eqe) 747 SE_DEBUG(DBG_LVL_1, "eqe is NULL\n"); 748 749 num_ioeq_processed = 0; 750 num_mcceq_processed = 0; 751 if (blk_iopoll_enabled) { 752 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 753 & EQE_VALID_MASK) { 754 if (((eqe->dw[offsetof(struct amap_eq_entry, 755 resource_id) / 32] & 756 EQE_RESID_MASK) >> 16) == mcc->id) { 757 spin_lock_irqsave(&phba->isr_lock, flags); 758 phba->todo_mcc_cq = 1; 759 spin_unlock_irqrestore(&phba->isr_lock, flags); 760 num_mcceq_processed++; 761 } else { 762 if (!blk_iopoll_sched_prep(&pbe_eq->iopoll)) 763 blk_iopoll_sched(&pbe_eq->iopoll); 764 num_ioeq_processed++; 765 } 766 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 767 queue_tail_inc(eq); 768 eqe = queue_tail_node(eq); 769 } 770 if (num_ioeq_processed || num_mcceq_processed) { 771 if (phba->todo_mcc_cq) 772 queue_work(phba->wq, &phba->work_cqs); 773 774 if ((num_mcceq_processed) && (!num_ioeq_processed)) 775 hwi_ring_eq_db(phba, eq->id, 0, 776 (num_ioeq_processed + 777 num_mcceq_processed) , 1, 1); 778 else 779 hwi_ring_eq_db(phba, eq->id, 0, 780 (num_ioeq_processed + 781 num_mcceq_processed), 0, 1); 782 783 return IRQ_HANDLED; 784 } else 785 return IRQ_NONE; 786 } else { 787 cq = &phwi_context->be_cq[0]; 788 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 789 & EQE_VALID_MASK) { 790 791 if (((eqe->dw[offsetof(struct amap_eq_entry, 792 resource_id) / 32] & 793 EQE_RESID_MASK) >> 16) != cq->id) { 794 spin_lock_irqsave(&phba->isr_lock, flags); 795 phba->todo_mcc_cq = 1; 796 spin_unlock_irqrestore(&phba->isr_lock, flags); 797 } else { 798 spin_lock_irqsave(&phba->isr_lock, flags); 799 phba->todo_cq = 1; 800 spin_unlock_irqrestore(&phba->isr_lock, flags); 801 } 802 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 803 queue_tail_inc(eq); 804 eqe = queue_tail_node(eq); 805 num_ioeq_processed++; 806 } 807 if (phba->todo_cq || phba->todo_mcc_cq) 808 queue_work(phba->wq, &phba->work_cqs); 809 810 if (num_ioeq_processed) { 811 hwi_ring_eq_db(phba, eq->id, 0, 812 num_ioeq_processed, 1, 1); 813 return IRQ_HANDLED; 814 } else 815 return IRQ_NONE; 816 } 817} 818 819static int beiscsi_init_irqs(struct beiscsi_hba *phba) 820{ 821 struct pci_dev *pcidev = phba->pcidev; 822 struct hwi_controller *phwi_ctrlr; 823 struct hwi_context_memory *phwi_context; 824 int ret, msix_vec, i, j; 825 826 phwi_ctrlr = phba->phwi_ctrlr; 827 phwi_context = phwi_ctrlr->phwi_ctxt; 828 829 if (phba->msix_enabled) { 830 for (i = 0; i < phba->num_cpus; i++) { 831 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, 832 GFP_KERNEL); 833 if (!phba->msi_name[i]) { 834 ret = -ENOMEM; 835 goto free_msix_irqs; 836 } 837 838 sprintf(phba->msi_name[i], "beiscsi_%02x_%02x", 839 phba->shost->host_no, i); 840 msix_vec = phba->msix_entries[i].vector; 841 ret = request_irq(msix_vec, be_isr_msix, 0, 842 phba->msi_name[i], 843 &phwi_context->be_eq[i]); 844 if (ret) { 845 shost_printk(KERN_ERR, phba->shost, 846 "beiscsi_init_irqs-Failed to" 847 "register msix for i = %d\n", i); 848 kfree(phba->msi_name[i]); 849 goto free_msix_irqs; 850 } 851 } 852 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL); 853 if (!phba->msi_name[i]) { 854 ret = -ENOMEM; 855 goto free_msix_irqs; 856 } 857 sprintf(phba->msi_name[i], "beiscsi_mcc_%02x", 858 phba->shost->host_no); 859 msix_vec = phba->msix_entries[i].vector; 860 ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i], 861 &phwi_context->be_eq[i]); 862 if (ret) { 863 shost_printk(KERN_ERR, phba->shost, "beiscsi_init_irqs-" 864 "Failed to register beiscsi_msix_mcc\n"); 865 kfree(phba->msi_name[i]); 866 goto free_msix_irqs; 867 } 868 869 } else { 870 ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED, 871 "beiscsi", phba); 872 if (ret) { 873 shost_printk(KERN_ERR, phba->shost, "beiscsi_init_irqs-" 874 "Failed to register irq\\n"); 875 return ret; 876 } 877 } 878 return 0; 879free_msix_irqs: 880 for (j = i - 1; j >= 0; j--) { 881 kfree(phba->msi_name[j]); 882 msix_vec = phba->msix_entries[j].vector; 883 free_irq(msix_vec, &phwi_context->be_eq[j]); 884 } 885 return ret; 886} 887 888static void hwi_ring_cq_db(struct beiscsi_hba *phba, 889 unsigned int id, unsigned int num_processed, 890 unsigned char rearm, unsigned char event) 891{ 892 u32 val = 0; 893 val |= id & DB_CQ_RING_ID_MASK; 894 if (rearm) 895 val |= 1 << DB_CQ_REARM_SHIFT; 896 val |= num_processed << DB_CQ_NUM_POPPED_SHIFT; 897 iowrite32(val, phba->db_va + DB_CQ_OFFSET); 898} 899 900static unsigned int 901beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn, 902 struct beiscsi_hba *phba, 903 unsigned short cid, 904 struct pdu_base *ppdu, 905 unsigned long pdu_len, 906 void *pbuffer, unsigned long buf_len) 907{ 908 struct iscsi_conn *conn = beiscsi_conn->conn; 909 struct iscsi_session *session = conn->session; 910 struct iscsi_task *task; 911 struct beiscsi_io_task *io_task; 912 struct iscsi_hdr *login_hdr; 913 914 switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] & 915 PDUBASE_OPCODE_MASK) { 916 case ISCSI_OP_NOOP_IN: 917 pbuffer = NULL; 918 buf_len = 0; 919 break; 920 case ISCSI_OP_ASYNC_EVENT: 921 break; 922 case ISCSI_OP_REJECT: 923 WARN_ON(!pbuffer); 924 WARN_ON(!(buf_len == 48)); 925 SE_DEBUG(DBG_LVL_1, "In ISCSI_OP_REJECT\n"); 926 break; 927 case ISCSI_OP_LOGIN_RSP: 928 case ISCSI_OP_TEXT_RSP: 929 task = conn->login_task; 930 io_task = task->dd_data; 931 login_hdr = (struct iscsi_hdr *)ppdu; 932 login_hdr->itt = io_task->libiscsi_itt; 933 break; 934 default: 935 shost_printk(KERN_WARNING, phba->shost, 936 "Unrecognized opcode 0x%x in async msg\n", 937 (ppdu-> 938 dw[offsetof(struct amap_pdu_base, opcode) / 32] 939 & PDUBASE_OPCODE_MASK)); 940 return 1; 941 } 942 943 spin_lock_bh(&session->lock); 944 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len); 945 spin_unlock_bh(&session->lock); 946 return 0; 947} 948 949static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba) 950{ 951 struct sgl_handle *psgl_handle; 952 953 if (phba->io_sgl_hndl_avbl) { 954 SE_DEBUG(DBG_LVL_8, 955 "In alloc_io_sgl_handle,io_sgl_alloc_index=%d\n", 956 phba->io_sgl_alloc_index); 957 psgl_handle = phba->io_sgl_hndl_base[phba-> 958 io_sgl_alloc_index]; 959 phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL; 960 phba->io_sgl_hndl_avbl--; 961 if (phba->io_sgl_alloc_index == (phba->params. 962 ios_per_ctrl - 1)) 963 phba->io_sgl_alloc_index = 0; 964 else 965 phba->io_sgl_alloc_index++; 966 } else 967 psgl_handle = NULL; 968 return psgl_handle; 969} 970 971static void 972free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle) 973{ 974 SE_DEBUG(DBG_LVL_8, "In free_,io_sgl_free_index=%d\n", 975 phba->io_sgl_free_index); 976 if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) { 977 /* 978 * this can happen if clean_task is called on a task that 979 * failed in xmit_task or alloc_pdu. 980 */ 981 SE_DEBUG(DBG_LVL_8, 982 "Double Free in IO SGL io_sgl_free_index=%d," 983 "value there=%p\n", phba->io_sgl_free_index, 984 phba->io_sgl_hndl_base[phba->io_sgl_free_index]); 985 return; 986 } 987 phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle; 988 phba->io_sgl_hndl_avbl++; 989 if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1)) 990 phba->io_sgl_free_index = 0; 991 else 992 phba->io_sgl_free_index++; 993} 994 995/** 996 * alloc_wrb_handle - To allocate a wrb handle 997 * @phba: The hba pointer 998 * @cid: The cid to use for allocation 999 * 1000 * This happens under session_lock until submission to chip 1001 */ 1002struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid) 1003{ 1004 struct hwi_wrb_context *pwrb_context; 1005 struct hwi_controller *phwi_ctrlr; 1006 struct wrb_handle *pwrb_handle, *pwrb_handle_tmp; 1007 1008 phwi_ctrlr = phba->phwi_ctrlr; 1009 pwrb_context = &phwi_ctrlr->wrb_context[cid]; 1010 if (pwrb_context->wrb_handles_available >= 2) { 1011 pwrb_handle = pwrb_context->pwrb_handle_base[ 1012 pwrb_context->alloc_index]; 1013 pwrb_context->wrb_handles_available--; 1014 if (pwrb_context->alloc_index == 1015 (phba->params.wrbs_per_cxn - 1)) 1016 pwrb_context->alloc_index = 0; 1017 else 1018 pwrb_context->alloc_index++; 1019 pwrb_handle_tmp = pwrb_context->pwrb_handle_base[ 1020 pwrb_context->alloc_index]; 1021 pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index; 1022 } else 1023 pwrb_handle = NULL; 1024 return pwrb_handle; 1025} 1026 1027/** 1028 * free_wrb_handle - To free the wrb handle back to pool 1029 * @phba: The hba pointer 1030 * @pwrb_context: The context to free from 1031 * @pwrb_handle: The wrb_handle to free 1032 * 1033 * This happens under session_lock until submission to chip 1034 */ 1035static void 1036free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context, 1037 struct wrb_handle *pwrb_handle) 1038{ 1039 pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle; 1040 pwrb_context->wrb_handles_available++; 1041 if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1)) 1042 pwrb_context->free_index = 0; 1043 else 1044 pwrb_context->free_index++; 1045 1046 SE_DEBUG(DBG_LVL_8, 1047 "FREE WRB: pwrb_handle=%p free_index=0x%x" 1048 "wrb_handles_available=%d\n", 1049 pwrb_handle, pwrb_context->free_index, 1050 pwrb_context->wrb_handles_available); 1051} 1052 1053static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba) 1054{ 1055 struct sgl_handle *psgl_handle; 1056 1057 if (phba->eh_sgl_hndl_avbl) { 1058 psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index]; 1059 phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL; 1060 SE_DEBUG(DBG_LVL_8, "mgmt_sgl_alloc_index=%d=0x%x\n", 1061 phba->eh_sgl_alloc_index, phba->eh_sgl_alloc_index); 1062 phba->eh_sgl_hndl_avbl--; 1063 if (phba->eh_sgl_alloc_index == 1064 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1065 1)) 1066 phba->eh_sgl_alloc_index = 0; 1067 else 1068 phba->eh_sgl_alloc_index++; 1069 } else 1070 psgl_handle = NULL; 1071 return psgl_handle; 1072} 1073 1074void 1075free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle) 1076{ 1077 1078 SE_DEBUG(DBG_LVL_8, "In free_mgmt_sgl_handle,eh_sgl_free_index=%d\n", 1079 phba->eh_sgl_free_index); 1080 if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) { 1081 /* 1082 * this can happen if clean_task is called on a task that 1083 * failed in xmit_task or alloc_pdu. 1084 */ 1085 SE_DEBUG(DBG_LVL_8, 1086 "Double Free in eh SGL ,eh_sgl_free_index=%d\n", 1087 phba->eh_sgl_free_index); 1088 return; 1089 } 1090 phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle; 1091 phba->eh_sgl_hndl_avbl++; 1092 if (phba->eh_sgl_free_index == 1093 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1)) 1094 phba->eh_sgl_free_index = 0; 1095 else 1096 phba->eh_sgl_free_index++; 1097} 1098 1099static void 1100be_complete_io(struct beiscsi_conn *beiscsi_conn, 1101 struct iscsi_task *task, struct sol_cqe *psol) 1102{ 1103 struct beiscsi_io_task *io_task = task->dd_data; 1104 struct be_status_bhs *sts_bhs = 1105 (struct be_status_bhs *)io_task->cmd_bhs; 1106 struct iscsi_conn *conn = beiscsi_conn->conn; 1107 unsigned int sense_len; 1108 unsigned char *sense; 1109 u32 resid = 0, exp_cmdsn, max_cmdsn; 1110 u8 rsp, status, flags; 1111 1112 exp_cmdsn = (psol-> 1113 dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32] 1114 & SOL_EXP_CMD_SN_MASK); 1115 max_cmdsn = ((psol-> 1116 dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32] 1117 & SOL_EXP_CMD_SN_MASK) + 1118 ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd) 1119 / 32] & SOL_CMD_WND_MASK) >> 24) - 1); 1120 rsp = ((psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 32] 1121 & SOL_RESP_MASK) >> 16); 1122 status = ((psol->dw[offsetof(struct amap_sol_cqe, i_sts) / 32] 1123 & SOL_STS_MASK) >> 8); 1124 flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32] 1125 & SOL_FLAGS_MASK) >> 24) | 0x80; 1126 1127 task->sc->result = (DID_OK << 16) | status; 1128 if (rsp != ISCSI_STATUS_CMD_COMPLETED) { 1129 task->sc->result = DID_ERROR << 16; 1130 goto unmap; 1131 } 1132 1133 /* bidi not initially supported */ 1134 if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) { 1135 resid = (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 1136 32] & SOL_RES_CNT_MASK); 1137 1138 if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW)) 1139 task->sc->result = DID_ERROR << 16; 1140 1141 if (flags & ISCSI_FLAG_CMD_UNDERFLOW) { 1142 scsi_set_resid(task->sc, resid); 1143 if (!status && (scsi_bufflen(task->sc) - resid < 1144 task->sc->underflow)) 1145 task->sc->result = DID_ERROR << 16; 1146 } 1147 } 1148 1149 if (status == SAM_STAT_CHECK_CONDITION) { 1150 unsigned short *slen = (unsigned short *)sts_bhs->sense_info; 1151 sense = sts_bhs->sense_info + sizeof(unsigned short); 1152 sense_len = cpu_to_be16(*slen); 1153 memcpy(task->sc->sense_buffer, sense, 1154 min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE)); 1155 } 1156 1157 if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) { 1158 if (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32] 1159 & SOL_RES_CNT_MASK) 1160 conn->rxdata_octets += (psol-> 1161 dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32] 1162 & SOL_RES_CNT_MASK); 1163 } 1164unmap: 1165 scsi_dma_unmap(io_task->scsi_cmnd); 1166 iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn); 1167} 1168 1169static void 1170be_complete_logout(struct beiscsi_conn *beiscsi_conn, 1171 struct iscsi_task *task, struct sol_cqe *psol) 1172{ 1173 struct iscsi_logout_rsp *hdr; 1174 struct beiscsi_io_task *io_task = task->dd_data; 1175 struct iscsi_conn *conn = beiscsi_conn->conn; 1176 1177 hdr = (struct iscsi_logout_rsp *)task->hdr; 1178 hdr->opcode = ISCSI_OP_LOGOUT_RSP; 1179 hdr->t2wait = 5; 1180 hdr->t2retain = 0; 1181 hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32] 1182 & SOL_FLAGS_MASK) >> 24) | 0x80; 1183 hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 1184 32] & SOL_RESP_MASK); 1185 hdr->exp_cmdsn = cpu_to_be32(psol-> 1186 dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32] 1187 & SOL_EXP_CMD_SN_MASK); 1188 hdr->max_cmdsn = be32_to_cpu((psol-> 1189 dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32] 1190 & SOL_EXP_CMD_SN_MASK) + 1191 ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd) 1192 / 32] & SOL_CMD_WND_MASK) >> 24) - 1); 1193 hdr->dlength[0] = 0; 1194 hdr->dlength[1] = 0; 1195 hdr->dlength[2] = 0; 1196 hdr->hlength = 0; 1197 hdr->itt = io_task->libiscsi_itt; 1198 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); 1199} 1200 1201static void 1202be_complete_tmf(struct beiscsi_conn *beiscsi_conn, 1203 struct iscsi_task *task, struct sol_cqe *psol) 1204{ 1205 struct iscsi_tm_rsp *hdr; 1206 struct iscsi_conn *conn = beiscsi_conn->conn; 1207 struct beiscsi_io_task *io_task = task->dd_data; 1208 1209 hdr = (struct iscsi_tm_rsp *)task->hdr; 1210 hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP; 1211 hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32] 1212 & SOL_FLAGS_MASK) >> 24) | 0x80; 1213 hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 1214 32] & SOL_RESP_MASK); 1215 hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe, 1216 i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK); 1217 hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe, 1218 i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) + 1219 ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd) 1220 / 32] & SOL_CMD_WND_MASK) >> 24) - 1); 1221 hdr->itt = io_task->libiscsi_itt; 1222 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); 1223} 1224 1225static void 1226hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn, 1227 struct beiscsi_hba *phba, struct sol_cqe *psol) 1228{ 1229 struct hwi_wrb_context *pwrb_context; 1230 struct wrb_handle *pwrb_handle = NULL; 1231 struct hwi_controller *phwi_ctrlr; 1232 struct iscsi_task *task; 1233 struct beiscsi_io_task *io_task; 1234 struct iscsi_conn *conn = beiscsi_conn->conn; 1235 struct iscsi_session *session = conn->session; 1236 1237 phwi_ctrlr = phba->phwi_ctrlr; 1238 pwrb_context = &phwi_ctrlr->wrb_context[((psol-> 1239 dw[offsetof(struct amap_sol_cqe, cid) / 32] & 1240 SOL_CID_MASK) >> 6) - 1241 phba->fw_config.iscsi_cid_start]; 1242 pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol-> 1243 dw[offsetof(struct amap_sol_cqe, wrb_index) / 1244 32] & SOL_WRB_INDEX_MASK) >> 16)]; 1245 task = pwrb_handle->pio_handle; 1246 1247 io_task = task->dd_data; 1248 spin_lock(&phba->mgmt_sgl_lock); 1249 free_mgmt_sgl_handle(phba, io_task->psgl_handle); 1250 spin_unlock(&phba->mgmt_sgl_lock); 1251 spin_lock_bh(&session->lock); 1252 free_wrb_handle(phba, pwrb_context, pwrb_handle); 1253 spin_unlock_bh(&session->lock); 1254} 1255 1256static void 1257be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn, 1258 struct iscsi_task *task, struct sol_cqe *psol) 1259{ 1260 struct iscsi_nopin *hdr; 1261 struct iscsi_conn *conn = beiscsi_conn->conn; 1262 struct beiscsi_io_task *io_task = task->dd_data; 1263 1264 hdr = (struct iscsi_nopin *)task->hdr; 1265 hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32] 1266 & SOL_FLAGS_MASK) >> 24) | 0x80; 1267 hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe, 1268 i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK); 1269 hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe, 1270 i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) + 1271 ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd) 1272 / 32] & SOL_CMD_WND_MASK) >> 24) - 1); 1273 hdr->opcode = ISCSI_OP_NOOP_IN; 1274 hdr->itt = io_task->libiscsi_itt; 1275 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); 1276} 1277 1278static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn, 1279 struct beiscsi_hba *phba, struct sol_cqe *psol) 1280{ 1281 struct hwi_wrb_context *pwrb_context; 1282 struct wrb_handle *pwrb_handle; 1283 struct iscsi_wrb *pwrb = NULL; 1284 struct hwi_controller *phwi_ctrlr; 1285 struct iscsi_task *task; 1286 unsigned int type; 1287 struct iscsi_conn *conn = beiscsi_conn->conn; 1288 struct iscsi_session *session = conn->session; 1289 1290 phwi_ctrlr = phba->phwi_ctrlr; 1291 pwrb_context = &phwi_ctrlr->wrb_context[((psol->dw[offsetof 1292 (struct amap_sol_cqe, cid) / 32] 1293 & SOL_CID_MASK) >> 6) - 1294 phba->fw_config.iscsi_cid_start]; 1295 pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol-> 1296 dw[offsetof(struct amap_sol_cqe, wrb_index) / 1297 32] & SOL_WRB_INDEX_MASK) >> 16)]; 1298 task = pwrb_handle->pio_handle; 1299 pwrb = pwrb_handle->pwrb; 1300 type = (pwrb->dw[offsetof(struct amap_iscsi_wrb, type) / 32] & 1301 WRB_TYPE_MASK) >> 28; 1302 1303 spin_lock_bh(&session->lock); 1304 switch (type) { 1305 case HWH_TYPE_IO: 1306 case HWH_TYPE_IO_RD: 1307 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == 1308 ISCSI_OP_NOOP_OUT) 1309 be_complete_nopin_resp(beiscsi_conn, task, psol); 1310 else 1311 be_complete_io(beiscsi_conn, task, psol); 1312 break; 1313 1314 case HWH_TYPE_LOGOUT: 1315 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT) 1316 be_complete_logout(beiscsi_conn, task, psol); 1317 else 1318 be_complete_tmf(beiscsi_conn, task, psol); 1319 1320 break; 1321 1322 case HWH_TYPE_LOGIN: 1323 SE_DEBUG(DBG_LVL_1, 1324 "\t\t No HWH_TYPE_LOGIN Expected in hwi_complete_cmd" 1325 "- Solicited path\n"); 1326 break; 1327 1328 case HWH_TYPE_NOP: 1329 be_complete_nopin_resp(beiscsi_conn, task, psol); 1330 break; 1331 1332 default: 1333 shost_printk(KERN_WARNING, phba->shost, 1334 "In hwi_complete_cmd, unknown type = %d" 1335 "wrb_index 0x%x CID 0x%x\n", type, 1336 ((psol->dw[offsetof(struct amap_iscsi_wrb, 1337 type) / 32] & SOL_WRB_INDEX_MASK) >> 16), 1338 ((psol->dw[offsetof(struct amap_sol_cqe, 1339 cid) / 32] & SOL_CID_MASK) >> 6)); 1340 break; 1341 } 1342 1343 spin_unlock_bh(&session->lock); 1344} 1345 1346static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context 1347 *pasync_ctx, unsigned int is_header, 1348 unsigned int host_write_ptr) 1349{ 1350 if (is_header) 1351 return &pasync_ctx->async_entry[host_write_ptr]. 1352 header_busy_list; 1353 else 1354 return &pasync_ctx->async_entry[host_write_ptr].data_busy_list; 1355} 1356 1357static struct async_pdu_handle * 1358hwi_get_async_handle(struct beiscsi_hba *phba, 1359 struct beiscsi_conn *beiscsi_conn, 1360 struct hwi_async_pdu_context *pasync_ctx, 1361 struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index) 1362{ 1363 struct be_bus_address phys_addr; 1364 struct list_head *pbusy_list; 1365 struct async_pdu_handle *pasync_handle = NULL; 1366 int buffer_len = 0; 1367 unsigned char buffer_index = -1; 1368 unsigned char is_header = 0; 1369 1370 phys_addr.u.a32.address_lo = 1371 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_lo) / 32] - 1372 ((pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32] 1373 & PDUCQE_DPL_MASK) >> 16); 1374 phys_addr.u.a32.address_hi = 1375 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_hi) / 32]; 1376 1377 phys_addr.u.a64.address = 1378 *((unsigned long long *)(&phys_addr.u.a64.address)); 1379 1380 switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32] 1381 & PDUCQE_CODE_MASK) { 1382 case UNSOL_HDR_NOTIFY: 1383 is_header = 1; 1384 1385 pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1, 1386 (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, 1387 index) / 32] & PDUCQE_INDEX_MASK)); 1388 1389 buffer_len = (unsigned int)(phys_addr.u.a64.address - 1390 pasync_ctx->async_header.pa_base.u.a64.address); 1391 1392 buffer_index = buffer_len / 1393 pasync_ctx->async_header.buffer_size; 1394 1395 break; 1396 case UNSOL_DATA_NOTIFY: 1397 pbusy_list = hwi_get_async_busy_list(pasync_ctx, 0, (pdpdu_cqe-> 1398 dw[offsetof(struct amap_i_t_dpdu_cqe, 1399 index) / 32] & PDUCQE_INDEX_MASK)); 1400 buffer_len = (unsigned long)(phys_addr.u.a64.address - 1401 pasync_ctx->async_data.pa_base.u. 1402 a64.address); 1403 buffer_index = buffer_len / pasync_ctx->async_data.buffer_size; 1404 break; 1405 default: 1406 pbusy_list = NULL; 1407 shost_printk(KERN_WARNING, phba->shost, 1408 "Unexpected code=%d\n", 1409 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, 1410 code) / 32] & PDUCQE_CODE_MASK); 1411 return NULL; 1412 } 1413 1414 WARN_ON(!(buffer_index <= pasync_ctx->async_data.num_entries)); 1415 WARN_ON(list_empty(pbusy_list)); 1416 list_for_each_entry(pasync_handle, pbusy_list, link) { 1417 WARN_ON(pasync_handle->consumed); 1418 if (pasync_handle->index == buffer_index) 1419 break; 1420 } 1421 1422 WARN_ON(!pasync_handle); 1423 1424 pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid - 1425 phba->fw_config.iscsi_cid_start; 1426 pasync_handle->is_header = is_header; 1427 pasync_handle->buffer_len = ((pdpdu_cqe-> 1428 dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32] 1429 & PDUCQE_DPL_MASK) >> 16); 1430 1431 *pcq_index = (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, 1432 index) / 32] & PDUCQE_INDEX_MASK); 1433 return pasync_handle; 1434} 1435 1436static unsigned int 1437hwi_update_async_writables(struct hwi_async_pdu_context *pasync_ctx, 1438 unsigned int is_header, unsigned int cq_index) 1439{ 1440 struct list_head *pbusy_list; 1441 struct async_pdu_handle *pasync_handle; 1442 unsigned int num_entries, writables = 0; 1443 unsigned int *pep_read_ptr, *pwritables; 1444 1445 1446 if (is_header) { 1447 pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr; 1448 pwritables = &pasync_ctx->async_header.writables; 1449 num_entries = pasync_ctx->async_header.num_entries; 1450 } else { 1451 pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr; 1452 pwritables = &pasync_ctx->async_data.writables; 1453 num_entries = pasync_ctx->async_data.num_entries; 1454 } 1455 1456 while ((*pep_read_ptr) != cq_index) { 1457 (*pep_read_ptr)++; 1458 *pep_read_ptr = (*pep_read_ptr) % num_entries; 1459 1460 pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header, 1461 *pep_read_ptr); 1462 if (writables == 0) 1463 WARN_ON(list_empty(pbusy_list)); 1464 1465 if (!list_empty(pbusy_list)) { 1466 pasync_handle = list_entry(pbusy_list->next, 1467 struct async_pdu_handle, 1468 link); 1469 WARN_ON(!pasync_handle); 1470 pasync_handle->consumed = 1; 1471 } 1472 1473 writables++; 1474 } 1475 1476 if (!writables) { 1477 SE_DEBUG(DBG_LVL_1, 1478 "Duplicate notification received - index 0x%x!!\n", 1479 cq_index); 1480 WARN_ON(1); 1481 } 1482 1483 *pwritables = *pwritables + writables; 1484 return 0; 1485} 1486 1487static unsigned int hwi_free_async_msg(struct beiscsi_hba *phba, 1488 unsigned int cri) 1489{ 1490 struct hwi_controller *phwi_ctrlr; 1491 struct hwi_async_pdu_context *pasync_ctx; 1492 struct async_pdu_handle *pasync_handle, *tmp_handle; 1493 struct list_head *plist; 1494 unsigned int i = 0; 1495 1496 phwi_ctrlr = phba->phwi_ctrlr; 1497 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr); 1498 1499 plist = &pasync_ctx->async_entry[cri].wait_queue.list; 1500 1501 list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) { 1502 list_del(&pasync_handle->link); 1503 1504 if (i == 0) { 1505 list_add_tail(&pasync_handle->link, 1506 &pasync_ctx->async_header.free_list); 1507 pasync_ctx->async_header.free_entries++; 1508 i++; 1509 } else { 1510 list_add_tail(&pasync_handle->link, 1511 &pasync_ctx->async_data.free_list); 1512 pasync_ctx->async_data.free_entries++; 1513 i++; 1514 } 1515 } 1516 1517 INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list); 1518 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0; 1519 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0; 1520 return 0; 1521} 1522 1523static struct phys_addr * 1524hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx, 1525 unsigned int is_header, unsigned int host_write_ptr) 1526{ 1527 struct phys_addr *pasync_sge = NULL; 1528 1529 if (is_header) 1530 pasync_sge = pasync_ctx->async_header.ring_base; 1531 else 1532 pasync_sge = pasync_ctx->async_data.ring_base; 1533 1534 return pasync_sge + host_write_ptr; 1535} 1536 1537static void hwi_post_async_buffers(struct beiscsi_hba *phba, 1538 unsigned int is_header) 1539{ 1540 struct hwi_controller *phwi_ctrlr; 1541 struct hwi_async_pdu_context *pasync_ctx; 1542 struct async_pdu_handle *pasync_handle; 1543 struct list_head *pfree_link, *pbusy_list; 1544 struct phys_addr *pasync_sge; 1545 unsigned int ring_id, num_entries; 1546 unsigned int host_write_num; 1547 unsigned int writables; 1548 unsigned int i = 0; 1549 u32 doorbell = 0; 1550 1551 phwi_ctrlr = phba->phwi_ctrlr; 1552 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr); 1553 1554 if (is_header) { 1555 num_entries = pasync_ctx->async_header.num_entries; 1556 writables = min(pasync_ctx->async_header.writables, 1557 pasync_ctx->async_header.free_entries); 1558 pfree_link = pasync_ctx->async_header.free_list.next; 1559 host_write_num = pasync_ctx->async_header.host_write_ptr; 1560 ring_id = phwi_ctrlr->default_pdu_hdr.id; 1561 } else { 1562 num_entries = pasync_ctx->async_data.num_entries; 1563 writables = min(pasync_ctx->async_data.writables, 1564 pasync_ctx->async_data.free_entries); 1565 pfree_link = pasync_ctx->async_data.free_list.next; 1566 host_write_num = pasync_ctx->async_data.host_write_ptr; 1567 ring_id = phwi_ctrlr->default_pdu_data.id; 1568 } 1569 1570 writables = (writables / 8) * 8; 1571 if (writables) { 1572 for (i = 0; i < writables; i++) { 1573 pbusy_list = 1574 hwi_get_async_busy_list(pasync_ctx, is_header, 1575 host_write_num); 1576 pasync_handle = 1577 list_entry(pfree_link, struct async_pdu_handle, 1578 link); 1579 WARN_ON(!pasync_handle); 1580 pasync_handle->consumed = 0; 1581 1582 pfree_link = pfree_link->next; 1583 1584 pasync_sge = hwi_get_ring_address(pasync_ctx, 1585 is_header, host_write_num); 1586 1587 pasync_sge->hi = pasync_handle->pa.u.a32.address_lo; 1588 pasync_sge->lo = pasync_handle->pa.u.a32.address_hi; 1589 1590 list_move(&pasync_handle->link, pbusy_list); 1591 1592 host_write_num++; 1593 host_write_num = host_write_num % num_entries; 1594 } 1595 1596 if (is_header) { 1597 pasync_ctx->async_header.host_write_ptr = 1598 host_write_num; 1599 pasync_ctx->async_header.free_entries -= writables; 1600 pasync_ctx->async_header.writables -= writables; 1601 pasync_ctx->async_header.busy_entries += writables; 1602 } else { 1603 pasync_ctx->async_data.host_write_ptr = host_write_num; 1604 pasync_ctx->async_data.free_entries -= writables; 1605 pasync_ctx->async_data.writables -= writables; 1606 pasync_ctx->async_data.busy_entries += writables; 1607 } 1608 1609 doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK; 1610 doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT; 1611 doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT; 1612 doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK) 1613 << DB_DEF_PDU_CQPROC_SHIFT; 1614 1615 iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET); 1616 } 1617} 1618 1619static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba, 1620 struct beiscsi_conn *beiscsi_conn, 1621 struct i_t_dpdu_cqe *pdpdu_cqe) 1622{ 1623 struct hwi_controller *phwi_ctrlr; 1624 struct hwi_async_pdu_context *pasync_ctx; 1625 struct async_pdu_handle *pasync_handle = NULL; 1626 unsigned int cq_index = -1; 1627 1628 phwi_ctrlr = phba->phwi_ctrlr; 1629 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr); 1630 1631 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx, 1632 pdpdu_cqe, &cq_index); 1633 BUG_ON(pasync_handle->is_header != 0); 1634 if (pasync_handle->consumed == 0) 1635 hwi_update_async_writables(pasync_ctx, pasync_handle->is_header, 1636 cq_index); 1637 1638 hwi_free_async_msg(phba, pasync_handle->cri); 1639 hwi_post_async_buffers(phba, pasync_handle->is_header); 1640} 1641 1642static unsigned int 1643hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn, 1644 struct beiscsi_hba *phba, 1645 struct hwi_async_pdu_context *pasync_ctx, unsigned short cri) 1646{ 1647 struct list_head *plist; 1648 struct async_pdu_handle *pasync_handle; 1649 void *phdr = NULL; 1650 unsigned int hdr_len = 0, buf_len = 0; 1651 unsigned int status, index = 0, offset = 0; 1652 void *pfirst_buffer = NULL; 1653 unsigned int num_buf = 0; 1654 1655 plist = &pasync_ctx->async_entry[cri].wait_queue.list; 1656 1657 list_for_each_entry(pasync_handle, plist, link) { 1658 if (index == 0) { 1659 phdr = pasync_handle->pbuffer; 1660 hdr_len = pasync_handle->buffer_len; 1661 } else { 1662 buf_len = pasync_handle->buffer_len; 1663 if (!num_buf) { 1664 pfirst_buffer = pasync_handle->pbuffer; 1665 num_buf++; 1666 } 1667 memcpy(pfirst_buffer + offset, 1668 pasync_handle->pbuffer, buf_len); 1669 offset = buf_len; 1670 } 1671 index++; 1672 } 1673 1674 status = beiscsi_process_async_pdu(beiscsi_conn, phba, 1675 (beiscsi_conn->beiscsi_conn_cid - 1676 phba->fw_config.iscsi_cid_start), 1677 phdr, hdr_len, pfirst_buffer, 1678 buf_len); 1679 1680 if (status == 0) 1681 hwi_free_async_msg(phba, cri); 1682 return 0; 1683} 1684 1685static unsigned int 1686hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn, 1687 struct beiscsi_hba *phba, 1688 struct async_pdu_handle *pasync_handle) 1689{ 1690 struct hwi_async_pdu_context *pasync_ctx; 1691 struct hwi_controller *phwi_ctrlr; 1692 unsigned int bytes_needed = 0, status = 0; 1693 unsigned short cri = pasync_handle->cri; 1694 struct pdu_base *ppdu; 1695 1696 phwi_ctrlr = phba->phwi_ctrlr; 1697 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr); 1698 1699 list_del(&pasync_handle->link); 1700 if (pasync_handle->is_header) { 1701 pasync_ctx->async_header.busy_entries--; 1702 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) { 1703 hwi_free_async_msg(phba, cri); 1704 BUG(); 1705 } 1706 1707 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0; 1708 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1; 1709 pasync_ctx->async_entry[cri].wait_queue.hdr_len = 1710 (unsigned short)pasync_handle->buffer_len; 1711 list_add_tail(&pasync_handle->link, 1712 &pasync_ctx->async_entry[cri].wait_queue.list); 1713 1714 ppdu = pasync_handle->pbuffer; 1715 bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base, 1716 data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) & 1717 0xFFFF0000) | ((be16_to_cpu((ppdu-> 1718 dw[offsetof(struct amap_pdu_base, data_len_lo) / 32] 1719 & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF)); 1720 1721 if (status == 0) { 1722 pasync_ctx->async_entry[cri].wait_queue.bytes_needed = 1723 bytes_needed; 1724 1725 if (bytes_needed == 0) 1726 status = hwi_fwd_async_msg(beiscsi_conn, phba, 1727 pasync_ctx, cri); 1728 } 1729 } else { 1730 pasync_ctx->async_data.busy_entries--; 1731 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) { 1732 list_add_tail(&pasync_handle->link, 1733 &pasync_ctx->async_entry[cri].wait_queue. 1734 list); 1735 pasync_ctx->async_entry[cri].wait_queue. 1736 bytes_received += 1737 (unsigned short)pasync_handle->buffer_len; 1738 1739 if (pasync_ctx->async_entry[cri].wait_queue. 1740 bytes_received >= 1741 pasync_ctx->async_entry[cri].wait_queue. 1742 bytes_needed) 1743 status = hwi_fwd_async_msg(beiscsi_conn, phba, 1744 pasync_ctx, cri); 1745 } 1746 } 1747 return status; 1748} 1749 1750static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn, 1751 struct beiscsi_hba *phba, 1752 struct i_t_dpdu_cqe *pdpdu_cqe) 1753{ 1754 struct hwi_controller *phwi_ctrlr; 1755 struct hwi_async_pdu_context *pasync_ctx; 1756 struct async_pdu_handle *pasync_handle = NULL; 1757 unsigned int cq_index = -1; 1758 1759 phwi_ctrlr = phba->phwi_ctrlr; 1760 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr); 1761 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx, 1762 pdpdu_cqe, &cq_index); 1763 1764 if (pasync_handle->consumed == 0) 1765 hwi_update_async_writables(pasync_ctx, pasync_handle->is_header, 1766 cq_index); 1767 hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle); 1768 hwi_post_async_buffers(phba, pasync_handle->is_header); 1769} 1770 1771static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba) 1772{ 1773 struct be_queue_info *mcc_cq; 1774 struct be_mcc_compl *mcc_compl; 1775 unsigned int num_processed = 0; 1776 1777 mcc_cq = &phba->ctrl.mcc_obj.cq; 1778 mcc_compl = queue_tail_node(mcc_cq); 1779 mcc_compl->flags = le32_to_cpu(mcc_compl->flags); 1780 while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) { 1781 1782 if (num_processed >= 32) { 1783 hwi_ring_cq_db(phba, mcc_cq->id, 1784 num_processed, 0, 0); 1785 num_processed = 0; 1786 } 1787 if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) { 1788 /* Interpret flags as an async trailer */ 1789 if (is_link_state_evt(mcc_compl->flags)) 1790 /* Interpret compl as a async link evt */ 1791 beiscsi_async_link_state_process(phba, 1792 (struct be_async_event_link_state *) mcc_compl); 1793 else 1794 SE_DEBUG(DBG_LVL_1, 1795 " Unsupported Async Event, flags" 1796 " = 0x%08x\n", mcc_compl->flags); 1797 } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) { 1798 be_mcc_compl_process_isr(&phba->ctrl, mcc_compl); 1799 atomic_dec(&phba->ctrl.mcc_obj.q.used); 1800 } 1801 1802 mcc_compl->flags = 0; 1803 queue_tail_inc(mcc_cq); 1804 mcc_compl = queue_tail_node(mcc_cq); 1805 mcc_compl->flags = le32_to_cpu(mcc_compl->flags); 1806 num_processed++; 1807 } 1808 1809 if (num_processed > 0) 1810 hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0); 1811 1812} 1813 1814static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq) 1815{ 1816 struct be_queue_info *cq; 1817 struct sol_cqe *sol; 1818 struct dmsg_cqe *dmsg; 1819 unsigned int num_processed = 0; 1820 unsigned int tot_nump = 0; 1821 struct beiscsi_conn *beiscsi_conn; 1822 struct beiscsi_endpoint *beiscsi_ep; 1823 struct iscsi_endpoint *ep; 1824 struct beiscsi_hba *phba; 1825 1826 cq = pbe_eq->cq; 1827 sol = queue_tail_node(cq); 1828 phba = pbe_eq->phba; 1829 1830 while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] & 1831 CQE_VALID_MASK) { 1832 be_dws_le_to_cpu(sol, sizeof(struct sol_cqe)); 1833 1834 ep = phba->ep_array[(u32) ((sol-> 1835 dw[offsetof(struct amap_sol_cqe, cid) / 32] & 1836 SOL_CID_MASK) >> 6) - 1837 phba->fw_config.iscsi_cid_start]; 1838 1839 beiscsi_ep = ep->dd_data; 1840 beiscsi_conn = beiscsi_ep->conn; 1841 1842 if (num_processed >= 32) { 1843 hwi_ring_cq_db(phba, cq->id, 1844 num_processed, 0, 0); 1845 tot_nump += num_processed; 1846 num_processed = 0; 1847 } 1848 1849 switch ((u32) sol->dw[offsetof(struct amap_sol_cqe, code) / 1850 32] & CQE_CODE_MASK) { 1851 case SOL_CMD_COMPLETE: 1852 hwi_complete_cmd(beiscsi_conn, phba, sol); 1853 break; 1854 case DRIVERMSG_NOTIFY: 1855 SE_DEBUG(DBG_LVL_8, "Received DRIVERMSG_NOTIFY\n"); 1856 dmsg = (struct dmsg_cqe *)sol; 1857 hwi_complete_drvr_msgs(beiscsi_conn, phba, sol); 1858 break; 1859 case UNSOL_HDR_NOTIFY: 1860 SE_DEBUG(DBG_LVL_8, "Received UNSOL_HDR_ NOTIFY\n"); 1861 hwi_process_default_pdu_ring(beiscsi_conn, phba, 1862 (struct i_t_dpdu_cqe *)sol); 1863 break; 1864 case UNSOL_DATA_NOTIFY: 1865 SE_DEBUG(DBG_LVL_8, "Received UNSOL_DATA_NOTIFY\n"); 1866 hwi_process_default_pdu_ring(beiscsi_conn, phba, 1867 (struct i_t_dpdu_cqe *)sol); 1868 break; 1869 case CXN_INVALIDATE_INDEX_NOTIFY: 1870 case CMD_INVALIDATED_NOTIFY: 1871 case CXN_INVALIDATE_NOTIFY: 1872 SE_DEBUG(DBG_LVL_1, 1873 "Ignoring CQ Error notification for cmd/cxn" 1874 "invalidate\n"); 1875 break; 1876 case SOL_CMD_KILLED_DATA_DIGEST_ERR: 1877 case CMD_KILLED_INVALID_STATSN_RCVD: 1878 case CMD_KILLED_INVALID_R2T_RCVD: 1879 case CMD_CXN_KILLED_LUN_INVALID: 1880 case CMD_CXN_KILLED_ICD_INVALID: 1881 case CMD_CXN_KILLED_ITT_INVALID: 1882 case CMD_CXN_KILLED_SEQ_OUTOFORDER: 1883 case CMD_CXN_KILLED_INVALID_DATASN_RCVD: 1884 SE_DEBUG(DBG_LVL_1, 1885 "CQ Error notification for cmd.. " 1886 "code %d cid 0x%x\n", 1887 sol->dw[offsetof(struct amap_sol_cqe, code) / 1888 32] & CQE_CODE_MASK, 1889 (sol->dw[offsetof(struct amap_sol_cqe, cid) / 1890 32] & SOL_CID_MASK)); 1891 break; 1892 case UNSOL_DATA_DIGEST_ERROR_NOTIFY: 1893 SE_DEBUG(DBG_LVL_1, 1894 "Digest error on def pdu ring, dropping..\n"); 1895 hwi_flush_default_pdu_buffer(phba, beiscsi_conn, 1896 (struct i_t_dpdu_cqe *) sol); 1897 break; 1898 case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL: 1899 case CXN_KILLED_BURST_LEN_MISMATCH: 1900 case CXN_KILLED_AHS_RCVD: 1901 case CXN_KILLED_HDR_DIGEST_ERR: 1902 case CXN_KILLED_UNKNOWN_HDR: 1903 case CXN_KILLED_STALE_ITT_TTT_RCVD: 1904 case CXN_KILLED_INVALID_ITT_TTT_RCVD: 1905 case CXN_KILLED_TIMED_OUT: 1906 case CXN_KILLED_FIN_RCVD: 1907 case CXN_KILLED_BAD_UNSOL_PDU_RCVD: 1908 case CXN_KILLED_BAD_WRB_INDEX_ERROR: 1909 case CXN_KILLED_OVER_RUN_RESIDUAL: 1910 case CXN_KILLED_UNDER_RUN_RESIDUAL: 1911 case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN: 1912 SE_DEBUG(DBG_LVL_1, "CQ Error %d, reset CID " 1913 "0x%x...\n", 1914 sol->dw[offsetof(struct amap_sol_cqe, code) / 1915 32] & CQE_CODE_MASK, 1916 (sol->dw[offsetof(struct amap_sol_cqe, cid) / 1917 32] & CQE_CID_MASK)); 1918 iscsi_conn_failure(beiscsi_conn->conn, 1919 ISCSI_ERR_CONN_FAILED); 1920 break; 1921 case CXN_KILLED_RST_SENT: 1922 case CXN_KILLED_RST_RCVD: 1923 SE_DEBUG(DBG_LVL_1, "CQ Error %d, reset" 1924 "received/sent on CID 0x%x...\n", 1925 sol->dw[offsetof(struct amap_sol_cqe, code) / 1926 32] & CQE_CODE_MASK, 1927 (sol->dw[offsetof(struct amap_sol_cqe, cid) / 1928 32] & CQE_CID_MASK)); 1929 iscsi_conn_failure(beiscsi_conn->conn, 1930 ISCSI_ERR_CONN_FAILED); 1931 break; 1932 default: 1933 SE_DEBUG(DBG_LVL_1, "CQ Error Invalid code= %d " 1934 "received on CID 0x%x...\n", 1935 sol->dw[offsetof(struct amap_sol_cqe, code) / 1936 32] & CQE_CODE_MASK, 1937 (sol->dw[offsetof(struct amap_sol_cqe, cid) / 1938 32] & CQE_CID_MASK)); 1939 break; 1940 } 1941 1942 AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0); 1943 queue_tail_inc(cq); 1944 sol = queue_tail_node(cq); 1945 num_processed++; 1946 } 1947 1948 if (num_processed > 0) { 1949 tot_nump += num_processed; 1950 hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0); 1951 } 1952 return tot_nump; 1953} 1954 1955void beiscsi_process_all_cqs(struct work_struct *work) 1956{ 1957 unsigned long flags; 1958 struct hwi_controller *phwi_ctrlr; 1959 struct hwi_context_memory *phwi_context; 1960 struct be_eq_obj *pbe_eq; 1961 struct beiscsi_hba *phba = 1962 container_of(work, struct beiscsi_hba, work_cqs); 1963 1964 phwi_ctrlr = phba->phwi_ctrlr; 1965 phwi_context = phwi_ctrlr->phwi_ctxt; 1966 if (phba->msix_enabled) 1967 pbe_eq = &phwi_context->be_eq[phba->num_cpus]; 1968 else 1969 pbe_eq = &phwi_context->be_eq[0]; 1970 1971 if (phba->todo_mcc_cq) { 1972 spin_lock_irqsave(&phba->isr_lock, flags); 1973 phba->todo_mcc_cq = 0; 1974 spin_unlock_irqrestore(&phba->isr_lock, flags); 1975 beiscsi_process_mcc_isr(phba); 1976 } 1977 1978 if (phba->todo_cq) { 1979 spin_lock_irqsave(&phba->isr_lock, flags); 1980 phba->todo_cq = 0; 1981 spin_unlock_irqrestore(&phba->isr_lock, flags); 1982 beiscsi_process_cq(pbe_eq); 1983 } 1984} 1985 1986static int be_iopoll(struct blk_iopoll *iop, int budget) 1987{ 1988 static unsigned int ret; 1989 struct beiscsi_hba *phba; 1990 struct be_eq_obj *pbe_eq; 1991 1992 pbe_eq = container_of(iop, struct be_eq_obj, iopoll); 1993 ret = beiscsi_process_cq(pbe_eq); 1994 if (ret < budget) { 1995 phba = pbe_eq->phba; 1996 blk_iopoll_complete(iop); 1997 SE_DEBUG(DBG_LVL_8, "rearm pbe_eq->q.id =%d\n", pbe_eq->q.id); 1998 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); 1999 } 2000 return ret; 2001} 2002 2003static void 2004hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg, 2005 unsigned int num_sg, struct beiscsi_io_task *io_task) 2006{ 2007 struct iscsi_sge *psgl; 2008 unsigned int sg_len, index; 2009 unsigned int sge_len = 0; 2010 unsigned long long addr; 2011 struct scatterlist *l_sg; 2012 unsigned int offset; 2013 2014 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb, 2015 io_task->bhs_pa.u.a32.address_lo); 2016 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb, 2017 io_task->bhs_pa.u.a32.address_hi); 2018 2019 l_sg = sg; 2020 for (index = 0; (index < num_sg) && (index < 2); index++, 2021 sg = sg_next(sg)) { 2022 if (index == 0) { 2023 sg_len = sg_dma_len(sg); 2024 addr = (u64) sg_dma_address(sg); 2025 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb, 2026 ((u32)(addr & 0xFFFFFFFF))); 2027 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb, 2028 ((u32)(addr >> 32))); 2029 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb, 2030 sg_len); 2031 sge_len = sg_len; 2032 } else { 2033 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset, 2034 pwrb, sge_len); 2035 sg_len = sg_dma_len(sg); 2036 addr = (u64) sg_dma_address(sg); 2037 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb, 2038 ((u32)(addr & 0xFFFFFFFF))); 2039 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb, 2040 ((u32)(addr >> 32))); 2041 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb, 2042 sg_len); 2043 } 2044 } 2045 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; 2046 memset(psgl, 0, sizeof(*psgl) * BE2_SGE); 2047 2048 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2); 2049 2050 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2051 io_task->bhs_pa.u.a32.address_hi); 2052 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2053 io_task->bhs_pa.u.a32.address_lo); 2054 2055 if (num_sg == 1) { 2056 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 2057 1); 2058 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, 2059 0); 2060 } else if (num_sg == 2) { 2061 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 2062 0); 2063 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, 2064 1); 2065 } else { 2066 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 2067 0); 2068 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, 2069 0); 2070 } 2071 sg = l_sg; 2072 psgl++; 2073 psgl++; 2074 offset = 0; 2075 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) { 2076 sg_len = sg_dma_len(sg); 2077 addr = (u64) sg_dma_address(sg); 2078 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2079 (addr & 0xFFFFFFFF)); 2080 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2081 (addr >> 32)); 2082 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len); 2083 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset); 2084 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); 2085 offset += sg_len; 2086 } 2087 psgl--; 2088 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); 2089} 2090 2091static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task) 2092{ 2093 struct iscsi_sge *psgl; 2094 unsigned long long addr; 2095 struct beiscsi_io_task *io_task = task->dd_data; 2096 struct beiscsi_conn *beiscsi_conn = io_task->conn; 2097 struct beiscsi_hba *phba = beiscsi_conn->phba; 2098 2099 io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2; 2100 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb, 2101 io_task->bhs_pa.u.a32.address_lo); 2102 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb, 2103 io_task->bhs_pa.u.a32.address_hi); 2104 2105 if (task->data) { 2106 if (task->data_count) { 2107 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1); 2108 addr = (u64) pci_map_single(phba->pcidev, 2109 task->data, 2110 task->data_count, 1); 2111 } else { 2112 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); 2113 addr = 0; 2114 } 2115 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb, 2116 ((u32)(addr & 0xFFFFFFFF))); 2117 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb, 2118 ((u32)(addr >> 32))); 2119 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb, 2120 task->data_count); 2121 2122 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1); 2123 } else { 2124 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); 2125 addr = 0; 2126 } 2127 2128 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; 2129 2130 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len); 2131 2132 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2133 io_task->bhs_pa.u.a32.address_hi); 2134 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2135 io_task->bhs_pa.u.a32.address_lo); 2136 if (task->data) { 2137 psgl++; 2138 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0); 2139 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0); 2140 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0); 2141 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0); 2142 AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0); 2143 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); 2144 2145 psgl++; 2146 if (task->data) { 2147 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2148 ((u32)(addr & 0xFFFFFFFF))); 2149 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2150 ((u32)(addr >> 32))); 2151 } 2152 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106); 2153 } 2154 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); 2155} 2156 2157static void beiscsi_find_mem_req(struct beiscsi_hba *phba) 2158{ 2159 unsigned int num_cq_pages, num_async_pdu_buf_pages; 2160 unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn; 2161 unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages; 2162 2163 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \ 2164 sizeof(struct sol_cqe)); 2165 num_async_pdu_buf_pages = 2166 PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \ 2167 phba->params.defpdu_hdr_sz); 2168 num_async_pdu_buf_sgl_pages = 2169 PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \ 2170 sizeof(struct phys_addr)); 2171 num_async_pdu_data_pages = 2172 PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \ 2173 phba->params.defpdu_data_sz); 2174 num_async_pdu_data_sgl_pages = 2175 PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \ 2176 sizeof(struct phys_addr)); 2177 2178 phba->params.hwi_ws_sz = sizeof(struct hwi_controller); 2179 2180 phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 * 2181 BE_ISCSI_PDU_HEADER_SIZE; 2182 phba->mem_req[HWI_MEM_ADDN_CONTEXT] = 2183 sizeof(struct hwi_context_memory); 2184 2185 2186 phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb) 2187 * (phba->params.wrbs_per_cxn) 2188 * phba->params.cxns_per_ctrl; 2189 wrb_sz_per_cxn = sizeof(struct wrb_handle) * 2190 (phba->params.wrbs_per_cxn); 2191 phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) * 2192 phba->params.cxns_per_ctrl); 2193 2194 phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) * 2195 phba->params.icds_per_ctrl; 2196 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) * 2197 phba->params.num_sge_per_io * phba->params.icds_per_ctrl; 2198 2199 phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] = 2200 num_async_pdu_buf_pages * PAGE_SIZE; 2201 phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] = 2202 num_async_pdu_data_pages * PAGE_SIZE; 2203 phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] = 2204 num_async_pdu_buf_sgl_pages * PAGE_SIZE; 2205 phba->mem_req[HWI_MEM_ASYNC_DATA_RING] = 2206 num_async_pdu_data_sgl_pages * PAGE_SIZE; 2207 phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] = 2208 phba->params.asyncpdus_per_ctrl * 2209 sizeof(struct async_pdu_handle); 2210 phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] = 2211 phba->params.asyncpdus_per_ctrl * 2212 sizeof(struct async_pdu_handle); 2213 phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] = 2214 sizeof(struct hwi_async_pdu_context) + 2215 (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry)); 2216} 2217 2218static int beiscsi_alloc_mem(struct beiscsi_hba *phba) 2219{ 2220 struct be_mem_descriptor *mem_descr; 2221 dma_addr_t bus_add; 2222 struct mem_array *mem_arr, *mem_arr_orig; 2223 unsigned int i, j, alloc_size, curr_alloc_size; 2224 2225 phba->phwi_ctrlr = kmalloc(phba->params.hwi_ws_sz, GFP_KERNEL); 2226 if (!phba->phwi_ctrlr) 2227 return -ENOMEM; 2228 2229 phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr), 2230 GFP_KERNEL); 2231 if (!phba->init_mem) { 2232 kfree(phba->phwi_ctrlr); 2233 return -ENOMEM; 2234 } 2235 2236 mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT, 2237 GFP_KERNEL); 2238 if (!mem_arr_orig) { 2239 kfree(phba->init_mem); 2240 kfree(phba->phwi_ctrlr); 2241 return -ENOMEM; 2242 } 2243 2244 mem_descr = phba->init_mem; 2245 for (i = 0; i < SE_MEM_MAX; i++) { 2246 j = 0; 2247 mem_arr = mem_arr_orig; 2248 alloc_size = phba->mem_req[i]; 2249 memset(mem_arr, 0, sizeof(struct mem_array) * 2250 BEISCSI_MAX_FRAGS_INIT); 2251 curr_alloc_size = min(be_max_phys_size * 1024, alloc_size); 2252 do { 2253 mem_arr->virtual_address = pci_alloc_consistent( 2254 phba->pcidev, 2255 curr_alloc_size, 2256 &bus_add); 2257 if (!mem_arr->virtual_address) { 2258 if (curr_alloc_size <= BE_MIN_MEM_SIZE) 2259 goto free_mem; 2260 if (curr_alloc_size - 2261 rounddown_pow_of_two(curr_alloc_size)) 2262 curr_alloc_size = rounddown_pow_of_two 2263 (curr_alloc_size); 2264 else 2265 curr_alloc_size = curr_alloc_size / 2; 2266 } else { 2267 mem_arr->bus_address.u. 2268 a64.address = (__u64) bus_add; 2269 mem_arr->size = curr_alloc_size; 2270 alloc_size -= curr_alloc_size; 2271 curr_alloc_size = min(be_max_phys_size * 2272 1024, alloc_size); 2273 j++; 2274 mem_arr++; 2275 } 2276 } while (alloc_size); 2277 mem_descr->num_elements = j; 2278 mem_descr->size_in_bytes = phba->mem_req[i]; 2279 mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j, 2280 GFP_KERNEL); 2281 if (!mem_descr->mem_array) 2282 goto free_mem; 2283 2284 memcpy(mem_descr->mem_array, mem_arr_orig, 2285 sizeof(struct mem_array) * j); 2286 mem_descr++; 2287 } 2288 kfree(mem_arr_orig); 2289 return 0; 2290free_mem: 2291 mem_descr->num_elements = j; 2292 while ((i) || (j)) { 2293 for (j = mem_descr->num_elements; j > 0; j--) { 2294 pci_free_consistent(phba->pcidev, 2295 mem_descr->mem_array[j - 1].size, 2296 mem_descr->mem_array[j - 1]. 2297 virtual_address, 2298 (unsigned long)mem_descr-> 2299 mem_array[j - 1]. 2300 bus_address.u.a64.address); 2301 } 2302 if (i) { 2303 i--; 2304 kfree(mem_descr->mem_array); 2305 mem_descr--; 2306 } 2307 } 2308 kfree(mem_arr_orig); 2309 kfree(phba->init_mem); 2310 kfree(phba->phwi_ctrlr); 2311 return -ENOMEM; 2312} 2313 2314static int beiscsi_get_memory(struct beiscsi_hba *phba) 2315{ 2316 beiscsi_find_mem_req(phba); 2317 return beiscsi_alloc_mem(phba); 2318} 2319 2320static void iscsi_init_global_templates(struct beiscsi_hba *phba) 2321{ 2322 struct pdu_data_out *pdata_out; 2323 struct pdu_nop_out *pnop_out; 2324 struct be_mem_descriptor *mem_descr; 2325 2326 mem_descr = phba->init_mem; 2327 mem_descr += ISCSI_MEM_GLOBAL_HEADER; 2328 pdata_out = 2329 (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address; 2330 memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE); 2331 2332 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out, 2333 IIOC_SCSI_DATA); 2334 2335 pnop_out = 2336 (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0]. 2337 virtual_address + BE_ISCSI_PDU_HEADER_SIZE); 2338 2339 memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE); 2340 AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF); 2341 AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1); 2342 AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0); 2343} 2344 2345static void beiscsi_init_wrb_handle(struct beiscsi_hba *phba) 2346{ 2347 struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb; 2348 struct wrb_handle *pwrb_handle; 2349 struct hwi_controller *phwi_ctrlr; 2350 struct hwi_wrb_context *pwrb_context; 2351 struct iscsi_wrb *pwrb; 2352 unsigned int num_cxn_wrbh; 2353 unsigned int num_cxn_wrb, j, idx, index; 2354 2355 mem_descr_wrbh = phba->init_mem; 2356 mem_descr_wrbh += HWI_MEM_WRBH; 2357 2358 mem_descr_wrb = phba->init_mem; 2359 mem_descr_wrb += HWI_MEM_WRB; 2360 2361 idx = 0; 2362 pwrb_handle = mem_descr_wrbh->mem_array[idx].virtual_address; 2363 num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) / 2364 ((sizeof(struct wrb_handle)) * 2365 phba->params.wrbs_per_cxn)); 2366 phwi_ctrlr = phba->phwi_ctrlr; 2367 2368 for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) { 2369 pwrb_context = &phwi_ctrlr->wrb_context[index]; 2370 pwrb_context->pwrb_handle_base = 2371 kzalloc(sizeof(struct wrb_handle *) * 2372 phba->params.wrbs_per_cxn, GFP_KERNEL); 2373 pwrb_context->pwrb_handle_basestd = 2374 kzalloc(sizeof(struct wrb_handle *) * 2375 phba->params.wrbs_per_cxn, GFP_KERNEL); 2376 if (num_cxn_wrbh) { 2377 pwrb_context->alloc_index = 0; 2378 pwrb_context->wrb_handles_available = 0; 2379 for (j = 0; j < phba->params.wrbs_per_cxn; j++) { 2380 pwrb_context->pwrb_handle_base[j] = pwrb_handle; 2381 pwrb_context->pwrb_handle_basestd[j] = 2382 pwrb_handle; 2383 pwrb_context->wrb_handles_available++; 2384 pwrb_handle->wrb_index = j; 2385 pwrb_handle++; 2386 } 2387 pwrb_context->free_index = 0; 2388 num_cxn_wrbh--; 2389 } else { 2390 idx++; 2391 pwrb_handle = 2392 mem_descr_wrbh->mem_array[idx].virtual_address; 2393 num_cxn_wrbh = 2394 ((mem_descr_wrbh->mem_array[idx].size) / 2395 ((sizeof(struct wrb_handle)) * 2396 phba->params.wrbs_per_cxn)); 2397 pwrb_context->alloc_index = 0; 2398 for (j = 0; j < phba->params.wrbs_per_cxn; j++) { 2399 pwrb_context->pwrb_handle_base[j] = pwrb_handle; 2400 pwrb_context->pwrb_handle_basestd[j] = 2401 pwrb_handle; 2402 pwrb_context->wrb_handles_available++; 2403 pwrb_handle->wrb_index = j; 2404 pwrb_handle++; 2405 } 2406 pwrb_context->free_index = 0; 2407 num_cxn_wrbh--; 2408 } 2409 } 2410 idx = 0; 2411 pwrb = mem_descr_wrb->mem_array[idx].virtual_address; 2412 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) / 2413 ((sizeof(struct iscsi_wrb) * 2414 phba->params.wrbs_per_cxn)); 2415 for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) { 2416 pwrb_context = &phwi_ctrlr->wrb_context[index]; 2417 if (num_cxn_wrb) { 2418 for (j = 0; j < phba->params.wrbs_per_cxn; j++) { 2419 pwrb_handle = pwrb_context->pwrb_handle_base[j]; 2420 pwrb_handle->pwrb = pwrb; 2421 pwrb++; 2422 } 2423 num_cxn_wrb--; 2424 } else { 2425 idx++; 2426 pwrb = mem_descr_wrb->mem_array[idx].virtual_address; 2427 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) / 2428 ((sizeof(struct iscsi_wrb) * 2429 phba->params.wrbs_per_cxn)); 2430 for (j = 0; j < phba->params.wrbs_per_cxn; j++) { 2431 pwrb_handle = pwrb_context->pwrb_handle_base[j]; 2432 pwrb_handle->pwrb = pwrb; 2433 pwrb++; 2434 } 2435 num_cxn_wrb--; 2436 } 2437 } 2438} 2439 2440static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba) 2441{ 2442 struct hwi_controller *phwi_ctrlr; 2443 struct hba_parameters *p = &phba->params; 2444 struct hwi_async_pdu_context *pasync_ctx; 2445 struct async_pdu_handle *pasync_header_h, *pasync_data_h; 2446 unsigned int index; 2447 struct be_mem_descriptor *mem_descr; 2448 2449 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2450 mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT; 2451 2452 phwi_ctrlr = phba->phwi_ctrlr; 2453 phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *) 2454 mem_descr->mem_array[0].virtual_address; 2455 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx; 2456 memset(pasync_ctx, 0, sizeof(*pasync_ctx)); 2457 2458 pasync_ctx->async_header.num_entries = p->asyncpdus_per_ctrl; 2459 pasync_ctx->async_header.buffer_size = p->defpdu_hdr_sz; 2460 pasync_ctx->async_data.buffer_size = p->defpdu_data_sz; 2461 pasync_ctx->async_data.num_entries = p->asyncpdus_per_ctrl; 2462 2463 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2464 mem_descr += HWI_MEM_ASYNC_HEADER_BUF; 2465 if (mem_descr->mem_array[0].virtual_address) { 2466 SE_DEBUG(DBG_LVL_8, 2467 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_BUF" 2468 "va=%p\n", mem_descr->mem_array[0].virtual_address); 2469 } else 2470 shost_printk(KERN_WARNING, phba->shost, 2471 "No Virtual address\n"); 2472 2473 pasync_ctx->async_header.va_base = 2474 mem_descr->mem_array[0].virtual_address; 2475 2476 pasync_ctx->async_header.pa_base.u.a64.address = 2477 mem_descr->mem_array[0].bus_address.u.a64.address; 2478 2479 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2480 mem_descr += HWI_MEM_ASYNC_HEADER_RING; 2481 if (mem_descr->mem_array[0].virtual_address) { 2482 SE_DEBUG(DBG_LVL_8, 2483 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_RING" 2484 "va=%p\n", mem_descr->mem_array[0].virtual_address); 2485 } else 2486 shost_printk(KERN_WARNING, phba->shost, 2487 "No Virtual address\n"); 2488 pasync_ctx->async_header.ring_base = 2489 mem_descr->mem_array[0].virtual_address; 2490 2491 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2492 mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE; 2493 if (mem_descr->mem_array[0].virtual_address) { 2494 SE_DEBUG(DBG_LVL_8, 2495 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_HANDLE" 2496 "va=%p\n", mem_descr->mem_array[0].virtual_address); 2497 } else 2498 shost_printk(KERN_WARNING, phba->shost, 2499 "No Virtual address\n"); 2500 2501 pasync_ctx->async_header.handle_base = 2502 mem_descr->mem_array[0].virtual_address; 2503 pasync_ctx->async_header.writables = 0; 2504 INIT_LIST_HEAD(&pasync_ctx->async_header.free_list); 2505 2506 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2507 mem_descr += HWI_MEM_ASYNC_DATA_BUF; 2508 if (mem_descr->mem_array[0].virtual_address) { 2509 SE_DEBUG(DBG_LVL_8, 2510 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_DATA_BUF" 2511 "va=%p\n", mem_descr->mem_array[0].virtual_address); 2512 } else 2513 shost_printk(KERN_WARNING, phba->shost, 2514 "No Virtual address\n"); 2515 pasync_ctx->async_data.va_base = 2516 mem_descr->mem_array[0].virtual_address; 2517 pasync_ctx->async_data.pa_base.u.a64.address = 2518 mem_descr->mem_array[0].bus_address.u.a64.address; 2519 2520 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2521 mem_descr += HWI_MEM_ASYNC_DATA_RING; 2522 if (mem_descr->mem_array[0].virtual_address) { 2523 SE_DEBUG(DBG_LVL_8, 2524 "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_DATA_RING" 2525 "va=%p\n", mem_descr->mem_array[0].virtual_address); 2526 } else 2527 shost_printk(KERN_WARNING, phba->shost, 2528 "No Virtual address\n"); 2529 2530 pasync_ctx->async_data.ring_base = 2531 mem_descr->mem_array[0].virtual_address; 2532 2533 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2534 mem_descr += HWI_MEM_ASYNC_DATA_HANDLE; 2535 if (!mem_descr->mem_array[0].virtual_address) 2536 shost_printk(KERN_WARNING, phba->shost, 2537 "No Virtual address\n"); 2538 2539 pasync_ctx->async_data.handle_base = 2540 mem_descr->mem_array[0].virtual_address; 2541 pasync_ctx->async_data.writables = 0; 2542 INIT_LIST_HEAD(&pasync_ctx->async_data.free_list); 2543 2544 pasync_header_h = 2545 (struct async_pdu_handle *)pasync_ctx->async_header.handle_base; 2546 pasync_data_h = 2547 (struct async_pdu_handle *)pasync_ctx->async_data.handle_base; 2548 2549 for (index = 0; index < p->asyncpdus_per_ctrl; index++) { 2550 pasync_header_h->cri = -1; 2551 pasync_header_h->index = (char)index; 2552 INIT_LIST_HEAD(&pasync_header_h->link); 2553 pasync_header_h->pbuffer = 2554 (void *)((unsigned long) 2555 (pasync_ctx->async_header.va_base) + 2556 (p->defpdu_hdr_sz * index)); 2557 2558 pasync_header_h->pa.u.a64.address = 2559 pasync_ctx->async_header.pa_base.u.a64.address + 2560 (p->defpdu_hdr_sz * index); 2561 2562 list_add_tail(&pasync_header_h->link, 2563 &pasync_ctx->async_header.free_list); 2564 pasync_header_h++; 2565 pasync_ctx->async_header.free_entries++; 2566 pasync_ctx->async_header.writables++; 2567 2568 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list); 2569 INIT_LIST_HEAD(&pasync_ctx->async_entry[index]. 2570 header_busy_list); 2571 pasync_data_h->cri = -1; 2572 pasync_data_h->index = (char)index; 2573 INIT_LIST_HEAD(&pasync_data_h->link); 2574 pasync_data_h->pbuffer = 2575 (void *)((unsigned long) 2576 (pasync_ctx->async_data.va_base) + 2577 (p->defpdu_data_sz * index)); 2578 2579 pasync_data_h->pa.u.a64.address = 2580 pasync_ctx->async_data.pa_base.u.a64.address + 2581 (p->defpdu_data_sz * index); 2582 2583 list_add_tail(&pasync_data_h->link, 2584 &pasync_ctx->async_data.free_list); 2585 pasync_data_h++; 2586 pasync_ctx->async_data.free_entries++; 2587 pasync_ctx->async_data.writables++; 2588 2589 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list); 2590 } 2591 2592 pasync_ctx->async_header.host_write_ptr = 0; 2593 pasync_ctx->async_header.ep_read_ptr = -1; 2594 pasync_ctx->async_data.host_write_ptr = 0; 2595 pasync_ctx->async_data.ep_read_ptr = -1; 2596} 2597 2598static int 2599be_sgl_create_contiguous(void *virtual_address, 2600 u64 physical_address, u32 length, 2601 struct be_dma_mem *sgl) 2602{ 2603 WARN_ON(!virtual_address); 2604 WARN_ON(!physical_address); 2605 WARN_ON(!length > 0); 2606 WARN_ON(!sgl); 2607 2608 sgl->va = virtual_address; 2609 sgl->dma = (unsigned long)physical_address; 2610 sgl->size = length; 2611 2612 return 0; 2613} 2614 2615static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl) 2616{ 2617 memset(sgl, 0, sizeof(*sgl)); 2618} 2619 2620static void 2621hwi_build_be_sgl_arr(struct beiscsi_hba *phba, 2622 struct mem_array *pmem, struct be_dma_mem *sgl) 2623{ 2624 if (sgl->va) 2625 be_sgl_destroy_contiguous(sgl); 2626 2627 be_sgl_create_contiguous(pmem->virtual_address, 2628 pmem->bus_address.u.a64.address, 2629 pmem->size, sgl); 2630} 2631 2632static void 2633hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba, 2634 struct mem_array *pmem, struct be_dma_mem *sgl) 2635{ 2636 if (sgl->va) 2637 be_sgl_destroy_contiguous(sgl); 2638 2639 be_sgl_create_contiguous((unsigned char *)pmem->virtual_address, 2640 pmem->bus_address.u.a64.address, 2641 pmem->size, sgl); 2642} 2643 2644static int be_fill_queue(struct be_queue_info *q, 2645 u16 len, u16 entry_size, void *vaddress) 2646{ 2647 struct be_dma_mem *mem = &q->dma_mem; 2648 2649 memset(q, 0, sizeof(*q)); 2650 q->len = len; 2651 q->entry_size = entry_size; 2652 mem->size = len * entry_size; 2653 mem->va = vaddress; 2654 if (!mem->va) 2655 return -ENOMEM; 2656 memset(mem->va, 0, mem->size); 2657 return 0; 2658} 2659 2660static int beiscsi_create_eqs(struct beiscsi_hba *phba, 2661 struct hwi_context_memory *phwi_context) 2662{ 2663 unsigned int i, num_eq_pages; 2664 int ret, eq_for_mcc; 2665 struct be_queue_info *eq; 2666 struct be_dma_mem *mem; 2667 void *eq_vaddress; 2668 dma_addr_t paddr; 2669 2670 num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \ 2671 sizeof(struct be_eq_entry)); 2672 2673 if (phba->msix_enabled) 2674 eq_for_mcc = 1; 2675 else 2676 eq_for_mcc = 0; 2677 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { 2678 eq = &phwi_context->be_eq[i].q; 2679 mem = &eq->dma_mem; 2680 phwi_context->be_eq[i].phba = phba; 2681 eq_vaddress = pci_alloc_consistent(phba->pcidev, 2682 num_eq_pages * PAGE_SIZE, 2683 &paddr); 2684 if (!eq_vaddress) 2685 goto create_eq_error; 2686 2687 mem->va = eq_vaddress; 2688 ret = be_fill_queue(eq, phba->params.num_eq_entries, 2689 sizeof(struct be_eq_entry), eq_vaddress); 2690 if (ret) { 2691 shost_printk(KERN_ERR, phba->shost, 2692 "be_fill_queue Failed for EQ\n"); 2693 goto create_eq_error; 2694 } 2695 2696 mem->dma = paddr; 2697 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq, 2698 phwi_context->cur_eqd); 2699 if (ret) { 2700 shost_printk(KERN_ERR, phba->shost, 2701 "beiscsi_cmd_eq_create" 2702 "Failedfor EQ\n"); 2703 goto create_eq_error; 2704 } 2705 SE_DEBUG(DBG_LVL_8, "eqid = %d\n", phwi_context->be_eq[i].q.id); 2706 } 2707 return 0; 2708create_eq_error: 2709 for (i = 0; i < (phba->num_cpus + 1); i++) { 2710 eq = &phwi_context->be_eq[i].q; 2711 mem = &eq->dma_mem; 2712 if (mem->va) 2713 pci_free_consistent(phba->pcidev, num_eq_pages 2714 * PAGE_SIZE, 2715 mem->va, mem->dma); 2716 } 2717 return ret; 2718} 2719 2720static int beiscsi_create_cqs(struct beiscsi_hba *phba, 2721 struct hwi_context_memory *phwi_context) 2722{ 2723 unsigned int i, num_cq_pages; 2724 int ret; 2725 struct be_queue_info *cq, *eq; 2726 struct be_dma_mem *mem; 2727 struct be_eq_obj *pbe_eq; 2728 void *cq_vaddress; 2729 dma_addr_t paddr; 2730 2731 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \ 2732 sizeof(struct sol_cqe)); 2733 2734 for (i = 0; i < phba->num_cpus; i++) { 2735 cq = &phwi_context->be_cq[i]; 2736 eq = &phwi_context->be_eq[i].q; 2737 pbe_eq = &phwi_context->be_eq[i]; 2738 pbe_eq->cq = cq; 2739 pbe_eq->phba = phba; 2740 mem = &cq->dma_mem; 2741 cq_vaddress = pci_alloc_consistent(phba->pcidev, 2742 num_cq_pages * PAGE_SIZE, 2743 &paddr); 2744 if (!cq_vaddress) 2745 goto create_cq_error; 2746 ret = be_fill_queue(cq, phba->params.num_cq_entries, 2747 sizeof(struct sol_cqe), cq_vaddress); 2748 if (ret) { 2749 shost_printk(KERN_ERR, phba->shost, 2750 "be_fill_queue Failed for ISCSI CQ\n"); 2751 goto create_cq_error; 2752 } 2753 2754 mem->dma = paddr; 2755 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false, 2756 false, 0); 2757 if (ret) { 2758 shost_printk(KERN_ERR, phba->shost, 2759 "beiscsi_cmd_eq_create" 2760 "Failed for ISCSI CQ\n"); 2761 goto create_cq_error; 2762 } 2763 SE_DEBUG(DBG_LVL_8, "iscsi cq_id is %d for eq_id %d\n", 2764 cq->id, eq->id); 2765 SE_DEBUG(DBG_LVL_8, "ISCSI CQ CREATED\n"); 2766 } 2767 return 0; 2768 2769create_cq_error: 2770 for (i = 0; i < phba->num_cpus; i++) { 2771 cq = &phwi_context->be_cq[i]; 2772 mem = &cq->dma_mem; 2773 if (mem->va) 2774 pci_free_consistent(phba->pcidev, num_cq_pages 2775 * PAGE_SIZE, 2776 mem->va, mem->dma); 2777 } 2778 return ret; 2779 2780} 2781 2782static int 2783beiscsi_create_def_hdr(struct beiscsi_hba *phba, 2784 struct hwi_context_memory *phwi_context, 2785 struct hwi_controller *phwi_ctrlr, 2786 unsigned int def_pdu_ring_sz) 2787{ 2788 unsigned int idx; 2789 int ret; 2790 struct be_queue_info *dq, *cq; 2791 struct be_dma_mem *mem; 2792 struct be_mem_descriptor *mem_descr; 2793 void *dq_vaddress; 2794 2795 idx = 0; 2796 dq = &phwi_context->be_def_hdrq; 2797 cq = &phwi_context->be_cq[0]; 2798 mem = &dq->dma_mem; 2799 mem_descr = phba->init_mem; 2800 mem_descr += HWI_MEM_ASYNC_HEADER_RING; 2801 dq_vaddress = mem_descr->mem_array[idx].virtual_address; 2802 ret = be_fill_queue(dq, mem_descr->mem_array[0].size / 2803 sizeof(struct phys_addr), 2804 sizeof(struct phys_addr), dq_vaddress); 2805 if (ret) { 2806 shost_printk(KERN_ERR, phba->shost, 2807 "be_fill_queue Failed for DEF PDU HDR\n"); 2808 return ret; 2809 } 2810 mem->dma = (unsigned long)mem_descr->mem_array[idx]. 2811 bus_address.u.a64.address; 2812 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq, 2813 def_pdu_ring_sz, 2814 phba->params.defpdu_hdr_sz); 2815 if (ret) { 2816 shost_printk(KERN_ERR, phba->shost, 2817 "be_cmd_create_default_pdu_queue Failed DEFHDR\n"); 2818 return ret; 2819 } 2820 phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id; 2821 SE_DEBUG(DBG_LVL_8, "iscsi def pdu id is %d\n", 2822 phwi_context->be_def_hdrq.id); 2823 hwi_post_async_buffers(phba, 1); 2824 return 0; 2825} 2826 2827static int 2828beiscsi_create_def_data(struct beiscsi_hba *phba, 2829 struct hwi_context_memory *phwi_context, 2830 struct hwi_controller *phwi_ctrlr, 2831 unsigned int def_pdu_ring_sz) 2832{ 2833 unsigned int idx; 2834 int ret; 2835 struct be_queue_info *dataq, *cq; 2836 struct be_dma_mem *mem; 2837 struct be_mem_descriptor *mem_descr; 2838 void *dq_vaddress; 2839 2840 idx = 0; 2841 dataq = &phwi_context->be_def_dataq; 2842 cq = &phwi_context->be_cq[0]; 2843 mem = &dataq->dma_mem; 2844 mem_descr = phba->init_mem; 2845 mem_descr += HWI_MEM_ASYNC_DATA_RING; 2846 dq_vaddress = mem_descr->mem_array[idx].virtual_address; 2847 ret = be_fill_queue(dataq, mem_descr->mem_array[0].size / 2848 sizeof(struct phys_addr), 2849 sizeof(struct phys_addr), dq_vaddress); 2850 if (ret) { 2851 shost_printk(KERN_ERR, phba->shost, 2852 "be_fill_queue Failed for DEF PDU DATA\n"); 2853 return ret; 2854 } 2855 mem->dma = (unsigned long)mem_descr->mem_array[idx]. 2856 bus_address.u.a64.address; 2857 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq, 2858 def_pdu_ring_sz, 2859 phba->params.defpdu_data_sz); 2860 if (ret) { 2861 shost_printk(KERN_ERR, phba->shost, 2862 "be_cmd_create_default_pdu_queue Failed" 2863 " for DEF PDU DATA\n"); 2864 return ret; 2865 } 2866 phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id; 2867 SE_DEBUG(DBG_LVL_8, "iscsi def data id is %d\n", 2868 phwi_context->be_def_dataq.id); 2869 hwi_post_async_buffers(phba, 0); 2870 SE_DEBUG(DBG_LVL_8, "DEFAULT PDU DATA RING CREATED\n"); 2871 return 0; 2872} 2873 2874static int 2875beiscsi_post_pages(struct beiscsi_hba *phba) 2876{ 2877 struct be_mem_descriptor *mem_descr; 2878 struct mem_array *pm_arr; 2879 unsigned int page_offset, i; 2880 struct be_dma_mem sgl; 2881 int status; 2882 2883 mem_descr = phba->init_mem; 2884 mem_descr += HWI_MEM_SGE; 2885 pm_arr = mem_descr->mem_array; 2886 2887 page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io * 2888 phba->fw_config.iscsi_icd_start) / PAGE_SIZE; 2889 for (i = 0; i < mem_descr->num_elements; i++) { 2890 hwi_build_be_sgl_arr(phba, pm_arr, &sgl); 2891 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl, 2892 page_offset, 2893 (pm_arr->size / PAGE_SIZE)); 2894 page_offset += pm_arr->size / PAGE_SIZE; 2895 if (status != 0) { 2896 shost_printk(KERN_ERR, phba->shost, 2897 "post sgl failed.\n"); 2898 return status; 2899 } 2900 pm_arr++; 2901 } 2902 SE_DEBUG(DBG_LVL_8, "POSTED PAGES\n"); 2903 return 0; 2904} 2905 2906static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q) 2907{ 2908 struct be_dma_mem *mem = &q->dma_mem; 2909 if (mem->va) 2910 pci_free_consistent(phba->pcidev, mem->size, 2911 mem->va, mem->dma); 2912} 2913 2914static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q, 2915 u16 len, u16 entry_size) 2916{ 2917 struct be_dma_mem *mem = &q->dma_mem; 2918 2919 memset(q, 0, sizeof(*q)); 2920 q->len = len; 2921 q->entry_size = entry_size; 2922 mem->size = len * entry_size; 2923 mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma); 2924 if (!mem->va) 2925 return -ENOMEM; 2926 memset(mem->va, 0, mem->size); 2927 return 0; 2928} 2929 2930static int 2931beiscsi_create_wrb_rings(struct beiscsi_hba *phba, 2932 struct hwi_context_memory *phwi_context, 2933 struct hwi_controller *phwi_ctrlr) 2934{ 2935 unsigned int wrb_mem_index, offset, size, num_wrb_rings; 2936 u64 pa_addr_lo; 2937 unsigned int idx, num, i; 2938 struct mem_array *pwrb_arr; 2939 void *wrb_vaddr; 2940 struct be_dma_mem sgl; 2941 struct be_mem_descriptor *mem_descr; 2942 int status; 2943 2944 idx = 0; 2945 mem_descr = phba->init_mem; 2946 mem_descr += HWI_MEM_WRB; 2947 pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl, 2948 GFP_KERNEL); 2949 if (!pwrb_arr) { 2950 shost_printk(KERN_ERR, phba->shost, 2951 "Memory alloc failed in create wrb ring.\n"); 2952 return -ENOMEM; 2953 } 2954 wrb_vaddr = mem_descr->mem_array[idx].virtual_address; 2955 pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address; 2956 num_wrb_rings = mem_descr->mem_array[idx].size / 2957 (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb)); 2958 2959 for (num = 0; num < phba->params.cxns_per_ctrl; num++) { 2960 if (num_wrb_rings) { 2961 pwrb_arr[num].virtual_address = wrb_vaddr; 2962 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo; 2963 pwrb_arr[num].size = phba->params.wrbs_per_cxn * 2964 sizeof(struct iscsi_wrb); 2965 wrb_vaddr += pwrb_arr[num].size; 2966 pa_addr_lo += pwrb_arr[num].size; 2967 num_wrb_rings--; 2968 } else { 2969 idx++; 2970 wrb_vaddr = mem_descr->mem_array[idx].virtual_address; 2971 pa_addr_lo = mem_descr->mem_array[idx].\ 2972 bus_address.u.a64.address; 2973 num_wrb_rings = mem_descr->mem_array[idx].size / 2974 (phba->params.wrbs_per_cxn * 2975 sizeof(struct iscsi_wrb)); 2976 pwrb_arr[num].virtual_address = wrb_vaddr; 2977 pwrb_arr[num].bus_address.u.a64.address\ 2978 = pa_addr_lo; 2979 pwrb_arr[num].size = phba->params.wrbs_per_cxn * 2980 sizeof(struct iscsi_wrb); 2981 wrb_vaddr += pwrb_arr[num].size; 2982 pa_addr_lo += pwrb_arr[num].size; 2983 num_wrb_rings--; 2984 } 2985 } 2986 for (i = 0; i < phba->params.cxns_per_ctrl; i++) { 2987 wrb_mem_index = 0; 2988 offset = 0; 2989 size = 0; 2990 2991 hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl); 2992 status = be_cmd_wrbq_create(&phba->ctrl, &sgl, 2993 &phwi_context->be_wrbq[i]); 2994 if (status != 0) { 2995 shost_printk(KERN_ERR, phba->shost, 2996 "wrbq create failed."); 2997 kfree(pwrb_arr); 2998 return status; 2999 } 3000 phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i]. 3001 id; 3002 } 3003 kfree(pwrb_arr); 3004 return 0; 3005} 3006 3007static void free_wrb_handles(struct beiscsi_hba *phba) 3008{ 3009 unsigned int index; 3010 struct hwi_controller *phwi_ctrlr; 3011 struct hwi_wrb_context *pwrb_context; 3012 3013 phwi_ctrlr = phba->phwi_ctrlr; 3014 for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) { 3015 pwrb_context = &phwi_ctrlr->wrb_context[index]; 3016 kfree(pwrb_context->pwrb_handle_base); 3017 kfree(pwrb_context->pwrb_handle_basestd); 3018 } 3019} 3020 3021static void be_mcc_queues_destroy(struct beiscsi_hba *phba) 3022{ 3023 struct be_queue_info *q; 3024 struct be_ctrl_info *ctrl = &phba->ctrl; 3025 3026 q = &phba->ctrl.mcc_obj.q; 3027 if (q->created) 3028 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ); 3029 be_queue_free(phba, q); 3030 3031 q = &phba->ctrl.mcc_obj.cq; 3032 if (q->created) 3033 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ); 3034 be_queue_free(phba, q); 3035} 3036 3037static void hwi_cleanup(struct beiscsi_hba *phba) 3038{ 3039 struct be_queue_info *q; 3040 struct be_ctrl_info *ctrl = &phba->ctrl; 3041 struct hwi_controller *phwi_ctrlr; 3042 struct hwi_context_memory *phwi_context; 3043 int i, eq_num; 3044 3045 phwi_ctrlr = phba->phwi_ctrlr; 3046 phwi_context = phwi_ctrlr->phwi_ctxt; 3047 for (i = 0; i < phba->params.cxns_per_ctrl; i++) { 3048 q = &phwi_context->be_wrbq[i]; 3049 if (q->created) 3050 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ); 3051 } 3052 free_wrb_handles(phba); 3053 3054 q = &phwi_context->be_def_hdrq; 3055 if (q->created) 3056 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ); 3057 3058 q = &phwi_context->be_def_dataq; 3059 if (q->created) 3060 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ); 3061 3062 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL); 3063 3064 for (i = 0; i < (phba->num_cpus); i++) { 3065 q = &phwi_context->be_cq[i]; 3066 if (q->created) 3067 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ); 3068 } 3069 if (phba->msix_enabled) 3070 eq_num = 1; 3071 else 3072 eq_num = 0; 3073 for (i = 0; i < (phba->num_cpus + eq_num); i++) { 3074 q = &phwi_context->be_eq[i].q; 3075 if (q->created) 3076 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ); 3077 } 3078 be_mcc_queues_destroy(phba); 3079} 3080 3081static int be_mcc_queues_create(struct beiscsi_hba *phba, 3082 struct hwi_context_memory *phwi_context) 3083{ 3084 struct be_queue_info *q, *cq; 3085 struct be_ctrl_info *ctrl = &phba->ctrl; 3086 3087 /* Alloc MCC compl queue */ 3088 cq = &phba->ctrl.mcc_obj.cq; 3089 if (be_queue_alloc(phba, cq, MCC_CQ_LEN, 3090 sizeof(struct be_mcc_compl))) 3091 goto err; 3092 /* Ask BE to create MCC compl queue; */ 3093 if (phba->msix_enabled) { 3094 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq 3095 [phba->num_cpus].q, false, true, 0)) 3096 goto mcc_cq_free; 3097 } else { 3098 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q, 3099 false, true, 0)) 3100 goto mcc_cq_free; 3101 } 3102 3103 /* Alloc MCC queue */ 3104 q = &phba->ctrl.mcc_obj.q; 3105 if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb))) 3106 goto mcc_cq_destroy; 3107 3108 /* Ask BE to create MCC queue */ 3109 if (beiscsi_cmd_mccq_create(phba, q, cq)) 3110 goto mcc_q_free; 3111 3112 return 0; 3113 3114mcc_q_free: 3115 be_queue_free(phba, q); 3116mcc_cq_destroy: 3117 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ); 3118mcc_cq_free: 3119 be_queue_free(phba, cq); 3120err: 3121 return -ENOMEM; 3122} 3123 3124static int find_num_cpus(void) 3125{ 3126 int num_cpus = 0; 3127 3128 num_cpus = num_online_cpus(); 3129 if (num_cpus >= MAX_CPUS) 3130 num_cpus = MAX_CPUS - 1; 3131 3132 SE_DEBUG(DBG_LVL_8, "num_cpus = %d\n", num_cpus); 3133 return num_cpus; 3134} 3135 3136static int hwi_init_port(struct beiscsi_hba *phba) 3137{ 3138 struct hwi_controller *phwi_ctrlr; 3139 struct hwi_context_memory *phwi_context; 3140 unsigned int def_pdu_ring_sz; 3141 struct be_ctrl_info *ctrl = &phba->ctrl; 3142 int status; 3143 3144 def_pdu_ring_sz = 3145 phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr); 3146 phwi_ctrlr = phba->phwi_ctrlr; 3147 phwi_context = phwi_ctrlr->phwi_ctxt; 3148 phwi_context->max_eqd = 0; 3149 phwi_context->min_eqd = 0; 3150 phwi_context->cur_eqd = 64; 3151 be_cmd_fw_initialize(&phba->ctrl); 3152 3153 status = beiscsi_create_eqs(phba, phwi_context); 3154 if (status != 0) { 3155 shost_printk(KERN_ERR, phba->shost, "EQ not created\n"); 3156 goto error; 3157 } 3158 3159 status = be_mcc_queues_create(phba, phwi_context); 3160 if (status != 0) 3161 goto error; 3162 3163 status = mgmt_check_supported_fw(ctrl, phba); 3164 if (status != 0) { 3165 shost_printk(KERN_ERR, phba->shost, 3166 "Unsupported fw version\n"); 3167 goto error; 3168 } 3169 3170 status = beiscsi_create_cqs(phba, phwi_context); 3171 if (status != 0) { 3172 shost_printk(KERN_ERR, phba->shost, "CQ not created\n"); 3173 goto error; 3174 } 3175 3176 status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr, 3177 def_pdu_ring_sz); 3178 if (status != 0) { 3179 shost_printk(KERN_ERR, phba->shost, 3180 "Default Header not created\n"); 3181 goto error; 3182 } 3183 3184 status = beiscsi_create_def_data(phba, phwi_context, 3185 phwi_ctrlr, def_pdu_ring_sz); 3186 if (status != 0) { 3187 shost_printk(KERN_ERR, phba->shost, 3188 "Default Data not created\n"); 3189 goto error; 3190 } 3191 3192 status = beiscsi_post_pages(phba); 3193 if (status != 0) { 3194 shost_printk(KERN_ERR, phba->shost, "Post SGL Pages Failed\n"); 3195 goto error; 3196 } 3197 3198 status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr); 3199 if (status != 0) { 3200 shost_printk(KERN_ERR, phba->shost, 3201 "WRB Rings not created\n"); 3202 goto error; 3203 } 3204 3205 SE_DEBUG(DBG_LVL_8, "hwi_init_port success\n"); 3206 return 0; 3207 3208error: 3209 shost_printk(KERN_ERR, phba->shost, "hwi_init_port failed"); 3210 hwi_cleanup(phba); 3211 return -ENOMEM; 3212} 3213 3214static int hwi_init_controller(struct beiscsi_hba *phba) 3215{ 3216 struct hwi_controller *phwi_ctrlr; 3217 3218 phwi_ctrlr = phba->phwi_ctrlr; 3219 if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) { 3220 phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba-> 3221 init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address; 3222 SE_DEBUG(DBG_LVL_8, " phwi_ctrlr->phwi_ctxt=%p\n", 3223 phwi_ctrlr->phwi_ctxt); 3224 } else { 3225 shost_printk(KERN_ERR, phba->shost, 3226 "HWI_MEM_ADDN_CONTEXT is more than one element." 3227 "Failing to load\n"); 3228 return -ENOMEM; 3229 } 3230 3231 iscsi_init_global_templates(phba); 3232 beiscsi_init_wrb_handle(phba); 3233 hwi_init_async_pdu_ctx(phba); 3234 if (hwi_init_port(phba) != 0) { 3235 shost_printk(KERN_ERR, phba->shost, 3236 "hwi_init_controller failed\n"); 3237 return -ENOMEM; 3238 } 3239 return 0; 3240} 3241 3242static void beiscsi_free_mem(struct beiscsi_hba *phba) 3243{ 3244 struct be_mem_descriptor *mem_descr; 3245 int i, j; 3246 3247 mem_descr = phba->init_mem; 3248 i = 0; 3249 j = 0; 3250 for (i = 0; i < SE_MEM_MAX; i++) { 3251 for (j = mem_descr->num_elements; j > 0; j--) { 3252 pci_free_consistent(phba->pcidev, 3253 mem_descr->mem_array[j - 1].size, 3254 mem_descr->mem_array[j - 1].virtual_address, 3255 (unsigned long)mem_descr->mem_array[j - 1]. 3256 bus_address.u.a64.address); 3257 } 3258 kfree(mem_descr->mem_array); 3259 mem_descr++; 3260 } 3261 kfree(phba->init_mem); 3262 kfree(phba->phwi_ctrlr); 3263} 3264 3265static int beiscsi_init_controller(struct beiscsi_hba *phba) 3266{ 3267 int ret = -ENOMEM; 3268 3269 ret = beiscsi_get_memory(phba); 3270 if (ret < 0) { 3271 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe -" 3272 "Failed in beiscsi_alloc_memory\n"); 3273 return ret; 3274 } 3275 3276 ret = hwi_init_controller(phba); 3277 if (ret) 3278 goto free_init; 3279 SE_DEBUG(DBG_LVL_8, "Return success from beiscsi_init_controller"); 3280 return 0; 3281 3282free_init: 3283 beiscsi_free_mem(phba); 3284 return -ENOMEM; 3285} 3286 3287static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba) 3288{ 3289 struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg; 3290 struct sgl_handle *psgl_handle; 3291 struct iscsi_sge *pfrag; 3292 unsigned int arr_index, i, idx; 3293 3294 phba->io_sgl_hndl_avbl = 0; 3295 phba->eh_sgl_hndl_avbl = 0; 3296 3297 mem_descr_sglh = phba->init_mem; 3298 mem_descr_sglh += HWI_MEM_SGLH; 3299 if (1 == mem_descr_sglh->num_elements) { 3300 phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) * 3301 phba->params.ios_per_ctrl, 3302 GFP_KERNEL); 3303 if (!phba->io_sgl_hndl_base) { 3304 shost_printk(KERN_ERR, phba->shost, 3305 "Mem Alloc Failed. Failing to load\n"); 3306 return -ENOMEM; 3307 } 3308 phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) * 3309 (phba->params.icds_per_ctrl - 3310 phba->params.ios_per_ctrl), 3311 GFP_KERNEL); 3312 if (!phba->eh_sgl_hndl_base) { 3313 kfree(phba->io_sgl_hndl_base); 3314 shost_printk(KERN_ERR, phba->shost, 3315 "Mem Alloc Failed. Failing to load\n"); 3316 return -ENOMEM; 3317 } 3318 } else { 3319 shost_printk(KERN_ERR, phba->shost, 3320 "HWI_MEM_SGLH is more than one element." 3321 "Failing to load\n"); 3322 return -ENOMEM; 3323 } 3324 3325 arr_index = 0; 3326 idx = 0; 3327 while (idx < mem_descr_sglh->num_elements) { 3328 psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address; 3329 3330 for (i = 0; i < (mem_descr_sglh->mem_array[idx].size / 3331 sizeof(struct sgl_handle)); i++) { 3332 if (arr_index < phba->params.ios_per_ctrl) { 3333 phba->io_sgl_hndl_base[arr_index] = psgl_handle; 3334 phba->io_sgl_hndl_avbl++; 3335 arr_index++; 3336 } else { 3337 phba->eh_sgl_hndl_base[arr_index - 3338 phba->params.ios_per_ctrl] = 3339 psgl_handle; 3340 arr_index++; 3341 phba->eh_sgl_hndl_avbl++; 3342 } 3343 psgl_handle++; 3344 } 3345 idx++; 3346 } 3347 SE_DEBUG(DBG_LVL_8, 3348 "phba->io_sgl_hndl_avbl=%d" 3349 "phba->eh_sgl_hndl_avbl=%d\n", 3350 phba->io_sgl_hndl_avbl, 3351 phba->eh_sgl_hndl_avbl); 3352 mem_descr_sg = phba->init_mem; 3353 mem_descr_sg += HWI_MEM_SGE; 3354 SE_DEBUG(DBG_LVL_8, "\n mem_descr_sg->num_elements=%d\n", 3355 mem_descr_sg->num_elements); 3356 arr_index = 0; 3357 idx = 0; 3358 while (idx < mem_descr_sg->num_elements) { 3359 pfrag = mem_descr_sg->mem_array[idx].virtual_address; 3360 3361 for (i = 0; 3362 i < (mem_descr_sg->mem_array[idx].size) / 3363 (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io); 3364 i++) { 3365 if (arr_index < phba->params.ios_per_ctrl) 3366 psgl_handle = phba->io_sgl_hndl_base[arr_index]; 3367 else 3368 psgl_handle = phba->eh_sgl_hndl_base[arr_index - 3369 phba->params.ios_per_ctrl]; 3370 psgl_handle->pfrag = pfrag; 3371 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0); 3372 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0); 3373 pfrag += phba->params.num_sge_per_io; 3374 psgl_handle->sgl_index = 3375 phba->fw_config.iscsi_icd_start + arr_index++; 3376 } 3377 idx++; 3378 } 3379 phba->io_sgl_free_index = 0; 3380 phba->io_sgl_alloc_index = 0; 3381 phba->eh_sgl_free_index = 0; 3382 phba->eh_sgl_alloc_index = 0; 3383 return 0; 3384} 3385 3386static int hba_setup_cid_tbls(struct beiscsi_hba *phba) 3387{ 3388 int i, new_cid; 3389 3390 phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl, 3391 GFP_KERNEL); 3392 if (!phba->cid_array) { 3393 shost_printk(KERN_ERR, phba->shost, 3394 "Failed to allocate memory in " 3395 "hba_setup_cid_tbls\n"); 3396 return -ENOMEM; 3397 } 3398 phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) * 3399 phba->params.cxns_per_ctrl * 2, GFP_KERNEL); 3400 if (!phba->ep_array) { 3401 shost_printk(KERN_ERR, phba->shost, 3402 "Failed to allocate memory in " 3403 "hba_setup_cid_tbls\n"); 3404 kfree(phba->cid_array); 3405 return -ENOMEM; 3406 } 3407 new_cid = phba->fw_config.iscsi_cid_start; 3408 for (i = 0; i < phba->params.cxns_per_ctrl; i++) { 3409 phba->cid_array[i] = new_cid; 3410 new_cid += 2; 3411 } 3412 phba->avlbl_cids = phba->params.cxns_per_ctrl; 3413 return 0; 3414} 3415 3416static void hwi_enable_intr(struct beiscsi_hba *phba) 3417{ 3418 struct be_ctrl_info *ctrl = &phba->ctrl; 3419 struct hwi_controller *phwi_ctrlr; 3420 struct hwi_context_memory *phwi_context; 3421 struct be_queue_info *eq; 3422 u8 __iomem *addr; 3423 u32 reg, i; 3424 u32 enabled; 3425 3426 phwi_ctrlr = phba->phwi_ctrlr; 3427 phwi_context = phwi_ctrlr->phwi_ctxt; 3428 3429 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg + 3430 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET); 3431 reg = ioread32(addr); 3432 3433 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 3434 if (!enabled) { 3435 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 3436 SE_DEBUG(DBG_LVL_8, "reg =x%08x addr=%p\n", reg, addr); 3437 iowrite32(reg, addr); 3438 } 3439 3440 if (!phba->msix_enabled) { 3441 eq = &phwi_context->be_eq[0].q; 3442 SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id); 3443 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); 3444 } else { 3445 for (i = 0; i <= phba->num_cpus; i++) { 3446 eq = &phwi_context->be_eq[i].q; 3447 SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id); 3448 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); 3449 } 3450 } 3451} 3452 3453static void hwi_disable_intr(struct beiscsi_hba *phba) 3454{ 3455 struct be_ctrl_info *ctrl = &phba->ctrl; 3456 3457 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET; 3458 u32 reg = ioread32(addr); 3459 3460 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 3461 if (enabled) { 3462 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 3463 iowrite32(reg, addr); 3464 } else 3465 shost_printk(KERN_WARNING, phba->shost, 3466 "In hwi_disable_intr, Already Disabled\n"); 3467} 3468 3469static int beiscsi_get_boot_info(struct beiscsi_hba *phba) 3470{ 3471 struct be_cmd_resp_get_boot_target *boot_resp; 3472 struct be_cmd_resp_get_session *session_resp; 3473 struct be_mcc_wrb *wrb; 3474 struct be_dma_mem nonemb_cmd; 3475 unsigned int tag, wrb_num; 3476 unsigned short status, extd_status; 3477 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; 3478 int ret = -ENOMEM; 3479 3480 tag = beiscsi_get_boot_target(phba); 3481 if (!tag) { 3482 SE_DEBUG(DBG_LVL_1, "be_cmd_get_mac_addr Failed\n"); 3483 return -EAGAIN; 3484 } else 3485 wait_event_interruptible(phba->ctrl.mcc_wait[tag], 3486 phba->ctrl.mcc_numtag[tag]); 3487 3488 wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16; 3489 extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8; 3490 status = phba->ctrl.mcc_numtag[tag] & 0x000000FF; 3491 if (status || extd_status) { 3492 SE_DEBUG(DBG_LVL_1, "be_cmd_get_mac_addr Failed" 3493 " status = %d extd_status = %d\n", 3494 status, extd_status); 3495 free_mcc_tag(&phba->ctrl, tag); 3496 return -EBUSY; 3497 } 3498 wrb = queue_get_wrb(mccq, wrb_num); 3499 free_mcc_tag(&phba->ctrl, tag); 3500 boot_resp = embedded_payload(wrb); 3501 3502 if (boot_resp->boot_session_handle < 0) { 3503 shost_printk(KERN_INFO, phba->shost, "No Boot Session.\n"); 3504 return -ENXIO; 3505 } 3506 3507 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, 3508 sizeof(*session_resp), 3509 &nonemb_cmd.dma); 3510 if (nonemb_cmd.va == NULL) { 3511 SE_DEBUG(DBG_LVL_1, 3512 "Failed to allocate memory for" 3513 "beiscsi_get_session_info\n"); 3514 return -ENOMEM; 3515 } 3516 3517 memset(nonemb_cmd.va, 0, sizeof(*session_resp)); 3518 tag = beiscsi_get_session_info(phba, 3519 boot_resp->boot_session_handle, &nonemb_cmd); 3520 if (!tag) { 3521 SE_DEBUG(DBG_LVL_1, "beiscsi_get_session_info" 3522 " Failed\n"); 3523 goto boot_freemem; 3524 } else 3525 wait_event_interruptible(phba->ctrl.mcc_wait[tag], 3526 phba->ctrl.mcc_numtag[tag]); 3527 3528 wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16; 3529 extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8; 3530 status = phba->ctrl.mcc_numtag[tag] & 0x000000FF; 3531 if (status || extd_status) { 3532 SE_DEBUG(DBG_LVL_1, "beiscsi_get_session_info Failed" 3533 " status = %d extd_status = %d\n", 3534 status, extd_status); 3535 free_mcc_tag(&phba->ctrl, tag); 3536 goto boot_freemem; 3537 } 3538 wrb = queue_get_wrb(mccq, wrb_num); 3539 free_mcc_tag(&phba->ctrl, tag); 3540 session_resp = nonemb_cmd.va ; 3541 3542 memcpy(&phba->boot_sess, &session_resp->session_info, 3543 sizeof(struct mgmt_session_info)); 3544 ret = 0; 3545 3546boot_freemem: 3547 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, 3548 nonemb_cmd.va, nonemb_cmd.dma); 3549 return ret; 3550} 3551 3552static void beiscsi_boot_release(void *data) 3553{ 3554 struct beiscsi_hba *phba = data; 3555 3556 scsi_host_put(phba->shost); 3557} 3558 3559static int beiscsi_setup_boot_info(struct beiscsi_hba *phba) 3560{ 3561 struct iscsi_boot_kobj *boot_kobj; 3562 3563 /* get boot info using mgmt cmd */ 3564 if (beiscsi_get_boot_info(phba)) 3565 /* Try to see if we can carry on without this */ 3566 return 0; 3567 3568 phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no); 3569 if (!phba->boot_kset) 3570 return -ENOMEM; 3571 3572 /* get a ref because the show function will ref the phba */ 3573 if (!scsi_host_get(phba->shost)) 3574 goto free_kset; 3575 boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba, 3576 beiscsi_show_boot_tgt_info, 3577 beiscsi_tgt_get_attr_visibility, 3578 beiscsi_boot_release); 3579 if (!boot_kobj) 3580 goto put_shost; 3581 3582 if (!scsi_host_get(phba->shost)) 3583 goto free_kset; 3584 boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba, 3585 beiscsi_show_boot_ini_info, 3586 beiscsi_ini_get_attr_visibility, 3587 beiscsi_boot_release); 3588 if (!boot_kobj) 3589 goto put_shost; 3590 3591 if (!scsi_host_get(phba->shost)) 3592 goto free_kset; 3593 boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba, 3594 beiscsi_show_boot_eth_info, 3595 beiscsi_eth_get_attr_visibility, 3596 beiscsi_boot_release); 3597 if (!boot_kobj) 3598 goto put_shost; 3599 return 0; 3600 3601put_shost: 3602 scsi_host_put(phba->shost); 3603free_kset: 3604 iscsi_boot_destroy_kset(phba->boot_kset); 3605 return -ENOMEM; 3606} 3607 3608static int beiscsi_init_port(struct beiscsi_hba *phba) 3609{ 3610 int ret; 3611 3612 ret = beiscsi_init_controller(phba); 3613 if (ret < 0) { 3614 shost_printk(KERN_ERR, phba->shost, 3615 "beiscsi_dev_probe - Failed in" 3616 "beiscsi_init_controller\n"); 3617 return ret; 3618 } 3619 ret = beiscsi_init_sgl_handle(phba); 3620 if (ret < 0) { 3621 shost_printk(KERN_ERR, phba->shost, 3622 "beiscsi_dev_probe - Failed in" 3623 "beiscsi_init_sgl_handle\n"); 3624 goto do_cleanup_ctrlr; 3625 } 3626 3627 if (hba_setup_cid_tbls(phba)) { 3628 shost_printk(KERN_ERR, phba->shost, 3629 "Failed in hba_setup_cid_tbls\n"); 3630 kfree(phba->io_sgl_hndl_base); 3631 kfree(phba->eh_sgl_hndl_base); 3632 goto do_cleanup_ctrlr; 3633 } 3634 3635 return ret; 3636 3637do_cleanup_ctrlr: 3638 hwi_cleanup(phba); 3639 return ret; 3640} 3641 3642static void hwi_purge_eq(struct beiscsi_hba *phba) 3643{ 3644 struct hwi_controller *phwi_ctrlr; 3645 struct hwi_context_memory *phwi_context; 3646 struct be_queue_info *eq; 3647 struct be_eq_entry *eqe = NULL; 3648 int i, eq_msix; 3649 unsigned int num_processed; 3650 3651 phwi_ctrlr = phba->phwi_ctrlr; 3652 phwi_context = phwi_ctrlr->phwi_ctxt; 3653 if (phba->msix_enabled) 3654 eq_msix = 1; 3655 else 3656 eq_msix = 0; 3657 3658 for (i = 0; i < (phba->num_cpus + eq_msix); i++) { 3659 eq = &phwi_context->be_eq[i].q; 3660 eqe = queue_tail_node(eq); 3661 num_processed = 0; 3662 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 3663 & EQE_VALID_MASK) { 3664 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 3665 queue_tail_inc(eq); 3666 eqe = queue_tail_node(eq); 3667 num_processed++; 3668 } 3669 3670 if (num_processed) 3671 hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1); 3672 } 3673} 3674 3675static void beiscsi_clean_port(struct beiscsi_hba *phba) 3676{ 3677 int mgmt_status; 3678 3679 mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0); 3680 if (mgmt_status) 3681 shost_printk(KERN_WARNING, phba->shost, 3682 "mgmt_epfw_cleanup FAILED\n"); 3683 3684 hwi_purge_eq(phba); 3685 hwi_cleanup(phba); 3686 kfree(phba->io_sgl_hndl_base); 3687 kfree(phba->eh_sgl_hndl_base); 3688 kfree(phba->cid_array); 3689 kfree(phba->ep_array); 3690} 3691 3692void 3693beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn, 3694 struct beiscsi_offload_params *params) 3695{ 3696 struct wrb_handle *pwrb_handle; 3697 struct iscsi_target_context_update_wrb *pwrb = NULL; 3698 struct be_mem_descriptor *mem_descr; 3699 struct beiscsi_hba *phba = beiscsi_conn->phba; 3700 u32 doorbell = 0; 3701 3702 /* 3703 * We can always use 0 here because it is reserved by libiscsi for 3704 * login/startup related tasks. 3705 */ 3706 pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid - 3707 phba->fw_config.iscsi_cid_start)); 3708 pwrb = (struct iscsi_target_context_update_wrb *)pwrb_handle->pwrb; 3709 memset(pwrb, 0, sizeof(*pwrb)); 3710 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, 3711 max_burst_length, pwrb, params->dw[offsetof 3712 (struct amap_beiscsi_offload_params, 3713 max_burst_length) / 32]); 3714 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, 3715 max_send_data_segment_length, pwrb, 3716 params->dw[offsetof(struct amap_beiscsi_offload_params, 3717 max_send_data_segment_length) / 32]); 3718 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, 3719 first_burst_length, 3720 pwrb, 3721 params->dw[offsetof(struct amap_beiscsi_offload_params, 3722 first_burst_length) / 32]); 3723 3724 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, erl, pwrb, 3725 (params->dw[offsetof(struct amap_beiscsi_offload_params, 3726 erl) / 32] & OFFLD_PARAMS_ERL)); 3727 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, dde, pwrb, 3728 (params->dw[offsetof(struct amap_beiscsi_offload_params, 3729 dde) / 32] & OFFLD_PARAMS_DDE) >> 2); 3730 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, hde, pwrb, 3731 (params->dw[offsetof(struct amap_beiscsi_offload_params, 3732 hde) / 32] & OFFLD_PARAMS_HDE) >> 3); 3733 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ir2t, pwrb, 3734 (params->dw[offsetof(struct amap_beiscsi_offload_params, 3735 ir2t) / 32] & OFFLD_PARAMS_IR2T) >> 4); 3736 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, imd, pwrb, 3737 (params->dw[offsetof(struct amap_beiscsi_offload_params, 3738 imd) / 32] & OFFLD_PARAMS_IMD) >> 5); 3739 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, stat_sn, 3740 pwrb, 3741 (params->dw[offsetof(struct amap_beiscsi_offload_params, 3742 exp_statsn) / 32] + 1)); 3743 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, type, pwrb, 3744 0x7); 3745 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, wrb_idx, 3746 pwrb, pwrb_handle->wrb_index); 3747 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ptr2nextwrb, 3748 pwrb, pwrb_handle->nxt_wrb_index); 3749 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, 3750 session_state, pwrb, 0); 3751 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, compltonack, 3752 pwrb, 1); 3753 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, notpredblq, 3754 pwrb, 0); 3755 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, mode, pwrb, 3756 0); 3757 3758 mem_descr = phba->init_mem; 3759 mem_descr += ISCSI_MEM_GLOBAL_HEADER; 3760 3761 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, 3762 pad_buffer_addr_hi, pwrb, 3763 mem_descr->mem_array[0].bus_address.u.a32.address_hi); 3764 AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, 3765 pad_buffer_addr_lo, pwrb, 3766 mem_descr->mem_array[0].bus_address.u.a32.address_lo); 3767 3768 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_target_context_update_wrb)); 3769 3770 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; 3771 doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK) 3772 << DB_DEF_PDU_WRB_INDEX_SHIFT; 3773 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 3774 3775 iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET); 3776} 3777 3778static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt, 3779 int *index, int *age) 3780{ 3781 *index = (int)itt; 3782 if (age) 3783 *age = conn->session->age; 3784} 3785 3786/** 3787 * beiscsi_alloc_pdu - allocates pdu and related resources 3788 * @task: libiscsi task 3789 * @opcode: opcode of pdu for task 3790 * 3791 * This is called with the session lock held. It will allocate 3792 * the wrb and sgl if needed for the command. And it will prep 3793 * the pdu's itt. beiscsi_parse_pdu will later translate 3794 * the pdu itt to the libiscsi task itt. 3795 */ 3796static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode) 3797{ 3798 struct beiscsi_io_task *io_task = task->dd_data; 3799 struct iscsi_conn *conn = task->conn; 3800 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 3801 struct beiscsi_hba *phba = beiscsi_conn->phba; 3802 struct hwi_wrb_context *pwrb_context; 3803 struct hwi_controller *phwi_ctrlr; 3804 itt_t itt; 3805 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess; 3806 dma_addr_t paddr; 3807 3808 io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool, 3809 GFP_ATOMIC, &paddr); 3810 if (!io_task->cmd_bhs) 3811 return -ENOMEM; 3812 io_task->bhs_pa.u.a64.address = paddr; 3813 io_task->libiscsi_itt = (itt_t)task->itt; 3814 io_task->conn = beiscsi_conn; 3815 3816 task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr; 3817 task->hdr_max = sizeof(struct be_cmd_bhs); 3818 io_task->psgl_handle = NULL; 3819 io_task->psgl_handle = NULL; 3820 3821 if (task->sc) { 3822 spin_lock(&phba->io_sgl_lock); 3823 io_task->psgl_handle = alloc_io_sgl_handle(phba); 3824 spin_unlock(&phba->io_sgl_lock); 3825 if (!io_task->psgl_handle) 3826 goto free_hndls; 3827 io_task->pwrb_handle = alloc_wrb_handle(phba, 3828 beiscsi_conn->beiscsi_conn_cid - 3829 phba->fw_config.iscsi_cid_start); 3830 if (!io_task->pwrb_handle) 3831 goto free_io_hndls; 3832 } else { 3833 io_task->scsi_cmnd = NULL; 3834 if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) { 3835 if (!beiscsi_conn->login_in_progress) { 3836 spin_lock(&phba->mgmt_sgl_lock); 3837 io_task->psgl_handle = (struct sgl_handle *) 3838 alloc_mgmt_sgl_handle(phba); 3839 spin_unlock(&phba->mgmt_sgl_lock); 3840 if (!io_task->psgl_handle) 3841 goto free_hndls; 3842 3843 beiscsi_conn->login_in_progress = 1; 3844 beiscsi_conn->plogin_sgl_handle = 3845 io_task->psgl_handle; 3846 io_task->pwrb_handle = 3847 alloc_wrb_handle(phba, 3848 beiscsi_conn->beiscsi_conn_cid - 3849 phba->fw_config.iscsi_cid_start); 3850 if (!io_task->pwrb_handle) 3851 goto free_io_hndls; 3852 beiscsi_conn->plogin_wrb_handle = 3853 io_task->pwrb_handle; 3854 3855 } else { 3856 io_task->psgl_handle = 3857 beiscsi_conn->plogin_sgl_handle; 3858 io_task->pwrb_handle = 3859 beiscsi_conn->plogin_wrb_handle; 3860 } 3861 } else { 3862 spin_lock(&phba->mgmt_sgl_lock); 3863 io_task->psgl_handle = alloc_mgmt_sgl_handle(phba); 3864 spin_unlock(&phba->mgmt_sgl_lock); 3865 if (!io_task->psgl_handle) 3866 goto free_hndls; 3867 io_task->pwrb_handle = 3868 alloc_wrb_handle(phba, 3869 beiscsi_conn->beiscsi_conn_cid - 3870 phba->fw_config.iscsi_cid_start); 3871 if (!io_task->pwrb_handle) 3872 goto free_mgmt_hndls; 3873 3874 } 3875 } 3876 itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle-> 3877 wrb_index << 16) | (unsigned int) 3878 (io_task->psgl_handle->sgl_index)); 3879 io_task->pwrb_handle->pio_handle = task; 3880 3881 io_task->cmd_bhs->iscsi_hdr.itt = itt; 3882 return 0; 3883 3884free_io_hndls: 3885 spin_lock(&phba->io_sgl_lock); 3886 free_io_sgl_handle(phba, io_task->psgl_handle); 3887 spin_unlock(&phba->io_sgl_lock); 3888 goto free_hndls; 3889free_mgmt_hndls: 3890 spin_lock(&phba->mgmt_sgl_lock); 3891 free_mgmt_sgl_handle(phba, io_task->psgl_handle); 3892 spin_unlock(&phba->mgmt_sgl_lock); 3893free_hndls: 3894 phwi_ctrlr = phba->phwi_ctrlr; 3895 pwrb_context = &phwi_ctrlr->wrb_context[ 3896 beiscsi_conn->beiscsi_conn_cid - 3897 phba->fw_config.iscsi_cid_start]; 3898 if (io_task->pwrb_handle) 3899 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle); 3900 io_task->pwrb_handle = NULL; 3901 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs, 3902 io_task->bhs_pa.u.a64.address); 3903 SE_DEBUG(DBG_LVL_1, "Alloc of SGL_ICD Failed\n"); 3904 return -ENOMEM; 3905} 3906 3907static void beiscsi_cleanup_task(struct iscsi_task *task) 3908{ 3909 struct beiscsi_io_task *io_task = task->dd_data; 3910 struct iscsi_conn *conn = task->conn; 3911 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 3912 struct beiscsi_hba *phba = beiscsi_conn->phba; 3913 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess; 3914 struct hwi_wrb_context *pwrb_context; 3915 struct hwi_controller *phwi_ctrlr; 3916 3917 phwi_ctrlr = phba->phwi_ctrlr; 3918 pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid 3919 - phba->fw_config.iscsi_cid_start]; 3920 if (io_task->pwrb_handle) { 3921 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle); 3922 io_task->pwrb_handle = NULL; 3923 } 3924 3925 if (io_task->cmd_bhs) { 3926 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs, 3927 io_task->bhs_pa.u.a64.address); 3928 } 3929 3930 if (task->sc) { 3931 if (io_task->psgl_handle) { 3932 spin_lock(&phba->io_sgl_lock); 3933 free_io_sgl_handle(phba, io_task->psgl_handle); 3934 spin_unlock(&phba->io_sgl_lock); 3935 io_task->psgl_handle = NULL; 3936 } 3937 } else { 3938 if (task->hdr && 3939 ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN)) 3940 return; 3941 if (io_task->psgl_handle) { 3942 spin_lock(&phba->mgmt_sgl_lock); 3943 free_mgmt_sgl_handle(phba, io_task->psgl_handle); 3944 spin_unlock(&phba->mgmt_sgl_lock); 3945 io_task->psgl_handle = NULL; 3946 } 3947 } 3948} 3949 3950static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg, 3951 unsigned int num_sg, unsigned int xferlen, 3952 unsigned int writedir) 3953{ 3954 3955 struct beiscsi_io_task *io_task = task->dd_data; 3956 struct iscsi_conn *conn = task->conn; 3957 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 3958 struct beiscsi_hba *phba = beiscsi_conn->phba; 3959 struct iscsi_wrb *pwrb = NULL; 3960 unsigned int doorbell = 0; 3961 3962 pwrb = io_task->pwrb_handle->pwrb; 3963 io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0; 3964 io_task->bhs_len = sizeof(struct be_cmd_bhs); 3965 3966 if (writedir) { 3967 memset(&io_task->cmd_bhs->iscsi_data_pdu, 0, 48); 3968 AMAP_SET_BITS(struct amap_pdu_data_out, itt, 3969 &io_task->cmd_bhs->iscsi_data_pdu, 3970 (unsigned int)io_task->cmd_bhs->iscsi_hdr.itt); 3971 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, 3972 &io_task->cmd_bhs->iscsi_data_pdu, 3973 ISCSI_OPCODE_SCSI_DATA_OUT); 3974 AMAP_SET_BITS(struct amap_pdu_data_out, final_bit, 3975 &io_task->cmd_bhs->iscsi_data_pdu, 1); 3976 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 3977 INI_WR_CMD); 3978 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1); 3979 } else { 3980 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 3981 INI_RD_CMD); 3982 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); 3983 } 3984 memcpy(&io_task->cmd_bhs->iscsi_data_pdu. 3985 dw[offsetof(struct amap_pdu_data_out, lun) / 32], 3986 &io_task->cmd_bhs->iscsi_hdr.lun, sizeof(struct scsi_lun)); 3987 3988 AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb, 3989 cpu_to_be16(*(unsigned short *)&io_task->cmd_bhs->iscsi_hdr.lun)); 3990 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen); 3991 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb, 3992 io_task->pwrb_handle->wrb_index); 3993 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 3994 be32_to_cpu(task->cmdsn)); 3995 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, 3996 io_task->psgl_handle->sgl_index); 3997 3998 hwi_write_sgl(pwrb, sg, num_sg, io_task); 3999 4000 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb, 4001 io_task->pwrb_handle->nxt_wrb_index); 4002 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb)); 4003 4004 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; 4005 doorbell |= (io_task->pwrb_handle->wrb_index & 4006 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT; 4007 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4008 4009 iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET); 4010 return 0; 4011} 4012 4013static int beiscsi_mtask(struct iscsi_task *task) 4014{ 4015 struct beiscsi_io_task *io_task = task->dd_data; 4016 struct iscsi_conn *conn = task->conn; 4017 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4018 struct beiscsi_hba *phba = beiscsi_conn->phba; 4019 struct iscsi_wrb *pwrb = NULL; 4020 unsigned int doorbell = 0; 4021 unsigned int cid; 4022 4023 cid = beiscsi_conn->beiscsi_conn_cid; 4024 pwrb = io_task->pwrb_handle->pwrb; 4025 memset(pwrb, 0, sizeof(*pwrb)); 4026 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 4027 be32_to_cpu(task->cmdsn)); 4028 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb, 4029 io_task->pwrb_handle->wrb_index); 4030 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, 4031 io_task->psgl_handle->sgl_index); 4032 4033 switch (task->hdr->opcode & ISCSI_OPCODE_MASK) { 4034 case ISCSI_OP_LOGIN: 4035 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 4036 TGT_DM_CMD); 4037 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0); 4038 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1); 4039 hwi_write_buffer(pwrb, task); 4040 break; 4041 case ISCSI_OP_NOOP_OUT: 4042 if (task->hdr->ttt != ISCSI_RESERVED_TAG) { 4043 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 4044 TGT_DM_CMD); 4045 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, 4046 pwrb, 0); 4047 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0); 4048 } else { 4049 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 4050 INI_RD_CMD); 4051 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 1); 4052 } 4053 hwi_write_buffer(pwrb, task); 4054 break; 4055 case ISCSI_OP_TEXT: 4056 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 4057 TGT_DM_CMD); 4058 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0); 4059 hwi_write_buffer(pwrb, task); 4060 break; 4061 case ISCSI_OP_SCSI_TMFUNC: 4062 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 4063 INI_TMF_CMD); 4064 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0); 4065 hwi_write_buffer(pwrb, task); 4066 break; 4067 case ISCSI_OP_LOGOUT: 4068 AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0); 4069 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 4070 HWH_TYPE_LOGOUT); 4071 hwi_write_buffer(pwrb, task); 4072 break; 4073 4074 default: 4075 SE_DEBUG(DBG_LVL_1, "opcode =%d Not supported\n", 4076 task->hdr->opcode & ISCSI_OPCODE_MASK); 4077 return -EINVAL; 4078 } 4079 4080 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, 4081 task->data_count); 4082 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb, 4083 io_task->pwrb_handle->nxt_wrb_index); 4084 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb)); 4085 4086 doorbell |= cid & DB_WRB_POST_CID_MASK; 4087 doorbell |= (io_task->pwrb_handle->wrb_index & 4088 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT; 4089 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4090 iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET); 4091 return 0; 4092} 4093 4094static int beiscsi_task_xmit(struct iscsi_task *task) 4095{ 4096 struct beiscsi_io_task *io_task = task->dd_data; 4097 struct scsi_cmnd *sc = task->sc; 4098 struct scatterlist *sg; 4099 int num_sg; 4100 unsigned int writedir = 0, xferlen = 0; 4101 4102 if (!sc) 4103 return beiscsi_mtask(task); 4104 4105 io_task->scsi_cmnd = sc; 4106 num_sg = scsi_dma_map(sc); 4107 if (num_sg < 0) { 4108 SE_DEBUG(DBG_LVL_1, " scsi_dma_map Failed\n") 4109 return num_sg; 4110 } 4111 xferlen = scsi_bufflen(sc); 4112 sg = scsi_sglist(sc); 4113 if (sc->sc_data_direction == DMA_TO_DEVICE) { 4114 writedir = 1; 4115 SE_DEBUG(DBG_LVL_4, "task->imm_count=0x%08x\n", 4116 task->imm_count); 4117 } else 4118 writedir = 0; 4119 return beiscsi_iotask(task, sg, num_sg, xferlen, writedir); 4120} 4121 4122static void beiscsi_quiesce(struct beiscsi_hba *phba) 4123{ 4124 struct hwi_controller *phwi_ctrlr; 4125 struct hwi_context_memory *phwi_context; 4126 struct be_eq_obj *pbe_eq; 4127 unsigned int i, msix_vec; 4128 u8 *real_offset = 0; 4129 u32 value = 0; 4130 4131 phwi_ctrlr = phba->phwi_ctrlr; 4132 phwi_context = phwi_ctrlr->phwi_ctxt; 4133 hwi_disable_intr(phba); 4134 if (phba->msix_enabled) { 4135 for (i = 0; i <= phba->num_cpus; i++) { 4136 msix_vec = phba->msix_entries[i].vector; 4137 free_irq(msix_vec, &phwi_context->be_eq[i]); 4138 kfree(phba->msi_name[i]); 4139 } 4140 } else 4141 if (phba->pcidev->irq) 4142 free_irq(phba->pcidev->irq, phba); 4143 pci_disable_msix(phba->pcidev); 4144 destroy_workqueue(phba->wq); 4145 if (blk_iopoll_enabled) 4146 for (i = 0; i < phba->num_cpus; i++) { 4147 pbe_eq = &phwi_context->be_eq[i]; 4148 blk_iopoll_disable(&pbe_eq->iopoll); 4149 } 4150 4151 beiscsi_clean_port(phba); 4152 beiscsi_free_mem(phba); 4153 real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE; 4154 4155 value = readl((void *)real_offset); 4156 4157 if (value & 0x00010000) { 4158 value &= 0xfffeffff; 4159 writel(value, (void *)real_offset); 4160 } 4161 beiscsi_unmap_pci_function(phba); 4162 pci_free_consistent(phba->pcidev, 4163 phba->ctrl.mbox_mem_alloced.size, 4164 phba->ctrl.mbox_mem_alloced.va, 4165 phba->ctrl.mbox_mem_alloced.dma); 4166} 4167 4168static void beiscsi_remove(struct pci_dev *pcidev) 4169{ 4170 4171 struct beiscsi_hba *phba = NULL; 4172 4173 phba = pci_get_drvdata(pcidev); 4174 if (!phba) { 4175 dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n"); 4176 return; 4177 } 4178 4179 beiscsi_quiesce(phba); 4180 iscsi_boot_destroy_kset(phba->boot_kset); 4181 iscsi_host_remove(phba->shost); 4182 pci_dev_put(phba->pcidev); 4183 iscsi_host_free(phba->shost); 4184 pci_disable_device(pcidev); 4185} 4186 4187static void beiscsi_shutdown(struct pci_dev *pcidev) 4188{ 4189 4190 struct beiscsi_hba *phba = NULL; 4191 4192 phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev); 4193 if (!phba) { 4194 dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n"); 4195 return; 4196 } 4197 4198 beiscsi_quiesce(phba); 4199 pci_disable_device(pcidev); 4200} 4201 4202static void beiscsi_msix_enable(struct beiscsi_hba *phba) 4203{ 4204 int i, status; 4205 4206 for (i = 0; i <= phba->num_cpus; i++) 4207 phba->msix_entries[i].entry = i; 4208 4209 status = pci_enable_msix(phba->pcidev, phba->msix_entries, 4210 (phba->num_cpus + 1)); 4211 if (!status) 4212 phba->msix_enabled = true; 4213 4214 return; 4215} 4216 4217static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev, 4218 const struct pci_device_id *id) 4219{ 4220 struct beiscsi_hba *phba = NULL; 4221 struct hwi_controller *phwi_ctrlr; 4222 struct hwi_context_memory *phwi_context; 4223 struct be_eq_obj *pbe_eq; 4224 int ret, num_cpus, i; 4225 u8 *real_offset = 0; 4226 u32 value = 0; 4227 4228 ret = beiscsi_enable_pci(pcidev); 4229 if (ret < 0) { 4230 dev_err(&pcidev->dev, "beiscsi_dev_probe-" 4231 " Failed to enable pci device\n"); 4232 return ret; 4233 } 4234 4235 phba = beiscsi_hba_alloc(pcidev); 4236 if (!phba) { 4237 dev_err(&pcidev->dev, "beiscsi_dev_probe-" 4238 " Failed in beiscsi_hba_alloc\n"); 4239 goto disable_pci; 4240 } 4241 4242 switch (pcidev->device) { 4243 case BE_DEVICE_ID1: 4244 case OC_DEVICE_ID1: 4245 case OC_DEVICE_ID2: 4246 phba->generation = BE_GEN2; 4247 break; 4248 case BE_DEVICE_ID2: 4249 case OC_DEVICE_ID3: 4250 phba->generation = BE_GEN3; 4251 break; 4252 default: 4253 phba->generation = 0; 4254 } 4255 4256 if (enable_msix) 4257 num_cpus = find_num_cpus(); 4258 else 4259 num_cpus = 1; 4260 phba->num_cpus = num_cpus; 4261 SE_DEBUG(DBG_LVL_8, "num_cpus = %d\n", phba->num_cpus); 4262 4263 if (enable_msix) 4264 beiscsi_msix_enable(phba); 4265 ret = be_ctrl_init(phba, pcidev); 4266 if (ret) { 4267 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-" 4268 "Failed in be_ctrl_init\n"); 4269 goto hba_free; 4270 } 4271 4272 if (!num_hba) { 4273 real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE; 4274 value = readl((void *)real_offset); 4275 if (value & 0x00010000) { 4276 gcrashmode++; 4277 shost_printk(KERN_ERR, phba->shost, 4278 "Loading Driver in crashdump mode\n"); 4279 ret = beiscsi_cmd_reset_function(phba); 4280 if (ret) { 4281 shost_printk(KERN_ERR, phba->shost, 4282 "Reset Failed. Aborting Crashdump\n"); 4283 goto hba_free; 4284 } 4285 ret = be_chk_reset_complete(phba); 4286 if (ret) { 4287 shost_printk(KERN_ERR, phba->shost, 4288 "Failed to get out of reset." 4289 "Aborting Crashdump\n"); 4290 goto hba_free; 4291 } 4292 } else { 4293 value |= 0x00010000; 4294 writel(value, (void *)real_offset); 4295 num_hba++; 4296 } 4297 } 4298 4299 spin_lock_init(&phba->io_sgl_lock); 4300 spin_lock_init(&phba->mgmt_sgl_lock); 4301 spin_lock_init(&phba->isr_lock); 4302 ret = mgmt_get_fw_config(&phba->ctrl, phba); 4303 if (ret != 0) { 4304 shost_printk(KERN_ERR, phba->shost, 4305 "Error getting fw config\n"); 4306 goto free_port; 4307 } 4308 phba->shost->max_id = phba->fw_config.iscsi_cid_count; 4309 beiscsi_get_params(phba); 4310 phba->shost->can_queue = phba->params.ios_per_ctrl; 4311 ret = beiscsi_init_port(phba); 4312 if (ret < 0) { 4313 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-" 4314 "Failed in beiscsi_init_port\n"); 4315 goto free_port; 4316 } 4317 4318 for (i = 0; i < MAX_MCC_CMD ; i++) { 4319 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]); 4320 phba->ctrl.mcc_tag[i] = i + 1; 4321 phba->ctrl.mcc_numtag[i + 1] = 0; 4322 phba->ctrl.mcc_tag_available++; 4323 } 4324 4325 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0; 4326 4327 snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_q_irq%u", 4328 phba->shost->host_no); 4329 phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1); 4330 if (!phba->wq) { 4331 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-" 4332 "Failed to allocate work queue\n"); 4333 goto free_twq; 4334 } 4335 4336 INIT_WORK(&phba->work_cqs, beiscsi_process_all_cqs); 4337 4338 phwi_ctrlr = phba->phwi_ctrlr; 4339 phwi_context = phwi_ctrlr->phwi_ctxt; 4340 if (blk_iopoll_enabled) { 4341 for (i = 0; i < phba->num_cpus; i++) { 4342 pbe_eq = &phwi_context->be_eq[i]; 4343 blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget, 4344 be_iopoll); 4345 blk_iopoll_enable(&pbe_eq->iopoll); 4346 } 4347 } 4348 ret = beiscsi_init_irqs(phba); 4349 if (ret < 0) { 4350 shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-" 4351 "Failed to beiscsi_init_irqs\n"); 4352 goto free_blkenbld; 4353 } 4354 hwi_enable_intr(phba); 4355 4356 if (beiscsi_setup_boot_info(phba)) 4357 /* 4358 * log error but continue, because we may not be using 4359 * iscsi boot. 4360 */ 4361 shost_printk(KERN_ERR, phba->shost, "Could not set up " 4362 "iSCSI boot info."); 4363 4364 SE_DEBUG(DBG_LVL_8, "\n\n\n SUCCESS - DRIVER LOADED\n\n\n"); 4365 return 0; 4366 4367free_blkenbld: 4368 destroy_workqueue(phba->wq); 4369 if (blk_iopoll_enabled) 4370 for (i = 0; i < phba->num_cpus; i++) { 4371 pbe_eq = &phwi_context->be_eq[i]; 4372 blk_iopoll_disable(&pbe_eq->iopoll); 4373 } 4374free_twq: 4375 beiscsi_clean_port(phba); 4376 beiscsi_free_mem(phba); 4377free_port: 4378 real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE; 4379 4380 value = readl((void *)real_offset); 4381 4382 if (value & 0x00010000) { 4383 value &= 0xfffeffff; 4384 writel(value, (void *)real_offset); 4385 } 4386 4387 pci_free_consistent(phba->pcidev, 4388 phba->ctrl.mbox_mem_alloced.size, 4389 phba->ctrl.mbox_mem_alloced.va, 4390 phba->ctrl.mbox_mem_alloced.dma); 4391 beiscsi_unmap_pci_function(phba); 4392hba_free: 4393 if (phba->msix_enabled) 4394 pci_disable_msix(phba->pcidev); 4395 iscsi_host_remove(phba->shost); 4396 pci_dev_put(phba->pcidev); 4397 iscsi_host_free(phba->shost); 4398disable_pci: 4399 pci_disable_device(pcidev); 4400 return ret; 4401} 4402 4403struct iscsi_transport beiscsi_iscsi_transport = { 4404 .owner = THIS_MODULE, 4405 .name = DRV_NAME, 4406 .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO | 4407 CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD, 4408 .create_session = beiscsi_session_create, 4409 .destroy_session = beiscsi_session_destroy, 4410 .create_conn = beiscsi_conn_create, 4411 .bind_conn = beiscsi_conn_bind, 4412 .destroy_conn = iscsi_conn_teardown, 4413 .attr_is_visible = be2iscsi_attr_is_visible, 4414 .set_param = beiscsi_set_param, 4415 .get_conn_param = iscsi_conn_get_param, 4416 .get_session_param = iscsi_session_get_param, 4417 .get_host_param = beiscsi_get_host_param, 4418 .start_conn = beiscsi_conn_start, 4419 .stop_conn = iscsi_conn_stop, 4420 .send_pdu = iscsi_conn_send_pdu, 4421 .xmit_task = beiscsi_task_xmit, 4422 .cleanup_task = beiscsi_cleanup_task, 4423 .alloc_pdu = beiscsi_alloc_pdu, 4424 .parse_pdu_itt = beiscsi_parse_pdu, 4425 .get_stats = beiscsi_conn_get_stats, 4426 .get_ep_param = beiscsi_ep_get_param, 4427 .ep_connect = beiscsi_ep_connect, 4428 .ep_poll = beiscsi_ep_poll, 4429 .ep_disconnect = beiscsi_ep_disconnect, 4430 .session_recovery_timedout = iscsi_session_recovery_timedout, 4431}; 4432 4433static struct pci_driver beiscsi_pci_driver = { 4434 .name = DRV_NAME, 4435 .probe = beiscsi_dev_probe, 4436 .remove = beiscsi_remove, 4437 .shutdown = beiscsi_shutdown, 4438 .id_table = beiscsi_pci_id_table 4439}; 4440 4441 4442static int __init beiscsi_module_init(void) 4443{ 4444 int ret; 4445 4446 beiscsi_scsi_transport = 4447 iscsi_register_transport(&beiscsi_iscsi_transport); 4448 if (!beiscsi_scsi_transport) { 4449 SE_DEBUG(DBG_LVL_1, 4450 "beiscsi_module_init - Unable to register beiscsi" 4451 "transport.\n"); 4452 return -ENOMEM; 4453 } 4454 SE_DEBUG(DBG_LVL_8, "In beiscsi_module_init, tt=%p\n", 4455 &beiscsi_iscsi_transport); 4456 4457 ret = pci_register_driver(&beiscsi_pci_driver); 4458 if (ret) { 4459 SE_DEBUG(DBG_LVL_1, 4460 "beiscsi_module_init - Unable to register" 4461 "beiscsi pci driver.\n"); 4462 goto unregister_iscsi_transport; 4463 } 4464 return 0; 4465 4466unregister_iscsi_transport: 4467 iscsi_unregister_transport(&beiscsi_iscsi_transport); 4468 return ret; 4469} 4470 4471static void __exit beiscsi_module_exit(void) 4472{ 4473 pci_unregister_driver(&beiscsi_pci_driver); 4474 iscsi_unregister_transport(&beiscsi_iscsi_transport); 4475} 4476 4477module_init(beiscsi_module_init); 4478module_exit(beiscsi_module_exit); 4479