1/*
2 *    Disk Array driver for HP Smart Array SAS controllers
3 *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 *    This program is free software; you can redistribute it and/or modify
6 *    it under the terms of the GNU General Public License as published by
7 *    the Free Software Foundation; version 2 of the License.
8 *
9 *    This program is distributed in the hope that it will be useful,
10 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
11 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
13 *
14 *    You should have received a copy of the GNU General Public License
15 *    along with this program; if not, write to the Free Software
16 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21#ifndef HPSA_H
22#define HPSA_H
23
24#include <scsi/scsicam.h>
25
26#define IO_OK		0
27#define IO_ERROR	1
28
29struct ctlr_info;
30
31struct access_method {
32	void (*submit_command)(struct ctlr_info *h,
33		struct CommandList *c);
34	void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
35	unsigned long (*fifo_full)(struct ctlr_info *h);
36	bool (*intr_pending)(struct ctlr_info *h);
37	unsigned long (*command_completed)(struct ctlr_info *h);
38};
39
40struct hpsa_scsi_dev_t {
41	int devtype;
42	int bus, target, lun;		/* as presented to the OS */
43	unsigned char scsi3addr[8];	/* as presented to the HW */
44#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
45	unsigned char device_id[16];    /* from inquiry pg. 0x83 */
46	unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
47	unsigned char model[16];        /* bytes 16-31 of inquiry data */
48	unsigned char raid_level;	/* from inquiry page 0xC1 */
49};
50
51struct ctlr_info {
52	int	ctlr;
53	char	devname[8];
54	char    *product_name;
55	struct pci_dev *pdev;
56	u32	board_id;
57	void __iomem *vaddr;
58	unsigned long paddr;
59	int 	nr_cmds; /* Number of commands allowed on this controller */
60	struct CfgTable __iomem *cfgtable;
61	int	interrupts_enabled;
62	int	major;
63	int 	max_commands;
64	int	commands_outstanding;
65	int 	max_outstanding; /* Debug */
66	int	usage_count;  /* number of opens all all minor devices */
67#	define PERF_MODE_INT	0
68#	define DOORBELL_INT	1
69#	define SIMPLE_MODE_INT	2
70#	define MEMQ_MODE_INT	3
71	unsigned int intr[4];
72	unsigned int msix_vector;
73	unsigned int msi_vector;
74	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
75	struct access_method access;
76
77	/* queue and queue Info */
78	struct list_head reqQ;
79	struct list_head cmpQ;
80	unsigned int Qdepth;
81	unsigned int maxQsinceinit;
82	unsigned int maxSG;
83	spinlock_t lock;
84	int maxsgentries;
85	u8 max_cmd_sg_entries;
86	int chainsize;
87	struct SGDescriptor **cmd_sg_list;
88
89	/* pointers to command and error info pool */
90	struct CommandList 	*cmd_pool;
91	dma_addr_t		cmd_pool_dhandle;
92	struct ErrorInfo 	*errinfo_pool;
93	dma_addr_t		errinfo_pool_dhandle;
94	unsigned long  		*cmd_pool_bits;
95	int			nr_allocs;
96	int			nr_frees;
97	int			scan_finished;
98	spinlock_t		scan_lock;
99	wait_queue_head_t	scan_wait_queue;
100
101	struct Scsi_Host *scsi_host;
102	spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
103	int ndevices; /* number of used elements in .dev[] array. */
104	struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
105	/*
106	 * Performant mode tables.
107	 */
108	u32 trans_support;
109	u32 trans_offset;
110	struct TransTable_struct *transtable;
111	unsigned long transMethod;
112
113	/*
114	 * Performant mode completion buffer
115	 */
116	u64 *reply_pool;
117	dma_addr_t reply_pool_dhandle;
118	u64 *reply_pool_head;
119	size_t reply_pool_size;
120	unsigned char reply_pool_wraparound;
121	u32 *blockFetchTable;
122	unsigned char *hba_inquiry_data;
123	u64 last_intr_timestamp;
124	u32 last_heartbeat;
125	u64 last_heartbeat_timestamp;
126	u32 lockup_detected;
127	struct list_head lockup_list;
128};
129#define HPSA_ABORT_MSG 0
130#define HPSA_DEVICE_RESET_MSG 1
131#define HPSA_RESET_TYPE_CONTROLLER 0x00
132#define HPSA_RESET_TYPE_BUS 0x01
133#define HPSA_RESET_TYPE_TARGET 0x03
134#define HPSA_RESET_TYPE_LUN 0x04
135#define HPSA_MSG_SEND_RETRY_LIMIT 10
136#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
137
138/* Maximum time in seconds driver will wait for command completions
139 * when polling before giving up.
140 */
141#define HPSA_MAX_POLL_TIME_SECS (20)
142
143/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
144 * how many times to retry TEST UNIT READY on a device
145 * while waiting for it to become ready before giving up.
146 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
147 * between sending TURs while waiting for a device
148 * to become ready.
149 */
150#define HPSA_TUR_RETRY_LIMIT (20)
151#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
152
153/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
154 * to become ready, in seconds, before giving up on it.
155 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
156 * between polling the board to see if it is ready, in
157 * milliseconds.  HPSA_BOARD_READY_POLL_INTERVAL and
158 * HPSA_BOARD_READY_ITERATIONS are derived from those.
159 */
160#define HPSA_BOARD_READY_WAIT_SECS (120)
161#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
162#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
163#define HPSA_BOARD_READY_POLL_INTERVAL \
164	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
165#define HPSA_BOARD_READY_ITERATIONS \
166	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
167		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
168#define HPSA_BOARD_NOT_READY_ITERATIONS \
169	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
170		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
171#define HPSA_POST_RESET_PAUSE_MSECS (3000)
172#define HPSA_POST_RESET_NOOP_RETRIES (12)
173
174/*  Defining the diffent access_menthods */
175/*
176 * Memory mapped FIFO interface (SMART 53xx cards)
177 */
178#define SA5_DOORBELL	0x20
179#define SA5_REQUEST_PORT_OFFSET	0x40
180#define SA5_REPLY_INTR_MASK_OFFSET	0x34
181#define SA5_REPLY_PORT_OFFSET		0x44
182#define SA5_INTR_STATUS		0x30
183#define SA5_SCRATCHPAD_OFFSET	0xB0
184
185#define SA5_CTCFG_OFFSET	0xB4
186#define SA5_CTMEM_OFFSET	0xB8
187
188#define SA5_INTR_OFF		0x08
189#define SA5B_INTR_OFF		0x04
190#define SA5_INTR_PENDING	0x08
191#define SA5B_INTR_PENDING	0x04
192#define FIFO_EMPTY		0xffffffff
193#define HPSA_FIRMWARE_READY	0xffff0000 /* value in scratchpad register */
194
195#define HPSA_ERROR_BIT		0x02
196
197/* Performant mode flags */
198#define SA5_PERF_INTR_PENDING   0x04
199#define SA5_PERF_INTR_OFF       0x05
200#define SA5_OUTDB_STATUS_PERF_BIT       0x01
201#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
202#define SA5_OUTDB_CLEAR         0xA0
203#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
204#define SA5_OUTDB_STATUS        0x9C
205
206
207#define HPSA_INTR_ON 	1
208#define HPSA_INTR_OFF	0
209/*
210	Send the command to the hardware
211*/
212static void SA5_submit_command(struct ctlr_info *h,
213	struct CommandList *c)
214{
215	dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
216		c->Header.Tag.lower);
217	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
218	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
219	h->commands_outstanding++;
220	if (h->commands_outstanding > h->max_outstanding)
221		h->max_outstanding = h->commands_outstanding;
222}
223
224/*
225 *  This card is the opposite of the other cards.
226 *   0 turns interrupts on...
227 *   0x08 turns them off...
228 */
229static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
230{
231	if (val) { /* Turn interrupts on */
232		h->interrupts_enabled = 1;
233		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
234		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
235	} else { /* Turn them off */
236		h->interrupts_enabled = 0;
237		writel(SA5_INTR_OFF,
238			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
239		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
240	}
241}
242
243static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
244{
245	if (val) { /* turn on interrupts */
246		h->interrupts_enabled = 1;
247		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
248		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
249	} else {
250		h->interrupts_enabled = 0;
251		writel(SA5_PERF_INTR_OFF,
252			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
253		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
254	}
255}
256
257static unsigned long SA5_performant_completed(struct ctlr_info *h)
258{
259	unsigned long register_value = FIFO_EMPTY;
260
261	/* flush the controller write of the reply queue by reading
262	 * outbound doorbell status register.
263	 */
264	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
265	/* msi auto clears the interrupt pending bit. */
266	if (!(h->msi_vector || h->msix_vector)) {
267		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
268		/* Do a read in order to flush the write to the controller
269		 * (as per spec.)
270		 */
271		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
272	}
273
274	if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
275		register_value = *(h->reply_pool_head);
276		(h->reply_pool_head)++;
277		h->commands_outstanding--;
278	} else {
279		register_value = FIFO_EMPTY;
280	}
281	/* Check for wraparound */
282	if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
283		h->reply_pool_head = h->reply_pool;
284		h->reply_pool_wraparound ^= 1;
285	}
286
287	return register_value;
288}
289
290/*
291 *  Returns true if fifo is full.
292 *
293 */
294static unsigned long SA5_fifo_full(struct ctlr_info *h)
295{
296	if (h->commands_outstanding >= h->max_commands)
297		return 1;
298	else
299		return 0;
300
301}
302/*
303 *   returns value read from hardware.
304 *     returns FIFO_EMPTY if there is nothing to read
305 */
306static unsigned long SA5_completed(struct ctlr_info *h)
307{
308	unsigned long register_value
309		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
310
311	if (register_value != FIFO_EMPTY)
312		h->commands_outstanding--;
313
314#ifdef HPSA_DEBUG
315	if (register_value != FIFO_EMPTY)
316		dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
317			register_value);
318	else
319		dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
320#endif
321
322	return register_value;
323}
324/*
325 *	Returns true if an interrupt is pending..
326 */
327static bool SA5_intr_pending(struct ctlr_info *h)
328{
329	unsigned long register_value  =
330		readl(h->vaddr + SA5_INTR_STATUS);
331	dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
332	return register_value & SA5_INTR_PENDING;
333}
334
335static bool SA5_performant_intr_pending(struct ctlr_info *h)
336{
337	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
338
339	if (!register_value)
340		return false;
341
342	if (h->msi_vector || h->msix_vector)
343		return true;
344
345	/* Read outbound doorbell to flush */
346	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
347	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
348}
349
350static struct access_method SA5_access = {
351	SA5_submit_command,
352	SA5_intr_mask,
353	SA5_fifo_full,
354	SA5_intr_pending,
355	SA5_completed,
356};
357
358static struct access_method SA5_performant_access = {
359	SA5_submit_command,
360	SA5_performant_intr_mask,
361	SA5_fifo_full,
362	SA5_performant_intr_pending,
363	SA5_performant_completed,
364};
365
366struct board_type {
367	u32	board_id;
368	char	*product_name;
369	struct access_method *access;
370};
371
372#endif /* HPSA_H */
373
374