hpsa.h revision 8cd21da71c952843f9cc215436286cf7f991cc6e 
1/*
2 *    Disk Array driver for HP Smart Array SAS controllers
3 *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 *    This program is free software; you can redistribute it and/or modify
6 *    it under the terms of the GNU General Public License as published by
7 *    the Free Software Foundation; version 2 of the License.
8 *
9 *    This program is distributed in the hope that it will be useful,
10 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
11 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
13 *
14 *    You should have received a copy of the GNU General Public License
15 *    along with this program; if not, write to the Free Software
16 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21#ifndef HPSA_H
22#define HPSA_H
23
24#include <scsi/scsicam.h>
25
26#define IO_OK		0
27#define IO_ERROR	1
28
29struct ctlr_info;
30
31struct access_method {
32	void (*submit_command)(struct ctlr_info *h,
33		struct CommandList *c);
34	void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
35	unsigned long (*fifo_full)(struct ctlr_info *h);
36	bool (*intr_pending)(struct ctlr_info *h);
37	unsigned long (*command_completed)(struct ctlr_info *h);
38};
39
40struct hpsa_scsi_dev_t {
41	int devtype;
42	int bus, target, lun;		/* as presented to the OS */
43	unsigned char scsi3addr[8];	/* as presented to the HW */
44#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
45	unsigned char device_id[16];    /* from inquiry pg. 0x83 */
46	unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
47	unsigned char model[16];        /* bytes 16-31 of inquiry data */
48	unsigned char raid_level;	/* from inquiry page 0xC1 */
49};
50
51struct ctlr_info {
52	int	ctlr;
53	char	devname[8];
54	char    *product_name;
55	struct pci_dev *pdev;
56	u32	board_id;
57	void __iomem *vaddr;
58	unsigned long paddr;
59	int 	nr_cmds; /* Number of commands allowed on this controller */
60	struct CfgTable __iomem *cfgtable;
61	int     max_sg_entries;
62	int	interrupts_enabled;
63	int	major;
64	int 	max_commands;
65	int	commands_outstanding;
66	int 	max_outstanding; /* Debug */
67	int	usage_count;  /* number of opens all all minor devices */
68#	define PERF_MODE_INT	0
69#	define DOORBELL_INT	1
70#	define SIMPLE_MODE_INT	2
71#	define MEMQ_MODE_INT	3
72	unsigned int intr[4];
73	unsigned int msix_vector;
74	unsigned int msi_vector;
75	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
76	struct access_method access;
77
78	/* queue and queue Info */
79	struct list_head reqQ;
80	struct list_head cmpQ;
81	unsigned int Qdepth;
82	unsigned int maxQsinceinit;
83	unsigned int maxSG;
84	spinlock_t lock;
85	int maxsgentries;
86	u8 max_cmd_sg_entries;
87	int chainsize;
88	struct SGDescriptor **cmd_sg_list;
89
90	/* pointers to command and error info pool */
91	struct CommandList 	*cmd_pool;
92	dma_addr_t		cmd_pool_dhandle;
93	struct ErrorInfo 	*errinfo_pool;
94	dma_addr_t		errinfo_pool_dhandle;
95	unsigned long  		*cmd_pool_bits;
96	int			nr_allocs;
97	int			nr_frees;
98	int			busy_initializing;
99	int			busy_scanning;
100	int			scan_finished;
101	spinlock_t		scan_lock;
102	wait_queue_head_t	scan_wait_queue;
103
104	struct Scsi_Host *scsi_host;
105	spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
106	int ndevices; /* number of used elements in .dev[] array. */
107#define HPSA_MAX_SCSI_DEVS_PER_HBA 256
108	struct hpsa_scsi_dev_t *dev[HPSA_MAX_SCSI_DEVS_PER_HBA];
109	/*
110	 * Performant mode tables.
111	 */
112	u32 trans_support;
113	u32 trans_offset;
114	struct TransTable_struct *transtable;
115	unsigned long transMethod;
116
117	/*
118	 * Performant mode completion buffer
119	 */
120	u64 *reply_pool;
121	dma_addr_t reply_pool_dhandle;
122	u64 *reply_pool_head;
123	size_t reply_pool_size;
124	unsigned char reply_pool_wraparound;
125	u32 *blockFetchTable;
126	unsigned char *hba_inquiry_data;
127};
128#define HPSA_ABORT_MSG 0
129#define HPSA_DEVICE_RESET_MSG 1
130#define HPSA_BUS_RESET_MSG 2
131#define HPSA_HOST_RESET_MSG 3
132#define HPSA_MSG_SEND_RETRY_LIMIT 10
133#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS 1000
134
135/* Maximum time in seconds driver will wait for command completions
136 * when polling before giving up.
137 */
138#define HPSA_MAX_POLL_TIME_SECS (20)
139
140/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
141 * how many times to retry TEST UNIT READY on a device
142 * while waiting for it to become ready before giving up.
143 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
144 * between sending TURs while waiting for a device
145 * to become ready.
146 */
147#define HPSA_TUR_RETRY_LIMIT (20)
148#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
149
150/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
151 * to become ready, in seconds, before giving up on it.
152 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
153 * between polling the board to see if it is ready, in
154 * milliseconds.  HPSA_BOARD_READY_POLL_INTERVAL and
155 * HPSA_BOARD_READY_ITERATIONS are derived from those.
156 */
157#define HPSA_BOARD_READY_WAIT_SECS (120)
158#define HPSA_BOARD_NOT_READY_WAIT_SECS (10)
159#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
160#define HPSA_BOARD_READY_POLL_INTERVAL \
161	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
162#define HPSA_BOARD_READY_ITERATIONS \
163	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
164		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
165#define HPSA_BOARD_NOT_READY_ITERATIONS \
166	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
167		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
168#define HPSA_POST_RESET_PAUSE_MSECS (3000)
169#define HPSA_POST_RESET_NOOP_RETRIES (12)
170
171/*  Defining the diffent access_menthods */
172/*
173 * Memory mapped FIFO interface (SMART 53xx cards)
174 */
175#define SA5_DOORBELL	0x20
176#define SA5_REQUEST_PORT_OFFSET	0x40
177#define SA5_REPLY_INTR_MASK_OFFSET	0x34
178#define SA5_REPLY_PORT_OFFSET		0x44
179#define SA5_INTR_STATUS		0x30
180#define SA5_SCRATCHPAD_OFFSET	0xB0
181
182#define SA5_CTCFG_OFFSET	0xB4
183#define SA5_CTMEM_OFFSET	0xB8
184
185#define SA5_INTR_OFF		0x08
186#define SA5B_INTR_OFF		0x04
187#define SA5_INTR_PENDING	0x08
188#define SA5B_INTR_PENDING	0x04
189#define FIFO_EMPTY		0xffffffff
190#define HPSA_FIRMWARE_READY	0xffff0000 /* value in scratchpad register */
191
192#define HPSA_ERROR_BIT		0x02
193
194/* Performant mode flags */
195#define SA5_PERF_INTR_PENDING   0x04
196#define SA5_PERF_INTR_OFF       0x05
197#define SA5_OUTDB_STATUS_PERF_BIT       0x01
198#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
199#define SA5_OUTDB_CLEAR         0xA0
200#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
201#define SA5_OUTDB_STATUS        0x9C
202
203
204#define HPSA_INTR_ON 	1
205#define HPSA_INTR_OFF	0
206/*
207	Send the command to the hardware
208*/
209static void SA5_submit_command(struct ctlr_info *h,
210	struct CommandList *c)
211{
212	dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
213		c->Header.Tag.lower);
214	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
215	(void) readl(h->vaddr + SA5_REQUEST_PORT_OFFSET);
216	h->commands_outstanding++;
217	if (h->commands_outstanding > h->max_outstanding)
218		h->max_outstanding = h->commands_outstanding;
219}
220
221/*
222 *  This card is the opposite of the other cards.
223 *   0 turns interrupts on...
224 *   0x08 turns them off...
225 */
226static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
227{
228	if (val) { /* Turn interrupts on */
229		h->interrupts_enabled = 1;
230		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
231		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
232	} else { /* Turn them off */
233		h->interrupts_enabled = 0;
234		writel(SA5_INTR_OFF,
235			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
236		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
237	}
238}
239
240static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
241{
242	if (val) { /* turn on interrupts */
243		h->interrupts_enabled = 1;
244		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
245		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
246	} else {
247		h->interrupts_enabled = 0;
248		writel(SA5_PERF_INTR_OFF,
249			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
250		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
251	}
252}
253
254static unsigned long SA5_performant_completed(struct ctlr_info *h)
255{
256	unsigned long register_value = FIFO_EMPTY;
257
258	/* flush the controller write of the reply queue by reading
259	 * outbound doorbell status register.
260	 */
261	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
262	/* msi auto clears the interrupt pending bit. */
263	if (!(h->msi_vector || h->msix_vector)) {
264		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
265		/* Do a read in order to flush the write to the controller
266		 * (as per spec.)
267		 */
268		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
269	}
270
271	if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
272		register_value = *(h->reply_pool_head);
273		(h->reply_pool_head)++;
274		h->commands_outstanding--;
275	} else {
276		register_value = FIFO_EMPTY;
277	}
278	/* Check for wraparound */
279	if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
280		h->reply_pool_head = h->reply_pool;
281		h->reply_pool_wraparound ^= 1;
282	}
283
284	return register_value;
285}
286
287/*
288 *  Returns true if fifo is full.
289 *
290 */
291static unsigned long SA5_fifo_full(struct ctlr_info *h)
292{
293	if (h->commands_outstanding >= h->max_commands)
294		return 1;
295	else
296		return 0;
297
298}
299/*
300 *   returns value read from hardware.
301 *     returns FIFO_EMPTY if there is nothing to read
302 */
303static unsigned long SA5_completed(struct ctlr_info *h)
304{
305	unsigned long register_value
306		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
307
308	if (register_value != FIFO_EMPTY)
309		h->commands_outstanding--;
310
311#ifdef HPSA_DEBUG
312	if (register_value != FIFO_EMPTY)
313		dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
314			register_value);
315	else
316		dev_dbg(&h->pdev->dev, "hpsa: FIFO Empty read\n");
317#endif
318
319	return register_value;
320}
321/*
322 *	Returns true if an interrupt is pending..
323 */
324static bool SA5_intr_pending(struct ctlr_info *h)
325{
326	unsigned long register_value  =
327		readl(h->vaddr + SA5_INTR_STATUS);
328	dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
329	return register_value & SA5_INTR_PENDING;
330}
331
332static bool SA5_performant_intr_pending(struct ctlr_info *h)
333{
334	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
335
336	if (!register_value)
337		return false;
338
339	if (h->msi_vector || h->msix_vector)
340		return true;
341
342	/* Read outbound doorbell to flush */
343	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
344	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
345}
346
347static struct access_method SA5_access = {
348	SA5_submit_command,
349	SA5_intr_mask,
350	SA5_fifo_full,
351	SA5_intr_pending,
352	SA5_completed,
353};
354
355static struct access_method SA5_performant_access = {
356	SA5_submit_command,
357	SA5_performant_intr_mask,
358	SA5_fifo_full,
359	SA5_performant_intr_pending,
360	SA5_performant_completed,
361};
362
363struct board_type {
364	u32	board_id;
365	char	*product_name;
366	struct access_method *access;
367};
368
369#endif /* HPSA_H */
370
371