1/* 2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 #include <linux/slab.h> 41 #include "pm8001_sas.h" 42 #include "pm8001_hwi.h" 43 #include "pm8001_chips.h" 44 #include "pm8001_ctl.h" 45 46/** 47 * read_main_config_table - read the configure table and save it. 48 * @pm8001_ha: our hba card information 49 */ 50static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha) 51{ 52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 53 pm8001_ha->main_cfg_tbl.signature = pm8001_mr32(address, 0x00); 54 pm8001_ha->main_cfg_tbl.interface_rev = pm8001_mr32(address, 0x04); 55 pm8001_ha->main_cfg_tbl.firmware_rev = pm8001_mr32(address, 0x08); 56 pm8001_ha->main_cfg_tbl.max_out_io = pm8001_mr32(address, 0x0C); 57 pm8001_ha->main_cfg_tbl.max_sgl = pm8001_mr32(address, 0x10); 58 pm8001_ha->main_cfg_tbl.ctrl_cap_flag = pm8001_mr32(address, 0x14); 59 pm8001_ha->main_cfg_tbl.gst_offset = pm8001_mr32(address, 0x18); 60 pm8001_ha->main_cfg_tbl.inbound_queue_offset = 61 pm8001_mr32(address, MAIN_IBQ_OFFSET); 62 pm8001_ha->main_cfg_tbl.outbound_queue_offset = 63 pm8001_mr32(address, MAIN_OBQ_OFFSET); 64 pm8001_ha->main_cfg_tbl.hda_mode_flag = 65 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET); 66 67 /* read analog Setting offset from the configuration table */ 68 pm8001_ha->main_cfg_tbl.anolog_setup_table_offset = 69 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); 70 71 /* read Error Dump Offset and Length */ 72 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 = 73 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); 74 pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 = 75 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); 76 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 = 77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); 78 pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 = 79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); 80} 81 82/** 83 * read_general_status_table - read the general status table and save it. 84 * @pm8001_ha: our hba card information 85 */ 86static void __devinit 87read_general_status_table(struct pm8001_hba_info *pm8001_ha) 88{ 89 void __iomem *address = pm8001_ha->general_stat_tbl_addr; 90 pm8001_ha->gs_tbl.gst_len_mpistate = pm8001_mr32(address, 0x00); 91 pm8001_ha->gs_tbl.iq_freeze_state0 = pm8001_mr32(address, 0x04); 92 pm8001_ha->gs_tbl.iq_freeze_state1 = pm8001_mr32(address, 0x08); 93 pm8001_ha->gs_tbl.msgu_tcnt = pm8001_mr32(address, 0x0C); 94 pm8001_ha->gs_tbl.iop_tcnt = pm8001_mr32(address, 0x10); 95 pm8001_ha->gs_tbl.reserved = pm8001_mr32(address, 0x14); 96 pm8001_ha->gs_tbl.phy_state[0] = pm8001_mr32(address, 0x18); 97 pm8001_ha->gs_tbl.phy_state[1] = pm8001_mr32(address, 0x1C); 98 pm8001_ha->gs_tbl.phy_state[2] = pm8001_mr32(address, 0x20); 99 pm8001_ha->gs_tbl.phy_state[3] = pm8001_mr32(address, 0x24); 100 pm8001_ha->gs_tbl.phy_state[4] = pm8001_mr32(address, 0x28); 101 pm8001_ha->gs_tbl.phy_state[5] = pm8001_mr32(address, 0x2C); 102 pm8001_ha->gs_tbl.phy_state[6] = pm8001_mr32(address, 0x30); 103 pm8001_ha->gs_tbl.phy_state[7] = pm8001_mr32(address, 0x34); 104 pm8001_ha->gs_tbl.reserved1 = pm8001_mr32(address, 0x38); 105 pm8001_ha->gs_tbl.reserved2 = pm8001_mr32(address, 0x3C); 106 pm8001_ha->gs_tbl.reserved3 = pm8001_mr32(address, 0x40); 107 pm8001_ha->gs_tbl.recover_err_info[0] = pm8001_mr32(address, 0x44); 108 pm8001_ha->gs_tbl.recover_err_info[1] = pm8001_mr32(address, 0x48); 109 pm8001_ha->gs_tbl.recover_err_info[2] = pm8001_mr32(address, 0x4C); 110 pm8001_ha->gs_tbl.recover_err_info[3] = pm8001_mr32(address, 0x50); 111 pm8001_ha->gs_tbl.recover_err_info[4] = pm8001_mr32(address, 0x54); 112 pm8001_ha->gs_tbl.recover_err_info[5] = pm8001_mr32(address, 0x58); 113 pm8001_ha->gs_tbl.recover_err_info[6] = pm8001_mr32(address, 0x5C); 114 pm8001_ha->gs_tbl.recover_err_info[7] = pm8001_mr32(address, 0x60); 115} 116 117/** 118 * read_inbnd_queue_table - read the inbound queue table and save it. 119 * @pm8001_ha: our hba card information 120 */ 121static void __devinit 122read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 123{ 124 int inbQ_num = 1; 125 int i; 126 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 127 for (i = 0; i < inbQ_num; i++) { 128 u32 offset = i * 0x20; 129 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 130 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 131 pm8001_ha->inbnd_q_tbl[i].pi_offset = 132 pm8001_mr32(address, (offset + 0x18)); 133 } 134} 135 136/** 137 * read_outbnd_queue_table - read the outbound queue table and save it. 138 * @pm8001_ha: our hba card information 139 */ 140static void __devinit 141read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) 142{ 143 int outbQ_num = 1; 144 int i; 145 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 146 for (i = 0; i < outbQ_num; i++) { 147 u32 offset = i * 0x24; 148 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 149 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14))); 150 pm8001_ha->outbnd_q_tbl[i].ci_offset = 151 pm8001_mr32(address, (offset + 0x18)); 152 } 153} 154 155/** 156 * init_default_table_values - init the default table. 157 * @pm8001_ha: our hba card information 158 */ 159static void __devinit 160init_default_table_values(struct pm8001_hba_info *pm8001_ha) 161{ 162 int qn = 1; 163 int i; 164 u32 offsetib, offsetob; 165 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; 166 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; 167 168 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd = 0; 169 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3 = 0; 170 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7 = 0; 171 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3 = 0; 172 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7 = 0; 173 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3 = 0; 174 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7 = 0; 175 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3 = 0; 176 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7 = 0; 177 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3 = 0; 178 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7 = 0; 179 180 pm8001_ha->main_cfg_tbl.upper_event_log_addr = 181 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; 182 pm8001_ha->main_cfg_tbl.lower_event_log_addr = 183 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; 184 pm8001_ha->main_cfg_tbl.event_log_size = PM8001_EVENT_LOG_SIZE; 185 pm8001_ha->main_cfg_tbl.event_log_option = 0x01; 186 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr = 187 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; 188 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr = 189 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; 190 pm8001_ha->main_cfg_tbl.iop_event_log_size = PM8001_EVENT_LOG_SIZE; 191 pm8001_ha->main_cfg_tbl.iop_event_log_option = 0x01; 192 pm8001_ha->main_cfg_tbl.fatal_err_interrupt = 0x01; 193 for (i = 0; i < qn; i++) { 194 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = 195 0x00000100 | (0x00000040 << 16) | (0x00<<30); 196 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = 197 pm8001_ha->memoryMap.region[IB].phys_addr_hi; 198 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = 199 pm8001_ha->memoryMap.region[IB].phys_addr_lo; 200 pm8001_ha->inbnd_q_tbl[i].base_virt = 201 (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr; 202 pm8001_ha->inbnd_q_tbl[i].total_length = 203 pm8001_ha->memoryMap.region[IB].total_len; 204 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = 205 pm8001_ha->memoryMap.region[CI].phys_addr_hi; 206 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = 207 pm8001_ha->memoryMap.region[CI].phys_addr_lo; 208 pm8001_ha->inbnd_q_tbl[i].ci_virt = 209 pm8001_ha->memoryMap.region[CI].virt_ptr; 210 offsetib = i * 0x20; 211 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = 212 get_pci_bar_index(pm8001_mr32(addressib, 213 (offsetib + 0x14))); 214 pm8001_ha->inbnd_q_tbl[i].pi_offset = 215 pm8001_mr32(addressib, (offsetib + 0x18)); 216 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; 217 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; 218 } 219 for (i = 0; i < qn; i++) { 220 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = 221 256 | (64 << 16) | (1<<30); 222 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = 223 pm8001_ha->memoryMap.region[OB].phys_addr_hi; 224 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = 225 pm8001_ha->memoryMap.region[OB].phys_addr_lo; 226 pm8001_ha->outbnd_q_tbl[i].base_virt = 227 (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr; 228 pm8001_ha->outbnd_q_tbl[i].total_length = 229 pm8001_ha->memoryMap.region[OB].total_len; 230 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = 231 pm8001_ha->memoryMap.region[PI].phys_addr_hi; 232 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = 233 pm8001_ha->memoryMap.region[PI].phys_addr_lo; 234 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = 235 0 | (10 << 16) | (0 << 24); 236 pm8001_ha->outbnd_q_tbl[i].pi_virt = 237 pm8001_ha->memoryMap.region[PI].virt_ptr; 238 offsetob = i * 0x24; 239 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = 240 get_pci_bar_index(pm8001_mr32(addressob, 241 offsetob + 0x14)); 242 pm8001_ha->outbnd_q_tbl[i].ci_offset = 243 pm8001_mr32(addressob, (offsetob + 0x18)); 244 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; 245 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; 246 } 247} 248 249/** 250 * update_main_config_table - update the main default table to the HBA. 251 * @pm8001_ha: our hba card information 252 */ 253static void __devinit 254update_main_config_table(struct pm8001_hba_info *pm8001_ha) 255{ 256 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; 257 pm8001_mw32(address, 0x24, 258 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd); 259 pm8001_mw32(address, 0x28, 260 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3); 261 pm8001_mw32(address, 0x2C, 262 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7); 263 pm8001_mw32(address, 0x30, 264 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3); 265 pm8001_mw32(address, 0x34, 266 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7); 267 pm8001_mw32(address, 0x38, 268 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3); 269 pm8001_mw32(address, 0x3C, 270 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7); 271 pm8001_mw32(address, 0x40, 272 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3); 273 pm8001_mw32(address, 0x44, 274 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7); 275 pm8001_mw32(address, 0x48, 276 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3); 277 pm8001_mw32(address, 0x4C, 278 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7); 279 pm8001_mw32(address, 0x50, 280 pm8001_ha->main_cfg_tbl.upper_event_log_addr); 281 pm8001_mw32(address, 0x54, 282 pm8001_ha->main_cfg_tbl.lower_event_log_addr); 283 pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size); 284 pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option); 285 pm8001_mw32(address, 0x60, 286 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr); 287 pm8001_mw32(address, 0x64, 288 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr); 289 pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size); 290 pm8001_mw32(address, 0x6C, 291 pm8001_ha->main_cfg_tbl.iop_event_log_option); 292 pm8001_mw32(address, 0x70, 293 pm8001_ha->main_cfg_tbl.fatal_err_interrupt); 294} 295 296/** 297 * update_inbnd_queue_table - update the inbound queue table to the HBA. 298 * @pm8001_ha: our hba card information 299 */ 300static void __devinit 301update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number) 302{ 303 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; 304 u16 offset = number * 0x20; 305 pm8001_mw32(address, offset + 0x00, 306 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); 307 pm8001_mw32(address, offset + 0x04, 308 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); 309 pm8001_mw32(address, offset + 0x08, 310 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); 311 pm8001_mw32(address, offset + 0x0C, 312 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); 313 pm8001_mw32(address, offset + 0x10, 314 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); 315} 316 317/** 318 * update_outbnd_queue_table - update the outbound queue table to the HBA. 319 * @pm8001_ha: our hba card information 320 */ 321static void __devinit 322update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number) 323{ 324 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; 325 u16 offset = number * 0x24; 326 pm8001_mw32(address, offset + 0x00, 327 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); 328 pm8001_mw32(address, offset + 0x04, 329 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); 330 pm8001_mw32(address, offset + 0x08, 331 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); 332 pm8001_mw32(address, offset + 0x0C, 333 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); 334 pm8001_mw32(address, offset + 0x10, 335 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); 336 pm8001_mw32(address, offset + 0x1C, 337 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); 338} 339 340/** 341 * pm8001_bar4_shift - function is called to shift BAR base address 342 * @pm8001_ha : our hba card infomation 343 * @shiftValue : shifting value in memory bar. 344 */ 345int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue) 346{ 347 u32 regVal; 348 unsigned long start; 349 350 /* program the inbound AXI translation Lower Address */ 351 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); 352 353 /* confirm the setting is written */ 354 start = jiffies + HZ; /* 1 sec */ 355 do { 356 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); 357 } while ((regVal != shiftValue) && time_before(jiffies, start)); 358 359 if (regVal != shiftValue) { 360 PM8001_INIT_DBG(pm8001_ha, 361 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW" 362 " = 0x%x\n", regVal)); 363 return -1; 364 } 365 return 0; 366} 367 368/** 369 * mpi_set_phys_g3_with_ssc 370 * @pm8001_ha: our hba card information 371 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc. 372 */ 373static void __devinit 374mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit) 375{ 376 u32 value, offset, i; 377 unsigned long flags; 378 379#define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000 380#define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000 381#define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074 382#define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074 383#define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12 384#define PHY_G3_WITH_SSC_BIT_SHIFT 13 385#define SNW3_PHY_CAPABILITIES_PARITY 31 386 387 /* 388 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3) 389 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7) 390 */ 391 spin_lock_irqsave(&pm8001_ha->lock, flags); 392 if (-1 == pm8001_bar4_shift(pm8001_ha, 393 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) { 394 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 395 return; 396 } 397 398 for (i = 0; i < 4; i++) { 399 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i; 400 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 401 } 402 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */ 403 if (-1 == pm8001_bar4_shift(pm8001_ha, 404 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) { 405 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 406 return; 407 } 408 for (i = 4; i < 8; i++) { 409 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 410 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); 411 } 412 /************************************************************* 413 Change the SSC upspreading value to 0x0 so that upspreading is disabled. 414 Device MABC SMOD0 Controls 415 Address: (via MEMBASE-III): 416 Using shifted destination address 0x0_0000: with Offset 0xD8 417 418 31:28 R/W Reserved Do not change 419 27:24 R/W SAS_SMOD_SPRDUP 0000 420 23:20 R/W SAS_SMOD_SPRDDN 0000 421 19:0 R/W Reserved Do not change 422 Upon power-up this register will read as 0x8990c016, 423 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000 424 so that the written value will be 0x8090c016. 425 This will ensure only down-spreading SSC is enabled on the SPC. 426 *************************************************************/ 427 value = pm8001_cr32(pm8001_ha, 2, 0xd8); 428 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); 429 430 /*set the shifted destination address to 0x0 to avoid error operation */ 431 pm8001_bar4_shift(pm8001_ha, 0x0); 432 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 433 return; 434} 435 436/** 437 * mpi_set_open_retry_interval_reg 438 * @pm8001_ha: our hba card information 439 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us. 440 */ 441static void __devinit 442mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha, 443 u32 interval) 444{ 445 u32 offset; 446 u32 value; 447 u32 i; 448 unsigned long flags; 449 450#define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000 451#define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000 452#define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4 453#define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4 454#define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF 455 456 value = interval & OPEN_RETRY_INTERVAL_REG_MASK; 457 spin_lock_irqsave(&pm8001_ha->lock, flags); 458 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/ 459 if (-1 == pm8001_bar4_shift(pm8001_ha, 460 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) { 461 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 462 return; 463 } 464 for (i = 0; i < 4; i++) { 465 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i; 466 pm8001_cw32(pm8001_ha, 2, offset, value); 467 } 468 469 if (-1 == pm8001_bar4_shift(pm8001_ha, 470 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) { 471 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 472 return; 473 } 474 for (i = 4; i < 8; i++) { 475 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4); 476 pm8001_cw32(pm8001_ha, 2, offset, value); 477 } 478 /*set the shifted destination address to 0x0 to avoid error operation */ 479 pm8001_bar4_shift(pm8001_ha, 0x0); 480 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 481 return; 482} 483 484/** 485 * mpi_init_check - check firmware initialization status. 486 * @pm8001_ha: our hba card information 487 */ 488static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) 489{ 490 u32 max_wait_count; 491 u32 value; 492 u32 gst_len_mpistate; 493 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the 494 table is updated */ 495 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); 496 /* wait until Inbound DoorBell Clear Register toggled */ 497 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 498 do { 499 udelay(1); 500 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 501 value &= SPC_MSGU_CFG_TABLE_UPDATE; 502 } while ((value != 0) && (--max_wait_count)); 503 504 if (!max_wait_count) 505 return -1; 506 /* check the MPI-State for initialization */ 507 gst_len_mpistate = 508 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 509 GST_GSTLEN_MPIS_OFFSET); 510 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK)) 511 return -1; 512 /* check MPI Initialization error */ 513 gst_len_mpistate = gst_len_mpistate >> 16; 514 if (0x0000 != gst_len_mpistate) 515 return -1; 516 return 0; 517} 518 519/** 520 * check_fw_ready - The LLDD check if the FW is ready, if not, return error. 521 * @pm8001_ha: our hba card information 522 */ 523static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) 524{ 525 u32 value, value1; 526 u32 max_wait_count; 527 /* check error state */ 528 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 529 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 530 /* check AAP error */ 531 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) { 532 /* error state */ 533 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 534 return -1; 535 } 536 537 /* check IOP error */ 538 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) { 539 /* error state */ 540 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); 541 return -1; 542 } 543 544 /* bit 4-31 of scratch pad1 should be zeros if it is not 545 in error state*/ 546 if (value & SCRATCH_PAD1_STATE_MASK) { 547 /* error case */ 548 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); 549 return -1; 550 } 551 552 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not 553 in error state */ 554 if (value1 & SCRATCH_PAD2_STATE_MASK) { 555 /* error case */ 556 return -1; 557 } 558 559 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */ 560 561 /* wait until scratch pad 1 and 2 registers in ready state */ 562 do { 563 udelay(1); 564 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 565 & SCRATCH_PAD1_RDY; 566 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 567 & SCRATCH_PAD2_RDY; 568 if ((--max_wait_count) == 0) 569 return -1; 570 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY)); 571 return 0; 572} 573 574static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) 575{ 576 void __iomem *base_addr; 577 u32 value; 578 u32 offset; 579 u32 pcibar; 580 u32 pcilogic; 581 582 value = pm8001_cr32(pm8001_ha, 0, 0x44); 583 offset = value & 0x03FFFFFF; 584 PM8001_INIT_DBG(pm8001_ha, 585 pm8001_printk("Scratchpad 0 Offset: %x\n", offset)); 586 pcilogic = (value & 0xFC000000) >> 26; 587 pcibar = get_pci_bar_index(pcilogic); 588 PM8001_INIT_DBG(pm8001_ha, 589 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar)); 590 pm8001_ha->main_cfg_tbl_addr = base_addr = 591 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; 592 pm8001_ha->general_stat_tbl_addr = 593 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); 594 pm8001_ha->inbnd_q_tbl_addr = 595 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); 596 pm8001_ha->outbnd_q_tbl_addr = 597 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); 598} 599 600/** 601 * pm8001_chip_init - the main init function that initialize whole PM8001 chip. 602 * @pm8001_ha: our hba card information 603 */ 604static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha) 605{ 606 /* check the firmware status */ 607 if (-1 == check_fw_ready(pm8001_ha)) { 608 PM8001_FAIL_DBG(pm8001_ha, 609 pm8001_printk("Firmware is not ready!\n")); 610 return -EBUSY; 611 } 612 613 /* Initialize pci space address eg: mpi offset */ 614 init_pci_device_addresses(pm8001_ha); 615 init_default_table_values(pm8001_ha); 616 read_main_config_table(pm8001_ha); 617 read_general_status_table(pm8001_ha); 618 read_inbnd_queue_table(pm8001_ha); 619 read_outbnd_queue_table(pm8001_ha); 620 /* update main config table ,inbound table and outbound table */ 621 update_main_config_table(pm8001_ha); 622 update_inbnd_queue_table(pm8001_ha, 0); 623 update_outbnd_queue_table(pm8001_ha, 0); 624 mpi_set_phys_g3_with_ssc(pm8001_ha, 0); 625 /* 7->130ms, 34->500ms, 119->1.5s */ 626 mpi_set_open_retry_interval_reg(pm8001_ha, 119); 627 /* notify firmware update finished and check initialization status */ 628 if (0 == mpi_init_check(pm8001_ha)) { 629 PM8001_INIT_DBG(pm8001_ha, 630 pm8001_printk("MPI initialize successful!\n")); 631 } else 632 return -EBUSY; 633 /*This register is a 16-bit timer with a resolution of 1us. This is the 634 timer used for interrupt delay/coalescing in the PCIe Application Layer. 635 Zero is not a valid value. A value of 1 in the register will cause the 636 interrupts to be normal. A value greater than 1 will cause coalescing 637 delays.*/ 638 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); 639 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); 640 return 0; 641} 642 643static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) 644{ 645 u32 max_wait_count; 646 u32 value; 647 u32 gst_len_mpistate; 648 init_pci_device_addresses(pm8001_ha); 649 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the 650 table is stop */ 651 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); 652 653 /* wait until Inbound DoorBell Clear Register toggled */ 654 max_wait_count = 1 * 1000 * 1000;/* 1 sec */ 655 do { 656 udelay(1); 657 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); 658 value &= SPC_MSGU_CFG_TABLE_RESET; 659 } while ((value != 0) && (--max_wait_count)); 660 661 if (!max_wait_count) { 662 PM8001_FAIL_DBG(pm8001_ha, 663 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value)); 664 return -1; 665 } 666 667 /* check the MPI-State for termination in progress */ 668 /* wait until Inbound DoorBell Clear Register toggled */ 669 max_wait_count = 1 * 1000 * 1000; /* 1 sec */ 670 do { 671 udelay(1); 672 gst_len_mpistate = 673 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, 674 GST_GSTLEN_MPIS_OFFSET); 675 if (GST_MPI_STATE_UNINIT == 676 (gst_len_mpistate & GST_MPI_STATE_MASK)) 677 break; 678 } while (--max_wait_count); 679 if (!max_wait_count) { 680 PM8001_FAIL_DBG(pm8001_ha, 681 pm8001_printk(" TIME OUT MPI State = 0x%x\n", 682 gst_len_mpistate & GST_MPI_STATE_MASK)); 683 return -1; 684 } 685 return 0; 686} 687 688/** 689 * soft_reset_ready_check - Function to check FW is ready for soft reset. 690 * @pm8001_ha: our hba card information 691 */ 692static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha) 693{ 694 u32 regVal, regVal1, regVal2; 695 if (mpi_uninit_check(pm8001_ha) != 0) { 696 PM8001_FAIL_DBG(pm8001_ha, 697 pm8001_printk("MPI state is not ready\n")); 698 return -1; 699 } 700 /* read the scratch pad 2 register bit 2 */ 701 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) 702 & SCRATCH_PAD2_FWRDY_RST; 703 if (regVal == SCRATCH_PAD2_FWRDY_RST) { 704 PM8001_INIT_DBG(pm8001_ha, 705 pm8001_printk("Firmware is ready for reset .\n")); 706 } else { 707 unsigned long flags; 708 /* Trigger NMI twice via RB6 */ 709 spin_lock_irqsave(&pm8001_ha->lock, flags); 710 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) { 711 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 712 PM8001_FAIL_DBG(pm8001_ha, 713 pm8001_printk("Shift Bar4 to 0x%x failed\n", 714 RB6_ACCESS_REG)); 715 return -1; 716 } 717 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, 718 RB6_MAGIC_NUMBER_RST); 719 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); 720 /* wait for 100 ms */ 721 mdelay(100); 722 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & 723 SCRATCH_PAD2_FWRDY_RST; 724 if (regVal != SCRATCH_PAD2_FWRDY_RST) { 725 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 726 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 727 PM8001_FAIL_DBG(pm8001_ha, 728 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1" 729 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", 730 regVal1, regVal2)); 731 PM8001_FAIL_DBG(pm8001_ha, 732 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 733 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0))); 734 PM8001_FAIL_DBG(pm8001_ha, 735 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 736 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3))); 737 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 738 return -1; 739 } 740 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 741 } 742 return 0; 743} 744 745/** 746 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 747 * the FW register status to the originated status. 748 * @pm8001_ha: our hba card information 749 * @signature: signature in host scratch pad0 register. 750 */ 751static int 752pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature) 753{ 754 u32 regVal, toggleVal; 755 u32 max_wait_count; 756 u32 regVal1, regVal2, regVal3; 757 unsigned long flags; 758 759 /* step1: Check FW is ready for soft reset */ 760 if (soft_reset_ready_check(pm8001_ha) != 0) { 761 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n")); 762 return -1; 763 } 764 765 /* step 2: clear NMI status register on AAP1 and IOP, write the same 766 value to clear */ 767 /* map 0x60000 to BAR4(0x20), BAR2(win) */ 768 spin_lock_irqsave(&pm8001_ha->lock, flags); 769 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) { 770 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 771 PM8001_FAIL_DBG(pm8001_ha, 772 pm8001_printk("Shift Bar4 to 0x%x failed\n", 773 MBIC_AAP1_ADDR_BASE)); 774 return -1; 775 } 776 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); 777 PM8001_INIT_DBG(pm8001_ha, 778 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal)); 779 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); 780 /* map 0x70000 to BAR4(0x20), BAR2(win) */ 781 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) { 782 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 783 PM8001_FAIL_DBG(pm8001_ha, 784 pm8001_printk("Shift Bar4 to 0x%x failed\n", 785 MBIC_IOP_ADDR_BASE)); 786 return -1; 787 } 788 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); 789 PM8001_INIT_DBG(pm8001_ha, 790 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal)); 791 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); 792 793 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); 794 PM8001_INIT_DBG(pm8001_ha, 795 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal)); 796 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); 797 798 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); 799 PM8001_INIT_DBG(pm8001_ha, 800 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal)); 801 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); 802 803 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); 804 PM8001_INIT_DBG(pm8001_ha, 805 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal)); 806 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); 807 808 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); 809 PM8001_INIT_DBG(pm8001_ha, 810 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal)); 811 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); 812 813 /* read the scratch pad 1 register bit 2 */ 814 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) 815 & SCRATCH_PAD1_RST; 816 toggleVal = regVal ^ SCRATCH_PAD1_RST; 817 818 /* set signature in host scratch pad0 register to tell SPC that the 819 host performs the soft reset */ 820 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); 821 822 /* read required registers for confirmming */ 823 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 824 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 825 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 826 PM8001_FAIL_DBG(pm8001_ha, 827 pm8001_printk("Shift Bar4 to 0x%x failed\n", 828 GSM_ADDR_BASE)); 829 return -1; 830 } 831 PM8001_INIT_DBG(pm8001_ha, 832 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and" 833 " Reset = 0x%x\n", 834 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 835 836 /* step 3: host read GSM Configuration and Reset register */ 837 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 838 /* Put those bits to low */ 839 /* GSM XCBI offset = 0x70 0000 840 0x00 Bit 13 COM_SLV_SW_RSTB 1 841 0x00 Bit 12 QSSP_SW_RSTB 1 842 0x00 Bit 11 RAAE_SW_RSTB 1 843 0x00 Bit 9 RB_1_SW_RSTB 1 844 0x00 Bit 8 SM_SW_RSTB 1 845 */ 846 regVal &= ~(0x00003b00); 847 /* host write GSM Configuration and Reset register */ 848 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 849 PM8001_INIT_DBG(pm8001_ha, 850 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM " 851 "Configuration and Reset is set to = 0x%x\n", 852 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 853 854 /* step 4: */ 855 /* disable GSM - Read Address Parity Check */ 856 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 857 PM8001_INIT_DBG(pm8001_ha, 858 pm8001_printk("GSM 0x700038 - Read Address Parity Check " 859 "Enable = 0x%x\n", regVal1)); 860 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); 861 PM8001_INIT_DBG(pm8001_ha, 862 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" 863 "is set to = 0x%x\n", 864 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); 865 866 /* disable GSM - Write Address Parity Check */ 867 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 868 PM8001_INIT_DBG(pm8001_ha, 869 pm8001_printk("GSM 0x700040 - Write Address Parity Check" 870 " Enable = 0x%x\n", regVal2)); 871 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); 872 PM8001_INIT_DBG(pm8001_ha, 873 pm8001_printk("GSM 0x700040 - Write Address Parity Check " 874 "Enable is set to = 0x%x\n", 875 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); 876 877 /* disable GSM - Write Data Parity Check */ 878 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 879 PM8001_INIT_DBG(pm8001_ha, 880 pm8001_printk("GSM 0x300048 - Write Data Parity Check" 881 " Enable = 0x%x\n", regVal3)); 882 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); 883 PM8001_INIT_DBG(pm8001_ha, 884 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable" 885 "is set to = 0x%x\n", 886 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); 887 888 /* step 5: delay 10 usec */ 889 udelay(10); 890 /* step 5-b: set GPIO-0 output control to tristate anyway */ 891 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) { 892 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 893 PM8001_INIT_DBG(pm8001_ha, 894 pm8001_printk("Shift Bar4 to 0x%x failed\n", 895 GPIO_ADDR_BASE)); 896 return -1; 897 } 898 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); 899 PM8001_INIT_DBG(pm8001_ha, 900 pm8001_printk("GPIO Output Control Register:" 901 " = 0x%x\n", regVal)); 902 /* set GPIO-0 output control to tri-state */ 903 regVal &= 0xFFFFFFFC; 904 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); 905 906 /* Step 6: Reset the IOP and AAP1 */ 907 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 908 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 909 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 910 PM8001_FAIL_DBG(pm8001_ha, 911 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", 912 SPC_TOP_LEVEL_ADDR_BASE)); 913 return -1; 914 } 915 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 916 PM8001_INIT_DBG(pm8001_ha, 917 pm8001_printk("Top Register before resetting IOP/AAP1" 918 ":= 0x%x\n", regVal)); 919 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 920 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 921 922 /* step 7: Reset the BDMA/OSSP */ 923 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 924 PM8001_INIT_DBG(pm8001_ha, 925 pm8001_printk("Top Register before resetting BDMA/OSSP" 926 ": = 0x%x\n", regVal)); 927 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 928 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 929 930 /* step 8: delay 10 usec */ 931 udelay(10); 932 933 /* step 9: bring the BDMA and OSSP out of reset */ 934 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 935 PM8001_INIT_DBG(pm8001_ha, 936 pm8001_printk("Top Register before bringing up BDMA/OSSP" 937 ":= 0x%x\n", regVal)); 938 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP); 939 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 940 941 /* step 10: delay 10 usec */ 942 udelay(10); 943 944 /* step 11: reads and sets the GSM Configuration and Reset Register */ 945 /* map 0x0700000 to BAR4(0x20), BAR2(win) */ 946 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { 947 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 948 PM8001_FAIL_DBG(pm8001_ha, 949 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n", 950 GSM_ADDR_BASE)); 951 return -1; 952 } 953 PM8001_INIT_DBG(pm8001_ha, 954 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and " 955 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 956 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); 957 /* Put those bits to high */ 958 /* GSM XCBI offset = 0x70 0000 959 0x00 Bit 13 COM_SLV_SW_RSTB 1 960 0x00 Bit 12 QSSP_SW_RSTB 1 961 0x00 Bit 11 RAAE_SW_RSTB 1 962 0x00 Bit 9 RB_1_SW_RSTB 1 963 0x00 Bit 8 SM_SW_RSTB 1 964 */ 965 regVal |= (GSM_CONFIG_RESET_VALUE); 966 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); 967 PM8001_INIT_DBG(pm8001_ha, 968 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM" 969 " Configuration and Reset is set to = 0x%x\n", 970 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET))); 971 972 /* step 12: Restore GSM - Read Address Parity Check */ 973 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); 974 /* just for debugging */ 975 PM8001_INIT_DBG(pm8001_ha, 976 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable" 977 " = 0x%x\n", regVal)); 978 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); 979 PM8001_INIT_DBG(pm8001_ha, 980 pm8001_printk("GSM 0x700038 - Read Address Parity" 981 " Check Enable is set to = 0x%x\n", 982 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK))); 983 /* Restore GSM - Write Address Parity Check */ 984 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); 985 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); 986 PM8001_INIT_DBG(pm8001_ha, 987 pm8001_printk("GSM 0x700040 - Write Address Parity Check" 988 " Enable is set to = 0x%x\n", 989 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK))); 990 /* Restore GSM - Write Data Parity Check */ 991 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); 992 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); 993 PM8001_INIT_DBG(pm8001_ha, 994 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable" 995 "is set to = 0x%x\n", 996 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK))); 997 998 /* step 13: bring the IOP and AAP1 out of reset */ 999 /* map 0x00000 to BAR4(0x20), BAR2(win) */ 1000 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { 1001 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1002 PM8001_FAIL_DBG(pm8001_ha, 1003 pm8001_printk("Shift Bar4 to 0x%x failed\n", 1004 SPC_TOP_LEVEL_ADDR_BASE)); 1005 return -1; 1006 } 1007 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); 1008 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS); 1009 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); 1010 1011 /* step 14: delay 10 usec - Normal Mode */ 1012 udelay(10); 1013 /* check Soft Reset Normal mode or Soft Reset HDA mode */ 1014 if (signature == SPC_SOFT_RESET_SIGNATURE) { 1015 /* step 15 (Normal Mode): wait until scratch pad1 register 1016 bit 2 toggled */ 1017 max_wait_count = 2 * 1000 * 1000;/* 2 sec */ 1018 do { 1019 udelay(1); 1020 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & 1021 SCRATCH_PAD1_RST; 1022 } while ((regVal != toggleVal) && (--max_wait_count)); 1023 1024 if (!max_wait_count) { 1025 regVal = pm8001_cr32(pm8001_ha, 0, 1026 MSGU_SCRATCH_PAD_1); 1027 PM8001_FAIL_DBG(pm8001_ha, 1028 pm8001_printk("TIMEOUT : ToggleVal 0x%x," 1029 "MSGU_SCRATCH_PAD1 = 0x%x\n", 1030 toggleVal, regVal)); 1031 PM8001_FAIL_DBG(pm8001_ha, 1032 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 1033 pm8001_cr32(pm8001_ha, 0, 1034 MSGU_SCRATCH_PAD_0))); 1035 PM8001_FAIL_DBG(pm8001_ha, 1036 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n", 1037 pm8001_cr32(pm8001_ha, 0, 1038 MSGU_SCRATCH_PAD_2))); 1039 PM8001_FAIL_DBG(pm8001_ha, 1040 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 1041 pm8001_cr32(pm8001_ha, 0, 1042 MSGU_SCRATCH_PAD_3))); 1043 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1044 return -1; 1045 } 1046 1047 /* step 16 (Normal) - Clear ODMR and ODCR */ 1048 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1049 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1050 1051 /* step 17 (Normal Mode): wait for the FW and IOP to get 1052 ready - 1 sec timeout */ 1053 /* Wait for the SPC Configuration Table to be ready */ 1054 if (check_fw_ready(pm8001_ha) == -1) { 1055 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); 1056 /* return error if MPI Configuration Table not ready */ 1057 PM8001_INIT_DBG(pm8001_ha, 1058 pm8001_printk("FW not ready SCRATCH_PAD1" 1059 " = 0x%x\n", regVal)); 1060 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); 1061 /* return error if MPI Configuration Table not ready */ 1062 PM8001_INIT_DBG(pm8001_ha, 1063 pm8001_printk("FW not ready SCRATCH_PAD2" 1064 " = 0x%x\n", regVal)); 1065 PM8001_INIT_DBG(pm8001_ha, 1066 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n", 1067 pm8001_cr32(pm8001_ha, 0, 1068 MSGU_SCRATCH_PAD_0))); 1069 PM8001_INIT_DBG(pm8001_ha, 1070 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n", 1071 pm8001_cr32(pm8001_ha, 0, 1072 MSGU_SCRATCH_PAD_3))); 1073 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1074 return -1; 1075 } 1076 } 1077 pm8001_bar4_shift(pm8001_ha, 0); 1078 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1079 1080 PM8001_INIT_DBG(pm8001_ha, 1081 pm8001_printk("SPC soft reset Complete\n")); 1082 return 0; 1083} 1084 1085static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) 1086{ 1087 u32 i; 1088 u32 regVal; 1089 PM8001_INIT_DBG(pm8001_ha, 1090 pm8001_printk("chip reset start\n")); 1091 1092 /* do SPC chip reset. */ 1093 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1094 regVal &= ~(SPC_REG_RESET_DEVICE); 1095 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1096 1097 /* delay 10 usec */ 1098 udelay(10); 1099 1100 /* bring chip reset out of reset */ 1101 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); 1102 regVal |= SPC_REG_RESET_DEVICE; 1103 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); 1104 1105 /* delay 10 usec */ 1106 udelay(10); 1107 1108 /* wait for 20 msec until the firmware gets reloaded */ 1109 i = 20; 1110 do { 1111 mdelay(1); 1112 } while ((--i) != 0); 1113 1114 PM8001_INIT_DBG(pm8001_ha, 1115 pm8001_printk("chip reset finished\n")); 1116} 1117 1118/** 1119 * pm8001_chip_iounmap - which maped when initialized. 1120 * @pm8001_ha: our hba card information 1121 */ 1122static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha) 1123{ 1124 s8 bar, logical = 0; 1125 for (bar = 0; bar < 6; bar++) { 1126 /* 1127 ** logical BARs for SPC: 1128 ** bar 0 and 1 - logical BAR0 1129 ** bar 2 and 3 - logical BAR1 1130 ** bar4 - logical BAR2 1131 ** bar5 - logical BAR3 1132 ** Skip the appropriate assignments: 1133 */ 1134 if ((bar == 1) || (bar == 3)) 1135 continue; 1136 if (pm8001_ha->io_mem[logical].memvirtaddr) { 1137 iounmap(pm8001_ha->io_mem[logical].memvirtaddr); 1138 logical++; 1139 } 1140 } 1141} 1142 1143/** 1144 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1145 * @pm8001_ha: our hba card information 1146 */ 1147static void 1148pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1149{ 1150 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); 1151 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); 1152} 1153 1154 /** 1155 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1156 * @pm8001_ha: our hba card information 1157 */ 1158static void 1159pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1160{ 1161 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); 1162} 1163 1164/** 1165 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt 1166 * @pm8001_ha: our hba card information 1167 */ 1168static void 1169pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha, 1170 u32 int_vec_idx) 1171{ 1172 u32 msi_index; 1173 u32 value; 1174 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1175 msi_index += MSIX_TABLE_BASE; 1176 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); 1177 value = (1 << int_vec_idx); 1178 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); 1179 1180} 1181 1182/** 1183 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt 1184 * @pm8001_ha: our hba card information 1185 */ 1186static void 1187pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha, 1188 u32 int_vec_idx) 1189{ 1190 u32 msi_index; 1191 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE; 1192 msi_index += MSIX_TABLE_BASE; 1193 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); 1194} 1195 1196/** 1197 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt 1198 * @pm8001_ha: our hba card information 1199 */ 1200static void 1201pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha) 1202{ 1203#ifdef PM8001_USE_MSIX 1204 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0); 1205 return; 1206#endif 1207 pm8001_chip_intx_interrupt_enable(pm8001_ha); 1208 1209} 1210 1211/** 1212 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt 1213 * @pm8001_ha: our hba card information 1214 */ 1215static void 1216pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha) 1217{ 1218#ifdef PM8001_USE_MSIX 1219 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0); 1220 return; 1221#endif 1222 pm8001_chip_intx_interrupt_disable(pm8001_ha); 1223 1224} 1225 1226/** 1227 * mpi_msg_free_get- get the free message buffer for transfer inbound queue. 1228 * @circularQ: the inbound queue we want to transfer to HBA. 1229 * @messageSize: the message size of this transfer, normally it is 64 bytes 1230 * @messagePtr: the pointer to message. 1231 */ 1232static int mpi_msg_free_get(struct inbound_queue_table *circularQ, 1233 u16 messageSize, void **messagePtr) 1234{ 1235 u32 offset, consumer_index; 1236 struct mpi_msg_hdr *msgHeader; 1237 u8 bcCount = 1; /* only support single buffer */ 1238 1239 /* Checks is the requested message size can be allocated in this queue*/ 1240 if (messageSize > 64) { 1241 *messagePtr = NULL; 1242 return -1; 1243 } 1244 1245 /* Stores the new consumer index */ 1246 consumer_index = pm8001_read_32(circularQ->ci_virt); 1247 circularQ->consumer_index = cpu_to_le32(consumer_index); 1248 if (((circularQ->producer_idx + bcCount) % 256) == 1249 le32_to_cpu(circularQ->consumer_index)) { 1250 *messagePtr = NULL; 1251 return -1; 1252 } 1253 /* get memory IOMB buffer address */ 1254 offset = circularQ->producer_idx * 64; 1255 /* increment to next bcCount element */ 1256 circularQ->producer_idx = (circularQ->producer_idx + bcCount) % 256; 1257 /* Adds that distance to the base of the region virtual address plus 1258 the message header size*/ 1259 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset); 1260 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr); 1261 return 0; 1262} 1263 1264/** 1265 * mpi_build_cmd- build the message queue for transfer, update the PI to FW 1266 * to tell the fw to get this message from IOMB. 1267 * @pm8001_ha: our hba card information 1268 * @circularQ: the inbound queue we want to transfer to HBA. 1269 * @opCode: the operation code represents commands which LLDD and fw recognized. 1270 * @payload: the command payload of each operation command. 1271 */ 1272static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, 1273 struct inbound_queue_table *circularQ, 1274 u32 opCode, void *payload) 1275{ 1276 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02; 1277 u32 responseQueue = 0; 1278 void *pMessage; 1279 1280 if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) { 1281 PM8001_IO_DBG(pm8001_ha, 1282 pm8001_printk("No free mpi buffer\n")); 1283 return -1; 1284 } 1285 BUG_ON(!payload); 1286 /*Copy to the payload*/ 1287 memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr))); 1288 1289 /*Build the header*/ 1290 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24) 1291 | ((responseQueue & 0x3F) << 16) 1292 | ((category & 0xF) << 12) | (opCode & 0xFFF)); 1293 1294 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header)); 1295 /*Update the PI to the firmware*/ 1296 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, 1297 circularQ->pi_offset, circularQ->producer_idx); 1298 PM8001_IO_DBG(pm8001_ha, 1299 pm8001_printk("after PI= %d CI= %d\n", circularQ->producer_idx, 1300 circularQ->consumer_index)); 1301 return 0; 1302} 1303 1304static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, 1305 struct outbound_queue_table *circularQ, u8 bc) 1306{ 1307 u32 producer_index; 1308 struct mpi_msg_hdr *msgHeader; 1309 struct mpi_msg_hdr *pOutBoundMsgHeader; 1310 1311 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr)); 1312 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + 1313 circularQ->consumer_idx * 64); 1314 if (pOutBoundMsgHeader != msgHeader) { 1315 PM8001_FAIL_DBG(pm8001_ha, 1316 pm8001_printk("consumer_idx = %d msgHeader = %p\n", 1317 circularQ->consumer_idx, msgHeader)); 1318 1319 /* Update the producer index from SPC */ 1320 producer_index = pm8001_read_32(circularQ->pi_virt); 1321 circularQ->producer_index = cpu_to_le32(producer_index); 1322 PM8001_FAIL_DBG(pm8001_ha, 1323 pm8001_printk("consumer_idx = %d producer_index = %d" 1324 "msgHeader = %p\n", circularQ->consumer_idx, 1325 circularQ->producer_index, msgHeader)); 1326 return 0; 1327 } 1328 /* free the circular queue buffer elements associated with the message*/ 1329 circularQ->consumer_idx = (circularQ->consumer_idx + bc) % 256; 1330 /* update the CI of outbound queue */ 1331 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, 1332 circularQ->consumer_idx); 1333 /* Update the producer index from SPC*/ 1334 producer_index = pm8001_read_32(circularQ->pi_virt); 1335 circularQ->producer_index = cpu_to_le32(producer_index); 1336 PM8001_IO_DBG(pm8001_ha, 1337 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx, 1338 circularQ->producer_index)); 1339 return 0; 1340} 1341 1342/** 1343 * mpi_msg_consume- get the MPI message from outbound queue message table. 1344 * @pm8001_ha: our hba card information 1345 * @circularQ: the outbound queue table. 1346 * @messagePtr1: the message contents of this outbound message. 1347 * @pBC: the message size. 1348 */ 1349static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, 1350 struct outbound_queue_table *circularQ, 1351 void **messagePtr1, u8 *pBC) 1352{ 1353 struct mpi_msg_hdr *msgHeader; 1354 __le32 msgHeader_tmp; 1355 u32 header_tmp; 1356 do { 1357 /* If there are not-yet-delivered messages ... */ 1358 if (le32_to_cpu(circularQ->producer_index) 1359 != circularQ->consumer_idx) { 1360 /*Get the pointer to the circular queue buffer element*/ 1361 msgHeader = (struct mpi_msg_hdr *) 1362 (circularQ->base_virt + 1363 circularQ->consumer_idx * 64); 1364 /* read header */ 1365 header_tmp = pm8001_read_32(msgHeader); 1366 msgHeader_tmp = cpu_to_le32(header_tmp); 1367 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) { 1368 if (OPC_OUB_SKIP_ENTRY != 1369 (le32_to_cpu(msgHeader_tmp) & 0xfff)) { 1370 *messagePtr1 = 1371 ((u8 *)msgHeader) + 1372 sizeof(struct mpi_msg_hdr); 1373 *pBC = (u8)((le32_to_cpu(msgHeader_tmp) 1374 >> 24) & 0x1f); 1375 PM8001_IO_DBG(pm8001_ha, 1376 pm8001_printk(": CI=%d PI=%d " 1377 "msgHeader=%x\n", 1378 circularQ->consumer_idx, 1379 circularQ->producer_index, 1380 msgHeader_tmp)); 1381 return MPI_IO_STATUS_SUCCESS; 1382 } else { 1383 circularQ->consumer_idx = 1384 (circularQ->consumer_idx + 1385 ((le32_to_cpu(msgHeader_tmp) 1386 >> 24) & 0x1f)) % 256; 1387 msgHeader_tmp = 0; 1388 pm8001_write_32(msgHeader, 0, 0); 1389 /* update the CI of outbound queue */ 1390 pm8001_cw32(pm8001_ha, 1391 circularQ->ci_pci_bar, 1392 circularQ->ci_offset, 1393 circularQ->consumer_idx); 1394 } 1395 } else { 1396 circularQ->consumer_idx = 1397 (circularQ->consumer_idx + 1398 ((le32_to_cpu(msgHeader_tmp) >> 24) & 1399 0x1f)) % 256; 1400 msgHeader_tmp = 0; 1401 pm8001_write_32(msgHeader, 0, 0); 1402 /* update the CI of outbound queue */ 1403 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, 1404 circularQ->ci_offset, 1405 circularQ->consumer_idx); 1406 return MPI_IO_STATUS_FAIL; 1407 } 1408 } else { 1409 u32 producer_index; 1410 void *pi_virt = circularQ->pi_virt; 1411 /* Update the producer index from SPC */ 1412 producer_index = pm8001_read_32(pi_virt); 1413 circularQ->producer_index = cpu_to_le32(producer_index); 1414 } 1415 } while (le32_to_cpu(circularQ->producer_index) != 1416 circularQ->consumer_idx); 1417 /* while we don't have any more not-yet-delivered message */ 1418 /* report empty */ 1419 return MPI_IO_STATUS_BUSY; 1420} 1421 1422static void pm8001_work_fn(struct work_struct *work) 1423{ 1424 struct pm8001_work *pw = container_of(work, struct pm8001_work, work); 1425 struct pm8001_device *pm8001_dev; 1426 struct domain_device *dev; 1427 1428 /* 1429 * So far, all users of this stash an associated structure here. 1430 * If we get here, and this pointer is null, then the action 1431 * was cancelled. This nullification happens when the device 1432 * goes away. 1433 */ 1434 pm8001_dev = pw->data; /* Most stash device structure */ 1435 if ((pm8001_dev == NULL) 1436 || ((pw->handler != IO_XFER_ERROR_BREAK) 1437 && (pm8001_dev->dev_type == NO_DEVICE))) { 1438 kfree(pw); 1439 return; 1440 } 1441 1442 switch (pw->handler) { 1443 case IO_XFER_ERROR_BREAK: 1444 { /* This one stashes the sas_task instead */ 1445 struct sas_task *t = (struct sas_task *)pm8001_dev; 1446 u32 tag; 1447 struct pm8001_ccb_info *ccb; 1448 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1449 unsigned long flags, flags1; 1450 struct task_status_struct *ts; 1451 int i; 1452 1453 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC) 1454 break; /* Task still on lu */ 1455 spin_lock_irqsave(&pm8001_ha->lock, flags); 1456 1457 spin_lock_irqsave(&t->task_state_lock, flags1); 1458 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1459 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1460 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1461 break; /* Task got completed by another */ 1462 } 1463 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1464 1465 /* Search for a possible ccb that matches the task */ 1466 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1467 ccb = &pm8001_ha->ccb_info[i]; 1468 tag = ccb->ccb_tag; 1469 if ((tag != 0xFFFFFFFF) && (ccb->task == t)) 1470 break; 1471 } 1472 if (!ccb) { 1473 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1474 break; /* Task got freed by another */ 1475 } 1476 ts = &t->task_status; 1477 ts->resp = SAS_TASK_COMPLETE; 1478 /* Force the midlayer to retry */ 1479 ts->stat = SAS_QUEUE_FULL; 1480 pm8001_dev = ccb->device; 1481 if (pm8001_dev) 1482 pm8001_dev->running_req--; 1483 spin_lock_irqsave(&t->task_state_lock, flags1); 1484 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1485 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1486 t->task_state_flags |= SAS_TASK_STATE_DONE; 1487 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1488 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1489 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p" 1490 " done with event 0x%x resp 0x%x stat 0x%x but" 1491 " aborted by upper layer!\n", 1492 t, pw->handler, ts->resp, ts->stat)); 1493 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1494 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1495 } else { 1496 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1497 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1498 mb();/* in order to force CPU ordering */ 1499 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1500 t->task_done(t); 1501 } 1502 } break; 1503 case IO_XFER_OPEN_RETRY_TIMEOUT: 1504 { /* This one stashes the sas_task instead */ 1505 struct sas_task *t = (struct sas_task *)pm8001_dev; 1506 u32 tag; 1507 struct pm8001_ccb_info *ccb; 1508 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; 1509 unsigned long flags, flags1; 1510 int i, ret = 0; 1511 1512 PM8001_IO_DBG(pm8001_ha, 1513 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1514 1515 ret = pm8001_query_task(t); 1516 1517 PM8001_IO_DBG(pm8001_ha, 1518 switch (ret) { 1519 case TMF_RESP_FUNC_SUCC: 1520 pm8001_printk("...Task on lu\n"); 1521 break; 1522 1523 case TMF_RESP_FUNC_COMPLETE: 1524 pm8001_printk("...Task NOT on lu\n"); 1525 break; 1526 1527 default: 1528 pm8001_printk("...query task failed!!!\n"); 1529 break; 1530 }); 1531 1532 spin_lock_irqsave(&pm8001_ha->lock, flags); 1533 1534 spin_lock_irqsave(&t->task_state_lock, flags1); 1535 1536 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) { 1537 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1538 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1539 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1540 (void)pm8001_abort_task(t); 1541 break; /* Task got completed by another */ 1542 } 1543 1544 spin_unlock_irqrestore(&t->task_state_lock, flags1); 1545 1546 /* Search for a possible ccb that matches the task */ 1547 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) { 1548 ccb = &pm8001_ha->ccb_info[i]; 1549 tag = ccb->ccb_tag; 1550 if ((tag != 0xFFFFFFFF) && (ccb->task == t)) 1551 break; 1552 } 1553 if (!ccb) { 1554 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1555 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */ 1556 (void)pm8001_abort_task(t); 1557 break; /* Task got freed by another */ 1558 } 1559 1560 pm8001_dev = ccb->device; 1561 dev = pm8001_dev->sas_device; 1562 1563 switch (ret) { 1564 case TMF_RESP_FUNC_SUCC: /* task on lu */ 1565 ccb->open_retry = 1; /* Snub completion */ 1566 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1567 ret = pm8001_abort_task(t); 1568 ccb->open_retry = 0; 1569 switch (ret) { 1570 case TMF_RESP_FUNC_SUCC: 1571 case TMF_RESP_FUNC_COMPLETE: 1572 break; 1573 default: /* device misbehavior */ 1574 ret = TMF_RESP_FUNC_FAILED; 1575 PM8001_IO_DBG(pm8001_ha, 1576 pm8001_printk("...Reset phy\n")); 1577 pm8001_I_T_nexus_reset(dev); 1578 break; 1579 } 1580 break; 1581 1582 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */ 1583 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1584 /* Do we need to abort the task locally? */ 1585 break; 1586 1587 default: /* device misbehavior */ 1588 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 1589 ret = TMF_RESP_FUNC_FAILED; 1590 PM8001_IO_DBG(pm8001_ha, 1591 pm8001_printk("...Reset phy\n")); 1592 pm8001_I_T_nexus_reset(dev); 1593 } 1594 1595 if (ret == TMF_RESP_FUNC_FAILED) 1596 t = NULL; 1597 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev); 1598 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n")); 1599 } break; 1600 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1601 dev = pm8001_dev->sas_device; 1602 pm8001_I_T_nexus_reset(dev); 1603 break; 1604 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 1605 dev = pm8001_dev->sas_device; 1606 pm8001_I_T_nexus_reset(dev); 1607 break; 1608 case IO_DS_IN_ERROR: 1609 dev = pm8001_dev->sas_device; 1610 pm8001_I_T_nexus_reset(dev); 1611 break; 1612 case IO_DS_NON_OPERATIONAL: 1613 dev = pm8001_dev->sas_device; 1614 pm8001_I_T_nexus_reset(dev); 1615 break; 1616 } 1617 kfree(pw); 1618} 1619 1620static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data, 1621 int handler) 1622{ 1623 struct pm8001_work *pw; 1624 int ret = 0; 1625 1626 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC); 1627 if (pw) { 1628 pw->pm8001_ha = pm8001_ha; 1629 pw->data = data; 1630 pw->handler = handler; 1631 INIT_WORK(&pw->work, pm8001_work_fn); 1632 queue_work(pm8001_wq, &pw->work); 1633 } else 1634 ret = -ENOMEM; 1635 1636 return ret; 1637} 1638 1639/** 1640 * mpi_ssp_completion- process the event that FW response to the SSP request. 1641 * @pm8001_ha: our hba card information 1642 * @piomb: the message contents of this outbound message. 1643 * 1644 * When FW has completed a ssp request for example a IO request, after it has 1645 * filled the SG data with the data, it will trigger this event represent 1646 * that he has finished the job,please check the coresponding buffer. 1647 * So we will tell the caller who maybe waiting the result to tell upper layer 1648 * that the task has been finished. 1649 */ 1650static void 1651mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) 1652{ 1653 struct sas_task *t; 1654 struct pm8001_ccb_info *ccb; 1655 unsigned long flags; 1656 u32 status; 1657 u32 param; 1658 u32 tag; 1659 struct ssp_completion_resp *psspPayload; 1660 struct task_status_struct *ts; 1661 struct ssp_response_iu *iu; 1662 struct pm8001_device *pm8001_dev; 1663 psspPayload = (struct ssp_completion_resp *)(piomb + 4); 1664 status = le32_to_cpu(psspPayload->status); 1665 tag = le32_to_cpu(psspPayload->tag); 1666 ccb = &pm8001_ha->ccb_info[tag]; 1667 if ((status == IO_ABORTED) && ccb->open_retry) { 1668 /* Being completed by another */ 1669 ccb->open_retry = 0; 1670 return; 1671 } 1672 pm8001_dev = ccb->device; 1673 param = le32_to_cpu(psspPayload->param); 1674 1675 t = ccb->task; 1676 1677 if (status && status != IO_UNDERFLOW) 1678 PM8001_FAIL_DBG(pm8001_ha, 1679 pm8001_printk("sas IO status 0x%x\n", status)); 1680 if (unlikely(!t || !t->lldd_task || !t->dev)) 1681 return; 1682 ts = &t->task_status; 1683 switch (status) { 1684 case IO_SUCCESS: 1685 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS" 1686 ",param = %d\n", param)); 1687 if (param == 0) { 1688 ts->resp = SAS_TASK_COMPLETE; 1689 ts->stat = SAM_STAT_GOOD; 1690 } else { 1691 ts->resp = SAS_TASK_COMPLETE; 1692 ts->stat = SAS_PROTO_RESPONSE; 1693 ts->residual = param; 1694 iu = &psspPayload->ssp_resp_iu; 1695 sas_ssp_task_response(pm8001_ha->dev, t, iu); 1696 } 1697 if (pm8001_dev) 1698 pm8001_dev->running_req--; 1699 break; 1700 case IO_ABORTED: 1701 PM8001_IO_DBG(pm8001_ha, 1702 pm8001_printk("IO_ABORTED IOMB Tag\n")); 1703 ts->resp = SAS_TASK_COMPLETE; 1704 ts->stat = SAS_ABORTED_TASK; 1705 break; 1706 case IO_UNDERFLOW: 1707 /* SSP Completion with error */ 1708 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW" 1709 ",param = %d\n", param)); 1710 ts->resp = SAS_TASK_COMPLETE; 1711 ts->stat = SAS_DATA_UNDERRUN; 1712 ts->residual = param; 1713 if (pm8001_dev) 1714 pm8001_dev->running_req--; 1715 break; 1716 case IO_NO_DEVICE: 1717 PM8001_IO_DBG(pm8001_ha, 1718 pm8001_printk("IO_NO_DEVICE\n")); 1719 ts->resp = SAS_TASK_UNDELIVERED; 1720 ts->stat = SAS_PHY_DOWN; 1721 break; 1722 case IO_XFER_ERROR_BREAK: 1723 PM8001_IO_DBG(pm8001_ha, 1724 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1725 ts->resp = SAS_TASK_COMPLETE; 1726 ts->stat = SAS_OPEN_REJECT; 1727 /* Force the midlayer to retry */ 1728 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1729 break; 1730 case IO_XFER_ERROR_PHY_NOT_READY: 1731 PM8001_IO_DBG(pm8001_ha, 1732 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1733 ts->resp = SAS_TASK_COMPLETE; 1734 ts->stat = SAS_OPEN_REJECT; 1735 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1736 break; 1737 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1738 PM8001_IO_DBG(pm8001_ha, 1739 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 1740 ts->resp = SAS_TASK_COMPLETE; 1741 ts->stat = SAS_OPEN_REJECT; 1742 ts->open_rej_reason = SAS_OREJ_EPROTO; 1743 break; 1744 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1745 PM8001_IO_DBG(pm8001_ha, 1746 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1747 ts->resp = SAS_TASK_COMPLETE; 1748 ts->stat = SAS_OPEN_REJECT; 1749 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1750 break; 1751 case IO_OPEN_CNX_ERROR_BREAK: 1752 PM8001_IO_DBG(pm8001_ha, 1753 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1754 ts->resp = SAS_TASK_COMPLETE; 1755 ts->stat = SAS_OPEN_REJECT; 1756 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1757 break; 1758 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1759 PM8001_IO_DBG(pm8001_ha, 1760 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1761 ts->resp = SAS_TASK_COMPLETE; 1762 ts->stat = SAS_OPEN_REJECT; 1763 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1764 if (!t->uldd_task) 1765 pm8001_handle_event(pm8001_ha, 1766 pm8001_dev, 1767 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1768 break; 1769 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1770 PM8001_IO_DBG(pm8001_ha, 1771 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1772 ts->resp = SAS_TASK_COMPLETE; 1773 ts->stat = SAS_OPEN_REJECT; 1774 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1775 break; 1776 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1777 PM8001_IO_DBG(pm8001_ha, 1778 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 1779 "NOT_SUPPORTED\n")); 1780 ts->resp = SAS_TASK_COMPLETE; 1781 ts->stat = SAS_OPEN_REJECT; 1782 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1783 break; 1784 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1785 PM8001_IO_DBG(pm8001_ha, 1786 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1787 ts->resp = SAS_TASK_UNDELIVERED; 1788 ts->stat = SAS_OPEN_REJECT; 1789 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1790 break; 1791 case IO_XFER_ERROR_NAK_RECEIVED: 1792 PM8001_IO_DBG(pm8001_ha, 1793 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 1794 ts->resp = SAS_TASK_COMPLETE; 1795 ts->stat = SAS_OPEN_REJECT; 1796 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1797 break; 1798 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 1799 PM8001_IO_DBG(pm8001_ha, 1800 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 1801 ts->resp = SAS_TASK_COMPLETE; 1802 ts->stat = SAS_NAK_R_ERR; 1803 break; 1804 case IO_XFER_ERROR_DMA: 1805 PM8001_IO_DBG(pm8001_ha, 1806 pm8001_printk("IO_XFER_ERROR_DMA\n")); 1807 ts->resp = SAS_TASK_COMPLETE; 1808 ts->stat = SAS_OPEN_REJECT; 1809 break; 1810 case IO_XFER_OPEN_RETRY_TIMEOUT: 1811 PM8001_IO_DBG(pm8001_ha, 1812 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 1813 ts->resp = SAS_TASK_COMPLETE; 1814 ts->stat = SAS_OPEN_REJECT; 1815 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1816 break; 1817 case IO_XFER_ERROR_OFFSET_MISMATCH: 1818 PM8001_IO_DBG(pm8001_ha, 1819 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 1820 ts->resp = SAS_TASK_COMPLETE; 1821 ts->stat = SAS_OPEN_REJECT; 1822 break; 1823 case IO_PORT_IN_RESET: 1824 PM8001_IO_DBG(pm8001_ha, 1825 pm8001_printk("IO_PORT_IN_RESET\n")); 1826 ts->resp = SAS_TASK_COMPLETE; 1827 ts->stat = SAS_OPEN_REJECT; 1828 break; 1829 case IO_DS_NON_OPERATIONAL: 1830 PM8001_IO_DBG(pm8001_ha, 1831 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 1832 ts->resp = SAS_TASK_COMPLETE; 1833 ts->stat = SAS_OPEN_REJECT; 1834 if (!t->uldd_task) 1835 pm8001_handle_event(pm8001_ha, 1836 pm8001_dev, 1837 IO_DS_NON_OPERATIONAL); 1838 break; 1839 case IO_DS_IN_RECOVERY: 1840 PM8001_IO_DBG(pm8001_ha, 1841 pm8001_printk("IO_DS_IN_RECOVERY\n")); 1842 ts->resp = SAS_TASK_COMPLETE; 1843 ts->stat = SAS_OPEN_REJECT; 1844 break; 1845 case IO_TM_TAG_NOT_FOUND: 1846 PM8001_IO_DBG(pm8001_ha, 1847 pm8001_printk("IO_TM_TAG_NOT_FOUND\n")); 1848 ts->resp = SAS_TASK_COMPLETE; 1849 ts->stat = SAS_OPEN_REJECT; 1850 break; 1851 case IO_SSP_EXT_IU_ZERO_LEN_ERROR: 1852 PM8001_IO_DBG(pm8001_ha, 1853 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n")); 1854 ts->resp = SAS_TASK_COMPLETE; 1855 ts->stat = SAS_OPEN_REJECT; 1856 break; 1857 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 1858 PM8001_IO_DBG(pm8001_ha, 1859 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 1860 ts->resp = SAS_TASK_COMPLETE; 1861 ts->stat = SAS_OPEN_REJECT; 1862 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1863 break; 1864 default: 1865 PM8001_IO_DBG(pm8001_ha, 1866 pm8001_printk("Unknown status 0x%x\n", status)); 1867 /* not allowed case. Therefore, return failed status */ 1868 ts->resp = SAS_TASK_COMPLETE; 1869 ts->stat = SAS_OPEN_REJECT; 1870 break; 1871 } 1872 PM8001_IO_DBG(pm8001_ha, 1873 pm8001_printk("scsi_status = %x \n ", 1874 psspPayload->ssp_resp_iu.status)); 1875 spin_lock_irqsave(&t->task_state_lock, flags); 1876 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 1877 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 1878 t->task_state_flags |= SAS_TASK_STATE_DONE; 1879 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 1880 spin_unlock_irqrestore(&t->task_state_lock, flags); 1881 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 1882 " io_status 0x%x resp 0x%x " 1883 "stat 0x%x but aborted by upper layer!\n", 1884 t, status, ts->resp, ts->stat)); 1885 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1886 } else { 1887 spin_unlock_irqrestore(&t->task_state_lock, flags); 1888 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 1889 mb();/* in order to force CPU ordering */ 1890 t->task_done(t); 1891 } 1892} 1893 1894/*See the comments for mpi_ssp_completion */ 1895static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 1896{ 1897 struct sas_task *t; 1898 unsigned long flags; 1899 struct task_status_struct *ts; 1900 struct pm8001_ccb_info *ccb; 1901 struct pm8001_device *pm8001_dev; 1902 struct ssp_event_resp *psspPayload = 1903 (struct ssp_event_resp *)(piomb + 4); 1904 u32 event = le32_to_cpu(psspPayload->event); 1905 u32 tag = le32_to_cpu(psspPayload->tag); 1906 u32 port_id = le32_to_cpu(psspPayload->port_id); 1907 u32 dev_id = le32_to_cpu(psspPayload->device_id); 1908 1909 ccb = &pm8001_ha->ccb_info[tag]; 1910 t = ccb->task; 1911 pm8001_dev = ccb->device; 1912 if (event) 1913 PM8001_FAIL_DBG(pm8001_ha, 1914 pm8001_printk("sas IO status 0x%x\n", event)); 1915 if (unlikely(!t || !t->lldd_task || !t->dev)) 1916 return; 1917 ts = &t->task_status; 1918 PM8001_IO_DBG(pm8001_ha, 1919 pm8001_printk("port_id = %x,device_id = %x\n", 1920 port_id, dev_id)); 1921 switch (event) { 1922 case IO_OVERFLOW: 1923 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");) 1924 ts->resp = SAS_TASK_COMPLETE; 1925 ts->stat = SAS_DATA_OVERRUN; 1926 ts->residual = 0; 1927 if (pm8001_dev) 1928 pm8001_dev->running_req--; 1929 break; 1930 case IO_XFER_ERROR_BREAK: 1931 PM8001_IO_DBG(pm8001_ha, 1932 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 1933 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); 1934 return; 1935 case IO_XFER_ERROR_PHY_NOT_READY: 1936 PM8001_IO_DBG(pm8001_ha, 1937 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 1938 ts->resp = SAS_TASK_COMPLETE; 1939 ts->stat = SAS_OPEN_REJECT; 1940 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1941 break; 1942 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 1943 PM8001_IO_DBG(pm8001_ha, 1944 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 1945 "_SUPPORTED\n")); 1946 ts->resp = SAS_TASK_COMPLETE; 1947 ts->stat = SAS_OPEN_REJECT; 1948 ts->open_rej_reason = SAS_OREJ_EPROTO; 1949 break; 1950 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 1951 PM8001_IO_DBG(pm8001_ha, 1952 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 1953 ts->resp = SAS_TASK_COMPLETE; 1954 ts->stat = SAS_OPEN_REJECT; 1955 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1956 break; 1957 case IO_OPEN_CNX_ERROR_BREAK: 1958 PM8001_IO_DBG(pm8001_ha, 1959 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 1960 ts->resp = SAS_TASK_COMPLETE; 1961 ts->stat = SAS_OPEN_REJECT; 1962 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1963 break; 1964 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 1965 PM8001_IO_DBG(pm8001_ha, 1966 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 1967 ts->resp = SAS_TASK_COMPLETE; 1968 ts->stat = SAS_OPEN_REJECT; 1969 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1970 if (!t->uldd_task) 1971 pm8001_handle_event(pm8001_ha, 1972 pm8001_dev, 1973 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 1974 break; 1975 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 1976 PM8001_IO_DBG(pm8001_ha, 1977 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 1978 ts->resp = SAS_TASK_COMPLETE; 1979 ts->stat = SAS_OPEN_REJECT; 1980 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1981 break; 1982 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 1983 PM8001_IO_DBG(pm8001_ha, 1984 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 1985 "NOT_SUPPORTED\n")); 1986 ts->resp = SAS_TASK_COMPLETE; 1987 ts->stat = SAS_OPEN_REJECT; 1988 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1989 break; 1990 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 1991 PM8001_IO_DBG(pm8001_ha, 1992 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 1993 ts->resp = SAS_TASK_COMPLETE; 1994 ts->stat = SAS_OPEN_REJECT; 1995 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1996 break; 1997 case IO_XFER_ERROR_NAK_RECEIVED: 1998 PM8001_IO_DBG(pm8001_ha, 1999 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2000 ts->resp = SAS_TASK_COMPLETE; 2001 ts->stat = SAS_OPEN_REJECT; 2002 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2003 break; 2004 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2005 PM8001_IO_DBG(pm8001_ha, 2006 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2007 ts->resp = SAS_TASK_COMPLETE; 2008 ts->stat = SAS_NAK_R_ERR; 2009 break; 2010 case IO_XFER_OPEN_RETRY_TIMEOUT: 2011 PM8001_IO_DBG(pm8001_ha, 2012 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2013 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); 2014 return; 2015 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2016 PM8001_IO_DBG(pm8001_ha, 2017 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2018 ts->resp = SAS_TASK_COMPLETE; 2019 ts->stat = SAS_DATA_OVERRUN; 2020 break; 2021 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2022 PM8001_IO_DBG(pm8001_ha, 2023 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2024 ts->resp = SAS_TASK_COMPLETE; 2025 ts->stat = SAS_DATA_OVERRUN; 2026 break; 2027 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2028 PM8001_IO_DBG(pm8001_ha, 2029 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2030 ts->resp = SAS_TASK_COMPLETE; 2031 ts->stat = SAS_DATA_OVERRUN; 2032 break; 2033 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 2034 PM8001_IO_DBG(pm8001_ha, 2035 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n")); 2036 ts->resp = SAS_TASK_COMPLETE; 2037 ts->stat = SAS_DATA_OVERRUN; 2038 break; 2039 case IO_XFER_ERROR_OFFSET_MISMATCH: 2040 PM8001_IO_DBG(pm8001_ha, 2041 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2042 ts->resp = SAS_TASK_COMPLETE; 2043 ts->stat = SAS_DATA_OVERRUN; 2044 break; 2045 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2046 PM8001_IO_DBG(pm8001_ha, 2047 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2048 ts->resp = SAS_TASK_COMPLETE; 2049 ts->stat = SAS_DATA_OVERRUN; 2050 break; 2051 case IO_XFER_CMD_FRAME_ISSUED: 2052 PM8001_IO_DBG(pm8001_ha, 2053 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n")); 2054 return; 2055 default: 2056 PM8001_IO_DBG(pm8001_ha, 2057 pm8001_printk("Unknown status 0x%x\n", event)); 2058 /* not allowed case. Therefore, return failed status */ 2059 ts->resp = SAS_TASK_COMPLETE; 2060 ts->stat = SAS_DATA_OVERRUN; 2061 break; 2062 } 2063 spin_lock_irqsave(&t->task_state_lock, flags); 2064 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2065 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2066 t->task_state_flags |= SAS_TASK_STATE_DONE; 2067 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2068 spin_unlock_irqrestore(&t->task_state_lock, flags); 2069 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 2070 " event 0x%x resp 0x%x " 2071 "stat 0x%x but aborted by upper layer!\n", 2072 t, event, ts->resp, ts->stat)); 2073 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2074 } else { 2075 spin_unlock_irqrestore(&t->task_state_lock, flags); 2076 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2077 mb();/* in order to force CPU ordering */ 2078 t->task_done(t); 2079 } 2080} 2081 2082/*See the comments for mpi_ssp_completion */ 2083static void 2084mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2085{ 2086 struct sas_task *t; 2087 struct pm8001_ccb_info *ccb; 2088 u32 param; 2089 u32 status; 2090 u32 tag; 2091 struct sata_completion_resp *psataPayload; 2092 struct task_status_struct *ts; 2093 struct ata_task_resp *resp ; 2094 u32 *sata_resp; 2095 struct pm8001_device *pm8001_dev; 2096 unsigned long flags; 2097 2098 psataPayload = (struct sata_completion_resp *)(piomb + 4); 2099 status = le32_to_cpu(psataPayload->status); 2100 tag = le32_to_cpu(psataPayload->tag); 2101 2102 ccb = &pm8001_ha->ccb_info[tag]; 2103 param = le32_to_cpu(psataPayload->param); 2104 t = ccb->task; 2105 ts = &t->task_status; 2106 pm8001_dev = ccb->device; 2107 if (status) 2108 PM8001_FAIL_DBG(pm8001_ha, 2109 pm8001_printk("sata IO status 0x%x\n", status)); 2110 if (unlikely(!t || !t->lldd_task || !t->dev)) 2111 return; 2112 2113 switch (status) { 2114 case IO_SUCCESS: 2115 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2116 if (param == 0) { 2117 ts->resp = SAS_TASK_COMPLETE; 2118 ts->stat = SAM_STAT_GOOD; 2119 } else { 2120 u8 len; 2121 ts->resp = SAS_TASK_COMPLETE; 2122 ts->stat = SAS_PROTO_RESPONSE; 2123 ts->residual = param; 2124 PM8001_IO_DBG(pm8001_ha, 2125 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n", 2126 param)); 2127 sata_resp = &psataPayload->sata_resp[0]; 2128 resp = (struct ata_task_resp *)ts->buf; 2129 if (t->ata_task.dma_xfer == 0 && 2130 t->data_dir == PCI_DMA_FROMDEVICE) { 2131 len = sizeof(struct pio_setup_fis); 2132 PM8001_IO_DBG(pm8001_ha, 2133 pm8001_printk("PIO read len = %d\n", len)); 2134 } else if (t->ata_task.use_ncq) { 2135 len = sizeof(struct set_dev_bits_fis); 2136 PM8001_IO_DBG(pm8001_ha, 2137 pm8001_printk("FPDMA len = %d\n", len)); 2138 } else { 2139 len = sizeof(struct dev_to_host_fis); 2140 PM8001_IO_DBG(pm8001_ha, 2141 pm8001_printk("other len = %d\n", len)); 2142 } 2143 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { 2144 resp->frame_len = len; 2145 memcpy(&resp->ending_fis[0], sata_resp, len); 2146 ts->buf_valid_size = sizeof(*resp); 2147 } else 2148 PM8001_IO_DBG(pm8001_ha, 2149 pm8001_printk("response to large\n")); 2150 } 2151 if (pm8001_dev) 2152 pm8001_dev->running_req--; 2153 break; 2154 case IO_ABORTED: 2155 PM8001_IO_DBG(pm8001_ha, 2156 pm8001_printk("IO_ABORTED IOMB Tag\n")); 2157 ts->resp = SAS_TASK_COMPLETE; 2158 ts->stat = SAS_ABORTED_TASK; 2159 if (pm8001_dev) 2160 pm8001_dev->running_req--; 2161 break; 2162 /* following cases are to do cases */ 2163 case IO_UNDERFLOW: 2164 /* SATA Completion with error */ 2165 PM8001_IO_DBG(pm8001_ha, 2166 pm8001_printk("IO_UNDERFLOW param = %d\n", param)); 2167 ts->resp = SAS_TASK_COMPLETE; 2168 ts->stat = SAS_DATA_UNDERRUN; 2169 ts->residual = param; 2170 if (pm8001_dev) 2171 pm8001_dev->running_req--; 2172 break; 2173 case IO_NO_DEVICE: 2174 PM8001_IO_DBG(pm8001_ha, 2175 pm8001_printk("IO_NO_DEVICE\n")); 2176 ts->resp = SAS_TASK_UNDELIVERED; 2177 ts->stat = SAS_PHY_DOWN; 2178 break; 2179 case IO_XFER_ERROR_BREAK: 2180 PM8001_IO_DBG(pm8001_ha, 2181 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2182 ts->resp = SAS_TASK_COMPLETE; 2183 ts->stat = SAS_INTERRUPTED; 2184 break; 2185 case IO_XFER_ERROR_PHY_NOT_READY: 2186 PM8001_IO_DBG(pm8001_ha, 2187 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2188 ts->resp = SAS_TASK_COMPLETE; 2189 ts->stat = SAS_OPEN_REJECT; 2190 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2191 break; 2192 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2193 PM8001_IO_DBG(pm8001_ha, 2194 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2195 "_SUPPORTED\n")); 2196 ts->resp = SAS_TASK_COMPLETE; 2197 ts->stat = SAS_OPEN_REJECT; 2198 ts->open_rej_reason = SAS_OREJ_EPROTO; 2199 break; 2200 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2201 PM8001_IO_DBG(pm8001_ha, 2202 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2203 ts->resp = SAS_TASK_COMPLETE; 2204 ts->stat = SAS_OPEN_REJECT; 2205 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2206 break; 2207 case IO_OPEN_CNX_ERROR_BREAK: 2208 PM8001_IO_DBG(pm8001_ha, 2209 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2210 ts->resp = SAS_TASK_COMPLETE; 2211 ts->stat = SAS_OPEN_REJECT; 2212 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2213 break; 2214 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2215 PM8001_IO_DBG(pm8001_ha, 2216 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2217 ts->resp = SAS_TASK_COMPLETE; 2218 ts->stat = SAS_DEV_NO_RESPONSE; 2219 if (!t->uldd_task) { 2220 pm8001_handle_event(pm8001_ha, 2221 pm8001_dev, 2222 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2223 ts->resp = SAS_TASK_UNDELIVERED; 2224 ts->stat = SAS_QUEUE_FULL; 2225 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2226 mb();/*in order to force CPU ordering*/ 2227 spin_unlock_irq(&pm8001_ha->lock); 2228 t->task_done(t); 2229 spin_lock_irq(&pm8001_ha->lock); 2230 return; 2231 } 2232 break; 2233 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2234 PM8001_IO_DBG(pm8001_ha, 2235 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2236 ts->resp = SAS_TASK_UNDELIVERED; 2237 ts->stat = SAS_OPEN_REJECT; 2238 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2239 if (!t->uldd_task) { 2240 pm8001_handle_event(pm8001_ha, 2241 pm8001_dev, 2242 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2243 ts->resp = SAS_TASK_UNDELIVERED; 2244 ts->stat = SAS_QUEUE_FULL; 2245 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2246 mb();/*ditto*/ 2247 spin_unlock_irq(&pm8001_ha->lock); 2248 t->task_done(t); 2249 spin_lock_irq(&pm8001_ha->lock); 2250 return; 2251 } 2252 break; 2253 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2254 PM8001_IO_DBG(pm8001_ha, 2255 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2256 "NOT_SUPPORTED\n")); 2257 ts->resp = SAS_TASK_COMPLETE; 2258 ts->stat = SAS_OPEN_REJECT; 2259 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2260 break; 2261 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 2262 PM8001_IO_DBG(pm8001_ha, 2263 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES" 2264 "_BUSY\n")); 2265 ts->resp = SAS_TASK_COMPLETE; 2266 ts->stat = SAS_DEV_NO_RESPONSE; 2267 if (!t->uldd_task) { 2268 pm8001_handle_event(pm8001_ha, 2269 pm8001_dev, 2270 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); 2271 ts->resp = SAS_TASK_UNDELIVERED; 2272 ts->stat = SAS_QUEUE_FULL; 2273 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2274 mb();/* ditto*/ 2275 spin_unlock_irq(&pm8001_ha->lock); 2276 t->task_done(t); 2277 spin_lock_irq(&pm8001_ha->lock); 2278 return; 2279 } 2280 break; 2281 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2282 PM8001_IO_DBG(pm8001_ha, 2283 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2284 ts->resp = SAS_TASK_COMPLETE; 2285 ts->stat = SAS_OPEN_REJECT; 2286 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2287 break; 2288 case IO_XFER_ERROR_NAK_RECEIVED: 2289 PM8001_IO_DBG(pm8001_ha, 2290 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2291 ts->resp = SAS_TASK_COMPLETE; 2292 ts->stat = SAS_NAK_R_ERR; 2293 break; 2294 case IO_XFER_ERROR_ACK_NAK_TIMEOUT: 2295 PM8001_IO_DBG(pm8001_ha, 2296 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); 2297 ts->resp = SAS_TASK_COMPLETE; 2298 ts->stat = SAS_NAK_R_ERR; 2299 break; 2300 case IO_XFER_ERROR_DMA: 2301 PM8001_IO_DBG(pm8001_ha, 2302 pm8001_printk("IO_XFER_ERROR_DMA\n")); 2303 ts->resp = SAS_TASK_COMPLETE; 2304 ts->stat = SAS_ABORTED_TASK; 2305 break; 2306 case IO_XFER_ERROR_SATA_LINK_TIMEOUT: 2307 PM8001_IO_DBG(pm8001_ha, 2308 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n")); 2309 ts->resp = SAS_TASK_UNDELIVERED; 2310 ts->stat = SAS_DEV_NO_RESPONSE; 2311 break; 2312 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2313 PM8001_IO_DBG(pm8001_ha, 2314 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2315 ts->resp = SAS_TASK_COMPLETE; 2316 ts->stat = SAS_DATA_UNDERRUN; 2317 break; 2318 case IO_XFER_OPEN_RETRY_TIMEOUT: 2319 PM8001_IO_DBG(pm8001_ha, 2320 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2321 ts->resp = SAS_TASK_COMPLETE; 2322 ts->stat = SAS_OPEN_TO; 2323 break; 2324 case IO_PORT_IN_RESET: 2325 PM8001_IO_DBG(pm8001_ha, 2326 pm8001_printk("IO_PORT_IN_RESET\n")); 2327 ts->resp = SAS_TASK_COMPLETE; 2328 ts->stat = SAS_DEV_NO_RESPONSE; 2329 break; 2330 case IO_DS_NON_OPERATIONAL: 2331 PM8001_IO_DBG(pm8001_ha, 2332 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2333 ts->resp = SAS_TASK_COMPLETE; 2334 ts->stat = SAS_DEV_NO_RESPONSE; 2335 if (!t->uldd_task) { 2336 pm8001_handle_event(pm8001_ha, pm8001_dev, 2337 IO_DS_NON_OPERATIONAL); 2338 ts->resp = SAS_TASK_UNDELIVERED; 2339 ts->stat = SAS_QUEUE_FULL; 2340 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2341 mb();/*ditto*/ 2342 spin_unlock_irq(&pm8001_ha->lock); 2343 t->task_done(t); 2344 spin_lock_irq(&pm8001_ha->lock); 2345 return; 2346 } 2347 break; 2348 case IO_DS_IN_RECOVERY: 2349 PM8001_IO_DBG(pm8001_ha, 2350 pm8001_printk(" IO_DS_IN_RECOVERY\n")); 2351 ts->resp = SAS_TASK_COMPLETE; 2352 ts->stat = SAS_DEV_NO_RESPONSE; 2353 break; 2354 case IO_DS_IN_ERROR: 2355 PM8001_IO_DBG(pm8001_ha, 2356 pm8001_printk("IO_DS_IN_ERROR\n")); 2357 ts->resp = SAS_TASK_COMPLETE; 2358 ts->stat = SAS_DEV_NO_RESPONSE; 2359 if (!t->uldd_task) { 2360 pm8001_handle_event(pm8001_ha, pm8001_dev, 2361 IO_DS_IN_ERROR); 2362 ts->resp = SAS_TASK_UNDELIVERED; 2363 ts->stat = SAS_QUEUE_FULL; 2364 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2365 mb();/*ditto*/ 2366 spin_unlock_irq(&pm8001_ha->lock); 2367 t->task_done(t); 2368 spin_lock_irq(&pm8001_ha->lock); 2369 return; 2370 } 2371 break; 2372 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2373 PM8001_IO_DBG(pm8001_ha, 2374 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2375 ts->resp = SAS_TASK_COMPLETE; 2376 ts->stat = SAS_OPEN_REJECT; 2377 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2378 default: 2379 PM8001_IO_DBG(pm8001_ha, 2380 pm8001_printk("Unknown status 0x%x\n", status)); 2381 /* not allowed case. Therefore, return failed status */ 2382 ts->resp = SAS_TASK_COMPLETE; 2383 ts->stat = SAS_DEV_NO_RESPONSE; 2384 break; 2385 } 2386 spin_lock_irqsave(&t->task_state_lock, flags); 2387 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2388 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2389 t->task_state_flags |= SAS_TASK_STATE_DONE; 2390 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2391 spin_unlock_irqrestore(&t->task_state_lock, flags); 2392 PM8001_FAIL_DBG(pm8001_ha, 2393 pm8001_printk("task 0x%p done with io_status 0x%x" 2394 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2395 t, status, ts->resp, ts->stat)); 2396 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2397 } else if (t->uldd_task) { 2398 spin_unlock_irqrestore(&t->task_state_lock, flags); 2399 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2400 mb();/* ditto */ 2401 spin_unlock_irq(&pm8001_ha->lock); 2402 t->task_done(t); 2403 spin_lock_irq(&pm8001_ha->lock); 2404 } else if (!t->uldd_task) { 2405 spin_unlock_irqrestore(&t->task_state_lock, flags); 2406 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2407 mb();/*ditto*/ 2408 spin_unlock_irq(&pm8001_ha->lock); 2409 t->task_done(t); 2410 spin_lock_irq(&pm8001_ha->lock); 2411 } 2412} 2413 2414/*See the comments for mpi_ssp_completion */ 2415static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 2416{ 2417 struct sas_task *t; 2418 struct task_status_struct *ts; 2419 struct pm8001_ccb_info *ccb; 2420 struct pm8001_device *pm8001_dev; 2421 struct sata_event_resp *psataPayload = 2422 (struct sata_event_resp *)(piomb + 4); 2423 u32 event = le32_to_cpu(psataPayload->event); 2424 u32 tag = le32_to_cpu(psataPayload->tag); 2425 u32 port_id = le32_to_cpu(psataPayload->port_id); 2426 u32 dev_id = le32_to_cpu(psataPayload->device_id); 2427 unsigned long flags; 2428 2429 ccb = &pm8001_ha->ccb_info[tag]; 2430 t = ccb->task; 2431 pm8001_dev = ccb->device; 2432 if (event) 2433 PM8001_FAIL_DBG(pm8001_ha, 2434 pm8001_printk("sata IO status 0x%x\n", event)); 2435 if (unlikely(!t || !t->lldd_task || !t->dev)) 2436 return; 2437 ts = &t->task_status; 2438 PM8001_IO_DBG(pm8001_ha, 2439 pm8001_printk("port_id = %x,device_id = %x\n", 2440 port_id, dev_id)); 2441 switch (event) { 2442 case IO_OVERFLOW: 2443 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2444 ts->resp = SAS_TASK_COMPLETE; 2445 ts->stat = SAS_DATA_OVERRUN; 2446 ts->residual = 0; 2447 if (pm8001_dev) 2448 pm8001_dev->running_req--; 2449 break; 2450 case IO_XFER_ERROR_BREAK: 2451 PM8001_IO_DBG(pm8001_ha, 2452 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2453 ts->resp = SAS_TASK_COMPLETE; 2454 ts->stat = SAS_INTERRUPTED; 2455 break; 2456 case IO_XFER_ERROR_PHY_NOT_READY: 2457 PM8001_IO_DBG(pm8001_ha, 2458 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2459 ts->resp = SAS_TASK_COMPLETE; 2460 ts->stat = SAS_OPEN_REJECT; 2461 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2462 break; 2463 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2464 PM8001_IO_DBG(pm8001_ha, 2465 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT" 2466 "_SUPPORTED\n")); 2467 ts->resp = SAS_TASK_COMPLETE; 2468 ts->stat = SAS_OPEN_REJECT; 2469 ts->open_rej_reason = SAS_OREJ_EPROTO; 2470 break; 2471 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2472 PM8001_IO_DBG(pm8001_ha, 2473 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2474 ts->resp = SAS_TASK_COMPLETE; 2475 ts->stat = SAS_OPEN_REJECT; 2476 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2477 break; 2478 case IO_OPEN_CNX_ERROR_BREAK: 2479 PM8001_IO_DBG(pm8001_ha, 2480 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2481 ts->resp = SAS_TASK_COMPLETE; 2482 ts->stat = SAS_OPEN_REJECT; 2483 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2484 break; 2485 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2486 PM8001_IO_DBG(pm8001_ha, 2487 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2488 ts->resp = SAS_TASK_UNDELIVERED; 2489 ts->stat = SAS_DEV_NO_RESPONSE; 2490 if (!t->uldd_task) { 2491 pm8001_handle_event(pm8001_ha, 2492 pm8001_dev, 2493 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2494 ts->resp = SAS_TASK_COMPLETE; 2495 ts->stat = SAS_QUEUE_FULL; 2496 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2497 mb();/*ditto*/ 2498 spin_unlock_irq(&pm8001_ha->lock); 2499 t->task_done(t); 2500 spin_lock_irq(&pm8001_ha->lock); 2501 return; 2502 } 2503 break; 2504 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2505 PM8001_IO_DBG(pm8001_ha, 2506 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2507 ts->resp = SAS_TASK_UNDELIVERED; 2508 ts->stat = SAS_OPEN_REJECT; 2509 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2510 break; 2511 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2512 PM8001_IO_DBG(pm8001_ha, 2513 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2514 "NOT_SUPPORTED\n")); 2515 ts->resp = SAS_TASK_COMPLETE; 2516 ts->stat = SAS_OPEN_REJECT; 2517 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2518 break; 2519 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2520 PM8001_IO_DBG(pm8001_ha, 2521 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2522 ts->resp = SAS_TASK_COMPLETE; 2523 ts->stat = SAS_OPEN_REJECT; 2524 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2525 break; 2526 case IO_XFER_ERROR_NAK_RECEIVED: 2527 PM8001_IO_DBG(pm8001_ha, 2528 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); 2529 ts->resp = SAS_TASK_COMPLETE; 2530 ts->stat = SAS_NAK_R_ERR; 2531 break; 2532 case IO_XFER_ERROR_PEER_ABORTED: 2533 PM8001_IO_DBG(pm8001_ha, 2534 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n")); 2535 ts->resp = SAS_TASK_COMPLETE; 2536 ts->stat = SAS_NAK_R_ERR; 2537 break; 2538 case IO_XFER_ERROR_REJECTED_NCQ_MODE: 2539 PM8001_IO_DBG(pm8001_ha, 2540 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); 2541 ts->resp = SAS_TASK_COMPLETE; 2542 ts->stat = SAS_DATA_UNDERRUN; 2543 break; 2544 case IO_XFER_OPEN_RETRY_TIMEOUT: 2545 PM8001_IO_DBG(pm8001_ha, 2546 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2547 ts->resp = SAS_TASK_COMPLETE; 2548 ts->stat = SAS_OPEN_TO; 2549 break; 2550 case IO_XFER_ERROR_UNEXPECTED_PHASE: 2551 PM8001_IO_DBG(pm8001_ha, 2552 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); 2553 ts->resp = SAS_TASK_COMPLETE; 2554 ts->stat = SAS_OPEN_TO; 2555 break; 2556 case IO_XFER_ERROR_XFER_RDY_OVERRUN: 2557 PM8001_IO_DBG(pm8001_ha, 2558 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); 2559 ts->resp = SAS_TASK_COMPLETE; 2560 ts->stat = SAS_OPEN_TO; 2561 break; 2562 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: 2563 PM8001_IO_DBG(pm8001_ha, 2564 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); 2565 ts->resp = SAS_TASK_COMPLETE; 2566 ts->stat = SAS_OPEN_TO; 2567 break; 2568 case IO_XFER_ERROR_OFFSET_MISMATCH: 2569 PM8001_IO_DBG(pm8001_ha, 2570 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); 2571 ts->resp = SAS_TASK_COMPLETE; 2572 ts->stat = SAS_OPEN_TO; 2573 break; 2574 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: 2575 PM8001_IO_DBG(pm8001_ha, 2576 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); 2577 ts->resp = SAS_TASK_COMPLETE; 2578 ts->stat = SAS_OPEN_TO; 2579 break; 2580 case IO_XFER_CMD_FRAME_ISSUED: 2581 PM8001_IO_DBG(pm8001_ha, 2582 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); 2583 break; 2584 case IO_XFER_PIO_SETUP_ERROR: 2585 PM8001_IO_DBG(pm8001_ha, 2586 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n")); 2587 ts->resp = SAS_TASK_COMPLETE; 2588 ts->stat = SAS_OPEN_TO; 2589 break; 2590 default: 2591 PM8001_IO_DBG(pm8001_ha, 2592 pm8001_printk("Unknown status 0x%x\n", event)); 2593 /* not allowed case. Therefore, return failed status */ 2594 ts->resp = SAS_TASK_COMPLETE; 2595 ts->stat = SAS_OPEN_TO; 2596 break; 2597 } 2598 spin_lock_irqsave(&t->task_state_lock, flags); 2599 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2600 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2601 t->task_state_flags |= SAS_TASK_STATE_DONE; 2602 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2603 spin_unlock_irqrestore(&t->task_state_lock, flags); 2604 PM8001_FAIL_DBG(pm8001_ha, 2605 pm8001_printk("task 0x%p done with io_status 0x%x" 2606 " resp 0x%x stat 0x%x but aborted by upper layer!\n", 2607 t, event, ts->resp, ts->stat)); 2608 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2609 } else if (t->uldd_task) { 2610 spin_unlock_irqrestore(&t->task_state_lock, flags); 2611 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2612 mb();/* ditto */ 2613 spin_unlock_irq(&pm8001_ha->lock); 2614 t->task_done(t); 2615 spin_lock_irq(&pm8001_ha->lock); 2616 } else if (!t->uldd_task) { 2617 spin_unlock_irqrestore(&t->task_state_lock, flags); 2618 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2619 mb();/*ditto*/ 2620 spin_unlock_irq(&pm8001_ha->lock); 2621 t->task_done(t); 2622 spin_lock_irq(&pm8001_ha->lock); 2623 } 2624} 2625 2626/*See the comments for mpi_ssp_completion */ 2627static void 2628mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) 2629{ 2630 u32 param; 2631 struct sas_task *t; 2632 struct pm8001_ccb_info *ccb; 2633 unsigned long flags; 2634 u32 status; 2635 u32 tag; 2636 struct smp_completion_resp *psmpPayload; 2637 struct task_status_struct *ts; 2638 struct pm8001_device *pm8001_dev; 2639 2640 psmpPayload = (struct smp_completion_resp *)(piomb + 4); 2641 status = le32_to_cpu(psmpPayload->status); 2642 tag = le32_to_cpu(psmpPayload->tag); 2643 2644 ccb = &pm8001_ha->ccb_info[tag]; 2645 param = le32_to_cpu(psmpPayload->param); 2646 t = ccb->task; 2647 ts = &t->task_status; 2648 pm8001_dev = ccb->device; 2649 if (status) 2650 PM8001_FAIL_DBG(pm8001_ha, 2651 pm8001_printk("smp IO status 0x%x\n", status)); 2652 if (unlikely(!t || !t->lldd_task || !t->dev)) 2653 return; 2654 2655 switch (status) { 2656 case IO_SUCCESS: 2657 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 2658 ts->resp = SAS_TASK_COMPLETE; 2659 ts->stat = SAM_STAT_GOOD; 2660 if (pm8001_dev) 2661 pm8001_dev->running_req--; 2662 break; 2663 case IO_ABORTED: 2664 PM8001_IO_DBG(pm8001_ha, 2665 pm8001_printk("IO_ABORTED IOMB\n")); 2666 ts->resp = SAS_TASK_COMPLETE; 2667 ts->stat = SAS_ABORTED_TASK; 2668 if (pm8001_dev) 2669 pm8001_dev->running_req--; 2670 break; 2671 case IO_OVERFLOW: 2672 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); 2673 ts->resp = SAS_TASK_COMPLETE; 2674 ts->stat = SAS_DATA_OVERRUN; 2675 ts->residual = 0; 2676 if (pm8001_dev) 2677 pm8001_dev->running_req--; 2678 break; 2679 case IO_NO_DEVICE: 2680 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n")); 2681 ts->resp = SAS_TASK_COMPLETE; 2682 ts->stat = SAS_PHY_DOWN; 2683 break; 2684 case IO_ERROR_HW_TIMEOUT: 2685 PM8001_IO_DBG(pm8001_ha, 2686 pm8001_printk("IO_ERROR_HW_TIMEOUT\n")); 2687 ts->resp = SAS_TASK_COMPLETE; 2688 ts->stat = SAM_STAT_BUSY; 2689 break; 2690 case IO_XFER_ERROR_BREAK: 2691 PM8001_IO_DBG(pm8001_ha, 2692 pm8001_printk("IO_XFER_ERROR_BREAK\n")); 2693 ts->resp = SAS_TASK_COMPLETE; 2694 ts->stat = SAM_STAT_BUSY; 2695 break; 2696 case IO_XFER_ERROR_PHY_NOT_READY: 2697 PM8001_IO_DBG(pm8001_ha, 2698 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); 2699 ts->resp = SAS_TASK_COMPLETE; 2700 ts->stat = SAM_STAT_BUSY; 2701 break; 2702 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 2703 PM8001_IO_DBG(pm8001_ha, 2704 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); 2705 ts->resp = SAS_TASK_COMPLETE; 2706 ts->stat = SAS_OPEN_REJECT; 2707 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2708 break; 2709 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 2710 PM8001_IO_DBG(pm8001_ha, 2711 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); 2712 ts->resp = SAS_TASK_COMPLETE; 2713 ts->stat = SAS_OPEN_REJECT; 2714 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2715 break; 2716 case IO_OPEN_CNX_ERROR_BREAK: 2717 PM8001_IO_DBG(pm8001_ha, 2718 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); 2719 ts->resp = SAS_TASK_COMPLETE; 2720 ts->stat = SAS_OPEN_REJECT; 2721 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; 2722 break; 2723 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 2724 PM8001_IO_DBG(pm8001_ha, 2725 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); 2726 ts->resp = SAS_TASK_COMPLETE; 2727 ts->stat = SAS_OPEN_REJECT; 2728 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 2729 pm8001_handle_event(pm8001_ha, 2730 pm8001_dev, 2731 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); 2732 break; 2733 case IO_OPEN_CNX_ERROR_BAD_DESTINATION: 2734 PM8001_IO_DBG(pm8001_ha, 2735 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); 2736 ts->resp = SAS_TASK_COMPLETE; 2737 ts->stat = SAS_OPEN_REJECT; 2738 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 2739 break; 2740 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 2741 PM8001_IO_DBG(pm8001_ha, 2742 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_" 2743 "NOT_SUPPORTED\n")); 2744 ts->resp = SAS_TASK_COMPLETE; 2745 ts->stat = SAS_OPEN_REJECT; 2746 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 2747 break; 2748 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 2749 PM8001_IO_DBG(pm8001_ha, 2750 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); 2751 ts->resp = SAS_TASK_COMPLETE; 2752 ts->stat = SAS_OPEN_REJECT; 2753 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 2754 break; 2755 case IO_XFER_ERROR_RX_FRAME: 2756 PM8001_IO_DBG(pm8001_ha, 2757 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n")); 2758 ts->resp = SAS_TASK_COMPLETE; 2759 ts->stat = SAS_DEV_NO_RESPONSE; 2760 break; 2761 case IO_XFER_OPEN_RETRY_TIMEOUT: 2762 PM8001_IO_DBG(pm8001_ha, 2763 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); 2764 ts->resp = SAS_TASK_COMPLETE; 2765 ts->stat = SAS_OPEN_REJECT; 2766 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2767 break; 2768 case IO_ERROR_INTERNAL_SMP_RESOURCE: 2769 PM8001_IO_DBG(pm8001_ha, 2770 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n")); 2771 ts->resp = SAS_TASK_COMPLETE; 2772 ts->stat = SAS_QUEUE_FULL; 2773 break; 2774 case IO_PORT_IN_RESET: 2775 PM8001_IO_DBG(pm8001_ha, 2776 pm8001_printk("IO_PORT_IN_RESET\n")); 2777 ts->resp = SAS_TASK_COMPLETE; 2778 ts->stat = SAS_OPEN_REJECT; 2779 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2780 break; 2781 case IO_DS_NON_OPERATIONAL: 2782 PM8001_IO_DBG(pm8001_ha, 2783 pm8001_printk("IO_DS_NON_OPERATIONAL\n")); 2784 ts->resp = SAS_TASK_COMPLETE; 2785 ts->stat = SAS_DEV_NO_RESPONSE; 2786 break; 2787 case IO_DS_IN_RECOVERY: 2788 PM8001_IO_DBG(pm8001_ha, 2789 pm8001_printk("IO_DS_IN_RECOVERY\n")); 2790 ts->resp = SAS_TASK_COMPLETE; 2791 ts->stat = SAS_OPEN_REJECT; 2792 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2793 break; 2794 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 2795 PM8001_IO_DBG(pm8001_ha, 2796 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); 2797 ts->resp = SAS_TASK_COMPLETE; 2798 ts->stat = SAS_OPEN_REJECT; 2799 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2800 break; 2801 default: 2802 PM8001_IO_DBG(pm8001_ha, 2803 pm8001_printk("Unknown status 0x%x\n", status)); 2804 ts->resp = SAS_TASK_COMPLETE; 2805 ts->stat = SAS_DEV_NO_RESPONSE; 2806 /* not allowed case. Therefore, return failed status */ 2807 break; 2808 } 2809 spin_lock_irqsave(&t->task_state_lock, flags); 2810 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 2811 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 2812 t->task_state_flags |= SAS_TASK_STATE_DONE; 2813 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { 2814 spin_unlock_irqrestore(&t->task_state_lock, flags); 2815 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with" 2816 " io_status 0x%x resp 0x%x " 2817 "stat 0x%x but aborted by upper layer!\n", 2818 t, status, ts->resp, ts->stat)); 2819 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2820 } else { 2821 spin_unlock_irqrestore(&t->task_state_lock, flags); 2822 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 2823 mb();/* in order to force CPU ordering */ 2824 t->task_done(t); 2825 } 2826} 2827 2828static void 2829mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 2830{ 2831 struct set_dev_state_resp *pPayload = 2832 (struct set_dev_state_resp *)(piomb + 4); 2833 u32 tag = le32_to_cpu(pPayload->tag); 2834 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 2835 struct pm8001_device *pm8001_dev = ccb->device; 2836 u32 status = le32_to_cpu(pPayload->status); 2837 u32 device_id = le32_to_cpu(pPayload->device_id); 2838 u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS; 2839 u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS; 2840 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state " 2841 "from 0x%x to 0x%x status = 0x%x!\n", 2842 device_id, pds, nds, status)); 2843 complete(pm8001_dev->setds_completion); 2844 ccb->task = NULL; 2845 ccb->ccb_tag = 0xFFFFFFFF; 2846 pm8001_ccb_free(pm8001_ha, tag); 2847} 2848 2849static void 2850mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 2851{ 2852 struct get_nvm_data_resp *pPayload = 2853 (struct get_nvm_data_resp *)(piomb + 4); 2854 u32 tag = le32_to_cpu(pPayload->tag); 2855 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 2856 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 2857 complete(pm8001_ha->nvmd_completion); 2858 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n")); 2859 if ((dlen_status & NVMD_STAT) != 0) { 2860 PM8001_FAIL_DBG(pm8001_ha, 2861 pm8001_printk("Set nvm data error!\n")); 2862 return; 2863 } 2864 ccb->task = NULL; 2865 ccb->ccb_tag = 0xFFFFFFFF; 2866 pm8001_ccb_free(pm8001_ha, tag); 2867} 2868 2869static void 2870mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 2871{ 2872 struct fw_control_ex *fw_control_context; 2873 struct get_nvm_data_resp *pPayload = 2874 (struct get_nvm_data_resp *)(piomb + 4); 2875 u32 tag = le32_to_cpu(pPayload->tag); 2876 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 2877 u32 dlen_status = le32_to_cpu(pPayload->dlen_status); 2878 u32 ir_tds_bn_dps_das_nvm = 2879 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm); 2880 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr; 2881 fw_control_context = ccb->fw_control_context; 2882 2883 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n")); 2884 if ((dlen_status & NVMD_STAT) != 0) { 2885 PM8001_FAIL_DBG(pm8001_ha, 2886 pm8001_printk("Get nvm data error!\n")); 2887 complete(pm8001_ha->nvmd_completion); 2888 return; 2889 } 2890 2891 if (ir_tds_bn_dps_das_nvm & IPMode) { 2892 /* indirect mode - IR bit set */ 2893 PM8001_MSG_DBG(pm8001_ha, 2894 pm8001_printk("Get NVMD success, IR=1\n")); 2895 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) { 2896 if (ir_tds_bn_dps_das_nvm == 0x80a80200) { 2897 memcpy(pm8001_ha->sas_addr, 2898 ((u8 *)virt_addr + 4), 2899 SAS_ADDR_SIZE); 2900 PM8001_MSG_DBG(pm8001_ha, 2901 pm8001_printk("Get SAS address" 2902 " from VPD successfully!\n")); 2903 } 2904 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM) 2905 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) || 2906 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) { 2907 ; 2908 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP) 2909 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) { 2910 ; 2911 } else { 2912 /* Should not be happened*/ 2913 PM8001_MSG_DBG(pm8001_ha, 2914 pm8001_printk("(IR=1)Wrong Device type 0x%x\n", 2915 ir_tds_bn_dps_das_nvm)); 2916 } 2917 } else /* direct mode */{ 2918 PM8001_MSG_DBG(pm8001_ha, 2919 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n", 2920 (dlen_status & NVMD_LEN) >> 24)); 2921 } 2922 memcpy(fw_control_context->usrAddr, 2923 pm8001_ha->memoryMap.region[NVMD].virt_ptr, 2924 fw_control_context->len); 2925 complete(pm8001_ha->nvmd_completion); 2926 ccb->task = NULL; 2927 ccb->ccb_tag = 0xFFFFFFFF; 2928 pm8001_ccb_free(pm8001_ha, tag); 2929} 2930 2931static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb) 2932{ 2933 struct local_phy_ctl_resp *pPayload = 2934 (struct local_phy_ctl_resp *)(piomb + 4); 2935 u32 status = le32_to_cpu(pPayload->status); 2936 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS; 2937 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS; 2938 if (status != 0) { 2939 PM8001_MSG_DBG(pm8001_ha, 2940 pm8001_printk("%x phy execute %x phy op failed!\n", 2941 phy_id, phy_op)); 2942 } else 2943 PM8001_MSG_DBG(pm8001_ha, 2944 pm8001_printk("%x phy execute %x phy op success!\n", 2945 phy_id, phy_op)); 2946 return 0; 2947} 2948 2949/** 2950 * pm8001_bytes_dmaed - one of the interface function communication with libsas 2951 * @pm8001_ha: our hba card information 2952 * @i: which phy that received the event. 2953 * 2954 * when HBA driver received the identify done event or initiate FIS received 2955 * event(for SATA), it will invoke this function to notify the sas layer that 2956 * the sas toplogy has formed, please discover the the whole sas domain, 2957 * while receive a broadcast(change) primitive just tell the sas 2958 * layer to discover the changed domain rather than the whole domain. 2959 */ 2960static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i) 2961{ 2962 struct pm8001_phy *phy = &pm8001_ha->phy[i]; 2963 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2964 struct sas_ha_struct *sas_ha; 2965 if (!phy->phy_attached) 2966 return; 2967 2968 sas_ha = pm8001_ha->sas; 2969 if (sas_phy->phy) { 2970 struct sas_phy *sphy = sas_phy->phy; 2971 sphy->negotiated_linkrate = sas_phy->linkrate; 2972 sphy->minimum_linkrate = phy->minimum_linkrate; 2973 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 2974 sphy->maximum_linkrate = phy->maximum_linkrate; 2975 sphy->maximum_linkrate_hw = phy->maximum_linkrate; 2976 } 2977 2978 if (phy->phy_type & PORT_TYPE_SAS) { 2979 struct sas_identify_frame *id; 2980 id = (struct sas_identify_frame *)phy->frame_rcvd; 2981 id->dev_type = phy->identify.device_type; 2982 id->initiator_bits = SAS_PROTOCOL_ALL; 2983 id->target_bits = phy->identify.target_port_protocols; 2984 } else if (phy->phy_type & PORT_TYPE_SATA) { 2985 /*Nothing*/ 2986 } 2987 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i)); 2988 2989 sas_phy->frame_rcvd_size = phy->frame_rcvd_size; 2990 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED); 2991} 2992 2993/* Get the link rate speed */ 2994static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate) 2995{ 2996 struct sas_phy *sas_phy = phy->sas_phy.phy; 2997 2998 switch (link_rate) { 2999 case PHY_SPEED_60: 3000 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; 3001 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; 3002 break; 3003 case PHY_SPEED_30: 3004 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; 3005 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; 3006 break; 3007 case PHY_SPEED_15: 3008 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; 3009 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS; 3010 break; 3011 } 3012 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate; 3013 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS; 3014 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS; 3015 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS; 3016 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS; 3017} 3018 3019/** 3020 * asd_get_attached_sas_addr -- extract/generate attached SAS address 3021 * @phy: pointer to asd_phy 3022 * @sas_addr: pointer to buffer where the SAS address is to be written 3023 * 3024 * This function extracts the SAS address from an IDENTIFY frame 3025 * received. If OOB is SATA, then a SAS address is generated from the 3026 * HA tables. 3027 * 3028 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame 3029 * buffer. 3030 */ 3031static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, 3032 u8 *sas_addr) 3033{ 3034 if (phy->sas_phy.frame_rcvd[0] == 0x34 3035 && phy->sas_phy.oob_mode == SATA_OOB_MODE) { 3036 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha; 3037 /* FIS device-to-host */ 3038 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr); 3039 addr += phy->sas_phy.id; 3040 *(__be64 *)sas_addr = cpu_to_be64(addr); 3041 } else { 3042 struct sas_identify_frame *idframe = 3043 (void *) phy->sas_phy.frame_rcvd; 3044 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE); 3045 } 3046} 3047 3048/** 3049 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW. 3050 * @pm8001_ha: our hba card information 3051 * @Qnum: the outbound queue message number. 3052 * @SEA: source of event to ack 3053 * @port_id: port id. 3054 * @phyId: phy id. 3055 * @param0: parameter 0. 3056 * @param1: parameter 1. 3057 */ 3058static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, 3059 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) 3060{ 3061 struct hw_event_ack_req payload; 3062 u32 opc = OPC_INB_SAS_HW_EVENT_ACK; 3063 3064 struct inbound_queue_table *circularQ; 3065 3066 memset((u8 *)&payload, 0, sizeof(payload)); 3067 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; 3068 payload.tag = cpu_to_le32(1); 3069 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | 3070 ((phyId & 0x0F) << 4) | (port_id & 0x0F)); 3071 payload.param0 = cpu_to_le32(param0); 3072 payload.param1 = cpu_to_le32(param1); 3073 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 3074} 3075 3076static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 3077 u32 phyId, u32 phy_op); 3078 3079/** 3080 * hw_event_sas_phy_up -FW tells me a SAS phy up event. 3081 * @pm8001_ha: our hba card information 3082 * @piomb: IO message buffer 3083 */ 3084static void 3085hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3086{ 3087 struct hw_event_resp *pPayload = 3088 (struct hw_event_resp *)(piomb + 4); 3089 u32 lr_evt_status_phyid_portid = 3090 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3091 u8 link_rate = 3092 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3093 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3094 u8 phy_id = 3095 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3096 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3097 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3098 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3099 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3100 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3101 unsigned long flags; 3102 u8 deviceType = pPayload->sas_identify.dev_type; 3103 port->port_state = portstate; 3104 PM8001_MSG_DBG(pm8001_ha, 3105 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n", 3106 port_id, phy_id)); 3107 3108 switch (deviceType) { 3109 case SAS_PHY_UNUSED: 3110 PM8001_MSG_DBG(pm8001_ha, 3111 pm8001_printk("device type no device.\n")); 3112 break; 3113 case SAS_END_DEVICE: 3114 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n")); 3115 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id, 3116 PHY_NOTIFY_ENABLE_SPINUP); 3117 port->port_attached = 1; 3118 get_lrate_mode(phy, link_rate); 3119 break; 3120 case SAS_EDGE_EXPANDER_DEVICE: 3121 PM8001_MSG_DBG(pm8001_ha, 3122 pm8001_printk("expander device.\n")); 3123 port->port_attached = 1; 3124 get_lrate_mode(phy, link_rate); 3125 break; 3126 case SAS_FANOUT_EXPANDER_DEVICE: 3127 PM8001_MSG_DBG(pm8001_ha, 3128 pm8001_printk("fanout expander device.\n")); 3129 port->port_attached = 1; 3130 get_lrate_mode(phy, link_rate); 3131 break; 3132 default: 3133 PM8001_MSG_DBG(pm8001_ha, 3134 pm8001_printk("unknown device type(%x)\n", deviceType)); 3135 break; 3136 } 3137 phy->phy_type |= PORT_TYPE_SAS; 3138 phy->identify.device_type = deviceType; 3139 phy->phy_attached = 1; 3140 if (phy->identify.device_type == SAS_END_DEVICE) 3141 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; 3142 else if (phy->identify.device_type != SAS_PHY_UNUSED) 3143 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; 3144 phy->sas_phy.oob_mode = SAS_OOB_MODE; 3145 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3146 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3147 memcpy(phy->frame_rcvd, &pPayload->sas_identify, 3148 sizeof(struct sas_identify_frame)-4); 3149 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; 3150 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3151 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3152 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3153 mdelay(200);/*delay a moment to wait disk to spinup*/ 3154 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3155} 3156 3157/** 3158 * hw_event_sata_phy_up -FW tells me a SATA phy up event. 3159 * @pm8001_ha: our hba card information 3160 * @piomb: IO message buffer 3161 */ 3162static void 3163hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) 3164{ 3165 struct hw_event_resp *pPayload = 3166 (struct hw_event_resp *)(piomb + 4); 3167 u32 lr_evt_status_phyid_portid = 3168 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3169 u8 link_rate = 3170 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28); 3171 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3172 u8 phy_id = 3173 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3174 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3175 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3176 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3177 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3178 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3179 unsigned long flags; 3180 PM8001_MSG_DBG(pm8001_ha, 3181 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d," 3182 " phy id = %d\n", port_id, phy_id)); 3183 port->port_state = portstate; 3184 port->port_attached = 1; 3185 get_lrate_mode(phy, link_rate); 3186 phy->phy_type |= PORT_TYPE_SATA; 3187 phy->phy_attached = 1; 3188 phy->sas_phy.oob_mode = SATA_OOB_MODE; 3189 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); 3190 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); 3191 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), 3192 sizeof(struct dev_to_host_fis)); 3193 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 3194 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 3195 phy->identify.device_type = SATA_DEV; 3196 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); 3197 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); 3198 pm8001_bytes_dmaed(pm8001_ha, phy_id); 3199} 3200 3201/** 3202 * hw_event_phy_down -we should notify the libsas the phy is down. 3203 * @pm8001_ha: our hba card information 3204 * @piomb: IO message buffer 3205 */ 3206static void 3207hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) 3208{ 3209 struct hw_event_resp *pPayload = 3210 (struct hw_event_resp *)(piomb + 4); 3211 u32 lr_evt_status_phyid_portid = 3212 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3213 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3214 u8 phy_id = 3215 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3216 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate); 3217 u8 portstate = (u8)(npip_portstate & 0x0000000F); 3218 struct pm8001_port *port = &pm8001_ha->port[port_id]; 3219 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3220 port->port_state = portstate; 3221 phy->phy_type = 0; 3222 phy->identify.device_type = 0; 3223 phy->phy_attached = 0; 3224 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE); 3225 switch (portstate) { 3226 case PORT_VALID: 3227 break; 3228 case PORT_INVALID: 3229 PM8001_MSG_DBG(pm8001_ha, 3230 pm8001_printk(" PortInvalid portID %d\n", port_id)); 3231 PM8001_MSG_DBG(pm8001_ha, 3232 pm8001_printk(" Last phy Down and port invalid\n")); 3233 port->port_attached = 0; 3234 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3235 port_id, phy_id, 0, 0); 3236 break; 3237 case PORT_IN_RESET: 3238 PM8001_MSG_DBG(pm8001_ha, 3239 pm8001_printk(" Port In Reset portID %d\n", port_id)); 3240 break; 3241 case PORT_NOT_ESTABLISHED: 3242 PM8001_MSG_DBG(pm8001_ha, 3243 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n")); 3244 port->port_attached = 0; 3245 break; 3246 case PORT_LOSTCOMM: 3247 PM8001_MSG_DBG(pm8001_ha, 3248 pm8001_printk(" phy Down and PORT_LOSTCOMM\n")); 3249 PM8001_MSG_DBG(pm8001_ha, 3250 pm8001_printk(" Last phy Down and port invalid\n")); 3251 port->port_attached = 0; 3252 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, 3253 port_id, phy_id, 0, 0); 3254 break; 3255 default: 3256 port->port_attached = 0; 3257 PM8001_MSG_DBG(pm8001_ha, 3258 pm8001_printk(" phy Down and(default) = %x\n", 3259 portstate)); 3260 break; 3261 3262 } 3263} 3264 3265/** 3266 * mpi_reg_resp -process register device ID response. 3267 * @pm8001_ha: our hba card information 3268 * @piomb: IO message buffer 3269 * 3270 * when sas layer find a device it will notify LLDD, then the driver register 3271 * the domain device to FW, this event is the return device ID which the FW 3272 * has assigned, from now,inter-communication with FW is no longer using the 3273 * SAS address, use device ID which FW assigned. 3274 */ 3275static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3276{ 3277 u32 status; 3278 u32 device_id; 3279 u32 htag; 3280 struct pm8001_ccb_info *ccb; 3281 struct pm8001_device *pm8001_dev; 3282 struct dev_reg_resp *registerRespPayload = 3283 (struct dev_reg_resp *)(piomb + 4); 3284 3285 htag = le32_to_cpu(registerRespPayload->tag); 3286 ccb = &pm8001_ha->ccb_info[htag]; 3287 pm8001_dev = ccb->device; 3288 status = le32_to_cpu(registerRespPayload->status); 3289 device_id = le32_to_cpu(registerRespPayload->device_id); 3290 PM8001_MSG_DBG(pm8001_ha, 3291 pm8001_printk(" register device is status = %d\n", status)); 3292 switch (status) { 3293 case DEVREG_SUCCESS: 3294 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n")); 3295 pm8001_dev->device_id = device_id; 3296 break; 3297 case DEVREG_FAILURE_OUT_OF_RESOURCE: 3298 PM8001_MSG_DBG(pm8001_ha, 3299 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n")); 3300 break; 3301 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED: 3302 PM8001_MSG_DBG(pm8001_ha, 3303 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n")); 3304 break; 3305 case DEVREG_FAILURE_INVALID_PHY_ID: 3306 PM8001_MSG_DBG(pm8001_ha, 3307 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n")); 3308 break; 3309 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED: 3310 PM8001_MSG_DBG(pm8001_ha, 3311 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n")); 3312 break; 3313 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE: 3314 PM8001_MSG_DBG(pm8001_ha, 3315 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n")); 3316 break; 3317 case DEVREG_FAILURE_PORT_NOT_VALID_STATE: 3318 PM8001_MSG_DBG(pm8001_ha, 3319 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n")); 3320 break; 3321 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID: 3322 PM8001_MSG_DBG(pm8001_ha, 3323 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n")); 3324 break; 3325 default: 3326 PM8001_MSG_DBG(pm8001_ha, 3327 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n")); 3328 break; 3329 } 3330 complete(pm8001_dev->dcompletion); 3331 ccb->task = NULL; 3332 ccb->ccb_tag = 0xFFFFFFFF; 3333 pm8001_ccb_free(pm8001_ha, htag); 3334 return 0; 3335} 3336 3337static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3338{ 3339 u32 status; 3340 u32 device_id; 3341 struct dev_reg_resp *registerRespPayload = 3342 (struct dev_reg_resp *)(piomb + 4); 3343 3344 status = le32_to_cpu(registerRespPayload->status); 3345 device_id = le32_to_cpu(registerRespPayload->device_id); 3346 if (status != 0) 3347 PM8001_MSG_DBG(pm8001_ha, 3348 pm8001_printk(" deregister device failed ,status = %x" 3349 ", device_id = %x\n", status, device_id)); 3350 return 0; 3351} 3352 3353static int 3354mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3355{ 3356 u32 status; 3357 struct fw_control_ex fw_control_context; 3358 struct fw_flash_Update_resp *ppayload = 3359 (struct fw_flash_Update_resp *)(piomb + 4); 3360 u32 tag = ppayload->tag; 3361 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; 3362 status = le32_to_cpu(ppayload->status); 3363 memcpy(&fw_control_context, 3364 ccb->fw_control_context, 3365 sizeof(fw_control_context)); 3366 switch (status) { 3367 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT: 3368 PM8001_MSG_DBG(pm8001_ha, 3369 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n")); 3370 break; 3371 case FLASH_UPDATE_IN_PROGRESS: 3372 PM8001_MSG_DBG(pm8001_ha, 3373 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n")); 3374 break; 3375 case FLASH_UPDATE_HDR_ERR: 3376 PM8001_MSG_DBG(pm8001_ha, 3377 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n")); 3378 break; 3379 case FLASH_UPDATE_OFFSET_ERR: 3380 PM8001_MSG_DBG(pm8001_ha, 3381 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n")); 3382 break; 3383 case FLASH_UPDATE_CRC_ERR: 3384 PM8001_MSG_DBG(pm8001_ha, 3385 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n")); 3386 break; 3387 case FLASH_UPDATE_LENGTH_ERR: 3388 PM8001_MSG_DBG(pm8001_ha, 3389 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n")); 3390 break; 3391 case FLASH_UPDATE_HW_ERR: 3392 PM8001_MSG_DBG(pm8001_ha, 3393 pm8001_printk(": FLASH_UPDATE_HW_ERR\n")); 3394 break; 3395 case FLASH_UPDATE_DNLD_NOT_SUPPORTED: 3396 PM8001_MSG_DBG(pm8001_ha, 3397 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n")); 3398 break; 3399 case FLASH_UPDATE_DISABLED: 3400 PM8001_MSG_DBG(pm8001_ha, 3401 pm8001_printk(": FLASH_UPDATE_DISABLED\n")); 3402 break; 3403 default: 3404 PM8001_MSG_DBG(pm8001_ha, 3405 pm8001_printk("No matched status = %d\n", status)); 3406 break; 3407 } 3408 ccb->fw_control_context->fw_control->retcode = status; 3409 pci_free_consistent(pm8001_ha->pdev, 3410 fw_control_context.len, 3411 fw_control_context.virtAddr, 3412 fw_control_context.phys_addr); 3413 complete(pm8001_ha->nvmd_completion); 3414 ccb->task = NULL; 3415 ccb->ccb_tag = 0xFFFFFFFF; 3416 pm8001_ccb_free(pm8001_ha, tag); 3417 return 0; 3418} 3419 3420static int 3421mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb) 3422{ 3423 u32 status; 3424 int i; 3425 struct general_event_resp *pPayload = 3426 (struct general_event_resp *)(piomb + 4); 3427 status = le32_to_cpu(pPayload->status); 3428 PM8001_MSG_DBG(pm8001_ha, 3429 pm8001_printk(" status = 0x%x\n", status)); 3430 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++) 3431 PM8001_MSG_DBG(pm8001_ha, 3432 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i, 3433 pPayload->inb_IOMB_payload[i])); 3434 return 0; 3435} 3436 3437static int 3438mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) 3439{ 3440 struct sas_task *t; 3441 struct pm8001_ccb_info *ccb; 3442 unsigned long flags; 3443 u32 status ; 3444 u32 tag, scp; 3445 struct task_status_struct *ts; 3446 3447 struct task_abort_resp *pPayload = 3448 (struct task_abort_resp *)(piomb + 4); 3449 3450 status = le32_to_cpu(pPayload->status); 3451 tag = le32_to_cpu(pPayload->tag); 3452 scp = le32_to_cpu(pPayload->scp); 3453 ccb = &pm8001_ha->ccb_info[tag]; 3454 t = ccb->task; 3455 PM8001_IO_DBG(pm8001_ha, 3456 pm8001_printk(" status = 0x%x\n", status)); 3457 if (t == NULL) 3458 return -1; 3459 ts = &t->task_status; 3460 if (status != 0) 3461 PM8001_FAIL_DBG(pm8001_ha, 3462 pm8001_printk("task abort failed status 0x%x ," 3463 "tag = 0x%x, scp= 0x%x\n", status, tag, scp)); 3464 switch (status) { 3465 case IO_SUCCESS: 3466 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); 3467 ts->resp = SAS_TASK_COMPLETE; 3468 ts->stat = SAM_STAT_GOOD; 3469 break; 3470 case IO_NOT_VALID: 3471 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n")); 3472 ts->resp = TMF_RESP_FUNC_FAILED; 3473 break; 3474 } 3475 spin_lock_irqsave(&t->task_state_lock, flags); 3476 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; 3477 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; 3478 t->task_state_flags |= SAS_TASK_STATE_DONE; 3479 spin_unlock_irqrestore(&t->task_state_lock, flags); 3480 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); 3481 mb(); 3482 t->task_done(t); 3483 return 0; 3484} 3485 3486/** 3487 * mpi_hw_event -The hw event has come. 3488 * @pm8001_ha: our hba card information 3489 * @piomb: IO message buffer 3490 */ 3491static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb) 3492{ 3493 unsigned long flags; 3494 struct hw_event_resp *pPayload = 3495 (struct hw_event_resp *)(piomb + 4); 3496 u32 lr_evt_status_phyid_portid = 3497 le32_to_cpu(pPayload->lr_evt_status_phyid_portid); 3498 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F); 3499 u8 phy_id = 3500 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4); 3501 u16 eventType = 3502 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8); 3503 u8 status = 3504 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24); 3505 struct sas_ha_struct *sas_ha = pm8001_ha->sas; 3506 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 3507 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; 3508 PM8001_MSG_DBG(pm8001_ha, 3509 pm8001_printk("outbound queue HW event & event type : ")); 3510 switch (eventType) { 3511 case HW_EVENT_PHY_START_STATUS: 3512 PM8001_MSG_DBG(pm8001_ha, 3513 pm8001_printk("HW_EVENT_PHY_START_STATUS" 3514 " status = %x\n", status)); 3515 if (status == 0) { 3516 phy->phy_state = 1; 3517 if (pm8001_ha->flags == PM8001F_RUN_TIME) 3518 complete(phy->enable_completion); 3519 } 3520 break; 3521 case HW_EVENT_SAS_PHY_UP: 3522 PM8001_MSG_DBG(pm8001_ha, 3523 pm8001_printk("HW_EVENT_PHY_START_STATUS\n")); 3524 hw_event_sas_phy_up(pm8001_ha, piomb); 3525 break; 3526 case HW_EVENT_SATA_PHY_UP: 3527 PM8001_MSG_DBG(pm8001_ha, 3528 pm8001_printk("HW_EVENT_SATA_PHY_UP\n")); 3529 hw_event_sata_phy_up(pm8001_ha, piomb); 3530 break; 3531 case HW_EVENT_PHY_STOP_STATUS: 3532 PM8001_MSG_DBG(pm8001_ha, 3533 pm8001_printk("HW_EVENT_PHY_STOP_STATUS " 3534 "status = %x\n", status)); 3535 if (status == 0) 3536 phy->phy_state = 0; 3537 break; 3538 case HW_EVENT_SATA_SPINUP_HOLD: 3539 PM8001_MSG_DBG(pm8001_ha, 3540 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n")); 3541 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); 3542 break; 3543 case HW_EVENT_PHY_DOWN: 3544 PM8001_MSG_DBG(pm8001_ha, 3545 pm8001_printk("HW_EVENT_PHY_DOWN\n")); 3546 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); 3547 phy->phy_attached = 0; 3548 phy->phy_state = 0; 3549 hw_event_phy_down(pm8001_ha, piomb); 3550 break; 3551 case HW_EVENT_PORT_INVALID: 3552 PM8001_MSG_DBG(pm8001_ha, 3553 pm8001_printk("HW_EVENT_PORT_INVALID\n")); 3554 sas_phy_disconnected(sas_phy); 3555 phy->phy_attached = 0; 3556 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3557 break; 3558 /* the broadcast change primitive received, tell the LIBSAS this event 3559 to revalidate the sas domain*/ 3560 case HW_EVENT_BROADCAST_CHANGE: 3561 PM8001_MSG_DBG(pm8001_ha, 3562 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n")); 3563 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, 3564 port_id, phy_id, 1, 0); 3565 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3566 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; 3567 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3568 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3569 break; 3570 case HW_EVENT_PHY_ERROR: 3571 PM8001_MSG_DBG(pm8001_ha, 3572 pm8001_printk("HW_EVENT_PHY_ERROR\n")); 3573 sas_phy_disconnected(&phy->sas_phy); 3574 phy->phy_attached = 0; 3575 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); 3576 break; 3577 case HW_EVENT_BROADCAST_EXP: 3578 PM8001_MSG_DBG(pm8001_ha, 3579 pm8001_printk("HW_EVENT_BROADCAST_EXP\n")); 3580 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3581 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; 3582 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3583 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3584 break; 3585 case HW_EVENT_LINK_ERR_INVALID_DWORD: 3586 PM8001_MSG_DBG(pm8001_ha, 3587 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n")); 3588 pm8001_hw_event_ack_req(pm8001_ha, 0, 3589 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); 3590 sas_phy_disconnected(sas_phy); 3591 phy->phy_attached = 0; 3592 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3593 break; 3594 case HW_EVENT_LINK_ERR_DISPARITY_ERROR: 3595 PM8001_MSG_DBG(pm8001_ha, 3596 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n")); 3597 pm8001_hw_event_ack_req(pm8001_ha, 0, 3598 HW_EVENT_LINK_ERR_DISPARITY_ERROR, 3599 port_id, phy_id, 0, 0); 3600 sas_phy_disconnected(sas_phy); 3601 phy->phy_attached = 0; 3602 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3603 break; 3604 case HW_EVENT_LINK_ERR_CODE_VIOLATION: 3605 PM8001_MSG_DBG(pm8001_ha, 3606 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n")); 3607 pm8001_hw_event_ack_req(pm8001_ha, 0, 3608 HW_EVENT_LINK_ERR_CODE_VIOLATION, 3609 port_id, phy_id, 0, 0); 3610 sas_phy_disconnected(sas_phy); 3611 phy->phy_attached = 0; 3612 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3613 break; 3614 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: 3615 PM8001_MSG_DBG(pm8001_ha, 3616 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n")); 3617 pm8001_hw_event_ack_req(pm8001_ha, 0, 3618 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, 3619 port_id, phy_id, 0, 0); 3620 sas_phy_disconnected(sas_phy); 3621 phy->phy_attached = 0; 3622 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3623 break; 3624 case HW_EVENT_MALFUNCTION: 3625 PM8001_MSG_DBG(pm8001_ha, 3626 pm8001_printk("HW_EVENT_MALFUNCTION\n")); 3627 break; 3628 case HW_EVENT_BROADCAST_SES: 3629 PM8001_MSG_DBG(pm8001_ha, 3630 pm8001_printk("HW_EVENT_BROADCAST_SES\n")); 3631 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); 3632 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; 3633 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); 3634 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 3635 break; 3636 case HW_EVENT_INBOUND_CRC_ERROR: 3637 PM8001_MSG_DBG(pm8001_ha, 3638 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n")); 3639 pm8001_hw_event_ack_req(pm8001_ha, 0, 3640 HW_EVENT_INBOUND_CRC_ERROR, 3641 port_id, phy_id, 0, 0); 3642 break; 3643 case HW_EVENT_HARD_RESET_RECEIVED: 3644 PM8001_MSG_DBG(pm8001_ha, 3645 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n")); 3646 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); 3647 break; 3648 case HW_EVENT_ID_FRAME_TIMEOUT: 3649 PM8001_MSG_DBG(pm8001_ha, 3650 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n")); 3651 sas_phy_disconnected(sas_phy); 3652 phy->phy_attached = 0; 3653 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3654 break; 3655 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: 3656 PM8001_MSG_DBG(pm8001_ha, 3657 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n")); 3658 pm8001_hw_event_ack_req(pm8001_ha, 0, 3659 HW_EVENT_LINK_ERR_PHY_RESET_FAILED, 3660 port_id, phy_id, 0, 0); 3661 sas_phy_disconnected(sas_phy); 3662 phy->phy_attached = 0; 3663 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3664 break; 3665 case HW_EVENT_PORT_RESET_TIMER_TMO: 3666 PM8001_MSG_DBG(pm8001_ha, 3667 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n")); 3668 sas_phy_disconnected(sas_phy); 3669 phy->phy_attached = 0; 3670 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3671 break; 3672 case HW_EVENT_PORT_RECOVERY_TIMER_TMO: 3673 PM8001_MSG_DBG(pm8001_ha, 3674 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n")); 3675 sas_phy_disconnected(sas_phy); 3676 phy->phy_attached = 0; 3677 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); 3678 break; 3679 case HW_EVENT_PORT_RECOVER: 3680 PM8001_MSG_DBG(pm8001_ha, 3681 pm8001_printk("HW_EVENT_PORT_RECOVER\n")); 3682 break; 3683 case HW_EVENT_PORT_RESET_COMPLETE: 3684 PM8001_MSG_DBG(pm8001_ha, 3685 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n")); 3686 break; 3687 case EVENT_BROADCAST_ASYNCH_EVENT: 3688 PM8001_MSG_DBG(pm8001_ha, 3689 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n")); 3690 break; 3691 default: 3692 PM8001_MSG_DBG(pm8001_ha, 3693 pm8001_printk("Unknown event type = %x\n", eventType)); 3694 break; 3695 } 3696 return 0; 3697} 3698 3699/** 3700 * process_one_iomb - process one outbound Queue memory block 3701 * @pm8001_ha: our hba card information 3702 * @piomb: IO message buffer 3703 */ 3704static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) 3705{ 3706 u32 pHeader = (u32)*(u32 *)piomb; 3707 u8 opc = (u8)(pHeader & 0xFFF); 3708 3709 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:")); 3710 3711 switch (opc) { 3712 case OPC_OUB_ECHO: 3713 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n")); 3714 break; 3715 case OPC_OUB_HW_EVENT: 3716 PM8001_MSG_DBG(pm8001_ha, 3717 pm8001_printk("OPC_OUB_HW_EVENT\n")); 3718 mpi_hw_event(pm8001_ha, piomb); 3719 break; 3720 case OPC_OUB_SSP_COMP: 3721 PM8001_MSG_DBG(pm8001_ha, 3722 pm8001_printk("OPC_OUB_SSP_COMP\n")); 3723 mpi_ssp_completion(pm8001_ha, piomb); 3724 break; 3725 case OPC_OUB_SMP_COMP: 3726 PM8001_MSG_DBG(pm8001_ha, 3727 pm8001_printk("OPC_OUB_SMP_COMP\n")); 3728 mpi_smp_completion(pm8001_ha, piomb); 3729 break; 3730 case OPC_OUB_LOCAL_PHY_CNTRL: 3731 PM8001_MSG_DBG(pm8001_ha, 3732 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n")); 3733 mpi_local_phy_ctl(pm8001_ha, piomb); 3734 break; 3735 case OPC_OUB_DEV_REGIST: 3736 PM8001_MSG_DBG(pm8001_ha, 3737 pm8001_printk("OPC_OUB_DEV_REGIST\n")); 3738 mpi_reg_resp(pm8001_ha, piomb); 3739 break; 3740 case OPC_OUB_DEREG_DEV: 3741 PM8001_MSG_DBG(pm8001_ha, 3742 pm8001_printk("unregister the device\n")); 3743 mpi_dereg_resp(pm8001_ha, piomb); 3744 break; 3745 case OPC_OUB_GET_DEV_HANDLE: 3746 PM8001_MSG_DBG(pm8001_ha, 3747 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n")); 3748 break; 3749 case OPC_OUB_SATA_COMP: 3750 PM8001_MSG_DBG(pm8001_ha, 3751 pm8001_printk("OPC_OUB_SATA_COMP\n")); 3752 mpi_sata_completion(pm8001_ha, piomb); 3753 break; 3754 case OPC_OUB_SATA_EVENT: 3755 PM8001_MSG_DBG(pm8001_ha, 3756 pm8001_printk("OPC_OUB_SATA_EVENT\n")); 3757 mpi_sata_event(pm8001_ha, piomb); 3758 break; 3759 case OPC_OUB_SSP_EVENT: 3760 PM8001_MSG_DBG(pm8001_ha, 3761 pm8001_printk("OPC_OUB_SSP_EVENT\n")); 3762 mpi_ssp_event(pm8001_ha, piomb); 3763 break; 3764 case OPC_OUB_DEV_HANDLE_ARRIV: 3765 PM8001_MSG_DBG(pm8001_ha, 3766 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n")); 3767 /*This is for target*/ 3768 break; 3769 case OPC_OUB_SSP_RECV_EVENT: 3770 PM8001_MSG_DBG(pm8001_ha, 3771 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n")); 3772 /*This is for target*/ 3773 break; 3774 case OPC_OUB_DEV_INFO: 3775 PM8001_MSG_DBG(pm8001_ha, 3776 pm8001_printk("OPC_OUB_DEV_INFO\n")); 3777 break; 3778 case OPC_OUB_FW_FLASH_UPDATE: 3779 PM8001_MSG_DBG(pm8001_ha, 3780 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n")); 3781 mpi_fw_flash_update_resp(pm8001_ha, piomb); 3782 break; 3783 case OPC_OUB_GPIO_RESPONSE: 3784 PM8001_MSG_DBG(pm8001_ha, 3785 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n")); 3786 break; 3787 case OPC_OUB_GPIO_EVENT: 3788 PM8001_MSG_DBG(pm8001_ha, 3789 pm8001_printk("OPC_OUB_GPIO_EVENT\n")); 3790 break; 3791 case OPC_OUB_GENERAL_EVENT: 3792 PM8001_MSG_DBG(pm8001_ha, 3793 pm8001_printk("OPC_OUB_GENERAL_EVENT\n")); 3794 mpi_general_event(pm8001_ha, piomb); 3795 break; 3796 case OPC_OUB_SSP_ABORT_RSP: 3797 PM8001_MSG_DBG(pm8001_ha, 3798 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n")); 3799 mpi_task_abort_resp(pm8001_ha, piomb); 3800 break; 3801 case OPC_OUB_SATA_ABORT_RSP: 3802 PM8001_MSG_DBG(pm8001_ha, 3803 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n")); 3804 mpi_task_abort_resp(pm8001_ha, piomb); 3805 break; 3806 case OPC_OUB_SAS_DIAG_MODE_START_END: 3807 PM8001_MSG_DBG(pm8001_ha, 3808 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n")); 3809 break; 3810 case OPC_OUB_SAS_DIAG_EXECUTE: 3811 PM8001_MSG_DBG(pm8001_ha, 3812 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n")); 3813 break; 3814 case OPC_OUB_GET_TIME_STAMP: 3815 PM8001_MSG_DBG(pm8001_ha, 3816 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n")); 3817 break; 3818 case OPC_OUB_SAS_HW_EVENT_ACK: 3819 PM8001_MSG_DBG(pm8001_ha, 3820 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n")); 3821 break; 3822 case OPC_OUB_PORT_CONTROL: 3823 PM8001_MSG_DBG(pm8001_ha, 3824 pm8001_printk("OPC_OUB_PORT_CONTROL\n")); 3825 break; 3826 case OPC_OUB_SMP_ABORT_RSP: 3827 PM8001_MSG_DBG(pm8001_ha, 3828 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n")); 3829 mpi_task_abort_resp(pm8001_ha, piomb); 3830 break; 3831 case OPC_OUB_GET_NVMD_DATA: 3832 PM8001_MSG_DBG(pm8001_ha, 3833 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n")); 3834 mpi_get_nvmd_resp(pm8001_ha, piomb); 3835 break; 3836 case OPC_OUB_SET_NVMD_DATA: 3837 PM8001_MSG_DBG(pm8001_ha, 3838 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n")); 3839 mpi_set_nvmd_resp(pm8001_ha, piomb); 3840 break; 3841 case OPC_OUB_DEVICE_HANDLE_REMOVAL: 3842 PM8001_MSG_DBG(pm8001_ha, 3843 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n")); 3844 break; 3845 case OPC_OUB_SET_DEVICE_STATE: 3846 PM8001_MSG_DBG(pm8001_ha, 3847 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n")); 3848 mpi_set_dev_state_resp(pm8001_ha, piomb); 3849 break; 3850 case OPC_OUB_GET_DEVICE_STATE: 3851 PM8001_MSG_DBG(pm8001_ha, 3852 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n")); 3853 break; 3854 case OPC_OUB_SET_DEV_INFO: 3855 PM8001_MSG_DBG(pm8001_ha, 3856 pm8001_printk("OPC_OUB_SET_DEV_INFO\n")); 3857 break; 3858 case OPC_OUB_SAS_RE_INITIALIZE: 3859 PM8001_MSG_DBG(pm8001_ha, 3860 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n")); 3861 break; 3862 default: 3863 PM8001_MSG_DBG(pm8001_ha, 3864 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n", 3865 opc)); 3866 break; 3867 } 3868} 3869 3870static int process_oq(struct pm8001_hba_info *pm8001_ha) 3871{ 3872 struct outbound_queue_table *circularQ; 3873 void *pMsg1 = NULL; 3874 u8 uninitialized_var(bc); 3875 u32 ret = MPI_IO_STATUS_FAIL; 3876 unsigned long flags; 3877 3878 spin_lock_irqsave(&pm8001_ha->lock, flags); 3879 circularQ = &pm8001_ha->outbnd_q_tbl[0]; 3880 do { 3881 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); 3882 if (MPI_IO_STATUS_SUCCESS == ret) { 3883 /* process the outbound message */ 3884 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); 3885 /* free the message from the outbound circular buffer */ 3886 mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc); 3887 } 3888 if (MPI_IO_STATUS_BUSY == ret) { 3889 /* Update the producer index from SPC */ 3890 circularQ->producer_index = 3891 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); 3892 if (le32_to_cpu(circularQ->producer_index) == 3893 circularQ->consumer_idx) 3894 /* OQ is empty */ 3895 break; 3896 } 3897 } while (1); 3898 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 3899 return ret; 3900} 3901 3902/* PCI_DMA_... to our direction translation. */ 3903static const u8 data_dir_flags[] = { 3904 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */ 3905 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */ 3906 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */ 3907 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */ 3908}; 3909static void 3910pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd) 3911{ 3912 int i; 3913 struct scatterlist *sg; 3914 struct pm8001_prd *buf_prd = prd; 3915 3916 for_each_sg(scatter, sg, nr, i) { 3917 buf_prd->addr = cpu_to_le64(sg_dma_address(sg)); 3918 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg)); 3919 buf_prd->im_len.e = 0; 3920 buf_prd++; 3921 } 3922} 3923 3924static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd) 3925{ 3926 psmp_cmd->tag = hTag; 3927 psmp_cmd->device_id = cpu_to_le32(deviceID); 3928 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); 3929} 3930 3931/** 3932 * pm8001_chip_smp_req - send a SMP task to FW 3933 * @pm8001_ha: our hba card information. 3934 * @ccb: the ccb information this request used. 3935 */ 3936static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha, 3937 struct pm8001_ccb_info *ccb) 3938{ 3939 int elem, rc; 3940 struct sas_task *task = ccb->task; 3941 struct domain_device *dev = task->dev; 3942 struct pm8001_device *pm8001_dev = dev->lldd_dev; 3943 struct scatterlist *sg_req, *sg_resp; 3944 u32 req_len, resp_len; 3945 struct smp_req smp_cmd; 3946 u32 opc; 3947 struct inbound_queue_table *circularQ; 3948 3949 memset(&smp_cmd, 0, sizeof(smp_cmd)); 3950 /* 3951 * DMA-map SMP request, response buffers 3952 */ 3953 sg_req = &task->smp_task.smp_req; 3954 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE); 3955 if (!elem) 3956 return -ENOMEM; 3957 req_len = sg_dma_len(sg_req); 3958 3959 sg_resp = &task->smp_task.smp_resp; 3960 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE); 3961 if (!elem) { 3962 rc = -ENOMEM; 3963 goto err_out; 3964 } 3965 resp_len = sg_dma_len(sg_resp); 3966 /* must be in dwords */ 3967 if ((req_len & 0x3) || (resp_len & 0x3)) { 3968 rc = -EINVAL; 3969 goto err_out_2; 3970 } 3971 3972 opc = OPC_INB_SMP_REQUEST; 3973 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 3974 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); 3975 smp_cmd.long_smp_req.long_req_addr = 3976 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); 3977 smp_cmd.long_smp_req.long_req_size = 3978 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); 3979 smp_cmd.long_smp_req.long_resp_addr = 3980 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp)); 3981 smp_cmd.long_smp_req.long_resp_size = 3982 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4); 3983 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd); 3984 mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd); 3985 return 0; 3986 3987err_out_2: 3988 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, 3989 PCI_DMA_FROMDEVICE); 3990err_out: 3991 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, 3992 PCI_DMA_TODEVICE); 3993 return rc; 3994} 3995 3996/** 3997 * pm8001_chip_ssp_io_req - send a SSP task to FW 3998 * @pm8001_ha: our hba card information. 3999 * @ccb: the ccb information this request used. 4000 */ 4001static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, 4002 struct pm8001_ccb_info *ccb) 4003{ 4004 struct sas_task *task = ccb->task; 4005 struct domain_device *dev = task->dev; 4006 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4007 struct ssp_ini_io_start_req ssp_cmd; 4008 u32 tag = ccb->ccb_tag; 4009 int ret; 4010 u64 phys_addr; 4011 struct inbound_queue_table *circularQ; 4012 u32 opc = OPC_INB_SSPINIIOSTART; 4013 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); 4014 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); 4015 ssp_cmd.dir_m_tlr = 4016 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for 4017 SAS 1.1 compatible TLR*/ 4018 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4019 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4020 ssp_cmd.tag = cpu_to_le32(tag); 4021 if (task->ssp_task.enable_first_burst) 4022 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; 4023 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); 4024 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); 4025 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16); 4026 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4027 4028 /* fill in PRD (scatter/gather) table, if any */ 4029 if (task->num_scatter > 1) { 4030 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4031 phys_addr = ccb->ccb_dma_handle + 4032 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4033 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr)); 4034 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr)); 4035 ssp_cmd.esgl = cpu_to_le32(1<<31); 4036 } else if (task->num_scatter == 1) { 4037 u64 dma_addr = sg_dma_address(task->scatter); 4038 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); 4039 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr)); 4040 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4041 ssp_cmd.esgl = 0; 4042 } else if (task->num_scatter == 0) { 4043 ssp_cmd.addr_low = 0; 4044 ssp_cmd.addr_high = 0; 4045 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); 4046 ssp_cmd.esgl = 0; 4047 } 4048 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd); 4049 return ret; 4050} 4051 4052static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha, 4053 struct pm8001_ccb_info *ccb) 4054{ 4055 struct sas_task *task = ccb->task; 4056 struct domain_device *dev = task->dev; 4057 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; 4058 u32 tag = ccb->ccb_tag; 4059 int ret; 4060 struct sata_start_req sata_cmd; 4061 u32 hdr_tag, ncg_tag = 0; 4062 u64 phys_addr; 4063 u32 ATAP = 0x0; 4064 u32 dir; 4065 struct inbound_queue_table *circularQ; 4066 u32 opc = OPC_INB_SATA_HOST_OPSTART; 4067 memset(&sata_cmd, 0, sizeof(sata_cmd)); 4068 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4069 if (task->data_dir == PCI_DMA_NONE) { 4070 ATAP = 0x04; /* no data*/ 4071 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n")); 4072 } else if (likely(!task->ata_task.device_control_reg_update)) { 4073 if (task->ata_task.dma_xfer) { 4074 ATAP = 0x06; /* DMA */ 4075 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n")); 4076 } else { 4077 ATAP = 0x05; /* PIO*/ 4078 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n")); 4079 } 4080 if (task->ata_task.use_ncq && 4081 dev->sata_dev.command_set != ATAPI_COMMAND_SET) { 4082 ATAP = 0x07; /* FPDMA */ 4083 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n")); 4084 } 4085 } 4086 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) 4087 ncg_tag = hdr_tag; 4088 dir = data_dir_flags[task->data_dir] << 8; 4089 sata_cmd.tag = cpu_to_le32(tag); 4090 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); 4091 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); 4092 sata_cmd.ncqtag_atap_dir_m = 4093 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir); 4094 sata_cmd.sata_fis = task->ata_task.fis; 4095 if (likely(!task->ata_task.device_control_reg_update)) 4096 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ 4097 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ 4098 /* fill in PRD (scatter/gather) table, if any */ 4099 if (task->num_scatter > 1) { 4100 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd); 4101 phys_addr = ccb->ccb_dma_handle + 4102 offsetof(struct pm8001_ccb_info, buf_prd[0]); 4103 sata_cmd.addr_low = lower_32_bits(phys_addr); 4104 sata_cmd.addr_high = upper_32_bits(phys_addr); 4105 sata_cmd.esgl = cpu_to_le32(1 << 31); 4106 } else if (task->num_scatter == 1) { 4107 u64 dma_addr = sg_dma_address(task->scatter); 4108 sata_cmd.addr_low = lower_32_bits(dma_addr); 4109 sata_cmd.addr_high = upper_32_bits(dma_addr); 4110 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4111 sata_cmd.esgl = 0; 4112 } else if (task->num_scatter == 0) { 4113 sata_cmd.addr_low = 0; 4114 sata_cmd.addr_high = 0; 4115 sata_cmd.len = cpu_to_le32(task->total_xfer_len); 4116 sata_cmd.esgl = 0; 4117 } 4118 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd); 4119 return ret; 4120} 4121 4122/** 4123 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND 4124 * @pm8001_ha: our hba card information. 4125 * @num: the inbound queue number 4126 * @phy_id: the phy id which we wanted to start up. 4127 */ 4128static int 4129pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) 4130{ 4131 struct phy_start_req payload; 4132 struct inbound_queue_table *circularQ; 4133 int ret; 4134 u32 tag = 0x01; 4135 u32 opcode = OPC_INB_PHYSTART; 4136 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4137 memset(&payload, 0, sizeof(payload)); 4138 payload.tag = cpu_to_le32(tag); 4139 /* 4140 ** [0:7] PHY Identifier 4141 ** [8:11] link rate 1.5G, 3G, 6G 4142 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both 4143 ** [14] 0b disable spin up hold; 1b enable spin up hold 4144 */ 4145 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | 4146 LINKMODE_AUTO | LINKRATE_15 | 4147 LINKRATE_30 | LINKRATE_60 | phy_id); 4148 payload.sas_identify.dev_type = SAS_END_DEV; 4149 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; 4150 memcpy(payload.sas_identify.sas_addr, 4151 pm8001_ha->sas_addr, SAS_ADDR_SIZE); 4152 payload.sas_identify.phy_id = phy_id; 4153 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload); 4154 return ret; 4155} 4156 4157/** 4158 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND 4159 * @pm8001_ha: our hba card information. 4160 * @num: the inbound queue number 4161 * @phy_id: the phy id which we wanted to start up. 4162 */ 4163static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, 4164 u8 phy_id) 4165{ 4166 struct phy_stop_req payload; 4167 struct inbound_queue_table *circularQ; 4168 int ret; 4169 u32 tag = 0x01; 4170 u32 opcode = OPC_INB_PHYSTOP; 4171 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4172 memset(&payload, 0, sizeof(payload)); 4173 payload.tag = cpu_to_le32(tag); 4174 payload.phy_id = cpu_to_le32(phy_id); 4175 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload); 4176 return ret; 4177} 4178 4179/** 4180 * see comments on mpi_reg_resp. 4181 */ 4182static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, 4183 struct pm8001_device *pm8001_dev, u32 flag) 4184{ 4185 struct reg_dev_req payload; 4186 u32 opc; 4187 u32 stp_sspsmp_sata = 0x4; 4188 struct inbound_queue_table *circularQ; 4189 u32 linkrate, phy_id; 4190 int rc, tag = 0xdeadbeef; 4191 struct pm8001_ccb_info *ccb; 4192 u8 retryFlag = 0x1; 4193 u16 firstBurstSize = 0; 4194 u16 ITNT = 2000; 4195 struct domain_device *dev = pm8001_dev->sas_device; 4196 struct domain_device *parent_dev = dev->parent; 4197 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4198 4199 memset(&payload, 0, sizeof(payload)); 4200 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4201 if (rc) 4202 return rc; 4203 ccb = &pm8001_ha->ccb_info[tag]; 4204 ccb->device = pm8001_dev; 4205 ccb->ccb_tag = tag; 4206 payload.tag = cpu_to_le32(tag); 4207 if (flag == 1) 4208 stp_sspsmp_sata = 0x02; /*direct attached sata */ 4209 else { 4210 if (pm8001_dev->dev_type == SATA_DEV) 4211 stp_sspsmp_sata = 0x00; /* stp*/ 4212 else if (pm8001_dev->dev_type == SAS_END_DEV || 4213 pm8001_dev->dev_type == EDGE_DEV || 4214 pm8001_dev->dev_type == FANOUT_DEV) 4215 stp_sspsmp_sata = 0x01; /*ssp or smp*/ 4216 } 4217 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 4218 phy_id = parent_dev->ex_dev.ex_phy->phy_id; 4219 else 4220 phy_id = pm8001_dev->attached_phy; 4221 opc = OPC_INB_REG_DEV; 4222 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? 4223 pm8001_dev->sas_device->linkrate : dev->port->linkrate; 4224 payload.phyid_portid = 4225 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) | 4226 ((phy_id & 0x0F) << 4)); 4227 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) | 4228 ((linkrate & 0x0F) * 0x1000000) | 4229 ((stp_sspsmp_sata & 0x03) * 0x10000000)); 4230 payload.firstburstsize_ITNexustimeout = 4231 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); 4232 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, 4233 SAS_ADDR_SIZE); 4234 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 4235 return rc; 4236} 4237 4238/** 4239 * see comments on mpi_reg_resp. 4240 */ 4241static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, 4242 u32 device_id) 4243{ 4244 struct dereg_dev_req payload; 4245 u32 opc = OPC_INB_DEREG_DEV_HANDLE; 4246 int ret; 4247 struct inbound_queue_table *circularQ; 4248 4249 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4250 memset(&payload, 0, sizeof(payload)); 4251 payload.tag = cpu_to_le32(1); 4252 payload.device_id = cpu_to_le32(device_id); 4253 PM8001_MSG_DBG(pm8001_ha, 4254 pm8001_printk("unregister device device_id = %d\n", device_id)); 4255 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 4256 return ret; 4257} 4258 4259/** 4260 * pm8001_chip_phy_ctl_req - support the local phy operation 4261 * @pm8001_ha: our hba card information. 4262 * @num: the inbound queue number 4263 * @phy_id: the phy id which we wanted to operate 4264 * @phy_op: 4265 */ 4266static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, 4267 u32 phyId, u32 phy_op) 4268{ 4269 struct local_phy_ctl_req payload; 4270 struct inbound_queue_table *circularQ; 4271 int ret; 4272 u32 opc = OPC_INB_LOCAL_PHY_CONTROL; 4273 memset(&payload, 0, sizeof(payload)); 4274 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4275 payload.tag = cpu_to_le32(1); 4276 payload.phyop_phyid = 4277 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F)); 4278 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 4279 return ret; 4280} 4281 4282static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha) 4283{ 4284 u32 value; 4285#ifdef PM8001_USE_MSIX 4286 return 1; 4287#endif 4288 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); 4289 if (value) 4290 return 1; 4291 return 0; 4292 4293} 4294 4295/** 4296 * pm8001_chip_isr - PM8001 isr handler. 4297 * @pm8001_ha: our hba card information. 4298 * @irq: irq number. 4299 * @stat: stat. 4300 */ 4301static irqreturn_t 4302pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha) 4303{ 4304 pm8001_chip_interrupt_disable(pm8001_ha); 4305 process_oq(pm8001_ha); 4306 pm8001_chip_interrupt_enable(pm8001_ha); 4307 return IRQ_HANDLED; 4308} 4309 4310static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc, 4311 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag) 4312{ 4313 struct task_abort_req task_abort; 4314 struct inbound_queue_table *circularQ; 4315 int ret; 4316 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4317 memset(&task_abort, 0, sizeof(task_abort)); 4318 if (ABORT_SINGLE == (flag & ABORT_MASK)) { 4319 task_abort.abort_all = 0; 4320 task_abort.device_id = cpu_to_le32(dev_id); 4321 task_abort.tag_to_abort = cpu_to_le32(task_tag); 4322 task_abort.tag = cpu_to_le32(cmd_tag); 4323 } else if (ABORT_ALL == (flag & ABORT_MASK)) { 4324 task_abort.abort_all = cpu_to_le32(1); 4325 task_abort.device_id = cpu_to_le32(dev_id); 4326 task_abort.tag = cpu_to_le32(cmd_tag); 4327 } 4328 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort); 4329 return ret; 4330} 4331 4332/** 4333 * pm8001_chip_abort_task - SAS abort task when error or exception happened. 4334 * @task: the task we wanted to aborted. 4335 * @flag: the abort flag. 4336 */ 4337static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, 4338 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag) 4339{ 4340 u32 opc, device_id; 4341 int rc = TMF_RESP_FUNC_FAILED; 4342 PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag" 4343 " = %x", cmd_tag, task_tag)); 4344 if (pm8001_dev->dev_type == SAS_END_DEV) 4345 opc = OPC_INB_SSP_ABORT; 4346 else if (pm8001_dev->dev_type == SATA_DEV) 4347 opc = OPC_INB_SATA_ABORT; 4348 else 4349 opc = OPC_INB_SMP_ABORT;/* SMP */ 4350 device_id = pm8001_dev->device_id; 4351 rc = send_task_abort(pm8001_ha, opc, device_id, flag, 4352 task_tag, cmd_tag); 4353 if (rc != TMF_RESP_FUNC_COMPLETE) 4354 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc)); 4355 return rc; 4356} 4357 4358/** 4359 * pm8001_chip_ssp_tm_req - built the task management command. 4360 * @pm8001_ha: our hba card information. 4361 * @ccb: the ccb information. 4362 * @tmf: task management function. 4363 */ 4364static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, 4365 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf) 4366{ 4367 struct sas_task *task = ccb->task; 4368 struct domain_device *dev = task->dev; 4369 struct pm8001_device *pm8001_dev = dev->lldd_dev; 4370 u32 opc = OPC_INB_SSPINITMSTART; 4371 struct inbound_queue_table *circularQ; 4372 struct ssp_ini_tm_start_req sspTMCmd; 4373 int ret; 4374 4375 memset(&sspTMCmd, 0, sizeof(sspTMCmd)); 4376 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id); 4377 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed); 4378 sspTMCmd.tmf = cpu_to_le32(tmf->tmf); 4379 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8); 4380 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag); 4381 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4382 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd); 4383 return ret; 4384} 4385 4386static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4387 void *payload) 4388{ 4389 u32 opc = OPC_INB_GET_NVMD_DATA; 4390 u32 nvmd_type; 4391 int rc; 4392 u32 tag; 4393 struct pm8001_ccb_info *ccb; 4394 struct inbound_queue_table *circularQ; 4395 struct get_nvm_data_req nvmd_req; 4396 struct fw_control_ex *fw_control_context; 4397 struct pm8001_ioctl_payload *ioctl_payload = payload; 4398 4399 nvmd_type = ioctl_payload->minor_function; 4400 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4401 if (!fw_control_context) 4402 return -ENOMEM; 4403 fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0]; 4404 fw_control_context->len = ioctl_payload->length; 4405 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4406 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4407 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4408 if (rc) { 4409 kfree(fw_control_context); 4410 return rc; 4411 } 4412 ccb = &pm8001_ha->ccb_info[tag]; 4413 ccb->ccb_tag = tag; 4414 ccb->fw_control_context = fw_control_context; 4415 nvmd_req.tag = cpu_to_le32(tag); 4416 4417 switch (nvmd_type) { 4418 case TWI_DEVICE: { 4419 u32 twi_addr, twi_page_size; 4420 twi_addr = 0xa8; 4421 twi_page_size = 2; 4422 4423 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4424 twi_page_size << 8 | TWI_DEVICE); 4425 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4426 nvmd_req.resp_addr_hi = 4427 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4428 nvmd_req.resp_addr_lo = 4429 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4430 break; 4431 } 4432 case C_SEEPROM: { 4433 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4434 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4435 nvmd_req.resp_addr_hi = 4436 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4437 nvmd_req.resp_addr_lo = 4438 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4439 break; 4440 } 4441 case VPD_FLASH: { 4442 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4443 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4444 nvmd_req.resp_addr_hi = 4445 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4446 nvmd_req.resp_addr_lo = 4447 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4448 break; 4449 } 4450 case EXPAN_ROM: { 4451 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4452 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4453 nvmd_req.resp_addr_hi = 4454 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4455 nvmd_req.resp_addr_lo = 4456 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4457 break; 4458 } 4459 default: 4460 break; 4461 } 4462 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req); 4463 return rc; 4464} 4465 4466static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, 4467 void *payload) 4468{ 4469 u32 opc = OPC_INB_SET_NVMD_DATA; 4470 u32 nvmd_type; 4471 int rc; 4472 u32 tag; 4473 struct pm8001_ccb_info *ccb; 4474 struct inbound_queue_table *circularQ; 4475 struct set_nvm_data_req nvmd_req; 4476 struct fw_control_ex *fw_control_context; 4477 struct pm8001_ioctl_payload *ioctl_payload = payload; 4478 4479 nvmd_type = ioctl_payload->minor_function; 4480 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4481 if (!fw_control_context) 4482 return -ENOMEM; 4483 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4484 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr, 4485 ioctl_payload->func_specific, 4486 ioctl_payload->length); 4487 memset(&nvmd_req, 0, sizeof(nvmd_req)); 4488 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4489 if (rc) { 4490 kfree(fw_control_context); 4491 return rc; 4492 } 4493 ccb = &pm8001_ha->ccb_info[tag]; 4494 ccb->fw_control_context = fw_control_context; 4495 ccb->ccb_tag = tag; 4496 nvmd_req.tag = cpu_to_le32(tag); 4497 switch (nvmd_type) { 4498 case TWI_DEVICE: { 4499 u32 twi_addr, twi_page_size; 4500 twi_addr = 0xa8; 4501 twi_page_size = 2; 4502 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4503 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 | 4504 twi_page_size << 8 | TWI_DEVICE); 4505 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4506 nvmd_req.resp_addr_hi = 4507 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4508 nvmd_req.resp_addr_lo = 4509 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4510 break; 4511 } 4512 case C_SEEPROM: 4513 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM); 4514 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4515 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4516 nvmd_req.resp_addr_hi = 4517 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4518 nvmd_req.resp_addr_lo = 4519 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4520 break; 4521 case VPD_FLASH: 4522 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH); 4523 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4524 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4525 nvmd_req.resp_addr_hi = 4526 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4527 nvmd_req.resp_addr_lo = 4528 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4529 break; 4530 case EXPAN_ROM: 4531 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM); 4532 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length); 4533 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98); 4534 nvmd_req.resp_addr_hi = 4535 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); 4536 nvmd_req.resp_addr_lo = 4537 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); 4538 break; 4539 default: 4540 break; 4541 } 4542 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req); 4543 return rc; 4544} 4545 4546/** 4547 * pm8001_chip_fw_flash_update_build - support the firmware update operation 4548 * @pm8001_ha: our hba card information. 4549 * @fw_flash_updata_info: firmware flash update param 4550 */ 4551static int 4552pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, 4553 void *fw_flash_updata_info, u32 tag) 4554{ 4555 struct fw_flash_Update_req payload; 4556 struct fw_flash_updata_info *info; 4557 struct inbound_queue_table *circularQ; 4558 int ret; 4559 u32 opc = OPC_INB_FW_FLASH_UPDATE; 4560 4561 memset(&payload, 0, sizeof(struct fw_flash_Update_req)); 4562 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4563 info = fw_flash_updata_info; 4564 payload.tag = cpu_to_le32(tag); 4565 payload.cur_image_len = cpu_to_le32(info->cur_image_len); 4566 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset); 4567 payload.total_image_len = cpu_to_le32(info->total_image_len); 4568 payload.len = info->sgl.im_len.len ; 4569 payload.sgl_addr_lo = 4570 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr))); 4571 payload.sgl_addr_hi = 4572 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr))); 4573 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 4574 return ret; 4575} 4576 4577static int 4578pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, 4579 void *payload) 4580{ 4581 struct fw_flash_updata_info flash_update_info; 4582 struct fw_control_info *fw_control; 4583 struct fw_control_ex *fw_control_context; 4584 int rc; 4585 u32 tag; 4586 struct pm8001_ccb_info *ccb; 4587 void *buffer = NULL; 4588 dma_addr_t phys_addr; 4589 u32 phys_addr_hi; 4590 u32 phys_addr_lo; 4591 struct pm8001_ioctl_payload *ioctl_payload = payload; 4592 4593 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL); 4594 if (!fw_control_context) 4595 return -ENOMEM; 4596 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0]; 4597 if (fw_control->len != 0) { 4598 if (pm8001_mem_alloc(pm8001_ha->pdev, 4599 (void **)&buffer, 4600 &phys_addr, 4601 &phys_addr_hi, 4602 &phys_addr_lo, 4603 fw_control->len, 0) != 0) { 4604 PM8001_FAIL_DBG(pm8001_ha, 4605 pm8001_printk("Mem alloc failure\n")); 4606 kfree(fw_control_context); 4607 return -ENOMEM; 4608 } 4609 } 4610 memcpy(buffer, fw_control->buffer, fw_control->len); 4611 flash_update_info.sgl.addr = cpu_to_le64(phys_addr); 4612 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len); 4613 flash_update_info.sgl.im_len.e = 0; 4614 flash_update_info.cur_image_offset = fw_control->offset; 4615 flash_update_info.cur_image_len = fw_control->len; 4616 flash_update_info.total_image_len = fw_control->size; 4617 fw_control_context->fw_control = fw_control; 4618 fw_control_context->virtAddr = buffer; 4619 fw_control_context->len = fw_control->len; 4620 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4621 if (rc) { 4622 kfree(fw_control_context); 4623 return rc; 4624 } 4625 ccb = &pm8001_ha->ccb_info[tag]; 4626 ccb->fw_control_context = fw_control_context; 4627 ccb->ccb_tag = tag; 4628 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, 4629 tag); 4630 return rc; 4631} 4632 4633static int 4634pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, 4635 struct pm8001_device *pm8001_dev, u32 state) 4636{ 4637 struct set_dev_state_req payload; 4638 struct inbound_queue_table *circularQ; 4639 struct pm8001_ccb_info *ccb; 4640 int rc; 4641 u32 tag; 4642 u32 opc = OPC_INB_SET_DEVICE_STATE; 4643 memset(&payload, 0, sizeof(payload)); 4644 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4645 if (rc) 4646 return -1; 4647 ccb = &pm8001_ha->ccb_info[tag]; 4648 ccb->ccb_tag = tag; 4649 ccb->device = pm8001_dev; 4650 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4651 payload.tag = cpu_to_le32(tag); 4652 payload.device_id = cpu_to_le32(pm8001_dev->device_id); 4653 payload.nds = cpu_to_le32(state); 4654 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 4655 return rc; 4656 4657} 4658 4659static int 4660pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha) 4661{ 4662 struct sas_re_initialization_req payload; 4663 struct inbound_queue_table *circularQ; 4664 struct pm8001_ccb_info *ccb; 4665 int rc; 4666 u32 tag; 4667 u32 opc = OPC_INB_SAS_RE_INITIALIZE; 4668 memset(&payload, 0, sizeof(payload)); 4669 rc = pm8001_tag_alloc(pm8001_ha, &tag); 4670 if (rc) 4671 return -1; 4672 ccb = &pm8001_ha->ccb_info[tag]; 4673 ccb->ccb_tag = tag; 4674 circularQ = &pm8001_ha->inbnd_q_tbl[0]; 4675 payload.tag = cpu_to_le32(tag); 4676 payload.SSAHOLT = cpu_to_le32(0xd << 25); 4677 payload.sata_hol_tmo = cpu_to_le32(80); 4678 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff); 4679 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload); 4680 return rc; 4681 4682} 4683 4684const struct pm8001_dispatch pm8001_8001_dispatch = { 4685 .name = "pmc8001", 4686 .chip_init = pm8001_chip_init, 4687 .chip_soft_rst = pm8001_chip_soft_rst, 4688 .chip_rst = pm8001_hw_chip_rst, 4689 .chip_iounmap = pm8001_chip_iounmap, 4690 .isr = pm8001_chip_isr, 4691 .is_our_interupt = pm8001_chip_is_our_interupt, 4692 .isr_process_oq = process_oq, 4693 .interrupt_enable = pm8001_chip_interrupt_enable, 4694 .interrupt_disable = pm8001_chip_interrupt_disable, 4695 .make_prd = pm8001_chip_make_sg, 4696 .smp_req = pm8001_chip_smp_req, 4697 .ssp_io_req = pm8001_chip_ssp_io_req, 4698 .sata_req = pm8001_chip_sata_req, 4699 .phy_start_req = pm8001_chip_phy_start_req, 4700 .phy_stop_req = pm8001_chip_phy_stop_req, 4701 .reg_dev_req = pm8001_chip_reg_dev_req, 4702 .dereg_dev_req = pm8001_chip_dereg_dev_req, 4703 .phy_ctl_req = pm8001_chip_phy_ctl_req, 4704 .task_abort = pm8001_chip_abort_task, 4705 .ssp_tm_req = pm8001_chip_ssp_tm_req, 4706 .get_nvmd_req = pm8001_chip_get_nvmd_req, 4707 .set_nvmd_req = pm8001_chip_set_nvmd_req, 4708 .fw_flash_update_req = pm8001_chip_fw_flash_update_req, 4709 .set_dev_state_req = pm8001_chip_set_dev_state_req, 4710 .sas_re_init_req = pm8001_chip_sas_re_initialization, 4711}; 4712 4713