1/* 2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41#include <linux/slab.h> 42#include "pm8001_sas.h" 43#include "pm8001_chips.h" 44 45static struct scsi_transport_template *pm8001_stt; 46 47static const struct pm8001_chip_info pm8001_chips[] = { 48 [chip_8001] = { 8, &pm8001_8001_dispatch,}, 49}; 50static int pm8001_id; 51 52LIST_HEAD(hba_list); 53 54struct workqueue_struct *pm8001_wq; 55 56/** 57 * The main structure which LLDD must register for scsi core. 58 */ 59static struct scsi_host_template pm8001_sht = { 60 .module = THIS_MODULE, 61 .name = DRV_NAME, 62 .queuecommand = sas_queuecommand, 63 .target_alloc = sas_target_alloc, 64 .slave_configure = sas_slave_configure, 65 .scan_finished = pm8001_scan_finished, 66 .scan_start = pm8001_scan_start, 67 .change_queue_depth = sas_change_queue_depth, 68 .change_queue_type = sas_change_queue_type, 69 .bios_param = sas_bios_param, 70 .can_queue = 1, 71 .cmd_per_lun = 1, 72 .this_id = -1, 73 .sg_tablesize = SG_ALL, 74 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 75 .use_clustering = ENABLE_CLUSTERING, 76 .eh_device_reset_handler = sas_eh_device_reset_handler, 77 .eh_bus_reset_handler = sas_eh_bus_reset_handler, 78 .target_destroy = sas_target_destroy, 79 .ioctl = sas_ioctl, 80 .shost_attrs = pm8001_host_attrs, 81}; 82 83/** 84 * Sas layer call this function to execute specific task. 85 */ 86static struct sas_domain_function_template pm8001_transport_ops = { 87 .lldd_dev_found = pm8001_dev_found, 88 .lldd_dev_gone = pm8001_dev_gone, 89 90 .lldd_execute_task = pm8001_queue_command, 91 .lldd_control_phy = pm8001_phy_control, 92 93 .lldd_abort_task = pm8001_abort_task, 94 .lldd_abort_task_set = pm8001_abort_task_set, 95 .lldd_clear_aca = pm8001_clear_aca, 96 .lldd_clear_task_set = pm8001_clear_task_set, 97 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 98 .lldd_lu_reset = pm8001_lu_reset, 99 .lldd_query_task = pm8001_query_task, 100}; 101 102/** 103 *pm8001_phy_init - initiate our adapter phys 104 *@pm8001_ha: our hba structure. 105 *@phy_id: phy id. 106 */ 107static void __devinit pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, 108 int phy_id) 109{ 110 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 111 struct asd_sas_phy *sas_phy = &phy->sas_phy; 112 phy->phy_state = 0; 113 phy->pm8001_ha = pm8001_ha; 114 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 115 sas_phy->class = SAS; 116 sas_phy->iproto = SAS_PROTOCOL_ALL; 117 sas_phy->tproto = 0; 118 sas_phy->type = PHY_TYPE_PHYSICAL; 119 sas_phy->role = PHY_ROLE_INITIATOR; 120 sas_phy->oob_mode = OOB_NOT_CONNECTED; 121 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 122 sas_phy->id = phy_id; 123 sas_phy->sas_addr = &pm8001_ha->sas_addr[0]; 124 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 125 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 126 sas_phy->lldd_phy = phy; 127} 128 129/** 130 *pm8001_free - free hba 131 *@pm8001_ha: our hba structure. 132 * 133 */ 134static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 135{ 136 int i; 137 138 if (!pm8001_ha) 139 return; 140 141 for (i = 0; i < USI_MAX_MEMCNT; i++) { 142 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 143 pci_free_consistent(pm8001_ha->pdev, 144 pm8001_ha->memoryMap.region[i].element_size, 145 pm8001_ha->memoryMap.region[i].virt_ptr, 146 pm8001_ha->memoryMap.region[i].phys_addr); 147 } 148 } 149 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 150 if (pm8001_ha->shost) 151 scsi_host_put(pm8001_ha->shost); 152 flush_workqueue(pm8001_wq); 153 kfree(pm8001_ha->tags); 154 kfree(pm8001_ha); 155} 156 157#ifdef PM8001_USE_TASKLET 158static void pm8001_tasklet(unsigned long opaque) 159{ 160 struct pm8001_hba_info *pm8001_ha; 161 pm8001_ha = (struct pm8001_hba_info *)opaque; 162 if (unlikely(!pm8001_ha)) 163 BUG_ON(1); 164 PM8001_CHIP_DISP->isr(pm8001_ha); 165} 166#endif 167 168 169 /** 170 * pm8001_interrupt - when HBA originate a interrupt,we should invoke this 171 * dispatcher to handle each case. 172 * @irq: irq number. 173 * @opaque: the passed general host adapter struct 174 */ 175static irqreturn_t pm8001_interrupt(int irq, void *opaque) 176{ 177 struct pm8001_hba_info *pm8001_ha; 178 irqreturn_t ret = IRQ_HANDLED; 179 struct sas_ha_struct *sha = opaque; 180 pm8001_ha = sha->lldd_ha; 181 if (unlikely(!pm8001_ha)) 182 return IRQ_NONE; 183 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha)) 184 return IRQ_NONE; 185#ifdef PM8001_USE_TASKLET 186 tasklet_schedule(&pm8001_ha->tasklet); 187#else 188 ret = PM8001_CHIP_DISP->isr(pm8001_ha); 189#endif 190 return ret; 191} 192 193/** 194 * pm8001_alloc - initiate our hba structure and 6 DMAs area. 195 * @pm8001_ha:our hba structure. 196 * 197 */ 198static int __devinit pm8001_alloc(struct pm8001_hba_info *pm8001_ha) 199{ 200 int i; 201 spin_lock_init(&pm8001_ha->lock); 202 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 203 pm8001_phy_init(pm8001_ha, i); 204 pm8001_ha->port[i].wide_port_phymap = 0; 205 pm8001_ha->port[i].port_attached = 0; 206 pm8001_ha->port[i].port_state = 0; 207 INIT_LIST_HEAD(&pm8001_ha->port[i].list); 208 } 209 210 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL); 211 if (!pm8001_ha->tags) 212 goto err_out; 213 /* MPI Memory region 1 for AAP Event Log for fw */ 214 pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 215 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 216 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 217 pm8001_ha->memoryMap.region[AAP1].alignment = 32; 218 219 /* MPI Memory region 2 for IOP Event Log for fw */ 220 pm8001_ha->memoryMap.region[IOP].num_elements = 1; 221 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 222 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 223 pm8001_ha->memoryMap.region[IOP].alignment = 32; 224 225 /* MPI Memory region 3 for consumer Index of inbound queues */ 226 pm8001_ha->memoryMap.region[CI].num_elements = 1; 227 pm8001_ha->memoryMap.region[CI].element_size = 4; 228 pm8001_ha->memoryMap.region[CI].total_len = 4; 229 pm8001_ha->memoryMap.region[CI].alignment = 4; 230 231 /* MPI Memory region 4 for producer Index of outbound queues */ 232 pm8001_ha->memoryMap.region[PI].num_elements = 1; 233 pm8001_ha->memoryMap.region[PI].element_size = 4; 234 pm8001_ha->memoryMap.region[PI].total_len = 4; 235 pm8001_ha->memoryMap.region[PI].alignment = 4; 236 237 /* MPI Memory region 5 inbound queues */ 238 pm8001_ha->memoryMap.region[IB].num_elements = 256; 239 pm8001_ha->memoryMap.region[IB].element_size = 64; 240 pm8001_ha->memoryMap.region[IB].total_len = 256 * 64; 241 pm8001_ha->memoryMap.region[IB].alignment = 64; 242 243 /* MPI Memory region 6 inbound queues */ 244 pm8001_ha->memoryMap.region[OB].num_elements = 256; 245 pm8001_ha->memoryMap.region[OB].element_size = 64; 246 pm8001_ha->memoryMap.region[OB].total_len = 256 * 64; 247 pm8001_ha->memoryMap.region[OB].alignment = 64; 248 249 /* Memory region write DMA*/ 250 pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 251 pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 252 pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 253 /* Memory region for devices*/ 254 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1; 255 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES * 256 sizeof(struct pm8001_device); 257 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES * 258 sizeof(struct pm8001_device); 259 260 /* Memory region for ccb_info*/ 261 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1; 262 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB * 263 sizeof(struct pm8001_ccb_info); 264 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB * 265 sizeof(struct pm8001_ccb_info); 266 267 for (i = 0; i < USI_MAX_MEMCNT; i++) { 268 if (pm8001_mem_alloc(pm8001_ha->pdev, 269 &pm8001_ha->memoryMap.region[i].virt_ptr, 270 &pm8001_ha->memoryMap.region[i].phys_addr, 271 &pm8001_ha->memoryMap.region[i].phys_addr_hi, 272 &pm8001_ha->memoryMap.region[i].phys_addr_lo, 273 pm8001_ha->memoryMap.region[i].total_len, 274 pm8001_ha->memoryMap.region[i].alignment) != 0) { 275 PM8001_FAIL_DBG(pm8001_ha, 276 pm8001_printk("Mem%d alloc failed\n", 277 i)); 278 goto err_out; 279 } 280 } 281 282 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr; 283 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 284 pm8001_ha->devices[i].dev_type = NO_DEVICE; 285 pm8001_ha->devices[i].id = i; 286 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 287 pm8001_ha->devices[i].running_req = 0; 288 } 289 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr; 290 for (i = 0; i < PM8001_MAX_CCB; i++) { 291 pm8001_ha->ccb_info[i].ccb_dma_handle = 292 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr + 293 i * sizeof(struct pm8001_ccb_info); 294 pm8001_ha->ccb_info[i].task = NULL; 295 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff; 296 pm8001_ha->ccb_info[i].device = NULL; 297 ++pm8001_ha->tags_num; 298 } 299 pm8001_ha->flags = PM8001F_INIT_TIME; 300 /* Initialize tags */ 301 pm8001_tag_init(pm8001_ha); 302 return 0; 303err_out: 304 return 1; 305} 306 307/** 308 * pm8001_ioremap - remap the pci high physical address to kernal virtual 309 * address so that we can access them. 310 * @pm8001_ha:our hba structure. 311 */ 312static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 313{ 314 u32 bar; 315 u32 logicalBar = 0; 316 struct pci_dev *pdev; 317 318 pdev = pm8001_ha->pdev; 319 /* map pci mem (PMC pci base 0-3)*/ 320 for (bar = 0; bar < 6; bar++) { 321 /* 322 ** logical BARs for SPC: 323 ** bar 0 and 1 - logical BAR0 324 ** bar 2 and 3 - logical BAR1 325 ** bar4 - logical BAR2 326 ** bar5 - logical BAR3 327 ** Skip the appropriate assignments: 328 */ 329 if ((bar == 1) || (bar == 3)) 330 continue; 331 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 332 pm8001_ha->io_mem[logicalBar].membase = 333 pci_resource_start(pdev, bar); 334 pm8001_ha->io_mem[logicalBar].membase &= 335 (u32)PCI_BASE_ADDRESS_MEM_MASK; 336 pm8001_ha->io_mem[logicalBar].memsize = 337 pci_resource_len(pdev, bar); 338 pm8001_ha->io_mem[logicalBar].memvirtaddr = 339 ioremap(pm8001_ha->io_mem[logicalBar].membase, 340 pm8001_ha->io_mem[logicalBar].memsize); 341 PM8001_INIT_DBG(pm8001_ha, 342 pm8001_printk("PCI: bar %d, logicalBar %d " 343 "virt_addr=%lx,len=%d\n", bar, logicalBar, 344 (unsigned long) 345 pm8001_ha->io_mem[logicalBar].memvirtaddr, 346 pm8001_ha->io_mem[logicalBar].memsize)); 347 } else { 348 pm8001_ha->io_mem[logicalBar].membase = 0; 349 pm8001_ha->io_mem[logicalBar].memsize = 0; 350 pm8001_ha->io_mem[logicalBar].memvirtaddr = 0; 351 } 352 logicalBar++; 353 } 354 return 0; 355} 356 357/** 358 * pm8001_pci_alloc - initialize our ha card structure 359 * @pdev: pci device. 360 * @ent: ent 361 * @shost: scsi host struct which has been initialized before. 362 */ 363static struct pm8001_hba_info *__devinit 364pm8001_pci_alloc(struct pci_dev *pdev, u32 chip_id, struct Scsi_Host *shost) 365{ 366 struct pm8001_hba_info *pm8001_ha; 367 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 368 369 370 pm8001_ha = sha->lldd_ha; 371 if (!pm8001_ha) 372 return NULL; 373 374 pm8001_ha->pdev = pdev; 375 pm8001_ha->dev = &pdev->dev; 376 pm8001_ha->chip_id = chip_id; 377 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 378 pm8001_ha->irq = pdev->irq; 379 pm8001_ha->sas = sha; 380 pm8001_ha->shost = shost; 381 pm8001_ha->id = pm8001_id++; 382 pm8001_ha->logging_level = 0x01; 383 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 384#ifdef PM8001_USE_TASKLET 385 tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet, 386 (unsigned long)pm8001_ha); 387#endif 388 pm8001_ioremap(pm8001_ha); 389 if (!pm8001_alloc(pm8001_ha)) 390 return pm8001_ha; 391 pm8001_free(pm8001_ha); 392 return NULL; 393} 394 395/** 396 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 397 * @pdev: pci device. 398 */ 399static int pci_go_44(struct pci_dev *pdev) 400{ 401 int rc; 402 403 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) { 404 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44)); 405 if (rc) { 406 rc = pci_set_consistent_dma_mask(pdev, 407 DMA_BIT_MASK(32)); 408 if (rc) { 409 dev_printk(KERN_ERR, &pdev->dev, 410 "44-bit DMA enable failed\n"); 411 return rc; 412 } 413 } 414 } else { 415 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 416 if (rc) { 417 dev_printk(KERN_ERR, &pdev->dev, 418 "32-bit DMA enable failed\n"); 419 return rc; 420 } 421 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 422 if (rc) { 423 dev_printk(KERN_ERR, &pdev->dev, 424 "32-bit consistent DMA enable failed\n"); 425 return rc; 426 } 427 } 428 return rc; 429} 430 431/** 432 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 433 * @shost: scsi host which has been allocated outside. 434 * @chip_info: our ha struct. 435 */ 436static int __devinit pm8001_prep_sas_ha_init(struct Scsi_Host * shost, 437 const struct pm8001_chip_info *chip_info) 438{ 439 int phy_nr, port_nr; 440 struct asd_sas_phy **arr_phy; 441 struct asd_sas_port **arr_port; 442 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 443 444 phy_nr = chip_info->n_phy; 445 port_nr = phy_nr; 446 memset(sha, 0x00, sizeof(*sha)); 447 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 448 if (!arr_phy) 449 goto exit; 450 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 451 if (!arr_port) 452 goto exit_free2; 453 454 sha->sas_phy = arr_phy; 455 sha->sas_port = arr_port; 456 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 457 if (!sha->lldd_ha) 458 goto exit_free1; 459 460 shost->transportt = pm8001_stt; 461 shost->max_id = PM8001_MAX_DEVICES; 462 shost->max_lun = 8; 463 shost->max_channel = 0; 464 shost->unique_id = pm8001_id; 465 shost->max_cmd_len = 16; 466 shost->can_queue = PM8001_CAN_QUEUE; 467 shost->cmd_per_lun = 32; 468 return 0; 469exit_free1: 470 kfree(arr_port); 471exit_free2: 472 kfree(arr_phy); 473exit: 474 return -1; 475} 476 477/** 478 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 479 * @shost: scsi host which has been allocated outside 480 * @chip_info: our ha struct. 481 */ 482static void __devinit pm8001_post_sas_ha_init(struct Scsi_Host *shost, 483 const struct pm8001_chip_info *chip_info) 484{ 485 int i = 0; 486 struct pm8001_hba_info *pm8001_ha; 487 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 488 489 pm8001_ha = sha->lldd_ha; 490 for (i = 0; i < chip_info->n_phy; i++) { 491 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 492 sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 493 } 494 sha->sas_ha_name = DRV_NAME; 495 sha->dev = pm8001_ha->dev; 496 497 sha->lldd_module = THIS_MODULE; 498 sha->sas_addr = &pm8001_ha->sas_addr[0]; 499 sha->num_phys = chip_info->n_phy; 500 sha->lldd_max_execute_num = 1; 501 sha->lldd_queue_size = PM8001_CAN_QUEUE; 502 sha->core.shost = shost; 503} 504 505/** 506 * pm8001_init_sas_add - initialize sas address 507 * @chip_info: our ha struct. 508 * 509 * Currently we just set the fixed SAS address to our HBA,for manufacture, 510 * it should read from the EEPROM 511 */ 512static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 513{ 514 u8 i; 515#ifdef PM8001_READ_VPD 516 DECLARE_COMPLETION_ONSTACK(completion); 517 struct pm8001_ioctl_payload payload; 518 pm8001_ha->nvmd_completion = &completion; 519 payload.minor_function = 0; 520 payload.length = 128; 521 payload.func_specific = kzalloc(128, GFP_KERNEL); 522 PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 523 wait_for_completion(&completion); 524 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 525 memcpy(&pm8001_ha->phy[i].dev_sas_addr, pm8001_ha->sas_addr, 526 SAS_ADDR_SIZE); 527 PM8001_INIT_DBG(pm8001_ha, 528 pm8001_printk("phy %d sas_addr = %016llx \n", i, 529 pm8001_ha->phy[i].dev_sas_addr)); 530 } 531#else 532 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 533 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 534 pm8001_ha->phy[i].dev_sas_addr = 535 cpu_to_be64((u64) 536 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 537 } 538 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 539 SAS_ADDR_SIZE); 540#endif 541} 542 543#ifdef PM8001_USE_MSIX 544/** 545 * pm8001_setup_msix - enable MSI-X interrupt 546 * @chip_info: our ha struct. 547 * @irq_handler: irq_handler 548 */ 549static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha, 550 irq_handler_t irq_handler) 551{ 552 u32 i = 0, j = 0; 553 u32 number_of_intr = 1; 554 int flag = 0; 555 u32 max_entry; 556 int rc; 557 max_entry = sizeof(pm8001_ha->msix_entries) / 558 sizeof(pm8001_ha->msix_entries[0]); 559 flag |= IRQF_DISABLED; 560 for (i = 0; i < max_entry ; i++) 561 pm8001_ha->msix_entries[i].entry = i; 562 rc = pci_enable_msix(pm8001_ha->pdev, pm8001_ha->msix_entries, 563 number_of_intr); 564 pm8001_ha->number_of_intr = number_of_intr; 565 if (!rc) { 566 for (i = 0; i < number_of_intr; i++) { 567 if (request_irq(pm8001_ha->msix_entries[i].vector, 568 irq_handler, flag, DRV_NAME, 569 SHOST_TO_SAS_HA(pm8001_ha->shost))) { 570 for (j = 0; j < i; j++) 571 free_irq( 572 pm8001_ha->msix_entries[j].vector, 573 SHOST_TO_SAS_HA(pm8001_ha->shost)); 574 pci_disable_msix(pm8001_ha->pdev); 575 break; 576 } 577 } 578 } 579 return rc; 580} 581#endif 582 583/** 584 * pm8001_request_irq - register interrupt 585 * @chip_info: our ha struct. 586 */ 587static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 588{ 589 struct pci_dev *pdev; 590 irq_handler_t irq_handler = pm8001_interrupt; 591 int rc; 592 593 pdev = pm8001_ha->pdev; 594 595#ifdef PM8001_USE_MSIX 596 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) 597 return pm8001_setup_msix(pm8001_ha, irq_handler); 598 else 599 goto intx; 600#endif 601 602intx: 603 /* initialize the INT-X interrupt */ 604 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, DRV_NAME, 605 SHOST_TO_SAS_HA(pm8001_ha->shost)); 606 return rc; 607} 608 609/** 610 * pm8001_pci_probe - probe supported device 611 * @pdev: pci device which kernel has been prepared for. 612 * @ent: pci device id 613 * 614 * This function is the main initialization function, when register a new 615 * pci driver it is invoked, all struct an hardware initilization should be done 616 * here, also, register interrupt 617 */ 618static int __devinit pm8001_pci_probe(struct pci_dev *pdev, 619 const struct pci_device_id *ent) 620{ 621 unsigned int rc; 622 u32 pci_reg; 623 struct pm8001_hba_info *pm8001_ha; 624 struct Scsi_Host *shost = NULL; 625 const struct pm8001_chip_info *chip; 626 627 dev_printk(KERN_INFO, &pdev->dev, 628 "pm8001: driver version %s\n", DRV_VERSION); 629 rc = pci_enable_device(pdev); 630 if (rc) 631 goto err_out_enable; 632 pci_set_master(pdev); 633 /* 634 * Enable pci slot busmaster by setting pci command register. 635 * This is required by FW for Cyclone card. 636 */ 637 638 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 639 pci_reg |= 0x157; 640 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 641 rc = pci_request_regions(pdev, DRV_NAME); 642 if (rc) 643 goto err_out_disable; 644 rc = pci_go_44(pdev); 645 if (rc) 646 goto err_out_regions; 647 648 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 649 if (!shost) { 650 rc = -ENOMEM; 651 goto err_out_regions; 652 } 653 chip = &pm8001_chips[ent->driver_data]; 654 SHOST_TO_SAS_HA(shost) = 655 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 656 if (!SHOST_TO_SAS_HA(shost)) { 657 rc = -ENOMEM; 658 goto err_out_free_host; 659 } 660 661 rc = pm8001_prep_sas_ha_init(shost, chip); 662 if (rc) { 663 rc = -ENOMEM; 664 goto err_out_free; 665 } 666 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 667 pm8001_ha = pm8001_pci_alloc(pdev, chip_8001, shost); 668 if (!pm8001_ha) { 669 rc = -ENOMEM; 670 goto err_out_free; 671 } 672 list_add_tail(&pm8001_ha->list, &hba_list); 673 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd); 674 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 675 if (rc) 676 goto err_out_ha_free; 677 678 rc = scsi_add_host(shost, &pdev->dev); 679 if (rc) 680 goto err_out_ha_free; 681 rc = pm8001_request_irq(pm8001_ha); 682 if (rc) 683 goto err_out_shost; 684 685 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha); 686 pm8001_init_sas_add(pm8001_ha); 687 pm8001_post_sas_ha_init(shost, chip); 688 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 689 if (rc) 690 goto err_out_shost; 691 scsi_scan_host(pm8001_ha->shost); 692 return 0; 693 694err_out_shost: 695 scsi_remove_host(pm8001_ha->shost); 696err_out_ha_free: 697 pm8001_free(pm8001_ha); 698err_out_free: 699 kfree(SHOST_TO_SAS_HA(shost)); 700err_out_free_host: 701 kfree(shost); 702err_out_regions: 703 pci_release_regions(pdev); 704err_out_disable: 705 pci_disable_device(pdev); 706err_out_enable: 707 return rc; 708} 709 710static void __devexit pm8001_pci_remove(struct pci_dev *pdev) 711{ 712 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 713 struct pm8001_hba_info *pm8001_ha; 714 int i; 715 pm8001_ha = sha->lldd_ha; 716 pci_set_drvdata(pdev, NULL); 717 sas_unregister_ha(sha); 718 sas_remove_host(pm8001_ha->shost); 719 list_del(&pm8001_ha->list); 720 scsi_remove_host(pm8001_ha->shost); 721 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha); 722 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd); 723 724#ifdef PM8001_USE_MSIX 725 for (i = 0; i < pm8001_ha->number_of_intr; i++) 726 synchronize_irq(pm8001_ha->msix_entries[i].vector); 727 for (i = 0; i < pm8001_ha->number_of_intr; i++) 728 free_irq(pm8001_ha->msix_entries[i].vector, sha); 729 pci_disable_msix(pdev); 730#else 731 free_irq(pm8001_ha->irq, sha); 732#endif 733#ifdef PM8001_USE_TASKLET 734 tasklet_kill(&pm8001_ha->tasklet); 735#endif 736 pm8001_free(pm8001_ha); 737 kfree(sha->sas_phy); 738 kfree(sha->sas_port); 739 kfree(sha); 740 pci_release_regions(pdev); 741 pci_disable_device(pdev); 742} 743 744/** 745 * pm8001_pci_suspend - power management suspend main entry point 746 * @pdev: PCI device struct 747 * @state: PM state change to (usually PCI_D3) 748 * 749 * Returns 0 success, anything else error. 750 */ 751static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state) 752{ 753 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 754 struct pm8001_hba_info *pm8001_ha; 755 int i , pos; 756 u32 device_state; 757 pm8001_ha = sha->lldd_ha; 758 flush_workqueue(pm8001_wq); 759 scsi_block_requests(pm8001_ha->shost); 760 pos = pci_find_capability(pdev, PCI_CAP_ID_PM); 761 if (pos == 0) { 762 printk(KERN_ERR " PCI PM not supported\n"); 763 return -ENODEV; 764 } 765 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha); 766 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd); 767#ifdef PM8001_USE_MSIX 768 for (i = 0; i < pm8001_ha->number_of_intr; i++) 769 synchronize_irq(pm8001_ha->msix_entries[i].vector); 770 for (i = 0; i < pm8001_ha->number_of_intr; i++) 771 free_irq(pm8001_ha->msix_entries[i].vector, sha); 772 pci_disable_msix(pdev); 773#else 774 free_irq(pm8001_ha->irq, sha); 775#endif 776#ifdef PM8001_USE_TASKLET 777 tasklet_kill(&pm8001_ha->tasklet); 778#endif 779 device_state = pci_choose_state(pdev, state); 780 pm8001_printk("pdev=0x%p, slot=%s, entering " 781 "operating state [D%d]\n", pdev, 782 pm8001_ha->name, device_state); 783 pci_save_state(pdev); 784 pci_disable_device(pdev); 785 pci_set_power_state(pdev, device_state); 786 return 0; 787} 788 789/** 790 * pm8001_pci_resume - power management resume main entry point 791 * @pdev: PCI device struct 792 * 793 * Returns 0 success, anything else error. 794 */ 795static int pm8001_pci_resume(struct pci_dev *pdev) 796{ 797 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 798 struct pm8001_hba_info *pm8001_ha; 799 int rc; 800 u32 device_state; 801 pm8001_ha = sha->lldd_ha; 802 device_state = pdev->current_state; 803 804 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous " 805 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state); 806 807 pci_set_power_state(pdev, PCI_D0); 808 pci_enable_wake(pdev, PCI_D0, 0); 809 pci_restore_state(pdev); 810 rc = pci_enable_device(pdev); 811 if (rc) { 812 pm8001_printk("slot=%s Enable device failed during resume\n", 813 pm8001_ha->name); 814 goto err_out_enable; 815 } 816 817 pci_set_master(pdev); 818 rc = pci_go_44(pdev); 819 if (rc) 820 goto err_out_disable; 821 822 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd); 823 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 824 if (rc) 825 goto err_out_disable; 826 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha); 827 rc = pm8001_request_irq(pm8001_ha); 828 if (rc) 829 goto err_out_disable; 830 #ifdef PM8001_USE_TASKLET 831 tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet, 832 (unsigned long)pm8001_ha); 833 #endif 834 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha); 835 scsi_unblock_requests(pm8001_ha->shost); 836 return 0; 837 838err_out_disable: 839 scsi_remove_host(pm8001_ha->shost); 840 pci_disable_device(pdev); 841err_out_enable: 842 return rc; 843} 844 845static struct pci_device_id __devinitdata pm8001_pci_table[] = { 846 { 847 PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 848 }, 849 { 850 PCI_DEVICE(0x117c, 0x0042), 851 .driver_data = chip_8001 852 }, 853 {} /* terminate list */ 854}; 855 856static struct pci_driver pm8001_pci_driver = { 857 .name = DRV_NAME, 858 .id_table = pm8001_pci_table, 859 .probe = pm8001_pci_probe, 860 .remove = __devexit_p(pm8001_pci_remove), 861 .suspend = pm8001_pci_suspend, 862 .resume = pm8001_pci_resume, 863}; 864 865/** 866 * pm8001_init - initialize scsi transport template 867 */ 868static int __init pm8001_init(void) 869{ 870 int rc = -ENOMEM; 871 872 pm8001_wq = alloc_workqueue("pm8001", 0, 0); 873 if (!pm8001_wq) 874 goto err; 875 876 pm8001_id = 0; 877 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 878 if (!pm8001_stt) 879 goto err_wq; 880 rc = pci_register_driver(&pm8001_pci_driver); 881 if (rc) 882 goto err_tp; 883 return 0; 884 885err_tp: 886 sas_release_transport(pm8001_stt); 887err_wq: 888 destroy_workqueue(pm8001_wq); 889err: 890 return rc; 891} 892 893static void __exit pm8001_exit(void) 894{ 895 pci_unregister_driver(&pm8001_pci_driver); 896 sas_release_transport(pm8001_stt); 897 destroy_workqueue(pm8001_wq); 898} 899 900module_init(pm8001_init); 901module_exit(pm8001_exit); 902 903MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 904MODULE_DESCRIPTION("PMC-Sierra PM8001 SAS/SATA controller driver"); 905MODULE_VERSION(DRV_VERSION); 906MODULE_LICENSE("GPL"); 907MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 908 909