1/* 2 * comedi/drivers/adv_pci_dio.c 3 * 4 * Author: Michal Dobes <dobes@tesnet.cz> 5 * 6 * Hardware driver for Advantech PCI DIO cards. 7*/ 8/* 9Driver: adv_pci_dio 10Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U, 11 PCI-1736UP, PCI-1739U, PCI-1750, PCI-1751, PCI-1752, 12 PCI-1753/E, PCI-1754, PCI-1756, PCI-1760, PCI-1762 13Author: Michal Dobes <dobes@tesnet.cz> 14Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733, 15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750, 16 PCI-1751, PCI-1752, PCI-1753, 17 PCI-1753+PCI-1753E, PCI-1754, PCI-1756, 18 PCI-1760, PCI-1762 19Status: untested 20Updated: Mon, 09 Jan 2012 12:40:46 +0000 21 22This driver supports now only insn interface for DI/DO/DIO. 23 24Configuration options: 25 [0] - PCI bus of device (optional) 26 [1] - PCI slot of device (optional) 27 If bus/slot is not specified, the first available PCI 28 device will be used. 29 30*/ 31 32#include "../comedidev.h" 33 34#include <linux/delay.h> 35 36#include "comedi_pci.h" 37#include "8255.h" 38#include "8253.h" 39 40#undef PCI_DIO_EXTDEBUG /* if defined, enable extensive debug logging */ 41 42#undef DPRINTK 43#ifdef PCI_DIO_EXTDEBUG 44#define DPRINTK(fmt, args...) printk(fmt, ## args) 45#else 46#define DPRINTK(fmt, args...) 47#endif 48 49#define PCI_VENDOR_ID_ADVANTECH 0x13fe 50 51/* hardware types of the cards */ 52enum hw_cards_id { 53 TYPE_PCI1730, TYPE_PCI1733, TYPE_PCI1734, TYPE_PCI1735, TYPE_PCI1736, 54 TYPE_PCI1739, 55 TYPE_PCI1750, 56 TYPE_PCI1751, 57 TYPE_PCI1752, 58 TYPE_PCI1753, TYPE_PCI1753E, 59 TYPE_PCI1754, TYPE_PCI1756, 60 TYPE_PCI1760, 61 TYPE_PCI1762 62}; 63 64/* which I/O instructions to use */ 65enum hw_io_access { 66 IO_8b, IO_16b 67}; 68 69#define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */ 70#define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */ 71#define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per 72 * card */ 73#define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per 74 * card */ 75 /* (could be more than one 8254 per 76 * subdevice) */ 77 78#define SIZE_8254 4 /* 8254 IO space length */ 79#define SIZE_8255 4 /* 8255 IO space length */ 80 81#define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */ 82 83/* Register offset definitions */ 84/* Advantech PCI-1730/3/4 */ 85#define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */ 86#define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */ 87#define PCI1730_DI 2 /* R: Digital input 0-15 */ 88#define PCI1730_DO 2 /* W: Digital output 0-15 */ 89#define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */ 90#define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */ 91#define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for 92 * interrupts */ 93#define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */ 94#define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */ 95#define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */ 96 97/* Advantech PCI-1735U */ 98#define PCI1735_DI 0 /* R: Digital input 0-31 */ 99#define PCI1735_DO 0 /* W: Digital output 0-31 */ 100#define PCI1735_C8254 4 /* R/W: 8254 counter */ 101#define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */ 102 103/* Advantech PCI-1736UP */ 104#define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */ 105#define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */ 106#define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */ 107#define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for 108 * interrupts */ 109#define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */ 110#define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */ 111#define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */ 112 113/* Advantech PCI-1739U */ 114#define PCI1739_DIO 0 /* R/W: begin of 8255 registers block */ 115#define PCI1739_ICR 32 /* W: Interrupt control register */ 116#define PCI1739_ISR 32 /* R: Interrupt status register */ 117#define PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */ 118 119/* Advantech PCI-1750 */ 120#define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */ 121#define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */ 122#define PCI1750_ICR 32 /* W: Interrupt control register */ 123#define PCI1750_ISR 32 /* R: Interrupt status register */ 124 125/* Advantech PCI-1751/3/3E */ 126#define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */ 127#define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */ 128#define PCI1751_ICR 32 /* W: Interrupt control register */ 129#define PCI1751_ISR 32 /* R: Interrupt status register */ 130#define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */ 131#define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */ 132#define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */ 133#define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */ 134#define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */ 135#define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */ 136#define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */ 137#define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */ 138#define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */ 139#define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */ 140 141/* Advantech PCI-1752/4/6 */ 142#define PCI1752_IDO 0 /* R/W: Digital output 0-31 */ 143#define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */ 144#define PCI1754_IDI 0 /* R: Digital input 0-31 */ 145#define PCI1754_IDI2 4 /* R: Digital input 32-64 */ 146#define PCI1756_IDI 0 /* R: Digital input 0-31 */ 147#define PCI1756_IDO 4 /* R/W: Digital output 0-31 */ 148#define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */ 149#define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */ 150#define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */ 151#define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */ 152#define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */ 153#define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */ 154 155/* Advantech PCI-1762 registers */ 156#define PCI1762_RO 0 /* R/W: Relays status/output */ 157#define PCI1762_IDI 2 /* R: Isolated input status */ 158#define PCI1762_BOARDID 4 /* R: Board I/D switch */ 159#define PCI1762_ICR 6 /* W: Interrupt control register */ 160#define PCI1762_ISR 6 /* R: Interrupt status register */ 161 162/* Advantech PCI-1760 registers */ 163#define OMB0 0x0c /* W: Mailbox outgoing registers */ 164#define OMB1 0x0d 165#define OMB2 0x0e 166#define OMB3 0x0f 167#define IMB0 0x1c /* R: Mailbox incoming registers */ 168#define IMB1 0x1d 169#define IMB2 0x1e 170#define IMB3 0x1f 171#define INTCSR0 0x38 /* R/W: Interrupt control registers */ 172#define INTCSR1 0x39 173#define INTCSR2 0x3a 174#define INTCSR3 0x3b 175 176/* PCI-1760 mailbox commands */ 177#define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual 178 * DI status in IMB3 */ 179#define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */ 180#define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */ 181#define CMD_ReadCurrentStatus 0x07 /* Read the current status of the 182 * register in OMB0, result in IMB0 */ 183#define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in 184 * IMB1.IMB0 */ 185#define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in 186 * IMB1.IMB0 */ 187#define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in 188 * OMB0 */ 189#define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on 190 * bits in OMB0 */ 191#define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on 192 * bits in OMB0 */ 193#define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in 194 * OMB0 */ 195#define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in 196 * OMB0 to its reset values */ 197#define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow 198 * interrupts based on bits in OMB0 */ 199#define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value 200 * interrupts based on bits in OMB0 */ 201#define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0 202 * - rising, =1 - falling) */ 203#define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current 204 * value */ 205#define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value 206 * 256*OMB1+OMB0 */ 207#define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value 208 * 256*OMB1+OMB0 */ 209#define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value 210 * 256*OMB1+OMB0 */ 211#define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value 212 * 256*OMB1+OMB0 */ 213#define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value 214 * 256*OMB1+OMB0 */ 215#define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value 216 * 256*OMB1+OMB0 */ 217#define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value 218 * 256*OMB1+OMB0 */ 219#define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value 220 * 256*OMB1+OMB0 */ 221#define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value 222 * 256*OMB1+OMB0 */ 223#define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value 224 * 256*OMB1+OMB0 */ 225#define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value 226 * 256*OMB1+OMB0 */ 227#define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value 228 * 256*OMB1+OMB0 */ 229#define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value 230 * 256*OMB1+OMB0 */ 231#define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value 232 * 256*OMB1+OMB0 */ 233#define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value 234 * 256*OMB1+OMB0 */ 235#define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value 236 * 256*OMB1+OMB0 */ 237 238#define OMBCMD_RETRY 0x03 /* 3 times try request before error */ 239 240static int pci_dio_attach(struct comedi_device *dev, 241 struct comedi_devconfig *it); 242static int pci_dio_detach(struct comedi_device *dev); 243 244struct diosubd_data { 245 int chans; /* num of chans */ 246 int addr; /* PCI address ofset */ 247 int regs; /* number of registers to read or 8255 248 subdevices or 8254 chips */ 249 unsigned int specflags; /* addon subdevice flags */ 250}; 251 252struct dio_boardtype { 253 const char *name; /* board name */ 254 int vendor_id; /* vendor/device PCI ID */ 255 int device_id; 256 int main_pci_region; /* main I/O PCI region */ 257 enum hw_cards_id cardtype; 258 struct diosubd_data sdi[MAX_DI_SUBDEVS]; /* DI chans */ 259 struct diosubd_data sdo[MAX_DO_SUBDEVS]; /* DO chans */ 260 struct diosubd_data sdio[MAX_DIO_SUBDEVG]; /* DIO 8255 chans */ 261 struct diosubd_data boardid; /* card supports board ID switch */ 262 struct diosubd_data s8254[MAX_8254_SUBDEVS]; /* 8254 subdevices */ 263 enum hw_io_access io_access; 264}; 265 266static DEFINE_PCI_DEVICE_TABLE(pci_dio_pci_table) = { 267 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1730) }, 268 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1733) }, 269 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1734) }, 270 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1735) }, 271 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1736) }, 272 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1739) }, 273 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1750) }, 274 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1751) }, 275 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1752) }, 276 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1753) }, 277 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1754) }, 278 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1756) }, 279 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1760) }, 280 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1762) }, 281 { 0 } 282}; 283 284MODULE_DEVICE_TABLE(pci, pci_dio_pci_table); 285 286static const struct dio_boardtype boardtypes[] = { 287 {"pci1730", PCI_VENDOR_ID_ADVANTECH, 0x1730, PCIDIO_MAINREG, 288 TYPE_PCI1730, 289 { {16, PCI1730_DI, 2, 0}, {16, PCI1730_IDI, 2, 0} }, 290 { {16, PCI1730_DO, 2, 0}, {16, PCI1730_IDO, 2, 0} }, 291 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 292 {4, PCI173x_BOARDID, 1, SDF_INTERNAL}, 293 { {0, 0, 0, 0} }, 294 IO_8b}, 295 {"pci1733", PCI_VENDOR_ID_ADVANTECH, 0x1733, PCIDIO_MAINREG, 296 TYPE_PCI1733, 297 { {0, 0, 0, 0}, {32, PCI1733_IDI, 4, 0} }, 298 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 299 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 300 {4, PCI173x_BOARDID, 1, SDF_INTERNAL}, 301 { {0, 0, 0, 0} }, 302 IO_8b}, 303 {"pci1734", PCI_VENDOR_ID_ADVANTECH, 0x1734, PCIDIO_MAINREG, 304 TYPE_PCI1734, 305 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 306 { {0, 0, 0, 0}, {32, PCI1734_IDO, 4, 0} }, 307 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 308 {4, PCI173x_BOARDID, 1, SDF_INTERNAL}, 309 { {0, 0, 0, 0} }, 310 IO_8b}, 311 {"pci1735", PCI_VENDOR_ID_ADVANTECH, 0x1735, PCIDIO_MAINREG, 312 TYPE_PCI1735, 313 { {32, PCI1735_DI, 4, 0}, {0, 0, 0, 0} }, 314 { {32, PCI1735_DO, 4, 0}, {0, 0, 0, 0} }, 315 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 316 { 4, PCI1735_BOARDID, 1, SDF_INTERNAL}, 317 { {3, PCI1735_C8254, 1, 0} }, 318 IO_8b}, 319 {"pci1736", PCI_VENDOR_ID_ADVANTECH, 0x1736, PCI1736_MAINREG, 320 TYPE_PCI1736, 321 { {0, 0, 0, 0}, {16, PCI1736_IDI, 2, 0} }, 322 { {0, 0, 0, 0}, {16, PCI1736_IDO, 2, 0} }, 323 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 324 {4, PCI1736_BOARDID, 1, SDF_INTERNAL}, 325 { {0, 0, 0, 0} }, 326 IO_8b}, 327 {"pci1739", PCI_VENDOR_ID_ADVANTECH, 0x1739, PCIDIO_MAINREG, 328 TYPE_PCI1739, 329 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 330 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 331 { {48, PCI1739_DIO, 2, 0}, {0, 0, 0, 0} }, 332 {0, 0, 0, 0}, 333 { {0, 0, 0, 0} }, 334 IO_8b}, 335 {"pci1750", PCI_VENDOR_ID_ADVANTECH, 0x1750, PCIDIO_MAINREG, 336 TYPE_PCI1750, 337 { {0, 0, 0, 0}, {16, PCI1750_IDI, 2, 0} }, 338 { {0, 0, 0, 0}, {16, PCI1750_IDO, 2, 0} }, 339 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 340 {0, 0, 0, 0}, 341 { {0, 0, 0, 0} }, 342 IO_8b}, 343 {"pci1751", PCI_VENDOR_ID_ADVANTECH, 0x1751, PCIDIO_MAINREG, 344 TYPE_PCI1751, 345 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 346 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 347 { {48, PCI1751_DIO, 2, 0}, {0, 0, 0, 0} }, 348 {0, 0, 0, 0}, 349 { {3, PCI1751_CNT, 1, 0} }, 350 IO_8b}, 351 {"pci1752", PCI_VENDOR_ID_ADVANTECH, 0x1752, PCIDIO_MAINREG, 352 TYPE_PCI1752, 353 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 354 { {32, PCI1752_IDO, 2, 0}, {32, PCI1752_IDO2, 2, 0} }, 355 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 356 {4, PCI175x_BOARDID, 1, SDF_INTERNAL}, 357 { {0, 0, 0, 0} }, 358 IO_16b}, 359 {"pci1753", PCI_VENDOR_ID_ADVANTECH, 0x1753, PCIDIO_MAINREG, 360 TYPE_PCI1753, 361 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 362 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 363 { {96, PCI1753_DIO, 4, 0}, {0, 0, 0, 0} }, 364 {0, 0, 0, 0}, 365 { {0, 0, 0, 0} }, 366 IO_8b}, 367 {"pci1753e", PCI_VENDOR_ID_ADVANTECH, 0x1753, PCIDIO_MAINREG, 368 TYPE_PCI1753E, 369 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 370 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 371 { {96, PCI1753_DIO, 4, 0}, {96, PCI1753E_DIO, 4, 0} }, 372 {0, 0, 0, 0}, 373 { {0, 0, 0, 0} }, 374 IO_8b}, 375 {"pci1754", PCI_VENDOR_ID_ADVANTECH, 0x1754, PCIDIO_MAINREG, 376 TYPE_PCI1754, 377 { {32, PCI1754_IDI, 2, 0}, {32, PCI1754_IDI2, 2, 0} }, 378 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 379 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 380 {4, PCI175x_BOARDID, 1, SDF_INTERNAL}, 381 { {0, 0, 0, 0} }, 382 IO_16b}, 383 {"pci1756", PCI_VENDOR_ID_ADVANTECH, 0x1756, PCIDIO_MAINREG, 384 TYPE_PCI1756, 385 { {0, 0, 0, 0}, {32, PCI1756_IDI, 2, 0} }, 386 { {0, 0, 0, 0}, {32, PCI1756_IDO, 2, 0} }, 387 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 388 {4, PCI175x_BOARDID, 1, SDF_INTERNAL}, 389 { {0, 0, 0, 0} }, 390 IO_16b}, 391 {"pci1760", PCI_VENDOR_ID_ADVANTECH, 0x1760, 0, 392 TYPE_PCI1760, 393 { {0, 0, 0, 0}, {0, 0, 0, 0} }, /* This card have own setup work */ 394 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 395 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 396 {0, 0, 0, 0}, 397 { {0, 0, 0, 0} }, 398 IO_8b}, 399 {"pci1762", PCI_VENDOR_ID_ADVANTECH, 0x1762, PCIDIO_MAINREG, 400 TYPE_PCI1762, 401 { {0, 0, 0, 0}, {16, PCI1762_IDI, 1, 0} }, 402 { {0, 0, 0, 0}, {16, PCI1762_RO, 1, 0} }, 403 { {0, 0, 0, 0}, {0, 0, 0, 0} }, 404 {4, PCI1762_BOARDID, 1, SDF_INTERNAL}, 405 { {0, 0, 0, 0} }, 406 IO_16b} 407}; 408 409#define n_boardtypes (sizeof(boardtypes)/sizeof(struct dio_boardtype)) 410 411static struct comedi_driver driver_pci_dio = { 412 .driver_name = "adv_pci_dio", 413 .module = THIS_MODULE, 414 .attach = pci_dio_attach, 415 .detach = pci_dio_detach 416}; 417 418struct pci_dio_private { 419 struct pci_dio_private *prev; /* previous private struct */ 420 struct pci_dio_private *next; /* next private struct */ 421 struct pci_dev *pcidev; /* pointer to board's pci_dev */ 422 char valid; /* card is usable */ 423 char GlobalIrqEnabled; /* 1= any IRQ source is enabled */ 424 /* PCI-1760 specific data */ 425 unsigned char IDICntEnable; /* counter's counting enable status */ 426 unsigned char IDICntOverEnable; /* counter's overflow interrupts enable 427 * status */ 428 unsigned char IDICntMatchEnable; /* counter's match interrupts 429 * enable status */ 430 unsigned char IDICntEdge; /* counter's count edge value 431 * (bit=0 - rising, =1 - falling) */ 432 unsigned short CntResValue[8]; /* counters' reset value */ 433 unsigned short CntMatchValue[8]; /* counters' match interrupt value */ 434 unsigned char IDIFiltersEn; /* IDI's digital filters enable status */ 435 unsigned char IDIPatMatchEn; /* IDI's pattern match enable status */ 436 unsigned char IDIPatMatchValue; /* IDI's pattern match value */ 437 unsigned short IDIFiltrLow[8]; /* IDI's filter value low signal */ 438 unsigned short IDIFiltrHigh[8]; /* IDI's filter value high signal */ 439}; 440 441static struct pci_dio_private *pci_priv; /* list of allocated cards */ 442 443#define devpriv ((struct pci_dio_private *)dev->private) 444#define this_board ((const struct dio_boardtype *)dev->board_ptr) 445 446/* 447============================================================================== 448*/ 449static int pci_dio_insn_bits_di_b(struct comedi_device *dev, 450 struct comedi_subdevice *s, 451 struct comedi_insn *insn, unsigned int *data) 452{ 453 const struct diosubd_data *d = (const struct diosubd_data *)s->private; 454 int i; 455 456 data[1] = 0; 457 for (i = 0; i < d->regs; i++) 458 data[1] |= inb(dev->iobase + d->addr + i) << (8 * i); 459 460 461 return 2; 462} 463 464/* 465============================================================================== 466*/ 467static int pci_dio_insn_bits_di_w(struct comedi_device *dev, 468 struct comedi_subdevice *s, 469 struct comedi_insn *insn, unsigned int *data) 470{ 471 const struct diosubd_data *d = (const struct diosubd_data *)s->private; 472 int i; 473 474 data[1] = 0; 475 for (i = 0; i < d->regs; i++) 476 data[1] |= inw(dev->iobase + d->addr + 2 * i) << (16 * i); 477 478 return 2; 479} 480 481/* 482============================================================================== 483*/ 484static int pci_dio_insn_bits_do_b(struct comedi_device *dev, 485 struct comedi_subdevice *s, 486 struct comedi_insn *insn, unsigned int *data) 487{ 488 const struct diosubd_data *d = (const struct diosubd_data *)s->private; 489 int i; 490 491 if (data[0]) { 492 s->state &= ~data[0]; 493 s->state |= (data[0] & data[1]); 494 for (i = 0; i < d->regs; i++) 495 outb((s->state >> (8 * i)) & 0xff, 496 dev->iobase + d->addr + i); 497 } 498 data[1] = s->state; 499 500 return 2; 501} 502 503/* 504============================================================================== 505*/ 506static int pci_dio_insn_bits_do_w(struct comedi_device *dev, 507 struct comedi_subdevice *s, 508 struct comedi_insn *insn, unsigned int *data) 509{ 510 const struct diosubd_data *d = (const struct diosubd_data *)s->private; 511 int i; 512 513 if (data[0]) { 514 s->state &= ~data[0]; 515 s->state |= (data[0] & data[1]); 516 for (i = 0; i < d->regs; i++) 517 outw((s->state >> (16 * i)) & 0xffff, 518 dev->iobase + d->addr + 2 * i); 519 } 520 data[1] = s->state; 521 522 return 2; 523} 524 525/* 526============================================================================== 527*/ 528static int pci_8254_insn_read(struct comedi_device *dev, 529 struct comedi_subdevice *s, 530 struct comedi_insn *insn, unsigned int *data) 531{ 532 const struct diosubd_data *d = (const struct diosubd_data *)s->private; 533 unsigned int chan, chip, chipchan; 534 unsigned long flags; 535 536 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */ 537 chip = chan / 3; /* chip on subdevice */ 538 chipchan = chan - (3 * chip); /* channel on chip on subdevice */ 539 spin_lock_irqsave(&s->spin_lock, flags); 540 data[0] = i8254_read(dev->iobase + d->addr + (SIZE_8254 * chip), 541 0, chipchan); 542 spin_unlock_irqrestore(&s->spin_lock, flags); 543 return 1; 544} 545 546/* 547============================================================================== 548*/ 549static int pci_8254_insn_write(struct comedi_device *dev, 550 struct comedi_subdevice *s, 551 struct comedi_insn *insn, unsigned int *data) 552{ 553 const struct diosubd_data *d = (const struct diosubd_data *)s->private; 554 unsigned int chan, chip, chipchan; 555 unsigned long flags; 556 557 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */ 558 chip = chan / 3; /* chip on subdevice */ 559 chipchan = chan - (3 * chip); /* channel on chip on subdevice */ 560 spin_lock_irqsave(&s->spin_lock, flags); 561 i8254_write(dev->iobase + d->addr + (SIZE_8254 * chip), 562 0, chipchan, data[0]); 563 spin_unlock_irqrestore(&s->spin_lock, flags); 564 return 1; 565} 566 567/* 568============================================================================== 569*/ 570static int pci_8254_insn_config(struct comedi_device *dev, 571 struct comedi_subdevice *s, 572 struct comedi_insn *insn, unsigned int *data) 573{ 574 const struct diosubd_data *d = (const struct diosubd_data *)s->private; 575 unsigned int chan, chip, chipchan; 576 unsigned long iobase; 577 int ret = 0; 578 unsigned long flags; 579 580 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */ 581 chip = chan / 3; /* chip on subdevice */ 582 chipchan = chan - (3 * chip); /* channel on chip on subdevice */ 583 iobase = dev->iobase + d->addr + (SIZE_8254 * chip); 584 spin_lock_irqsave(&s->spin_lock, flags); 585 switch (data[0]) { 586 case INSN_CONFIG_SET_COUNTER_MODE: 587 ret = i8254_set_mode(iobase, 0, chipchan, data[1]); 588 if (ret < 0) 589 ret = -EINVAL; 590 break; 591 case INSN_CONFIG_8254_READ_STATUS: 592 data[1] = i8254_status(iobase, 0, chipchan); 593 break; 594 default: 595 ret = -EINVAL; 596 break; 597 } 598 spin_unlock_irqrestore(&s->spin_lock, flags); 599 return ret < 0 ? ret : insn->n; 600} 601 602/* 603============================================================================== 604*/ 605static int pci1760_unchecked_mbxrequest(struct comedi_device *dev, 606 unsigned char *omb, unsigned char *imb, 607 int repeats) 608{ 609 int cnt, tout, ok = 0; 610 611 for (cnt = 0; cnt < repeats; cnt++) { 612 outb(omb[0], dev->iobase + OMB0); 613 outb(omb[1], dev->iobase + OMB1); 614 outb(omb[2], dev->iobase + OMB2); 615 outb(omb[3], dev->iobase + OMB3); 616 for (tout = 0; tout < 251; tout++) { 617 imb[2] = inb(dev->iobase + IMB2); 618 if (imb[2] == omb[2]) { 619 imb[0] = inb(dev->iobase + IMB0); 620 imb[1] = inb(dev->iobase + IMB1); 621 imb[3] = inb(dev->iobase + IMB3); 622 ok = 1; 623 break; 624 } 625 udelay(1); 626 } 627 if (ok) 628 return 0; 629 } 630 631 comedi_error(dev, "PCI-1760 mailbox request timeout!"); 632 return -ETIME; 633} 634 635static int pci1760_clear_imb2(struct comedi_device *dev) 636{ 637 unsigned char omb[4] = { 0x0, 0x0, CMD_ClearIMB2, 0x0 }; 638 unsigned char imb[4]; 639 /* check if imb2 is already clear */ 640 if (inb(dev->iobase + IMB2) == CMD_ClearIMB2) 641 return 0; 642 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY); 643} 644 645static int pci1760_mbxrequest(struct comedi_device *dev, 646 unsigned char *omb, unsigned char *imb) 647{ 648 if (omb[2] == CMD_ClearIMB2) { 649 comedi_error(dev, 650 "bug! this function should not be used for CMD_ClearIMB2 command"); 651 return -EINVAL; 652 } 653 if (inb(dev->iobase + IMB2) == omb[2]) { 654 int retval; 655 retval = pci1760_clear_imb2(dev); 656 if (retval < 0) 657 return retval; 658 } 659 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY); 660} 661 662/* 663============================================================================== 664*/ 665static int pci1760_insn_bits_di(struct comedi_device *dev, 666 struct comedi_subdevice *s, 667 struct comedi_insn *insn, unsigned int *data) 668{ 669 data[1] = inb(dev->iobase + IMB3); 670 671 return 2; 672} 673 674/* 675============================================================================== 676*/ 677static int pci1760_insn_bits_do(struct comedi_device *dev, 678 struct comedi_subdevice *s, 679 struct comedi_insn *insn, unsigned int *data) 680{ 681 int ret; 682 unsigned char omb[4] = { 683 0x00, 684 0x00, 685 CMD_SetRelaysOutput, 686 0x00 687 }; 688 unsigned char imb[4]; 689 690 if (data[0]) { 691 s->state &= ~data[0]; 692 s->state |= (data[0] & data[1]); 693 omb[0] = s->state; 694 ret = pci1760_mbxrequest(dev, omb, imb); 695 if (!ret) 696 return ret; 697 } 698 data[1] = s->state; 699 700 return 2; 701} 702 703/* 704============================================================================== 705*/ 706static int pci1760_insn_cnt_read(struct comedi_device *dev, 707 struct comedi_subdevice *s, 708 struct comedi_insn *insn, unsigned int *data) 709{ 710 int ret, n; 711 unsigned char omb[4] = { 712 CR_CHAN(insn->chanspec) & 0x07, 713 0x00, 714 CMD_GetIDICntCurValue, 715 0x00 716 }; 717 unsigned char imb[4]; 718 719 for (n = 0; n < insn->n; n++) { 720 ret = pci1760_mbxrequest(dev, omb, imb); 721 if (!ret) 722 return ret; 723 data[n] = (imb[1] << 8) + imb[0]; 724 } 725 726 return n; 727} 728 729/* 730============================================================================== 731*/ 732static int pci1760_insn_cnt_write(struct comedi_device *dev, 733 struct comedi_subdevice *s, 734 struct comedi_insn *insn, unsigned int *data) 735{ 736 int ret; 737 unsigned char chan = CR_CHAN(insn->chanspec) & 0x07; 738 unsigned char bitmask = 1 << chan; 739 unsigned char omb[4] = { 740 data[0] & 0xff, 741 (data[0] >> 8) & 0xff, 742 CMD_SetIDI0CntResetValue + chan, 743 0x00 744 }; 745 unsigned char imb[4]; 746 747 /* Set reset value if different */ 748 if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) { 749 ret = pci1760_mbxrequest(dev, omb, imb); 750 if (!ret) 751 return ret; 752 devpriv->CntResValue[chan] = data[0] & 0xffff; 753 } 754 755 omb[0] = bitmask; /* reset counter to it reset value */ 756 omb[2] = CMD_ResetIDICounters; 757 ret = pci1760_mbxrequest(dev, omb, imb); 758 if (!ret) 759 return ret; 760 761 /* start counter if it don't run */ 762 if (!(bitmask & devpriv->IDICntEnable)) { 763 omb[0] = bitmask; 764 omb[2] = CMD_EnableIDICounters; 765 ret = pci1760_mbxrequest(dev, omb, imb); 766 if (!ret) 767 return ret; 768 devpriv->IDICntEnable |= bitmask; 769 } 770 return 1; 771} 772 773/* 774============================================================================== 775*/ 776static int pci1760_reset(struct comedi_device *dev) 777{ 778 int i; 779 unsigned char omb[4] = { 0x00, 0x00, 0x00, 0x00 }; 780 unsigned char imb[4]; 781 782 outb(0, dev->iobase + INTCSR0); /* disable IRQ */ 783 outb(0, dev->iobase + INTCSR1); 784 outb(0, dev->iobase + INTCSR2); 785 outb(0, dev->iobase + INTCSR3); 786 devpriv->GlobalIrqEnabled = 0; 787 788 omb[0] = 0x00; 789 omb[2] = CMD_SetRelaysOutput; /* reset relay outputs */ 790 pci1760_mbxrequest(dev, omb, imb); 791 792 omb[0] = 0x00; 793 omb[2] = CMD_EnableIDICounters; /* disable IDI up counters */ 794 pci1760_mbxrequest(dev, omb, imb); 795 devpriv->IDICntEnable = 0; 796 797 omb[0] = 0x00; 798 omb[2] = CMD_OverflowIDICounters; /* disable counters overflow 799 * interrupts */ 800 pci1760_mbxrequest(dev, omb, imb); 801 devpriv->IDICntOverEnable = 0; 802 803 omb[0] = 0x00; 804 omb[2] = CMD_MatchIntIDICounters; /* disable counters match value 805 * interrupts */ 806 pci1760_mbxrequest(dev, omb, imb); 807 devpriv->IDICntMatchEnable = 0; 808 809 omb[0] = 0x00; 810 omb[1] = 0x80; 811 for (i = 0; i < 8; i++) { /* set IDI up counters match value */ 812 omb[2] = CMD_SetIDI0CntMatchValue + i; 813 pci1760_mbxrequest(dev, omb, imb); 814 devpriv->CntMatchValue[i] = 0x8000; 815 } 816 817 omb[0] = 0x00; 818 omb[1] = 0x00; 819 for (i = 0; i < 8; i++) { /* set IDI up counters reset value */ 820 omb[2] = CMD_SetIDI0CntResetValue + i; 821 pci1760_mbxrequest(dev, omb, imb); 822 devpriv->CntResValue[i] = 0x0000; 823 } 824 825 omb[0] = 0xff; 826 omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset 827 * values */ 828 pci1760_mbxrequest(dev, omb, imb); 829 830 omb[0] = 0x00; 831 omb[2] = CMD_EdgeIDICounters; /* set IDI up counters count edge */ 832 pci1760_mbxrequest(dev, omb, imb); 833 devpriv->IDICntEdge = 0x00; 834 835 omb[0] = 0x00; 836 omb[2] = CMD_EnableIDIFilters; /* disable all digital in filters */ 837 pci1760_mbxrequest(dev, omb, imb); 838 devpriv->IDIFiltersEn = 0x00; 839 840 omb[0] = 0x00; 841 omb[2] = CMD_EnableIDIPatternMatch; /* disable pattern matching */ 842 pci1760_mbxrequest(dev, omb, imb); 843 devpriv->IDIPatMatchEn = 0x00; 844 845 omb[0] = 0x00; 846 omb[2] = CMD_SetIDIPatternMatch; /* set pattern match value */ 847 pci1760_mbxrequest(dev, omb, imb); 848 devpriv->IDIPatMatchValue = 0x00; 849 850 return 0; 851} 852 853/* 854============================================================================== 855*/ 856static int pci_dio_reset(struct comedi_device *dev) 857{ 858 DPRINTK("adv_pci_dio EDBG: BGN: pci171x_reset(...)\n"); 859 860 switch (this_board->cardtype) { 861 case TYPE_PCI1730: 862 outb(0, dev->iobase + PCI1730_DO); /* clear outputs */ 863 outb(0, dev->iobase + PCI1730_DO + 1); 864 outb(0, dev->iobase + PCI1730_IDO); 865 outb(0, dev->iobase + PCI1730_IDO + 1); 866 /* NO break there! */ 867 case TYPE_PCI1733: 868 /* disable interrupts */ 869 outb(0, dev->iobase + PCI1730_3_INT_EN); 870 /* clear interrupts */ 871 outb(0x0f, dev->iobase + PCI1730_3_INT_CLR); 872 /* set rising edge trigger */ 873 outb(0, dev->iobase + PCI1730_3_INT_RF); 874 break; 875 case TYPE_PCI1734: 876 outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */ 877 outb(0, dev->iobase + PCI1734_IDO + 1); 878 outb(0, dev->iobase + PCI1734_IDO + 2); 879 outb(0, dev->iobase + PCI1734_IDO + 3); 880 break; 881 case TYPE_PCI1735: 882 outb(0, dev->iobase + PCI1735_DO); /* clear outputs */ 883 outb(0, dev->iobase + PCI1735_DO + 1); 884 outb(0, dev->iobase + PCI1735_DO + 2); 885 outb(0, dev->iobase + PCI1735_DO + 3); 886 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 0, I8254_MODE0); 887 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 1, I8254_MODE0); 888 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 2, I8254_MODE0); 889 break; 890 891 case TYPE_PCI1736: 892 outb(0, dev->iobase + PCI1736_IDO); 893 outb(0, dev->iobase + PCI1736_IDO + 1); 894 /* disable interrupts */ 895 outb(0, dev->iobase + PCI1736_3_INT_EN); 896 /* clear interrupts */ 897 outb(0x0f, dev->iobase + PCI1736_3_INT_CLR); 898 /* set rising edge trigger */ 899 outb(0, dev->iobase + PCI1736_3_INT_RF); 900 break; 901 902 case TYPE_PCI1739: 903 /* disable & clear interrupts */ 904 outb(0x88, dev->iobase + PCI1739_ICR); 905 break; 906 907 case TYPE_PCI1750: 908 case TYPE_PCI1751: 909 /* disable & clear interrupts */ 910 outb(0x88, dev->iobase + PCI1750_ICR); 911 break; 912 case TYPE_PCI1752: 913 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze 914 * function */ 915 outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */ 916 outw(0, dev->iobase + PCI1752_IDO + 2); 917 outw(0, dev->iobase + PCI1752_IDO2); 918 outw(0, dev->iobase + PCI1752_IDO2 + 2); 919 break; 920 case TYPE_PCI1753E: 921 outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear 922 * interrupts */ 923 outb(0x80, dev->iobase + PCI1753E_ICR1); 924 outb(0x80, dev->iobase + PCI1753E_ICR2); 925 outb(0x80, dev->iobase + PCI1753E_ICR3); 926 /* NO break there! */ 927 case TYPE_PCI1753: 928 outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear 929 * interrupts */ 930 outb(0x80, dev->iobase + PCI1753_ICR1); 931 outb(0x80, dev->iobase + PCI1753_ICR2); 932 outb(0x80, dev->iobase + PCI1753_ICR3); 933 break; 934 case TYPE_PCI1754: 935 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear 936 * interrupts */ 937 outw(0x08, dev->iobase + PCI1754_6_ICR1); 938 outw(0x08, dev->iobase + PCI1754_ICR2); 939 outw(0x08, dev->iobase + PCI1754_ICR3); 940 break; 941 case TYPE_PCI1756: 942 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze 943 * function */ 944 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear 945 * interrupts */ 946 outw(0x08, dev->iobase + PCI1754_6_ICR1); 947 outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */ 948 outw(0, dev->iobase + PCI1756_IDO + 2); 949 break; 950 case TYPE_PCI1760: 951 pci1760_reset(dev); 952 break; 953 case TYPE_PCI1762: 954 outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear 955 * interrupts */ 956 break; 957 } 958 959 DPRINTK("adv_pci_dio EDBG: END: pci171x_reset(...)\n"); 960 961 return 0; 962} 963 964/* 965============================================================================== 966*/ 967static int pci1760_attach(struct comedi_device *dev, 968 struct comedi_devconfig *it) 969{ 970 struct comedi_subdevice *s; 971 int subdev = 0; 972 973 s = dev->subdevices + subdev; 974 s->type = COMEDI_SUBD_DI; 975 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON; 976 s->n_chan = 8; 977 s->maxdata = 1; 978 s->len_chanlist = 8; 979 s->range_table = &range_digital; 980 s->insn_bits = pci1760_insn_bits_di; 981 subdev++; 982 983 s = dev->subdevices + subdev; 984 s->type = COMEDI_SUBD_DO; 985 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON; 986 s->n_chan = 8; 987 s->maxdata = 1; 988 s->len_chanlist = 8; 989 s->range_table = &range_digital; 990 s->state = 0; 991 s->insn_bits = pci1760_insn_bits_do; 992 subdev++; 993 994 s = dev->subdevices + subdev; 995 s->type = COMEDI_SUBD_TIMER; 996 s->subdev_flags = SDF_WRITABLE | SDF_LSAMPL; 997 s->n_chan = 2; 998 s->maxdata = 0xffffffff; 999 s->len_chanlist = 2; 1000/* s->insn_config=pci1760_insn_pwm_cfg; */ 1001 subdev++; 1002 1003 s = dev->subdevices + subdev; 1004 s->type = COMEDI_SUBD_COUNTER; 1005 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; 1006 s->n_chan = 8; 1007 s->maxdata = 0xffff; 1008 s->len_chanlist = 8; 1009 s->insn_read = pci1760_insn_cnt_read; 1010 s->insn_write = pci1760_insn_cnt_write; 1011/* s->insn_config=pci1760_insn_cnt_cfg; */ 1012 subdev++; 1013 1014 return 0; 1015} 1016 1017/* 1018============================================================================== 1019*/ 1020static int pci_dio_add_di(struct comedi_device *dev, struct comedi_subdevice *s, 1021 const struct diosubd_data *d, int subdev) 1022{ 1023 s->type = COMEDI_SUBD_DI; 1024 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | d->specflags; 1025 if (d->chans > 16) 1026 s->subdev_flags |= SDF_LSAMPL; 1027 s->n_chan = d->chans; 1028 s->maxdata = 1; 1029 s->len_chanlist = d->chans; 1030 s->range_table = &range_digital; 1031 switch (this_board->io_access) { 1032 case IO_8b: 1033 s->insn_bits = pci_dio_insn_bits_di_b; 1034 break; 1035 case IO_16b: 1036 s->insn_bits = pci_dio_insn_bits_di_w; 1037 break; 1038 } 1039 s->private = (void *)d; 1040 1041 return 0; 1042} 1043 1044/* 1045============================================================================== 1046*/ 1047static int pci_dio_add_do(struct comedi_device *dev, struct comedi_subdevice *s, 1048 const struct diosubd_data *d, int subdev) 1049{ 1050 s->type = COMEDI_SUBD_DO; 1051 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON; 1052 if (d->chans > 16) 1053 s->subdev_flags |= SDF_LSAMPL; 1054 s->n_chan = d->chans; 1055 s->maxdata = 1; 1056 s->len_chanlist = d->chans; 1057 s->range_table = &range_digital; 1058 s->state = 0; 1059 switch (this_board->io_access) { 1060 case IO_8b: 1061 s->insn_bits = pci_dio_insn_bits_do_b; 1062 break; 1063 case IO_16b: 1064 s->insn_bits = pci_dio_insn_bits_do_w; 1065 break; 1066 } 1067 s->private = (void *)d; 1068 1069 return 0; 1070} 1071 1072/* 1073============================================================================== 1074*/ 1075static int pci_dio_add_8254(struct comedi_device *dev, 1076 struct comedi_subdevice *s, 1077 const struct diosubd_data *d, int subdev) 1078{ 1079 s->type = COMEDI_SUBD_COUNTER; 1080 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; 1081 s->n_chan = d->chans; 1082 s->maxdata = 65535; 1083 s->len_chanlist = d->chans; 1084 s->insn_read = pci_8254_insn_read; 1085 s->insn_write = pci_8254_insn_write; 1086 s->insn_config = pci_8254_insn_config; 1087 s->private = (void *)d; 1088 1089 return 0; 1090} 1091 1092/* 1093============================================================================== 1094*/ 1095static int CheckAndAllocCard(struct comedi_device *dev, 1096 struct comedi_devconfig *it, 1097 struct pci_dev *pcidev) 1098{ 1099 struct pci_dio_private *pr, *prev; 1100 1101 for (pr = pci_priv, prev = NULL; pr != NULL; prev = pr, pr = pr->next) { 1102 if (pr->pcidev == pcidev) 1103 return 0; /* this card is used, look for another */ 1104 1105 } 1106 1107 if (prev) { 1108 devpriv->prev = prev; 1109 prev->next = devpriv; 1110 } else { 1111 pci_priv = devpriv; 1112 } 1113 1114 devpriv->pcidev = pcidev; 1115 1116 return 1; 1117} 1118 1119/* 1120============================================================================== 1121*/ 1122static int pci_dio_attach(struct comedi_device *dev, 1123 struct comedi_devconfig *it) 1124{ 1125 struct comedi_subdevice *s; 1126 int ret, subdev, n_subdevices, i, j; 1127 unsigned long iobase; 1128 struct pci_dev *pcidev = NULL; 1129 1130 1131 ret = alloc_private(dev, sizeof(struct pci_dio_private)); 1132 if (ret < 0) 1133 return -ENOMEM; 1134 1135 for_each_pci_dev(pcidev) { 1136 /* loop through cards supported by this driver */ 1137 for (i = 0; i < n_boardtypes; ++i) { 1138 if (boardtypes[i].vendor_id != pcidev->vendor) 1139 continue; 1140 if (boardtypes[i].device_id != pcidev->device) 1141 continue; 1142 /* was a particular bus/slot requested? */ 1143 if (it->options[0] || it->options[1]) { 1144 /* are we on the wrong bus/slot? */ 1145 if (pcidev->bus->number != it->options[0] || 1146 PCI_SLOT(pcidev->devfn) != it->options[1]) { 1147 continue; 1148 } 1149 } 1150 ret = CheckAndAllocCard(dev, it, pcidev); 1151 if (ret != 1) 1152 continue; 1153 dev->board_ptr = boardtypes + i; 1154 break; 1155 } 1156 if (dev->board_ptr) 1157 break; 1158 } 1159 1160 if (!dev->board_ptr) { 1161 dev_err(dev->hw_dev, "Error: Requested type of the card was not found!\n"); 1162 return -EIO; 1163 } 1164 1165 if (comedi_pci_enable(pcidev, driver_pci_dio.driver_name)) { 1166 dev_err(dev->hw_dev, "Error: Can't enable PCI device and request regions!\n"); 1167 return -EIO; 1168 } 1169 iobase = pci_resource_start(pcidev, this_board->main_pci_region); 1170 dev_dbg(dev->hw_dev, "b:s:f=%d:%d:%d, io=0x%4lx\n", 1171 pcidev->bus->number, PCI_SLOT(pcidev->devfn), 1172 PCI_FUNC(pcidev->devfn), iobase); 1173 1174 dev->iobase = iobase; 1175 dev->board_name = this_board->name; 1176 1177 if (this_board->cardtype == TYPE_PCI1760) { 1178 n_subdevices = 4; /* 8 IDI, 8 IDO, 2 PWM, 8 CNT */ 1179 } else { 1180 n_subdevices = 0; 1181 for (i = 0; i < MAX_DI_SUBDEVS; i++) 1182 if (this_board->sdi[i].chans) 1183 n_subdevices++; 1184 for (i = 0; i < MAX_DO_SUBDEVS; i++) 1185 if (this_board->sdo[i].chans) 1186 n_subdevices++; 1187 for (i = 0; i < MAX_DIO_SUBDEVG; i++) 1188 n_subdevices += this_board->sdio[i].regs; 1189 if (this_board->boardid.chans) 1190 n_subdevices++; 1191 for (i = 0; i < MAX_8254_SUBDEVS; i++) 1192 if (this_board->s8254[i].chans) 1193 n_subdevices++; 1194 } 1195 1196 ret = alloc_subdevices(dev, n_subdevices); 1197 if (ret < 0) 1198 return ret; 1199 1200 subdev = 0; 1201 for (i = 0; i < MAX_DI_SUBDEVS; i++) 1202 if (this_board->sdi[i].chans) { 1203 s = dev->subdevices + subdev; 1204 pci_dio_add_di(dev, s, &this_board->sdi[i], subdev); 1205 subdev++; 1206 } 1207 1208 for (i = 0; i < MAX_DO_SUBDEVS; i++) 1209 if (this_board->sdo[i].chans) { 1210 s = dev->subdevices + subdev; 1211 pci_dio_add_do(dev, s, &this_board->sdo[i], subdev); 1212 subdev++; 1213 } 1214 1215 for (i = 0; i < MAX_DIO_SUBDEVG; i++) 1216 for (j = 0; j < this_board->sdio[i].regs; j++) { 1217 s = dev->subdevices + subdev; 1218 subdev_8255_init(dev, s, NULL, 1219 dev->iobase + 1220 this_board->sdio[i].addr + 1221 SIZE_8255 * j); 1222 subdev++; 1223 } 1224 1225 if (this_board->boardid.chans) { 1226 s = dev->subdevices + subdev; 1227 s->type = COMEDI_SUBD_DI; 1228 pci_dio_add_di(dev, s, &this_board->boardid, subdev); 1229 subdev++; 1230 } 1231 1232 for (i = 0; i < MAX_8254_SUBDEVS; i++) 1233 if (this_board->s8254[i].chans) { 1234 s = dev->subdevices + subdev; 1235 pci_dio_add_8254(dev, s, &this_board->s8254[i], subdev); 1236 subdev++; 1237 } 1238 1239 if (this_board->cardtype == TYPE_PCI1760) 1240 pci1760_attach(dev, it); 1241 1242 devpriv->valid = 1; 1243 1244 pci_dio_reset(dev); 1245 1246 return 0; 1247} 1248 1249/* 1250============================================================================== 1251*/ 1252static int pci_dio_detach(struct comedi_device *dev) 1253{ 1254 int i, j; 1255 struct comedi_subdevice *s; 1256 int subdev; 1257 1258 if (dev->private) { 1259 if (devpriv->valid) 1260 pci_dio_reset(dev); 1261 1262 1263 /* This shows the silliness of using this kind of 1264 * scheme for numbering subdevices. Don't do it. --ds */ 1265 subdev = 0; 1266 for (i = 0; i < MAX_DI_SUBDEVS; i++) { 1267 if (this_board->sdi[i].chans) 1268 subdev++; 1269 1270 } 1271 for (i = 0; i < MAX_DO_SUBDEVS; i++) { 1272 if (this_board->sdo[i].chans) 1273 subdev++; 1274 1275 } 1276 for (i = 0; i < MAX_DIO_SUBDEVG; i++) { 1277 for (j = 0; j < this_board->sdio[i].regs; j++) { 1278 s = dev->subdevices + subdev; 1279 subdev_8255_cleanup(dev, s); 1280 subdev++; 1281 } 1282 } 1283 1284 if (this_board->boardid.chans) 1285 subdev++; 1286 1287 for (i = 0; i < MAX_8254_SUBDEVS; i++) 1288 if (this_board->s8254[i].chans) 1289 subdev++; 1290 1291 for (i = 0; i < dev->n_subdevices; i++) { 1292 s = dev->subdevices + i; 1293 s->private = NULL; 1294 } 1295 1296 if (devpriv->pcidev) { 1297 if (dev->iobase) 1298 comedi_pci_disable(devpriv->pcidev); 1299 1300 pci_dev_put(devpriv->pcidev); 1301 } 1302 1303 if (devpriv->prev) 1304 devpriv->prev->next = devpriv->next; 1305 else 1306 pci_priv = devpriv->next; 1307 1308 if (devpriv->next) 1309 devpriv->next->prev = devpriv->prev; 1310 1311 } 1312 1313 return 0; 1314} 1315 1316/* 1317============================================================================== 1318*/ 1319static int __devinit driver_pci_dio_pci_probe(struct pci_dev *dev, 1320 const struct pci_device_id *ent) 1321{ 1322 return comedi_pci_auto_config(dev, driver_pci_dio.driver_name); 1323} 1324 1325static void __devexit driver_pci_dio_pci_remove(struct pci_dev *dev) 1326{ 1327 comedi_pci_auto_unconfig(dev); 1328} 1329 1330static struct pci_driver driver_pci_dio_pci_driver = { 1331 .id_table = pci_dio_pci_table, 1332 .probe = &driver_pci_dio_pci_probe, 1333 .remove = __devexit_p(&driver_pci_dio_pci_remove) 1334}; 1335 1336static int __init driver_pci_dio_init_module(void) 1337{ 1338 int retval; 1339 1340 retval = comedi_driver_register(&driver_pci_dio); 1341 if (retval < 0) 1342 return retval; 1343 1344 driver_pci_dio_pci_driver.name = (char *)driver_pci_dio.driver_name; 1345 return pci_register_driver(&driver_pci_dio_pci_driver); 1346} 1347 1348static void __exit driver_pci_dio_cleanup_module(void) 1349{ 1350 pci_unregister_driver(&driver_pci_dio_pci_driver); 1351 comedi_driver_unregister(&driver_pci_dio); 1352} 1353 1354module_init(driver_pci_dio_init_module); 1355module_exit(driver_pci_dio_cleanup_module); 1356/* 1357============================================================================== 1358*/ 1359 1360MODULE_AUTHOR("Comedi http://www.comedi.org"); 1361MODULE_DESCRIPTION("Comedi low-level driver"); 1362MODULE_LICENSE("GPL"); 1363