1/* 2 * AD7792/AD7793 SPI ADC driver 3 * 4 * Copyright 2011 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2. 7 */ 8 9#include <linux/interrupt.h> 10#include <linux/device.h> 11#include <linux/kernel.h> 12#include <linux/slab.h> 13#include <linux/sysfs.h> 14#include <linux/spi/spi.h> 15#include <linux/regulator/consumer.h> 16#include <linux/err.h> 17#include <linux/sched.h> 18#include <linux/delay.h> 19#include <linux/module.h> 20 21#include "../iio.h" 22#include "../sysfs.h" 23#include "../buffer.h" 24#include "../ring_sw.h" 25#include "../trigger.h" 26#include "../trigger_consumer.h" 27 28#include "ad7793.h" 29 30/* NOTE: 31 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output. 32 * In order to avoid contentions on the SPI bus, it's therefore necessary 33 * to use spi bus locking. 34 * 35 * The DOUT/RDY output must also be wired to an interrupt capable GPIO. 36 */ 37 38struct ad7793_chip_info { 39 struct iio_chan_spec channel[7]; 40}; 41 42struct ad7793_state { 43 struct spi_device *spi; 44 struct iio_trigger *trig; 45 const struct ad7793_chip_info *chip_info; 46 struct regulator *reg; 47 struct ad7793_platform_data *pdata; 48 wait_queue_head_t wq_data_avail; 49 bool done; 50 bool irq_dis; 51 u16 int_vref_mv; 52 u16 mode; 53 u16 conf; 54 u32 scale_avail[8][2]; 55 /* Note this uses fact that 8 the mask always fits in a long */ 56 unsigned long available_scan_masks[7]; 57 /* 58 * DMA (thus cache coherency maintenance) requires the 59 * transfer buffers to live in their own cache lines. 60 */ 61 u8 data[4] ____cacheline_aligned; 62}; 63 64enum ad7793_supported_device_ids { 65 ID_AD7792, 66 ID_AD7793, 67}; 68 69static int __ad7793_write_reg(struct ad7793_state *st, bool locked, 70 bool cs_change, unsigned char reg, 71 unsigned size, unsigned val) 72{ 73 u8 *data = st->data; 74 struct spi_transfer t = { 75 .tx_buf = data, 76 .len = size + 1, 77 .cs_change = cs_change, 78 }; 79 struct spi_message m; 80 81 data[0] = AD7793_COMM_WRITE | AD7793_COMM_ADDR(reg); 82 83 switch (size) { 84 case 3: 85 data[1] = val >> 16; 86 data[2] = val >> 8; 87 data[3] = val; 88 break; 89 case 2: 90 data[1] = val >> 8; 91 data[2] = val; 92 break; 93 case 1: 94 data[1] = val; 95 break; 96 default: 97 return -EINVAL; 98 } 99 100 spi_message_init(&m); 101 spi_message_add_tail(&t, &m); 102 103 if (locked) 104 return spi_sync_locked(st->spi, &m); 105 else 106 return spi_sync(st->spi, &m); 107} 108 109static int ad7793_write_reg(struct ad7793_state *st, 110 unsigned reg, unsigned size, unsigned val) 111{ 112 return __ad7793_write_reg(st, false, false, reg, size, val); 113} 114 115static int __ad7793_read_reg(struct ad7793_state *st, bool locked, 116 bool cs_change, unsigned char reg, 117 int *val, unsigned size) 118{ 119 u8 *data = st->data; 120 int ret; 121 struct spi_transfer t[] = { 122 { 123 .tx_buf = data, 124 .len = 1, 125 }, { 126 .rx_buf = data, 127 .len = size, 128 .cs_change = cs_change, 129 }, 130 }; 131 struct spi_message m; 132 133 data[0] = AD7793_COMM_READ | AD7793_COMM_ADDR(reg); 134 135 spi_message_init(&m); 136 spi_message_add_tail(&t[0], &m); 137 spi_message_add_tail(&t[1], &m); 138 139 if (locked) 140 ret = spi_sync_locked(st->spi, &m); 141 else 142 ret = spi_sync(st->spi, &m); 143 144 if (ret < 0) 145 return ret; 146 147 switch (size) { 148 case 3: 149 *val = data[0] << 16 | data[1] << 8 | data[2]; 150 break; 151 case 2: 152 *val = data[0] << 8 | data[1]; 153 break; 154 case 1: 155 *val = data[0]; 156 break; 157 default: 158 return -EINVAL; 159 } 160 161 return 0; 162} 163 164static int ad7793_read_reg(struct ad7793_state *st, 165 unsigned reg, int *val, unsigned size) 166{ 167 return __ad7793_read_reg(st, 0, 0, reg, val, size); 168} 169 170static int ad7793_read(struct ad7793_state *st, unsigned ch, 171 unsigned len, int *val) 172{ 173 int ret; 174 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch); 175 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) | 176 AD7793_MODE_SEL(AD7793_MODE_SINGLE); 177 178 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf); 179 180 spi_bus_lock(st->spi->master); 181 st->done = false; 182 183 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE, 184 sizeof(st->mode), st->mode); 185 if (ret < 0) 186 goto out; 187 188 st->irq_dis = false; 189 enable_irq(st->spi->irq); 190 wait_event_interruptible(st->wq_data_avail, st->done); 191 192 ret = __ad7793_read_reg(st, 1, 0, AD7793_REG_DATA, val, len); 193out: 194 spi_bus_unlock(st->spi->master); 195 196 return ret; 197} 198 199static int ad7793_calibrate(struct ad7793_state *st, unsigned mode, unsigned ch) 200{ 201 int ret; 202 203 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch); 204 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) | AD7793_MODE_SEL(mode); 205 206 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf); 207 208 spi_bus_lock(st->spi->master); 209 st->done = false; 210 211 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE, 212 sizeof(st->mode), st->mode); 213 if (ret < 0) 214 goto out; 215 216 st->irq_dis = false; 217 enable_irq(st->spi->irq); 218 wait_event_interruptible(st->wq_data_avail, st->done); 219 220 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) | 221 AD7793_MODE_SEL(AD7793_MODE_IDLE); 222 223 ret = __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE, 224 sizeof(st->mode), st->mode); 225out: 226 spi_bus_unlock(st->spi->master); 227 228 return ret; 229} 230 231static const u8 ad7793_calib_arr[6][2] = { 232 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M}, 233 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M}, 234 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M}, 235 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M}, 236 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M}, 237 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M} 238}; 239 240static int ad7793_calibrate_all(struct ad7793_state *st) 241{ 242 int i, ret; 243 244 for (i = 0; i < ARRAY_SIZE(ad7793_calib_arr); i++) { 245 ret = ad7793_calibrate(st, ad7793_calib_arr[i][0], 246 ad7793_calib_arr[i][1]); 247 if (ret) 248 goto out; 249 } 250 251 return 0; 252out: 253 dev_err(&st->spi->dev, "Calibration failed\n"); 254 return ret; 255} 256 257static int ad7793_setup(struct ad7793_state *st) 258{ 259 int i, ret = -1; 260 unsigned long long scale_uv; 261 u32 id; 262 263 /* reset the serial interface */ 264 ret = spi_write(st->spi, (u8 *)&ret, sizeof(ret)); 265 if (ret < 0) 266 goto out; 267 msleep(1); /* Wait for at least 500us */ 268 269 /* write/read test for device presence */ 270 ret = ad7793_read_reg(st, AD7793_REG_ID, &id, 1); 271 if (ret) 272 goto out; 273 274 id &= AD7793_ID_MASK; 275 276 if (!((id == AD7792_ID) || (id == AD7793_ID))) { 277 dev_err(&st->spi->dev, "device ID query failed\n"); 278 goto out; 279 } 280 281 st->mode = (st->pdata->mode & ~AD7793_MODE_SEL(-1)) | 282 AD7793_MODE_SEL(AD7793_MODE_IDLE); 283 st->conf = st->pdata->conf & ~AD7793_CONF_CHAN(-1); 284 285 ret = ad7793_write_reg(st, AD7793_REG_MODE, sizeof(st->mode), st->mode); 286 if (ret) 287 goto out; 288 289 ret = ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf); 290 if (ret) 291 goto out; 292 293 ret = ad7793_write_reg(st, AD7793_REG_IO, 294 sizeof(st->pdata->io), st->pdata->io); 295 if (ret) 296 goto out; 297 298 ret = ad7793_calibrate_all(st); 299 if (ret) 300 goto out; 301 302 /* Populate available ADC input ranges */ 303 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 304 scale_uv = ((u64)st->int_vref_mv * 100000000) 305 >> (st->chip_info->channel[0].scan_type.realbits - 306 (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1)); 307 scale_uv >>= i; 308 309 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; 310 st->scale_avail[i][0] = scale_uv; 311 } 312 313 return 0; 314out: 315 dev_err(&st->spi->dev, "setup failed\n"); 316 return ret; 317} 318 319static int ad7793_ring_preenable(struct iio_dev *indio_dev) 320{ 321 struct ad7793_state *st = iio_priv(indio_dev); 322 struct iio_buffer *ring = indio_dev->buffer; 323 size_t d_size; 324 unsigned channel; 325 326 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength)) 327 return -EINVAL; 328 329 channel = find_first_bit(indio_dev->active_scan_mask, 330 indio_dev->masklength); 331 332 d_size = bitmap_weight(indio_dev->active_scan_mask, 333 indio_dev->masklength) * 334 indio_dev->channels[0].scan_type.storagebits / 8; 335 336 if (ring->scan_timestamp) { 337 d_size += sizeof(s64); 338 339 if (d_size % sizeof(s64)) 340 d_size += sizeof(s64) - (d_size % sizeof(s64)); 341 } 342 343 if (indio_dev->buffer->access->set_bytes_per_datum) 344 indio_dev->buffer->access-> 345 set_bytes_per_datum(indio_dev->buffer, d_size); 346 347 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) | 348 AD7793_MODE_SEL(AD7793_MODE_CONT); 349 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | 350 AD7793_CONF_CHAN(indio_dev->channels[channel].address); 351 352 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf); 353 354 spi_bus_lock(st->spi->master); 355 __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE, 356 sizeof(st->mode), st->mode); 357 358 st->irq_dis = false; 359 enable_irq(st->spi->irq); 360 361 return 0; 362} 363 364static int ad7793_ring_postdisable(struct iio_dev *indio_dev) 365{ 366 struct ad7793_state *st = iio_priv(indio_dev); 367 368 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) | 369 AD7793_MODE_SEL(AD7793_MODE_IDLE); 370 371 st->done = false; 372 wait_event_interruptible(st->wq_data_avail, st->done); 373 374 if (!st->irq_dis) 375 disable_irq_nosync(st->spi->irq); 376 377 __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE, 378 sizeof(st->mode), st->mode); 379 380 return spi_bus_unlock(st->spi->master); 381} 382 383/** 384 * ad7793_trigger_handler() bh of trigger launched polling to ring buffer 385 **/ 386 387static irqreturn_t ad7793_trigger_handler(int irq, void *p) 388{ 389 struct iio_poll_func *pf = p; 390 struct iio_dev *indio_dev = pf->indio_dev; 391 struct iio_buffer *ring = indio_dev->buffer; 392 struct ad7793_state *st = iio_priv(indio_dev); 393 s64 dat64[2]; 394 s32 *dat32 = (s32 *)dat64; 395 396 if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength)) 397 __ad7793_read_reg(st, 1, 1, AD7793_REG_DATA, 398 dat32, 399 indio_dev->channels[0].scan_type.realbits/8); 400 401 /* Guaranteed to be aligned with 8 byte boundary */ 402 if (ring->scan_timestamp) 403 dat64[1] = pf->timestamp; 404 405 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp); 406 407 iio_trigger_notify_done(indio_dev->trig); 408 st->irq_dis = false; 409 enable_irq(st->spi->irq); 410 411 return IRQ_HANDLED; 412} 413 414static const struct iio_buffer_setup_ops ad7793_ring_setup_ops = { 415 .preenable = &ad7793_ring_preenable, 416 .postenable = &iio_triggered_buffer_postenable, 417 .predisable = &iio_triggered_buffer_predisable, 418 .postdisable = &ad7793_ring_postdisable, 419}; 420 421static int ad7793_register_ring_funcs_and_init(struct iio_dev *indio_dev) 422{ 423 int ret; 424 425 indio_dev->buffer = iio_sw_rb_allocate(indio_dev); 426 if (!indio_dev->buffer) { 427 ret = -ENOMEM; 428 goto error_ret; 429 } 430 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time, 431 &ad7793_trigger_handler, 432 IRQF_ONESHOT, 433 indio_dev, 434 "ad7793_consumer%d", 435 indio_dev->id); 436 if (indio_dev->pollfunc == NULL) { 437 ret = -ENOMEM; 438 goto error_deallocate_sw_rb; 439 } 440 441 /* Ring buffer functions - here trigger setup related */ 442 indio_dev->setup_ops = &ad7793_ring_setup_ops; 443 444 /* Flag that polled ring buffering is possible */ 445 indio_dev->modes |= INDIO_BUFFER_TRIGGERED; 446 return 0; 447 448error_deallocate_sw_rb: 449 iio_sw_rb_free(indio_dev->buffer); 450error_ret: 451 return ret; 452} 453 454static void ad7793_ring_cleanup(struct iio_dev *indio_dev) 455{ 456 iio_dealloc_pollfunc(indio_dev->pollfunc); 457 iio_sw_rb_free(indio_dev->buffer); 458} 459 460/** 461 * ad7793_data_rdy_trig_poll() the event handler for the data rdy trig 462 **/ 463static irqreturn_t ad7793_data_rdy_trig_poll(int irq, void *private) 464{ 465 struct ad7793_state *st = iio_priv(private); 466 467 st->done = true; 468 wake_up_interruptible(&st->wq_data_avail); 469 disable_irq_nosync(irq); 470 st->irq_dis = true; 471 iio_trigger_poll(st->trig, iio_get_time_ns()); 472 473 return IRQ_HANDLED; 474} 475 476static struct iio_trigger_ops ad7793_trigger_ops = { 477 .owner = THIS_MODULE, 478}; 479 480static int ad7793_probe_trigger(struct iio_dev *indio_dev) 481{ 482 struct ad7793_state *st = iio_priv(indio_dev); 483 int ret; 484 485 st->trig = iio_allocate_trigger("%s-dev%d", 486 spi_get_device_id(st->spi)->name, 487 indio_dev->id); 488 if (st->trig == NULL) { 489 ret = -ENOMEM; 490 goto error_ret; 491 } 492 st->trig->ops = &ad7793_trigger_ops; 493 494 ret = request_irq(st->spi->irq, 495 ad7793_data_rdy_trig_poll, 496 IRQF_TRIGGER_LOW, 497 spi_get_device_id(st->spi)->name, 498 indio_dev); 499 if (ret) 500 goto error_free_trig; 501 502 disable_irq_nosync(st->spi->irq); 503 st->irq_dis = true; 504 st->trig->dev.parent = &st->spi->dev; 505 st->trig->private_data = indio_dev; 506 507 ret = iio_trigger_register(st->trig); 508 509 /* select default trigger */ 510 indio_dev->trig = st->trig; 511 if (ret) 512 goto error_free_irq; 513 514 return 0; 515 516error_free_irq: 517 free_irq(st->spi->irq, indio_dev); 518error_free_trig: 519 iio_free_trigger(st->trig); 520error_ret: 521 return ret; 522} 523 524static void ad7793_remove_trigger(struct iio_dev *indio_dev) 525{ 526 struct ad7793_state *st = iio_priv(indio_dev); 527 528 iio_trigger_unregister(st->trig); 529 free_irq(st->spi->irq, indio_dev); 530 iio_free_trigger(st->trig); 531} 532 533static const u16 sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39, 33, 19, 534 17, 16, 12, 10, 8, 6, 4}; 535 536static ssize_t ad7793_read_frequency(struct device *dev, 537 struct device_attribute *attr, 538 char *buf) 539{ 540 struct iio_dev *indio_dev = dev_get_drvdata(dev); 541 struct ad7793_state *st = iio_priv(indio_dev); 542 543 return sprintf(buf, "%d\n", 544 sample_freq_avail[AD7793_MODE_RATE(st->mode)]); 545} 546 547static ssize_t ad7793_write_frequency(struct device *dev, 548 struct device_attribute *attr, 549 const char *buf, 550 size_t len) 551{ 552 struct iio_dev *indio_dev = dev_get_drvdata(dev); 553 struct ad7793_state *st = iio_priv(indio_dev); 554 long lval; 555 int i, ret; 556 557 mutex_lock(&indio_dev->mlock); 558 if (iio_buffer_enabled(indio_dev)) { 559 mutex_unlock(&indio_dev->mlock); 560 return -EBUSY; 561 } 562 mutex_unlock(&indio_dev->mlock); 563 564 ret = strict_strtol(buf, 10, &lval); 565 if (ret) 566 return ret; 567 568 ret = -EINVAL; 569 570 for (i = 0; i < ARRAY_SIZE(sample_freq_avail); i++) 571 if (lval == sample_freq_avail[i]) { 572 mutex_lock(&indio_dev->mlock); 573 st->mode &= ~AD7793_MODE_RATE(-1); 574 st->mode |= AD7793_MODE_RATE(i); 575 ad7793_write_reg(st, AD7793_REG_MODE, 576 sizeof(st->mode), st->mode); 577 mutex_unlock(&indio_dev->mlock); 578 ret = 0; 579 } 580 581 return ret ? ret : len; 582} 583 584static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO, 585 ad7793_read_frequency, 586 ad7793_write_frequency); 587 588static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( 589 "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4"); 590 591static ssize_t ad7793_show_scale_available(struct device *dev, 592 struct device_attribute *attr, char *buf) 593{ 594 struct iio_dev *indio_dev = dev_get_drvdata(dev); 595 struct ad7793_state *st = iio_priv(indio_dev); 596 int i, len = 0; 597 598 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 599 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0], 600 st->scale_avail[i][1]); 601 602 len += sprintf(buf + len, "\n"); 603 604 return len; 605} 606 607static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available, in-in_scale_available, 608 S_IRUGO, ad7793_show_scale_available, NULL, 0); 609 610static struct attribute *ad7793_attributes[] = { 611 &iio_dev_attr_sampling_frequency.dev_attr.attr, 612 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 613 &iio_dev_attr_in_m_in_scale_available.dev_attr.attr, 614 NULL 615}; 616 617static const struct attribute_group ad7793_attribute_group = { 618 .attrs = ad7793_attributes, 619}; 620 621static int ad7793_read_raw(struct iio_dev *indio_dev, 622 struct iio_chan_spec const *chan, 623 int *val, 624 int *val2, 625 long m) 626{ 627 struct ad7793_state *st = iio_priv(indio_dev); 628 int ret, smpl = 0; 629 unsigned long long scale_uv; 630 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR); 631 632 switch (m) { 633 case 0: 634 mutex_lock(&indio_dev->mlock); 635 if (iio_buffer_enabled(indio_dev)) 636 ret = -EBUSY; 637 else 638 ret = ad7793_read(st, chan->address, 639 chan->scan_type.realbits / 8, &smpl); 640 mutex_unlock(&indio_dev->mlock); 641 642 if (ret < 0) 643 return ret; 644 645 *val = (smpl >> chan->scan_type.shift) & 646 ((1 << (chan->scan_type.realbits)) - 1); 647 648 if (!unipolar) 649 *val -= (1 << (chan->scan_type.realbits - 1)); 650 651 return IIO_VAL_INT; 652 653 case IIO_CHAN_INFO_SCALE: 654 switch (chan->type) { 655 case IIO_VOLTAGE: 656 if (chan->differential) { 657 *val = st-> 658 scale_avail[(st->conf >> 8) & 0x7][0]; 659 *val2 = st-> 660 scale_avail[(st->conf >> 8) & 0x7][1]; 661 return IIO_VAL_INT_PLUS_NANO; 662 } else { 663 /* 1170mV / 2^23 * 6 */ 664 scale_uv = (1170ULL * 100000000ULL * 6ULL) 665 >> (chan->scan_type.realbits - 666 (unipolar ? 0 : 1)); 667 } 668 break; 669 case IIO_TEMP: 670 /* Always uses unity gain and internal ref */ 671 scale_uv = (2500ULL * 100000000ULL) 672 >> (chan->scan_type.realbits - 673 (unipolar ? 0 : 1)); 674 break; 675 default: 676 return -EINVAL; 677 } 678 679 *val2 = do_div(scale_uv, 100000000) * 10; 680 *val = scale_uv; 681 682 return IIO_VAL_INT_PLUS_NANO; 683 } 684 return -EINVAL; 685} 686 687static int ad7793_write_raw(struct iio_dev *indio_dev, 688 struct iio_chan_spec const *chan, 689 int val, 690 int val2, 691 long mask) 692{ 693 struct ad7793_state *st = iio_priv(indio_dev); 694 int ret, i; 695 unsigned int tmp; 696 697 mutex_lock(&indio_dev->mlock); 698 if (iio_buffer_enabled(indio_dev)) { 699 mutex_unlock(&indio_dev->mlock); 700 return -EBUSY; 701 } 702 703 switch (mask) { 704 case IIO_CHAN_INFO_SCALE: 705 ret = -EINVAL; 706 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 707 if (val2 == st->scale_avail[i][1]) { 708 tmp = st->conf; 709 st->conf &= ~AD7793_CONF_GAIN(-1); 710 st->conf |= AD7793_CONF_GAIN(i); 711 712 if (tmp != st->conf) { 713 ad7793_write_reg(st, AD7793_REG_CONF, 714 sizeof(st->conf), 715 st->conf); 716 ad7793_calibrate_all(st); 717 } 718 ret = 0; 719 } 720 721 default: 722 ret = -EINVAL; 723 } 724 725 mutex_unlock(&indio_dev->mlock); 726 return ret; 727} 728 729static int ad7793_validate_trigger(struct iio_dev *indio_dev, 730 struct iio_trigger *trig) 731{ 732 if (indio_dev->trig != trig) 733 return -EINVAL; 734 735 return 0; 736} 737 738static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev, 739 struct iio_chan_spec const *chan, 740 long mask) 741{ 742 return IIO_VAL_INT_PLUS_NANO; 743} 744 745static const struct iio_info ad7793_info = { 746 .read_raw = &ad7793_read_raw, 747 .write_raw = &ad7793_write_raw, 748 .write_raw_get_fmt = &ad7793_write_raw_get_fmt, 749 .attrs = &ad7793_attribute_group, 750 .validate_trigger = ad7793_validate_trigger, 751 .driver_module = THIS_MODULE, 752}; 753 754static const struct ad7793_chip_info ad7793_chip_info_tbl[] = { 755 [ID_AD7793] = { 756 .channel[0] = { 757 .type = IIO_VOLTAGE, 758 .differential = 1, 759 .indexed = 1, 760 .channel = 0, 761 .channel2 = 0, 762 .address = AD7793_CH_AIN1P_AIN1M, 763 .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT, 764 .scan_index = 0, 765 .scan_type = IIO_ST('s', 24, 32, 0) 766 }, 767 .channel[1] = { 768 .type = IIO_VOLTAGE, 769 .differential = 1, 770 .indexed = 1, 771 .channel = 1, 772 .channel2 = 1, 773 .address = AD7793_CH_AIN2P_AIN2M, 774 .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT, 775 .scan_index = 1, 776 .scan_type = IIO_ST('s', 24, 32, 0) 777 }, 778 .channel[2] = { 779 .type = IIO_VOLTAGE, 780 .differential = 1, 781 .indexed = 1, 782 .channel = 2, 783 .channel2 = 2, 784 .address = AD7793_CH_AIN3P_AIN3M, 785 .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT, 786 .scan_index = 2, 787 .scan_type = IIO_ST('s', 24, 32, 0) 788 }, 789 .channel[3] = { 790 .type = IIO_VOLTAGE, 791 .differential = 1, 792 .extend_name = "shorted", 793 .indexed = 1, 794 .channel = 2, 795 .channel2 = 2, 796 .address = AD7793_CH_AIN1M_AIN1M, 797 .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT, 798 .scan_index = 2, 799 .scan_type = IIO_ST('s', 24, 32, 0) 800 }, 801 .channel[4] = { 802 .type = IIO_TEMP, 803 .indexed = 1, 804 .channel = 0, 805 .address = AD7793_CH_TEMP, 806 .info_mask = IIO_CHAN_INFO_SCALE_SEPARATE_BIT, 807 .scan_index = 4, 808 .scan_type = IIO_ST('s', 24, 32, 0), 809 }, 810 .channel[5] = { 811 .type = IIO_VOLTAGE, 812 .extend_name = "supply", 813 .indexed = 1, 814 .channel = 4, 815 .address = AD7793_CH_AVDD_MONITOR, 816 .info_mask = IIO_CHAN_INFO_SCALE_SEPARATE_BIT, 817 .scan_index = 5, 818 .scan_type = IIO_ST('s', 24, 32, 0), 819 }, 820 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6), 821 }, 822 [ID_AD7792] = { 823 .channel[0] = { 824 .type = IIO_VOLTAGE, 825 .differential = 1, 826 .indexed = 1, 827 .channel = 0, 828 .channel2 = 0, 829 .address = AD7793_CH_AIN1P_AIN1M, 830 .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT, 831 .scan_index = 0, 832 .scan_type = IIO_ST('s', 16, 32, 0) 833 }, 834 .channel[1] = { 835 .type = IIO_VOLTAGE, 836 .differential = 1, 837 .indexed = 1, 838 .channel = 1, 839 .channel2 = 1, 840 .address = AD7793_CH_AIN2P_AIN2M, 841 .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT, 842 .scan_index = 1, 843 .scan_type = IIO_ST('s', 16, 32, 0) 844 }, 845 .channel[2] = { 846 .type = IIO_VOLTAGE, 847 .differential = 1, 848 .indexed = 1, 849 .channel = 2, 850 .channel2 = 2, 851 .address = AD7793_CH_AIN3P_AIN3M, 852 .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT, 853 .scan_index = 2, 854 .scan_type = IIO_ST('s', 16, 32, 0) 855 }, 856 .channel[3] = { 857 .type = IIO_VOLTAGE, 858 .differential = 1, 859 .extend_name = "shorted", 860 .indexed = 1, 861 .channel = 2, 862 .channel2 = 2, 863 .address = AD7793_CH_AIN1M_AIN1M, 864 .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT, 865 .scan_index = 2, 866 .scan_type = IIO_ST('s', 16, 32, 0) 867 }, 868 .channel[4] = { 869 .type = IIO_TEMP, 870 .indexed = 1, 871 .channel = 0, 872 .address = AD7793_CH_TEMP, 873 .info_mask = IIO_CHAN_INFO_SCALE_SEPARATE_BIT, 874 .scan_index = 4, 875 .scan_type = IIO_ST('s', 16, 32, 0), 876 }, 877 .channel[5] = { 878 .type = IIO_VOLTAGE, 879 .extend_name = "supply", 880 .indexed = 1, 881 .channel = 4, 882 .address = AD7793_CH_AVDD_MONITOR, 883 .info_mask = IIO_CHAN_INFO_SCALE_SEPARATE_BIT, 884 .scan_index = 5, 885 .scan_type = IIO_ST('s', 16, 32, 0), 886 }, 887 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6), 888 }, 889}; 890 891static int __devinit ad7793_probe(struct spi_device *spi) 892{ 893 struct ad7793_platform_data *pdata = spi->dev.platform_data; 894 struct ad7793_state *st; 895 struct iio_dev *indio_dev; 896 int ret, i, voltage_uv = 0; 897 898 if (!pdata) { 899 dev_err(&spi->dev, "no platform data?\n"); 900 return -ENODEV; 901 } 902 903 if (!spi->irq) { 904 dev_err(&spi->dev, "no IRQ?\n"); 905 return -ENODEV; 906 } 907 908 indio_dev = iio_allocate_device(sizeof(*st)); 909 if (indio_dev == NULL) 910 return -ENOMEM; 911 912 st = iio_priv(indio_dev); 913 914 st->reg = regulator_get(&spi->dev, "vcc"); 915 if (!IS_ERR(st->reg)) { 916 ret = regulator_enable(st->reg); 917 if (ret) 918 goto error_put_reg; 919 920 voltage_uv = regulator_get_voltage(st->reg); 921 } 922 923 st->chip_info = 924 &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data]; 925 926 st->pdata = pdata; 927 928 if (pdata && pdata->vref_mv) 929 st->int_vref_mv = pdata->vref_mv; 930 else if (voltage_uv) 931 st->int_vref_mv = voltage_uv / 1000; 932 else 933 st->int_vref_mv = 2500; /* Build-in ref */ 934 935 spi_set_drvdata(spi, indio_dev); 936 st->spi = spi; 937 938 indio_dev->dev.parent = &spi->dev; 939 indio_dev->name = spi_get_device_id(spi)->name; 940 indio_dev->modes = INDIO_DIRECT_MODE; 941 indio_dev->channels = st->chip_info->channel; 942 indio_dev->available_scan_masks = st->available_scan_masks; 943 indio_dev->num_channels = 7; 944 indio_dev->info = &ad7793_info; 945 946 for (i = 0; i < indio_dev->num_channels; i++) { 947 set_bit(i, &st->available_scan_masks[i]); 948 set_bit(indio_dev-> 949 channels[indio_dev->num_channels - 1].scan_index, 950 &st->available_scan_masks[i]); 951 } 952 953 init_waitqueue_head(&st->wq_data_avail); 954 955 ret = ad7793_register_ring_funcs_and_init(indio_dev); 956 if (ret) 957 goto error_disable_reg; 958 959 ret = ad7793_probe_trigger(indio_dev); 960 if (ret) 961 goto error_unreg_ring; 962 963 ret = iio_buffer_register(indio_dev, 964 indio_dev->channels, 965 indio_dev->num_channels); 966 if (ret) 967 goto error_remove_trigger; 968 969 ret = ad7793_setup(st); 970 if (ret) 971 goto error_uninitialize_ring; 972 973 ret = iio_device_register(indio_dev); 974 if (ret) 975 goto error_uninitialize_ring; 976 977 return 0; 978 979error_uninitialize_ring: 980 iio_buffer_unregister(indio_dev); 981error_remove_trigger: 982 ad7793_remove_trigger(indio_dev); 983error_unreg_ring: 984 ad7793_ring_cleanup(indio_dev); 985error_disable_reg: 986 if (!IS_ERR(st->reg)) 987 regulator_disable(st->reg); 988error_put_reg: 989 if (!IS_ERR(st->reg)) 990 regulator_put(st->reg); 991 992 iio_free_device(indio_dev); 993 994 return ret; 995} 996 997static int ad7793_remove(struct spi_device *spi) 998{ 999 struct iio_dev *indio_dev = spi_get_drvdata(spi); 1000 struct ad7793_state *st = iio_priv(indio_dev); 1001 1002 iio_device_unregister(indio_dev); 1003 iio_buffer_unregister(indio_dev); 1004 ad7793_remove_trigger(indio_dev); 1005 ad7793_ring_cleanup(indio_dev); 1006 1007 if (!IS_ERR(st->reg)) { 1008 regulator_disable(st->reg); 1009 regulator_put(st->reg); 1010 } 1011 1012 iio_free_device(indio_dev); 1013 1014 return 0; 1015} 1016 1017static const struct spi_device_id ad7793_id[] = { 1018 {"ad7792", ID_AD7792}, 1019 {"ad7793", ID_AD7793}, 1020 {} 1021}; 1022MODULE_DEVICE_TABLE(spi, ad7793_id); 1023 1024static struct spi_driver ad7793_driver = { 1025 .driver = { 1026 .name = "ad7793", 1027 .owner = THIS_MODULE, 1028 }, 1029 .probe = ad7793_probe, 1030 .remove = __devexit_p(ad7793_remove), 1031 .id_table = ad7793_id, 1032}; 1033module_spi_driver(ad7793_driver); 1034 1035MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); 1036MODULE_DESCRIPTION("Analog Devices AD7792/3 ADC"); 1037MODULE_LICENSE("GPL v2"); 1038