1/* 2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * 20 * File: rf.c 21 * 22 * Purpose: rf function code 23 * 24 * Author: Jerry Chen 25 * 26 * Date: Feb. 19, 2004 27 * 28 * Functions: 29 * IFRFbWriteEmbeded - Embeded write RF register via MAC 30 * 31 * Revision History: 32 * 33 */ 34 35#include "mac.h" 36#include "srom.h" 37#include "rf.h" 38#include "baseband.h" 39 40/*--------------------- Static Definitions -------------------------*/ 41 42//static int msglevel =MSG_LEVEL_INFO; 43 44#define BY_RF2959_REG_LEN 23 //24bits 45#define CB_RF2959_INIT_SEQ 15 46#define SWITCH_CHANNEL_DELAY_RF2959 200 //us 47#define RF2959_PWR_IDX_LEN 32 48 49#define BY_MA2825_REG_LEN 23 //24bit 50#define CB_MA2825_INIT_SEQ 13 51#define SWITCH_CHANNEL_DELAY_MA2825 200 //us 52#define MA2825_PWR_IDX_LEN 31 53 54#define BY_AL2230_REG_LEN 23 //24bit 55#define CB_AL2230_INIT_SEQ 15 56#define SWITCH_CHANNEL_DELAY_AL2230 200 //us 57#define AL2230_PWR_IDX_LEN 64 58 59 60#define BY_UW2451_REG_LEN 23 61#define CB_UW2451_INIT_SEQ 6 62#define SWITCH_CHANNEL_DELAY_UW2451 200 //us 63#define UW2451_PWR_IDX_LEN 25 64 65//{{ RobertYu: 20041118 66#define BY_MA2829_REG_LEN 23 //24bit 67#define CB_MA2829_INIT_SEQ 13 68#define SWITCH_CHANNEL_DELAY_MA2829 200 //us 69#define MA2829_PWR_IDX_LEN 64 70//}} RobertYu 71 72//{{ RobertYu:20050103 73#define BY_AL7230_REG_LEN 23 //24bit 74#define CB_AL7230_INIT_SEQ 16 75#define SWITCH_CHANNEL_DELAY_AL7230 200 //us 76#define AL7230_PWR_IDX_LEN 64 77//}} RobertYu 78 79//{{ RobertYu: 20041210 80#define BY_UW2452_REG_LEN 23 81#define CB_UW2452_INIT_SEQ 5 //RoberYu:20050113, Rev0.2 Programming Guide(remove R3, so 6-->5) 82#define SWITCH_CHANNEL_DELAY_UW2452 100 //us 83#define UW2452_PWR_IDX_LEN 64 84//}} RobertYu 85 86#define BY_VT3226_REG_LEN 23 87#define CB_VT3226_INIT_SEQ 12 88#define SWITCH_CHANNEL_DELAY_VT3226 200 //us 89#define VT3226_PWR_IDX_LEN 16 90 91/*--------------------- Static Classes ----------------------------*/ 92 93/*--------------------- Static Variables --------------------------*/ 94 95 96 97const unsigned long dwAL2230InitTable[CB_AL2230_INIT_SEQ] = { 98 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // 99 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // 100 0x01A00200+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // 101 0x00FFF300+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // 102 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // 103 0x0F4DC500+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // 104 0x0805B600+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // 105 0x0146C700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // 106 0x00068800+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // 107 0x0403B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // 108 0x00DBBA00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // 109 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // 110 0x0BDFFC00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 111 0x00000D00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 112 0x00580F00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW 113 }; 114 115const unsigned long dwAL2230ChannelTable0[CB_MAX_CHANNEL] = { 116 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz 117 0x03F79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz 118 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz 119 0x03E79000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz 120 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz 121 0x03F7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz 122 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz 123 0x03E7A000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz 124 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz 125 0x03F7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz 126 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz 127 0x03E7B000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz 128 0x03F7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz 129 0x03E7C000+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M 130 }; 131 132const unsigned long dwAL2230ChannelTable1[CB_MAX_CHANNEL] = { 133 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz 134 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz 135 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz 136 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz 137 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz 138 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz 139 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz 140 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz 141 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz 142 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz 143 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz 144 0x0B333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz 145 0x03333100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz 146 0x06666100+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW // channel = 14, Tf = 2412M 147 }; 148 149unsigned long dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = { 150 0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 151 0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 152 0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 153 0x04043900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 154 0x04044900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 155 0x04045900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 156 0x04046900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 157 0x04047900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 158 0x04048900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 159 0x04049900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 160 0x0404A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 161 0x0404B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 162 0x0404C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 163 0x0404D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 164 0x0404E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 165 0x0404F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 166 0x04050900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 167 0x04051900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 168 0x04052900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 169 0x04053900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 170 0x04054900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 171 0x04055900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 172 0x04056900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 173 0x04057900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 174 0x04058900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 175 0x04059900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 176 0x0405A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 177 0x0405B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 178 0x0405C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 179 0x0405D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 180 0x0405E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 181 0x0405F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 182 0x04060900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 183 0x04061900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 184 0x04062900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 185 0x04063900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 186 0x04064900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 187 0x04065900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 188 0x04066900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 189 0x04067900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 190 0x04068900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 191 0x04069900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 192 0x0406A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 193 0x0406B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 194 0x0406C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 195 0x0406D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 196 0x0406E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 197 0x0406F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 198 0x04070900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 199 0x04071900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 200 0x04072900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 201 0x04073900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 202 0x04074900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 203 0x04075900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 204 0x04076900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 205 0x04077900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 206 0x04078900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 207 0x04079900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 208 0x0407A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 209 0x0407B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 210 0x0407C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 211 0x0407D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 212 0x0407E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW, 213 0x0407F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW 214 }; 215 216//{{ RobertYu:20050104 217// 40MHz reference frequency 218// Need to Pull PLLON(PE3) low when writing channel registers through 3-wire. 219const unsigned long dwAL7230InitTable[CB_AL7230_INIT_SEQ] = { 220 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a 221 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel1 // Need modify for 11a 222 0x841FF200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 451FE2 223 0x3FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 5FDFA3 224 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11b/g // Need modify for 11a 225 //0x802B4500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B45 226 // RoberYu:20050113, Rev0.47 Regsiter Setting Guide 227 0x802B5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B55 228 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 229 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 860207 230 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 231 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 232 0xE0000A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: E0600A 233 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) 234 //0x00093C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C 235 // RoberYu:20050113, Rev0.47 Regsiter Setting Guide 236 0x000A3C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C 237 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 238 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 239 0x1ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11a: 12BACF 240 }; 241 242const unsigned long dwAL7230InitTableAMode[CB_AL7230_INIT_SEQ] = { 243 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g 244 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Channel184 // Need modify for 11b/g 245 0x451FE200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g 246 0x5FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g 247 0x67F78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // 11a // Need modify for 11b/g 248 0x853F5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g, RoberYu:20050113 249 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 250 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g 251 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 252 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 253 0xE0600A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g 254 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) 255 0x00147C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11b/g 256 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 257 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 258 0x12BACF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // Need modify for 11b/g 259 }; 260 261 262const unsigned long dwAL7230ChannelTable0[CB_MAX_CHANNEL] = { 263 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz 264 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz 265 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz 266 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz 267 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz 268 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz 269 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz 270 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49 271 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49 272 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49 273 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49 274 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49 275 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49 276 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz 277 278 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) 279 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15) 280 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16) 281 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17) 282 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18) 283 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19) 284 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20) 285 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21) 286 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22) 287 288 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, 289 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) 290 291 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23) 292 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24) 293 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25) 294 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26) 295 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27) 296 0x0FF55000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28) 297 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29) 298 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30) 299 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49 300 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32) 301 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33) 302 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34) 303 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35) 304 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36) 305 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37) 306 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38) 307 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39) 308 0x0FF59000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40) 309 310 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41) 311 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42) 312 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43) 313 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44) 314 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45) 315 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46) 316 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47) 317 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48) 318 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49) 319 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50) 320 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51) 321 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52) 322 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53) 323 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54) 324 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55) 325 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56) 326 }; 327 328const unsigned long dwAL7230ChannelTable1[CB_MAX_CHANNEL] = { 329 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz 330 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz 331 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz 332 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz 333 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz 334 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz 335 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz 336 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz 337 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz 338 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz 339 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz 340 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz 341 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz 342 0x06666100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz 343 344 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) 345 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15) 346 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16) 347 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17) 348 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18) 349 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19) 350 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20) 351 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21) 352 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22) 353 354 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, 355 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) 356 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23) 357 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24) 358 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25) 359 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26) 360 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27) 361 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28) 362 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29) 363 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30) 364 0x10000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) 365 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32) 366 0x1AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33) 367 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34) 368 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35) 369 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36) 370 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37) 371 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38) 372 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39) 373 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40) 374 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41) 375 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42) 376 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43) 377 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44) 378 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45) 379 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46) 380 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47) 381 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48) 382 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49) 383 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50) 384 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51) 385 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52) 386 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53) 387 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54) 388 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55) 389 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56) 390 }; 391 392const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = { 393 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz 394 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz 395 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz 396 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz 397 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz 398 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz 399 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz 400 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz 401 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz 402 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz 403 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz 404 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz 405 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz 406 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 14, Tf = 2484MHz 407 408 // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) 409 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 183, Tf = 4915MHz (15) 410 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 184, Tf = 4920MHz (16) 411 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 185, Tf = 4925MHz (17) 412 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 187, Tf = 4935MHz (18) 413 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 188, Tf = 4940MHz (19) 414 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 189, Tf = 4945MHz (20) 415 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 192, Tf = 4960MHz (21) 416 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 196, Tf = 4980MHz (22) 417 418 // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, 419 // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) 420 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 5035MHz (23) 421 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 5040MHz (24) 422 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 5045MHz (25) 423 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 5055MHz (26) 424 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 5060MHz (27) 425 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 16, Tf = 5080MHz (28) 426 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 34, Tf = 5170MHz (29) 427 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 36, Tf = 5180MHz (30) 428 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 38, Tf = 5190MHz (31) 429 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 40, Tf = 5200MHz (32) 430 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 42, Tf = 5210MHz (33) 431 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 44, Tf = 5220MHz (34) 432 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 46, Tf = 5230MHz (35) 433 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 48, Tf = 5240MHz (36) 434 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 52, Tf = 5260MHz (37) 435 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 56, Tf = 5280MHz (38) 436 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 60, Tf = 5300MHz (39) 437 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 64, Tf = 5320MHz (40) 438 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 100, Tf = 5500MHz (41) 439 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 104, Tf = 5520MHz (42) 440 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 108, Tf = 5540MHz (43) 441 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 112, Tf = 5560MHz (44) 442 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 116, Tf = 5580MHz (45) 443 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 120, Tf = 5600MHz (46) 444 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 124, Tf = 5620MHz (47) 445 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 128, Tf = 5640MHz (48) 446 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 132, Tf = 5660MHz (49) 447 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 136, Tf = 5680MHz (50) 448 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 140, Tf = 5700MHz (51) 449 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 149, Tf = 5745MHz (52) 450 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 153, Tf = 5765MHz (53) 451 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 157, Tf = 5785MHz (54) 452 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // channel = 161, Tf = 5805MHz (55) 453 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW // channel = 165, Tf = 5825MHz (56) 454 }; 455//}} RobertYu 456 457 458 459 460/*--------------------- Static Functions --------------------------*/ 461 462 463 464 465/* 466 * Description: AIROHA IFRF chip init function 467 * 468 * Parameters: 469 * In: 470 * dwIoBase - I/O base address 471 * Out: 472 * none 473 * 474 * Return Value: true if succeeded; false if failed. 475 * 476 */ 477bool s_bAL7230Init (unsigned long dwIoBase) 478{ 479 int ii; 480 bool bResult; 481 482 bResult = true; 483 484 //3-wire control for normal mode 485 VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0); 486 487 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | 488 SOFTPWRCTL_TXPEINV)); 489 BBvPowerSaveModeOFF(dwIoBase); //RobertYu:20050106, have DC value for Calibration 490 491 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) 492 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[ii]); 493 494 // PLL On 495 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); 496 497 //Calibration 498 MACvTimer0MicroSDelay(dwIoBase, 150);//150us 499 bResult &= IFRFbWriteEmbeded(dwIoBase, (0x9ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:active, RCK:diable 500 MACvTimer0MicroSDelay(dwIoBase, 30);//30us 501 bResult &= IFRFbWriteEmbeded(dwIoBase, (0x3ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); //TXDCOC:diable, RCK:active 502 MACvTimer0MicroSDelay(dwIoBase, 30);//30us 503 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]); //TXDCOC:diable, RCK:diable 504 505 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | 506 SOFTPWRCTL_SWPE2 | 507 SOFTPWRCTL_SWPECTI | 508 SOFTPWRCTL_TXPEINV)); 509 510 BBvPowerSaveModeON(dwIoBase); // RobertYu:20050106 511 512 // PE1: TX_ON, PE2: RX_ON, PE3: PLLON 513 //3-wire control for power saving mode 514 VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000 515 516 return bResult; 517} 518 519// Need to Pull PLLON low when writing channel registers through 3-wire interface 520bool s_bAL7230SelectChannel (unsigned long dwIoBase, unsigned char byChannel) 521{ 522 bool bResult; 523 524 bResult = true; 525 526 // PLLON Off 527 MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); 528 529 bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL7230ChannelTable0[byChannel-1]); //Reg0 530 bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL7230ChannelTable1[byChannel-1]); //Reg1 531 bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL7230ChannelTable2[byChannel-1]); //Reg4 532 533 // PLLOn On 534 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); 535 536 // Set Channel[7] = 0 to tell H/W channel is changing now. 537 VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); 538 MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL7230); 539 // Set Channel[7] = 1 to tell H/W channel change is done. 540 VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); 541 542 return bResult; 543} 544 545/* 546 * Description: Select channel with UW2452 chip 547 * 548 * Parameters: 549 * In: 550 * dwIoBase - I/O base address 551 * uChannel - Channel number 552 * Out: 553 * none 554 * 555 * Return Value: true if succeeded; false if failed. 556 * 557 */ 558 559 560//{{ RobertYu: 20041210 561/* 562 * Description: UW2452 IFRF chip init function 563 * 564 * Parameters: 565 * In: 566 * dwIoBase - I/O base address 567 * Out: 568 * none 569 * 570 * Return Value: true if succeeded; false if failed. 571 * 572 */ 573 574 575 576//}} RobertYu 577//////////////////////////////////////////////////////////////////////////////// 578 579/* 580 * Description: VT3226 IFRF chip init function 581 * 582 * Parameters: 583 * In: 584 * dwIoBase - I/O base address 585 * Out: 586 * none 587 * 588 * Return Value: true if succeeded; false if failed. 589 * 590 */ 591 592/* 593 * Description: Select channel with VT3226 chip 594 * 595 * Parameters: 596 * In: 597 * dwIoBase - I/O base address 598 * uChannel - Channel number 599 * Out: 600 * none 601 * 602 * Return Value: true if succeeded; false if failed. 603 * 604 */ 605 606 607 608/*--------------------- Export Variables --------------------------*/ 609 610/*--------------------- Export Functions --------------------------*/ 611 612/* 613 * Description: Write to IF/RF, by embeded programming 614 * 615 * Parameters: 616 * In: 617 * dwIoBase - I/O base address 618 * dwData - data to write 619 * Out: 620 * none 621 * 622 * Return Value: true if succeeded; false if failed. 623 * 624 */ 625bool IFRFbWriteEmbeded (unsigned long dwIoBase, unsigned long dwData) 626{ 627 unsigned short ww; 628 unsigned long dwValue; 629 630 VNSvOutPortD(dwIoBase + MAC_REG_IFREGCTL, dwData); 631 632 // W_MAX_TIMEOUT is the timeout period 633 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 634 VNSvInPortD(dwIoBase + MAC_REG_IFREGCTL, &dwValue); 635 if (dwValue & IFREGCTL_DONE) 636 break; 637 } 638 639 if (ww == W_MAX_TIMEOUT) { 640// DBG_PORT80_ALWAYS(0x32); 641 return false; 642 } 643 return true; 644} 645 646 647 648/* 649 * Description: RFMD RF2959 IFRF chip init function 650 * 651 * Parameters: 652 * In: 653 * dwIoBase - I/O base address 654 * Out: 655 * none 656 * 657 * Return Value: true if succeeded; false if failed. 658 * 659 */ 660 661/* 662 * Description: Select channel with RFMD 2959 chip 663 * 664 * Parameters: 665 * In: 666 * dwIoBase - I/O base address 667 * uChannel - Channel number 668 * Out: 669 * none 670 * 671 * Return Value: true if succeeded; false if failed. 672 * 673 */ 674 675/* 676 * Description: AIROHA IFRF chip init function 677 * 678 * Parameters: 679 * In: 680 * dwIoBase - I/O base address 681 * Out: 682 * none 683 * 684 * Return Value: true if succeeded; false if failed. 685 * 686 */ 687bool RFbAL2230Init (unsigned long dwIoBase) 688{ 689 int ii; 690 bool bResult; 691 692 bResult = true; 693 694 //3-wire control for normal mode 695 VNSvOutPortB(dwIoBase + MAC_REG_SOFTPWRCTL, 0); 696 697 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | 698 SOFTPWRCTL_TXPEINV)); 699//2008-8-21 chester <add> 700 // PLL Off 701 702 MACvWordRegBitsOff(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); 703 704 705 706 //patch abnormal AL2230 frequency output 707//2008-8-21 chester <add> 708 IFRFbWriteEmbeded(dwIoBase, (0x07168700+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); 709 710 711 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) 712 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL2230InitTable[ii]); 713//2008-8-21 chester <add> 714MACvTimer0MicroSDelay(dwIoBase, 30); //delay 30 us 715 716 // PLL On 717 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); 718 719 MACvTimer0MicroSDelay(dwIoBase, 150);//150us 720 bResult &= IFRFbWriteEmbeded(dwIoBase, (0x00d80f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); 721 MACvTimer0MicroSDelay(dwIoBase, 30);//30us 722 bResult &= IFRFbWriteEmbeded(dwIoBase, (0x00780f00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW)); 723 MACvTimer0MicroSDelay(dwIoBase, 30);//30us 724 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]); 725 726 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | 727 SOFTPWRCTL_SWPE2 | 728 SOFTPWRCTL_SWPECTI | 729 SOFTPWRCTL_TXPEINV)); 730 731 //3-wire control for power saving mode 732 VNSvOutPortB(dwIoBase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); //1100 0000 733 734 return bResult; 735} 736 737bool RFbAL2230SelectChannel (unsigned long dwIoBase, unsigned char byChannel) 738{ 739 bool bResult; 740 741 bResult = true; 742 743 bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL2230ChannelTable0[byChannel-1]); 744 bResult &= IFRFbWriteEmbeded (dwIoBase, dwAL2230ChannelTable1[byChannel-1]); 745 746 // Set Channel[7] = 0 to tell H/W channel is changing now. 747 VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel & 0x7F)); 748 MACvTimer0MicroSDelay(dwIoBase, SWITCH_CHANNEL_DELAY_AL2230); 749 // Set Channel[7] = 1 to tell H/W channel change is done. 750 VNSvOutPortB(dwIoBase + MAC_REG_CHANNEL, (byChannel | 0x80)); 751 752 return bResult; 753} 754 755/* 756 * Description: UW2451 IFRF chip init function 757 * 758 * Parameters: 759 * In: 760 * dwIoBase - I/O base address 761 * Out: 762 * none 763 * 764 * Return Value: true if succeeded; false if failed. 765 * 766 */ 767 768 769/* 770 * Description: Select channel with UW2451 chip 771 * 772 * Parameters: 773 * In: 774 * dwIoBase - I/O base address 775 * uChannel - Channel number 776 * Out: 777 * none 778 * 779 * Return Value: true if succeeded; false if failed. 780 * 781 */ 782 783/* 784 * Description: Set sleep mode to UW2451 chip 785 * 786 * Parameters: 787 * In: 788 * dwIoBase - I/O base address 789 * uChannel - Channel number 790 * Out: 791 * none 792 * 793 * Return Value: true if succeeded; false if failed. 794 * 795 */ 796 797/* 798 * Description: RF init function 799 * 800 * Parameters: 801 * In: 802 * byBBType 803 * byRFType 804 * Out: 805 * none 806 * 807 * Return Value: true if succeeded; false if failed. 808 * 809 */ 810bool RFbInit ( 811 PSDevice pDevice 812 ) 813{ 814bool bResult = true; 815 switch (pDevice->byRFType) { 816 case RF_AIROHA : 817 case RF_AL2230S: 818 pDevice->byMaxPwrLevel = AL2230_PWR_IDX_LEN; 819 bResult = RFbAL2230Init(pDevice->PortOffset); 820 break; 821 case RF_AIROHA7230 : 822 pDevice->byMaxPwrLevel = AL7230_PWR_IDX_LEN; 823 bResult = s_bAL7230Init(pDevice->PortOffset); 824 break; 825 case RF_NOTHING : 826 bResult = true; 827 break; 828 default : 829 bResult = false; 830 break; 831 } 832 return bResult; 833} 834 835/* 836 * Description: RF ShutDown function 837 * 838 * Parameters: 839 * In: 840 * byBBType 841 * byRFType 842 * Out: 843 * none 844 * 845 * Return Value: true if succeeded; false if failed. 846 * 847 */ 848bool RFbShutDown ( 849 PSDevice pDevice 850 ) 851{ 852bool bResult = true; 853 854 switch (pDevice->byRFType) { 855 case RF_AIROHA7230 : 856 bResult = IFRFbWriteEmbeded (pDevice->PortOffset, 0x1ABAEF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW); 857 break; 858 default : 859 bResult = true; 860 break; 861 } 862 return bResult; 863} 864 865/* 866 * Description: Select channel 867 * 868 * Parameters: 869 * In: 870 * byRFType 871 * byChannel - Channel number 872 * Out: 873 * none 874 * 875 * Return Value: true if succeeded; false if failed. 876 * 877 */ 878bool RFbSelectChannel (unsigned long dwIoBase, unsigned char byRFType, unsigned char byChannel) 879{ 880bool bResult = true; 881 switch (byRFType) { 882 883 case RF_AIROHA : 884 case RF_AL2230S: 885 bResult = RFbAL2230SelectChannel(dwIoBase, byChannel); 886 break; 887 //{{ RobertYu: 20050104 888 case RF_AIROHA7230 : 889 bResult = s_bAL7230SelectChannel(dwIoBase, byChannel); 890 break; 891 //}} RobertYu 892 case RF_NOTHING : 893 bResult = true; 894 break; 895 default: 896 bResult = false; 897 break; 898 } 899 return bResult; 900} 901 902/* 903 * Description: Write WakeProgSyn 904 * 905 * Parameters: 906 * In: 907 * dwIoBase - I/O base address 908 * uChannel - channel number 909 * bySleepCnt - SleepProgSyn count 910 * 911 * Return Value: None. 912 * 913 */ 914bool RFvWriteWakeProgSyn (unsigned long dwIoBase, unsigned char byRFType, unsigned int uChannel) 915{ 916 int ii; 917 unsigned char byInitCount = 0; 918 unsigned char bySleepCount = 0; 919 920 VNSvOutPortW(dwIoBase + MAC_REG_MISCFFNDEX, 0); 921 switch (byRFType) { 922 case RF_AIROHA: 923 case RF_AL2230S: 924 925 if (uChannel > CB_MAX_CHANNEL_24G) 926 return false; 927 928 byInitCount = CB_AL2230_INIT_SEQ + 2; // Init Reg + Channel Reg (2) 929 bySleepCount = 0; 930 if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) { 931 return false; 932 } 933 934 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++ ) { 935 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]); 936 } 937 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]); 938 ii ++; 939 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]); 940 break; 941 942 //{{ RobertYu: 20050104 943 // Need to check, PLLON need to be low for channel setting 944 case RF_AIROHA7230: 945 byInitCount = CB_AL7230_INIT_SEQ + 3; // Init Reg + Channel Reg (3) 946 bySleepCount = 0; 947 if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount)) { 948 return false; 949 } 950 951 if (uChannel <= CB_MAX_CHANNEL_24G) 952 { 953 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++ ) { 954 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]); 955 } 956 } 957 else 958 { 959 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++ ) { 960 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]); 961 } 962 } 963 964 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]); 965 ii ++; 966 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel-1]); 967 ii ++; 968 MACvSetMISCFifo(dwIoBase, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel-1]); 969 break; 970 //}} RobertYu 971 972 case RF_NOTHING : 973 return true; 974 break; 975 976 default: 977 return false; 978 break; 979 } 980 981 MACvSetMISCFifo(dwIoBase, MISCFIFO_SYNINFO_IDX, (unsigned long )MAKEWORD(bySleepCount, byInitCount)); 982 983 return true; 984} 985 986/* 987 * Description: Set Tx power 988 * 989 * Parameters: 990 * In: 991 * dwIoBase - I/O base address 992 * dwRFPowerTable - RF Tx Power Setting 993 * Out: 994 * none 995 * 996 * Return Value: true if succeeded; false if failed. 997 * 998 */ 999bool RFbSetPower ( 1000 PSDevice pDevice, 1001 unsigned int uRATE, 1002 unsigned int uCH 1003 ) 1004{ 1005bool bResult = true; 1006unsigned char byPwr = 0; 1007unsigned char byDec = 0; 1008unsigned char byPwrdBm = 0; 1009 1010 if (pDevice->dwDiagRefCount != 0) { 1011 return true; 1012 } 1013 if ((uCH < 1) || (uCH > CB_MAX_CHANNEL)) { 1014 return false; 1015 } 1016 1017 switch (uRATE) { 1018 case RATE_1M: 1019 case RATE_2M: 1020 case RATE_5M: 1021 case RATE_11M: 1022 byPwr = pDevice->abyCCKPwrTbl[uCH]; 1023 byPwrdBm = pDevice->abyCCKDefaultPwr[uCH]; 1024//PLICE_DEBUG-> 1025 //byPwr+=5; 1026//PLICE_DEBUG <- 1027 1028//printk("Rate <11:byPwr is %d\n",byPwr); 1029 break; 1030 case RATE_6M: 1031 case RATE_9M: 1032 case RATE_18M: 1033 byPwr = pDevice->abyOFDMPwrTbl[uCH]; 1034 if (pDevice->byRFType == RF_UW2452) { 1035 byDec = byPwr + 14; 1036 } else { 1037 byDec = byPwr + 10; 1038 } 1039 if (byDec >= pDevice->byMaxPwrLevel) { 1040 byDec = pDevice->byMaxPwrLevel-1; 1041 } 1042 if (pDevice->byRFType == RF_UW2452) { 1043 byPwrdBm = byDec - byPwr; 1044 byPwrdBm /= 3; 1045 } else { 1046 byPwrdBm = byDec - byPwr; 1047 byPwrdBm >>= 1; 1048 } 1049 byPwrdBm += pDevice->abyOFDMDefaultPwr[uCH]; 1050 byPwr = byDec; 1051//PLICE_DEBUG-> 1052 //byPwr+=5; 1053//PLICE_DEBUG<- 1054 1055//printk("Rate <24:byPwr is %d\n",byPwr); 1056 break; 1057 case RATE_24M: 1058 case RATE_36M: 1059 case RATE_48M: 1060 case RATE_54M: 1061 byPwr = pDevice->abyOFDMPwrTbl[uCH]; 1062 byPwrdBm = pDevice->abyOFDMDefaultPwr[uCH]; 1063//PLICE_DEBUG-> 1064 //byPwr+=5; 1065//PLICE_DEBUG<- 1066//printk("Rate < 54:byPwr is %d\n",byPwr); 1067 break; 1068 } 1069 1070#if 0 1071 1072 // 802.11h TPC 1073 if (pDevice->bLinkPass == true) { 1074 // do not over local constraint 1075 if (byPwrdBm > pDevice->abyLocalPwr[uCH]) { 1076 pDevice->byCurPwrdBm = pDevice->abyLocalPwr[uCH]; 1077 byDec = byPwrdBm - pDevice->abyLocalPwr[uCH]; 1078 if (pDevice->byRFType == RF_UW2452) { 1079 byDec *= 3; 1080 } else { 1081 byDec <<= 1; 1082 } 1083 if (byPwr > byDec) { 1084 byPwr -= byDec; 1085 } else { 1086 byPwr = 0; 1087 } 1088 } else { 1089 pDevice->byCurPwrdBm = byPwrdBm; 1090 } 1091 } else { 1092 // do not over regulatory constraint 1093 if (byPwrdBm > pDevice->abyRegPwr[uCH]) { 1094 pDevice->byCurPwrdBm = pDevice->abyRegPwr[uCH]; 1095 byDec = byPwrdBm - pDevice->abyRegPwr[uCH]; 1096 if (pDevice->byRFType == RF_UW2452) { 1097 byDec *= 3; 1098 } else { 1099 byDec <<= 1; 1100 } 1101 if (byPwr > byDec) { 1102 byPwr -= byDec; 1103 } else { 1104 byPwr = 0; 1105 } 1106 } else { 1107 pDevice->byCurPwrdBm = byPwrdBm; 1108 } 1109 } 1110#endif 1111 1112// if (pDevice->byLocalID <= REV_ID_VT3253_B1) { 1113 if (pDevice->byCurPwr == byPwr) { 1114 return true; 1115 } 1116 bResult = RFbRawSetPower(pDevice, byPwr, uRATE); 1117// } 1118 if (bResult == true) { 1119 pDevice->byCurPwr = byPwr; 1120 } 1121 return bResult; 1122} 1123 1124/* 1125 * Description: Set Tx power 1126 * 1127 * Parameters: 1128 * In: 1129 * dwIoBase - I/O base address 1130 * dwRFPowerTable - RF Tx Power Setting 1131 * Out: 1132 * none 1133 * 1134 * Return Value: true if succeeded; false if failed. 1135 * 1136 */ 1137 1138bool RFbRawSetPower ( 1139 PSDevice pDevice, 1140 unsigned char byPwr, 1141 unsigned int uRATE 1142 ) 1143{ 1144bool bResult = true; 1145unsigned long dwMax7230Pwr = 0; 1146 1147 if (byPwr >= pDevice->byMaxPwrLevel) { 1148 return (false); 1149 } 1150 switch (pDevice->byRFType) { 1151 1152 case RF_AIROHA : 1153 bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]); 1154 if (uRATE <= RATE_11M) { 1155 bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); 1156 } else { 1157 bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); 1158 } 1159 break; 1160 1161 1162 case RF_AL2230S : 1163 bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, dwAL2230PowerTable[byPwr]); 1164 if (uRATE <= RATE_11M) { 1165 bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); 1166 bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); 1167 }else { 1168 bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); 1169 bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW); 1170 } 1171 1172 break; 1173 1174 case RF_AIROHA7230: 1175 // 0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value 1176 dwMax7230Pwr = 0x080C0B00 | ( (byPwr) << 12 ) | 1177 (BY_AL7230_REG_LEN << 3 ) | IFREGCTL_REGW; 1178 1179 bResult &= IFRFbWriteEmbeded(pDevice->PortOffset, dwMax7230Pwr); 1180 break; 1181 1182 1183 default : 1184 break; 1185 } 1186 return bResult; 1187} 1188 1189/*+ 1190 * 1191 * Routine Description: 1192 * Translate RSSI to dBm 1193 * 1194 * Parameters: 1195 * In: 1196 * pDevice - The adapter to be translated 1197 * byCurrRSSI - RSSI to be translated 1198 * Out: 1199 * pdwdbm - Translated dbm number 1200 * 1201 * Return Value: none 1202 * 1203-*/ 1204void 1205RFvRSSITodBm ( 1206 PSDevice pDevice, 1207 unsigned char byCurrRSSI, 1208 long * pldBm 1209 ) 1210{ 1211 unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03); 1212 long b = (byCurrRSSI & 0x3F); 1213 long a = 0; 1214 unsigned char abyAIROHARF[4] = {0, 18, 0, 40}; 1215 1216 switch (pDevice->byRFType) { 1217 case RF_AIROHA: 1218 case RF_AL2230S: 1219 case RF_AIROHA7230: //RobertYu: 20040104 1220 a = abyAIROHARF[byIdx]; 1221 break; 1222 default: 1223 break; 1224 } 1225 1226 *pldBm = -1 * (a + b * 2); 1227} 1228 1229//////////////////////////////////////////////////////////////////////////////// 1230//{{ RobertYu: 20050104 1231 1232 1233// Post processing for the 11b/g and 11a. 1234// for save time on changing Reg2,3,5,7,10,12,15 1235bool RFbAL7230SelectChannelPostProcess (unsigned long dwIoBase, unsigned char byOldChannel, unsigned char byNewChannel) 1236{ 1237 bool bResult; 1238 1239 bResult = true; 1240 1241 // if change between 11 b/g and 11a need to update the following register 1242 // Channel Index 1~14 1243 1244 if( (byOldChannel <= CB_MAX_CHANNEL_24G) && (byNewChannel > CB_MAX_CHANNEL_24G) ) 1245 { 1246 // Change from 2.4G to 5G 1247 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[2]); //Reg2 1248 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[3]); //Reg3 1249 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[5]); //Reg5 1250 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[7]); //Reg7 1251 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[10]);//Reg10 1252 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[12]);//Reg12 1253 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTableAMode[15]);//Reg15 1254 } 1255 else if( (byOldChannel > CB_MAX_CHANNEL_24G) && (byNewChannel <= CB_MAX_CHANNEL_24G) ) 1256 { 1257 // change from 5G to 2.4G 1258 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[2]); //Reg2 1259 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[3]); //Reg3 1260 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[5]); //Reg5 1261 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[7]); //Reg7 1262 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[10]);//Reg10 1263 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[12]);//Reg12 1264 bResult &= IFRFbWriteEmbeded(dwIoBase, dwAL7230InitTable[15]);//Reg15 1265 } 1266 1267 return bResult; 1268} 1269 1270 1271//}} RobertYu 1272//////////////////////////////////////////////////////////////////////////////// 1273 1274