1/* sunsab.h: Register Definitions for the Siemens SAB82532 DUSCC 2 * 3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) 4 */ 5 6#ifndef _SUNSAB_H 7#define _SUNSAB_H 8 9struct sab82532_async_rd_regs { 10 u8 rfifo[0x20]; /* Receive FIFO */ 11 u8 star; /* Status Register */ 12 u8 __pad1; 13 u8 mode; /* Mode Register */ 14 u8 timr; /* Timer Register */ 15 u8 xon; /* XON Character */ 16 u8 xoff; /* XOFF Character */ 17 u8 tcr; /* Termination Character Register */ 18 u8 dafo; /* Data Format */ 19 u8 rfc; /* RFIFO Control Register */ 20 u8 __pad2; 21 u8 rbcl; /* Receive Byte Count Low */ 22 u8 rbch; /* Receive Byte Count High */ 23 u8 ccr0; /* Channel Configuration Register 0 */ 24 u8 ccr1; /* Channel Configuration Register 1 */ 25 u8 ccr2; /* Channel Configuration Register 2 */ 26 u8 ccr3; /* Channel Configuration Register 3 */ 27 u8 __pad3[4]; 28 u8 vstr; /* Version Status Register */ 29 u8 __pad4[3]; 30 u8 gis; /* Global Interrupt Status */ 31 u8 ipc; /* Interrupt Port Configuration */ 32 u8 isr0; /* Interrupt Status 0 */ 33 u8 isr1; /* Interrupt Status 1 */ 34 u8 pvr; /* Port Value Register */ 35 u8 pis; /* Port Interrupt Status */ 36 u8 pcr; /* Port Configuration Register */ 37 u8 ccr4; /* Channel Configuration Register 4 */ 38}; 39 40struct sab82532_async_wr_regs { 41 u8 xfifo[0x20]; /* Transmit FIFO */ 42 u8 cmdr; /* Command Register */ 43 u8 __pad1; 44 u8 mode; 45 u8 timr; 46 u8 xon; 47 u8 xoff; 48 u8 tcr; 49 u8 dafo; 50 u8 rfc; 51 u8 __pad2; 52 u8 xbcl; /* Transmit Byte Count Low */ 53 u8 xbch; /* Transmit Byte Count High */ 54 u8 ccr0; 55 u8 ccr1; 56 u8 ccr2; 57 u8 ccr3; 58 u8 tsax; /* Time-Slot Assignment Reg. Transmit */ 59 u8 tsar; /* Time-Slot Assignment Reg. Receive */ 60 u8 xccr; /* Transmit Channel Capacity Register */ 61 u8 rccr; /* Receive Channel Capacity Register */ 62 u8 bgr; /* Baud Rate Generator Register */ 63 u8 tic; /* Transmit Immediate Character */ 64 u8 mxn; /* Mask XON Character */ 65 u8 mxf; /* Mask XOFF Character */ 66 u8 iva; /* Interrupt Vector Address */ 67 u8 ipc; 68 u8 imr0; /* Interrupt Mask Register 0 */ 69 u8 imr1; /* Interrupt Mask Register 1 */ 70 u8 pvr; 71 u8 pim; /* Port Interrupt Mask */ 72 u8 pcr; 73 u8 ccr4; 74}; 75 76struct sab82532_async_rw_regs { /* Read/Write registers */ 77 u8 __pad1[0x20]; 78 u8 __pad2; 79 u8 __pad3; 80 u8 mode; 81 u8 timr; 82 u8 xon; 83 u8 xoff; 84 u8 tcr; 85 u8 dafo; 86 u8 rfc; 87 u8 __pad4; 88 u8 __pad5; 89 u8 __pad6; 90 u8 ccr0; 91 u8 ccr1; 92 u8 ccr2; 93 u8 ccr3; 94 u8 __pad7; 95 u8 __pad8; 96 u8 __pad9; 97 u8 __pad10; 98 u8 __pad11; 99 u8 __pad12; 100 u8 __pad13; 101 u8 __pad14; 102 u8 __pad15; 103 u8 ipc; 104 u8 __pad16; 105 u8 __pad17; 106 u8 pvr; 107 u8 __pad18; 108 u8 pcr; 109 u8 ccr4; 110}; 111 112union sab82532_async_regs { 113 __volatile__ struct sab82532_async_rd_regs r; 114 __volatile__ struct sab82532_async_wr_regs w; 115 __volatile__ struct sab82532_async_rw_regs rw; 116}; 117 118union sab82532_irq_status { 119 unsigned short stat; 120 struct { 121 unsigned char isr0; 122 unsigned char isr1; 123 } sreg; 124}; 125 126/* irqflags bits */ 127#define SAB82532_ALLS 0x00000001 128#define SAB82532_XPR 0x00000002 129#define SAB82532_REGS_PENDING 0x00000004 130 131/* RFIFO Status Byte */ 132#define SAB82532_RSTAT_PE 0x80 133#define SAB82532_RSTAT_FE 0x40 134#define SAB82532_RSTAT_PARITY 0x01 135 136/* Status Register (STAR) */ 137#define SAB82532_STAR_XDOV 0x80 138#define SAB82532_STAR_XFW 0x40 139#define SAB82532_STAR_RFNE 0x20 140#define SAB82532_STAR_FCS 0x10 141#define SAB82532_STAR_TEC 0x08 142#define SAB82532_STAR_CEC 0x04 143#define SAB82532_STAR_CTS 0x02 144 145/* Command Register (CMDR) */ 146#define SAB82532_CMDR_RMC 0x80 147#define SAB82532_CMDR_RRES 0x40 148#define SAB82532_CMDR_RFRD 0x20 149#define SAB82532_CMDR_STI 0x10 150#define SAB82532_CMDR_XF 0x08 151#define SAB82532_CMDR_XRES 0x01 152 153/* Mode Register (MODE) */ 154#define SAB82532_MODE_FRTS 0x40 155#define SAB82532_MODE_FCTS 0x20 156#define SAB82532_MODE_FLON 0x10 157#define SAB82532_MODE_RAC 0x08 158#define SAB82532_MODE_RTS 0x04 159#define SAB82532_MODE_TRS 0x02 160#define SAB82532_MODE_TLP 0x01 161 162/* Timer Register (TIMR) */ 163#define SAB82532_TIMR_CNT_MASK 0xe0 164#define SAB82532_TIMR_VALUE_MASK 0x1f 165 166/* Data Format (DAFO) */ 167#define SAB82532_DAFO_XBRK 0x40 168#define SAB82532_DAFO_STOP 0x20 169#define SAB82532_DAFO_PAR_SPACE 0x00 170#define SAB82532_DAFO_PAR_ODD 0x08 171#define SAB82532_DAFO_PAR_EVEN 0x10 172#define SAB82532_DAFO_PAR_MARK 0x18 173#define SAB82532_DAFO_PARE 0x04 174#define SAB82532_DAFO_CHL8 0x00 175#define SAB82532_DAFO_CHL7 0x01 176#define SAB82532_DAFO_CHL6 0x02 177#define SAB82532_DAFO_CHL5 0x03 178 179/* RFIFO Control Register (RFC) */ 180#define SAB82532_RFC_DPS 0x40 181#define SAB82532_RFC_DXS 0x20 182#define SAB82532_RFC_RFDF 0x10 183#define SAB82532_RFC_RFTH_1 0x00 184#define SAB82532_RFC_RFTH_4 0x04 185#define SAB82532_RFC_RFTH_16 0x08 186#define SAB82532_RFC_RFTH_32 0x0c 187#define SAB82532_RFC_TCDE 0x01 188 189/* Received Byte Count High (RBCH) */ 190#define SAB82532_RBCH_DMA 0x80 191#define SAB82532_RBCH_CAS 0x20 192 193/* Transmit Byte Count High (XBCH) */ 194#define SAB82532_XBCH_DMA 0x80 195#define SAB82532_XBCH_CAS 0x20 196#define SAB82532_XBCH_XC 0x10 197 198/* Channel Configuration Register 0 (CCR0) */ 199#define SAB82532_CCR0_PU 0x80 200#define SAB82532_CCR0_MCE 0x40 201#define SAB82532_CCR0_SC_NRZ 0x00 202#define SAB82532_CCR0_SC_NRZI 0x08 203#define SAB82532_CCR0_SC_FM0 0x10 204#define SAB82532_CCR0_SC_FM1 0x14 205#define SAB82532_CCR0_SC_MANCH 0x18 206#define SAB82532_CCR0_SM_HDLC 0x00 207#define SAB82532_CCR0_SM_SDLC_LOOP 0x01 208#define SAB82532_CCR0_SM_BISYNC 0x02 209#define SAB82532_CCR0_SM_ASYNC 0x03 210 211/* Channel Configuration Register 1 (CCR1) */ 212#define SAB82532_CCR1_ODS 0x10 213#define SAB82532_CCR1_BCR 0x08 214#define SAB82532_CCR1_CM_MASK 0x07 215 216/* Channel Configuration Register 2 (CCR2) */ 217#define SAB82532_CCR2_SOC1 0x80 218#define SAB82532_CCR2_SOC0 0x40 219#define SAB82532_CCR2_BR9 0x80 220#define SAB82532_CCR2_BR8 0x40 221#define SAB82532_CCR2_BDF 0x20 222#define SAB82532_CCR2_SSEL 0x10 223#define SAB82532_CCR2_XCS0 0x20 224#define SAB82532_CCR2_RCS0 0x10 225#define SAB82532_CCR2_TOE 0x08 226#define SAB82532_CCR2_RWX 0x04 227#define SAB82532_CCR2_DIV 0x01 228 229/* Channel Configuration Register 3 (CCR3) */ 230#define SAB82532_CCR3_PSD 0x01 231 232/* Time Slot Assignment Register Transmit (TSAX) */ 233#define SAB82532_TSAX_TSNX_MASK 0xfc 234#define SAB82532_TSAX_XCS2 0x02 /* see also CCR2 */ 235#define SAB82532_TSAX_XCS1 0x01 236 237/* Time Slot Assignment Register Receive (TSAR) */ 238#define SAB82532_TSAR_TSNR_MASK 0xfc 239#define SAB82532_TSAR_RCS2 0x02 /* see also CCR2 */ 240#define SAB82532_TSAR_RCS1 0x01 241 242/* Version Status Register (VSTR) */ 243#define SAB82532_VSTR_CD 0x80 244#define SAB82532_VSTR_DPLA 0x40 245#define SAB82532_VSTR_VN_MASK 0x0f 246#define SAB82532_VSTR_VN_1 0x00 247#define SAB82532_VSTR_VN_2 0x01 248#define SAB82532_VSTR_VN_3_2 0x02 249 250/* Global Interrupt Status Register (GIS) */ 251#define SAB82532_GIS_PI 0x80 252#define SAB82532_GIS_ISA1 0x08 253#define SAB82532_GIS_ISA0 0x04 254#define SAB82532_GIS_ISB1 0x02 255#define SAB82532_GIS_ISB0 0x01 256 257/* Interrupt Vector Address (IVA) */ 258#define SAB82532_IVA_MASK 0xf1 259 260/* Interrupt Port Configuration (IPC) */ 261#define SAB82532_IPC_VIS 0x80 262#define SAB82532_IPC_SLA1 0x10 263#define SAB82532_IPC_SLA0 0x08 264#define SAB82532_IPC_CASM 0x04 265#define SAB82532_IPC_IC_OPEN_DRAIN 0x00 266#define SAB82532_IPC_IC_ACT_LOW 0x01 267#define SAB82532_IPC_IC_ACT_HIGH 0x03 268 269/* Interrupt Status Register 0 (ISR0) */ 270#define SAB82532_ISR0_TCD 0x80 271#define SAB82532_ISR0_TIME 0x40 272#define SAB82532_ISR0_PERR 0x20 273#define SAB82532_ISR0_FERR 0x10 274#define SAB82532_ISR0_PLLA 0x08 275#define SAB82532_ISR0_CDSC 0x04 276#define SAB82532_ISR0_RFO 0x02 277#define SAB82532_ISR0_RPF 0x01 278 279/* Interrupt Status Register 1 (ISR1) */ 280#define SAB82532_ISR1_BRK 0x80 281#define SAB82532_ISR1_BRKT 0x40 282#define SAB82532_ISR1_ALLS 0x20 283#define SAB82532_ISR1_XOFF 0x10 284#define SAB82532_ISR1_TIN 0x08 285#define SAB82532_ISR1_CSC 0x04 286#define SAB82532_ISR1_XON 0x02 287#define SAB82532_ISR1_XPR 0x01 288 289/* Interrupt Mask Register 0 (IMR0) */ 290#define SAB82532_IMR0_TCD 0x80 291#define SAB82532_IMR0_TIME 0x40 292#define SAB82532_IMR0_PERR 0x20 293#define SAB82532_IMR0_FERR 0x10 294#define SAB82532_IMR0_PLLA 0x08 295#define SAB82532_IMR0_CDSC 0x04 296#define SAB82532_IMR0_RFO 0x02 297#define SAB82532_IMR0_RPF 0x01 298 299/* Interrupt Mask Register 1 (IMR1) */ 300#define SAB82532_IMR1_BRK 0x80 301#define SAB82532_IMR1_BRKT 0x40 302#define SAB82532_IMR1_ALLS 0x20 303#define SAB82532_IMR1_XOFF 0x10 304#define SAB82532_IMR1_TIN 0x08 305#define SAB82532_IMR1_CSC 0x04 306#define SAB82532_IMR1_XON 0x02 307#define SAB82532_IMR1_XPR 0x01 308 309/* Port Interrupt Status Register (PIS) */ 310#define SAB82532_PIS_SYNC_B 0x08 311#define SAB82532_PIS_DTR_B 0x04 312#define SAB82532_PIS_DTR_A 0x02 313#define SAB82532_PIS_SYNC_A 0x01 314 315/* Channel Configuration Register 4 (CCR4) */ 316#define SAB82532_CCR4_MCK4 0x80 317#define SAB82532_CCR4_EBRG 0x40 318#define SAB82532_CCR4_TST1 0x20 319#define SAB82532_CCR4_ICD 0x10 320 321 322#endif /* !(_SUNSAB_H) */ 323