1/* 2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs 3 * 4 * Copyright (C) 2010 Google, Inc. 5 * Copyright (C) 2009 NVIDIA Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 */ 18 19#include <linux/clk.h> 20#include <linux/platform_device.h> 21#include <linux/platform_data/tegra_usb.h> 22#include <linux/irq.h> 23#include <linux/usb/otg.h> 24#include <linux/gpio.h> 25#include <linux/of.h> 26#include <linux/of_gpio.h> 27#include <linux/pm_runtime.h> 28 29#include <mach/usb_phy.h> 30#include <mach/iomap.h> 31 32#define TEGRA_USB_DMA_ALIGN 32 33 34struct tegra_ehci_hcd { 35 struct ehci_hcd *ehci; 36 struct tegra_usb_phy *phy; 37 struct clk *clk; 38 struct clk *emc_clk; 39 struct usb_phy *transceiver; 40 int host_resumed; 41 int port_resuming; 42 enum tegra_usb_phy_port_speed port_speed; 43}; 44 45static void tegra_ehci_power_up(struct usb_hcd *hcd) 46{ 47 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 48 49 clk_enable(tegra->emc_clk); 50 clk_enable(tegra->clk); 51 tegra_usb_phy_power_on(tegra->phy); 52 tegra->host_resumed = 1; 53} 54 55static void tegra_ehci_power_down(struct usb_hcd *hcd) 56{ 57 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 58 59 tegra->host_resumed = 0; 60 tegra_usb_phy_power_off(tegra->phy); 61 clk_disable(tegra->clk); 62 clk_disable(tegra->emc_clk); 63} 64 65static int tegra_ehci_internal_port_reset( 66 struct ehci_hcd *ehci, 67 u32 __iomem *portsc_reg 68) 69{ 70 u32 temp; 71 unsigned long flags; 72 int retval = 0; 73 int i, tries; 74 u32 saved_usbintr; 75 76 spin_lock_irqsave(&ehci->lock, flags); 77 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); 78 /* disable USB interrupt */ 79 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 80 spin_unlock_irqrestore(&ehci->lock, flags); 81 82 /* 83 * Here we have to do Port Reset at most twice for 84 * Port Enable bit to be set. 85 */ 86 for (i = 0; i < 2; i++) { 87 temp = ehci_readl(ehci, portsc_reg); 88 temp |= PORT_RESET; 89 ehci_writel(ehci, temp, portsc_reg); 90 mdelay(10); 91 temp &= ~PORT_RESET; 92 ehci_writel(ehci, temp, portsc_reg); 93 mdelay(1); 94 tries = 100; 95 do { 96 mdelay(1); 97 /* 98 * Up to this point, Port Enable bit is 99 * expected to be set after 2 ms waiting. 100 * USB1 usually takes extra 45 ms, for safety, 101 * we take 100 ms as timeout. 102 */ 103 temp = ehci_readl(ehci, portsc_reg); 104 } while (!(temp & PORT_PE) && tries--); 105 if (temp & PORT_PE) 106 break; 107 } 108 if (i == 2) 109 retval = -ETIMEDOUT; 110 111 /* 112 * Clear Connect Status Change bit if it's set. 113 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared. 114 */ 115 if (temp & PORT_CSC) 116 ehci_writel(ehci, PORT_CSC, portsc_reg); 117 118 /* 119 * Write to clear any interrupt status bits that might be set 120 * during port reset. 121 */ 122 temp = ehci_readl(ehci, &ehci->regs->status); 123 ehci_writel(ehci, temp, &ehci->regs->status); 124 125 /* restore original interrupt enable bits */ 126 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); 127 return retval; 128} 129 130static int tegra_ehci_hub_control( 131 struct usb_hcd *hcd, 132 u16 typeReq, 133 u16 wValue, 134 u16 wIndex, 135 char *buf, 136 u16 wLength 137) 138{ 139 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 140 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 141 u32 __iomem *status_reg; 142 u32 temp; 143 unsigned long flags; 144 int retval = 0; 145 146 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; 147 148 spin_lock_irqsave(&ehci->lock, flags); 149 150 /* 151 * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits 152 * that are write on clear, by writing back the register read value, so 153 * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits 154 */ 155 if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) { 156 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS; 157 ehci_writel(ehci, temp & ~PORT_PE, status_reg); 158 goto done; 159 } 160 161 else if (typeReq == GetPortStatus) { 162 temp = ehci_readl(ehci, status_reg); 163 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) { 164 /* Resume completed, re-enable disconnect detection */ 165 tegra->port_resuming = 0; 166 tegra_usb_phy_postresume(tegra->phy); 167 } 168 } 169 170 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) { 171 temp = ehci_readl(ehci, status_reg); 172 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) { 173 retval = -EPIPE; 174 goto done; 175 } 176 177 temp &= ~PORT_WKCONN_E; 178 temp |= PORT_WKDISC_E | PORT_WKOC_E; 179 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); 180 181 /* 182 * If a transaction is in progress, there may be a delay in 183 * suspending the port. Poll until the port is suspended. 184 */ 185 if (handshake(ehci, status_reg, PORT_SUSPEND, 186 PORT_SUSPEND, 5000)) 187 pr_err("%s: timeout waiting for SUSPEND\n", __func__); 188 189 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports); 190 goto done; 191 } 192 193 /* For USB1 port we need to issue Port Reset twice internally */ 194 if (tegra->phy->instance == 0 && 195 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) { 196 spin_unlock_irqrestore(&ehci->lock, flags); 197 return tegra_ehci_internal_port_reset(ehci, status_reg); 198 } 199 200 /* 201 * Tegra host controller will time the resume operation to clear the bit 202 * when the port control state switches to HS or FS Idle. This behavior 203 * is different from EHCI where the host controller driver is required 204 * to set this bit to a zero after the resume duration is timed in the 205 * driver. 206 */ 207 else if (typeReq == ClearPortFeature && 208 wValue == USB_PORT_FEAT_SUSPEND) { 209 temp = ehci_readl(ehci, status_reg); 210 if ((temp & PORT_RESET) || !(temp & PORT_PE)) { 211 retval = -EPIPE; 212 goto done; 213 } 214 215 if (!(temp & PORT_SUSPEND)) 216 goto done; 217 218 /* Disable disconnect detection during port resume */ 219 tegra_usb_phy_preresume(tegra->phy); 220 221 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25); 222 223 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); 224 /* start resume signalling */ 225 ehci_writel(ehci, temp | PORT_RESUME, status_reg); 226 set_bit(wIndex-1, &ehci->resuming_ports); 227 228 spin_unlock_irqrestore(&ehci->lock, flags); 229 msleep(20); 230 spin_lock_irqsave(&ehci->lock, flags); 231 232 /* Poll until the controller clears RESUME and SUSPEND */ 233 if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000)) 234 pr_err("%s: timeout waiting for RESUME\n", __func__); 235 if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000)) 236 pr_err("%s: timeout waiting for SUSPEND\n", __func__); 237 238 ehci->reset_done[wIndex-1] = 0; 239 clear_bit(wIndex-1, &ehci->resuming_ports); 240 241 tegra->port_resuming = 1; 242 goto done; 243 } 244 245 spin_unlock_irqrestore(&ehci->lock, flags); 246 247 /* Handle the hub control events here */ 248 return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); 249done: 250 spin_unlock_irqrestore(&ehci->lock, flags); 251 return retval; 252} 253 254static void tegra_ehci_restart(struct usb_hcd *hcd) 255{ 256 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 257 258 ehci_reset(ehci); 259 260 /* setup the frame list and Async q heads */ 261 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); 262 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); 263 /* setup the command register and set the controller in RUN mode */ 264 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 265 ehci->command |= CMD_RUN; 266 ehci_writel(ehci, ehci->command, &ehci->regs->command); 267 268 down_write(&ehci_cf_port_reset_rwsem); 269 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 270 /* flush posted writes */ 271 ehci_readl(ehci, &ehci->regs->command); 272 up_write(&ehci_cf_port_reset_rwsem); 273} 274 275static void tegra_ehci_shutdown(struct usb_hcd *hcd) 276{ 277 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); 278 279 /* ehci_shutdown touches the USB controller registers, make sure 280 * controller has clocks to it */ 281 if (!tegra->host_resumed) 282 tegra_ehci_power_up(hcd); 283 284 ehci_shutdown(hcd); 285} 286 287static int tegra_ehci_setup(struct usb_hcd *hcd) 288{ 289 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 290 int retval; 291 292 /* EHCI registers start at offset 0x100 */ 293 ehci->caps = hcd->regs + 0x100; 294 ehci->regs = hcd->regs + 0x100 + 295 HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); 296 297 dbg_hcs_params(ehci, "reset"); 298 dbg_hcc_params(ehci, "reset"); 299 300 /* cache this readonly data; minimize chip reads */ 301 ehci->hcs_params = readl(&ehci->caps->hcs_params); 302 303 /* switch to host mode */ 304 hcd->has_tt = 1; 305 ehci_reset(ehci); 306 307 retval = ehci_halt(ehci); 308 if (retval) 309 return retval; 310 311 /* data structure init */ 312 retval = ehci_init(hcd); 313 if (retval) 314 return retval; 315 316 ehci->sbrn = 0x20; 317 318 ehci_port_power(ehci, 1); 319 return retval; 320} 321 322struct temp_buffer { 323 void *kmalloc_ptr; 324 void *old_xfer_buffer; 325 u8 data[0]; 326}; 327 328static void free_temp_buffer(struct urb *urb) 329{ 330 enum dma_data_direction dir; 331 struct temp_buffer *temp; 332 333 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 334 return; 335 336 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 337 338 temp = container_of(urb->transfer_buffer, struct temp_buffer, 339 data); 340 341 if (dir == DMA_FROM_DEVICE) 342 memcpy(temp->old_xfer_buffer, temp->data, 343 urb->transfer_buffer_length); 344 urb->transfer_buffer = temp->old_xfer_buffer; 345 kfree(temp->kmalloc_ptr); 346 347 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 348} 349 350static int alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) 351{ 352 enum dma_data_direction dir; 353 struct temp_buffer *temp, *kmalloc_ptr; 354 size_t kmalloc_size; 355 356 if (urb->num_sgs || urb->sg || 357 urb->transfer_buffer_length == 0 || 358 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1))) 359 return 0; 360 361 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 362 363 /* Allocate a buffer with enough padding for alignment */ 364 kmalloc_size = urb->transfer_buffer_length + 365 sizeof(struct temp_buffer) + TEGRA_USB_DMA_ALIGN - 1; 366 367 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 368 if (!kmalloc_ptr) 369 return -ENOMEM; 370 371 /* Position our struct temp_buffer such that data is aligned */ 372 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1; 373 374 temp->kmalloc_ptr = kmalloc_ptr; 375 temp->old_xfer_buffer = urb->transfer_buffer; 376 if (dir == DMA_TO_DEVICE) 377 memcpy(temp->data, urb->transfer_buffer, 378 urb->transfer_buffer_length); 379 urb->transfer_buffer = temp->data; 380 381 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 382 383 return 0; 384} 385 386static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 387 gfp_t mem_flags) 388{ 389 int ret; 390 391 ret = alloc_temp_buffer(urb, mem_flags); 392 if (ret) 393 return ret; 394 395 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 396 if (ret) 397 free_temp_buffer(urb); 398 399 return ret; 400} 401 402static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 403{ 404 usb_hcd_unmap_urb_for_dma(hcd, urb); 405 free_temp_buffer(urb); 406} 407 408static const struct hc_driver tegra_ehci_hc_driver = { 409 .description = hcd_name, 410 .product_desc = "Tegra EHCI Host Controller", 411 .hcd_priv_size = sizeof(struct ehci_hcd), 412 413 .flags = HCD_USB2 | HCD_MEMORY, 414 415 .reset = tegra_ehci_setup, 416 .irq = ehci_irq, 417 418 .start = ehci_run, 419 .stop = ehci_stop, 420 .shutdown = tegra_ehci_shutdown, 421 .urb_enqueue = ehci_urb_enqueue, 422 .urb_dequeue = ehci_urb_dequeue, 423 .map_urb_for_dma = tegra_ehci_map_urb_for_dma, 424 .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma, 425 .endpoint_disable = ehci_endpoint_disable, 426 .endpoint_reset = ehci_endpoint_reset, 427 .get_frame_number = ehci_get_frame, 428 .hub_status_data = ehci_hub_status_data, 429 .hub_control = tegra_ehci_hub_control, 430 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, 431#ifdef CONFIG_PM 432 .bus_suspend = ehci_bus_suspend, 433 .bus_resume = ehci_bus_resume, 434#endif 435 .relinquish_port = ehci_relinquish_port, 436 .port_handed_over = ehci_port_handed_over, 437}; 438 439static int setup_vbus_gpio(struct platform_device *pdev) 440{ 441 int err = 0; 442 int gpio; 443 444 if (!pdev->dev.of_node) 445 return 0; 446 447 gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0); 448 if (!gpio_is_valid(gpio)) 449 return 0; 450 451 err = gpio_request(gpio, "vbus_gpio"); 452 if (err) { 453 dev_err(&pdev->dev, "can't request vbus gpio %d", gpio); 454 return err; 455 } 456 err = gpio_direction_output(gpio, 1); 457 if (err) { 458 dev_err(&pdev->dev, "can't enable vbus\n"); 459 return err; 460 } 461 462 return err; 463} 464 465#ifdef CONFIG_PM 466 467static int controller_suspend(struct device *dev) 468{ 469 struct tegra_ehci_hcd *tegra = 470 platform_get_drvdata(to_platform_device(dev)); 471 struct ehci_hcd *ehci = tegra->ehci; 472 struct usb_hcd *hcd = ehci_to_hcd(ehci); 473 struct ehci_regs __iomem *hw = ehci->regs; 474 unsigned long flags; 475 476 if (time_before(jiffies, ehci->next_statechange)) 477 msleep(10); 478 479 spin_lock_irqsave(&ehci->lock, flags); 480 481 tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3; 482 ehci_halt(ehci); 483 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 484 485 spin_unlock_irqrestore(&ehci->lock, flags); 486 487 tegra_ehci_power_down(hcd); 488 return 0; 489} 490 491static int controller_resume(struct device *dev) 492{ 493 struct tegra_ehci_hcd *tegra = 494 platform_get_drvdata(to_platform_device(dev)); 495 struct ehci_hcd *ehci = tegra->ehci; 496 struct usb_hcd *hcd = ehci_to_hcd(ehci); 497 struct ehci_regs __iomem *hw = ehci->regs; 498 unsigned long val; 499 500 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 501 tegra_ehci_power_up(hcd); 502 503 if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) { 504 /* Wait for the phy to detect new devices 505 * before we restart the controller */ 506 msleep(10); 507 goto restart; 508 } 509 510 /* Force the phy to keep data lines in suspend state */ 511 tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed); 512 513 /* Enable host mode */ 514 tdi_reset(ehci); 515 516 /* Enable Port Power */ 517 val = readl(&hw->port_status[0]); 518 val |= PORT_POWER; 519 writel(val, &hw->port_status[0]); 520 udelay(10); 521 522 /* Check if the phy resume from LP0. When the phy resume from LP0 523 * USB register will be reset. */ 524 if (!readl(&hw->async_next)) { 525 /* Program the field PTC based on the saved speed mode */ 526 val = readl(&hw->port_status[0]); 527 val &= ~PORT_TEST(~0); 528 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH) 529 val |= PORT_TEST_FORCE; 530 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL) 531 val |= PORT_TEST(6); 532 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) 533 val |= PORT_TEST(7); 534 writel(val, &hw->port_status[0]); 535 udelay(10); 536 537 /* Disable test mode by setting PTC field to NORMAL_OP */ 538 val = readl(&hw->port_status[0]); 539 val &= ~PORT_TEST(~0); 540 writel(val, &hw->port_status[0]); 541 udelay(10); 542 } 543 544 /* Poll until CCS is enabled */ 545 if (handshake(ehci, &hw->port_status[0], PORT_CONNECT, 546 PORT_CONNECT, 2000)) { 547 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__); 548 goto restart; 549 } 550 551 /* Poll until PE is enabled */ 552 if (handshake(ehci, &hw->port_status[0], PORT_PE, 553 PORT_PE, 2000)) { 554 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__); 555 goto restart; 556 } 557 558 /* Clear the PCI status, to avoid an interrupt taken upon resume */ 559 val = readl(&hw->status); 560 val |= STS_PCD; 561 writel(val, &hw->status); 562 563 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */ 564 val = readl(&hw->port_status[0]); 565 if ((val & PORT_POWER) && (val & PORT_PE)) { 566 val |= PORT_SUSPEND; 567 writel(val, &hw->port_status[0]); 568 569 /* Wait until port suspend completes */ 570 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND, 571 PORT_SUSPEND, 1000)) { 572 pr_err("%s: timeout waiting for PORT_SUSPEND\n", 573 __func__); 574 goto restart; 575 } 576 } 577 578 tegra_ehci_phy_restore_end(tegra->phy); 579 goto done; 580 581 restart: 582 if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) 583 tegra_ehci_phy_restore_end(tegra->phy); 584 585 tegra_ehci_restart(hcd); 586 587 done: 588 tegra_usb_phy_preresume(tegra->phy); 589 tegra->port_resuming = 1; 590 return 0; 591} 592 593static int tegra_ehci_suspend(struct device *dev) 594{ 595 struct tegra_ehci_hcd *tegra = 596 platform_get_drvdata(to_platform_device(dev)); 597 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); 598 int rc = 0; 599 600 /* 601 * When system sleep is supported and USB controller wakeup is 602 * implemented: If the controller is runtime-suspended and the 603 * wakeup setting needs to be changed, call pm_runtime_resume(). 604 */ 605 if (HCD_HW_ACCESSIBLE(hcd)) 606 rc = controller_suspend(dev); 607 return rc; 608} 609 610static int tegra_ehci_resume(struct device *dev) 611{ 612 int rc; 613 614 rc = controller_resume(dev); 615 if (rc == 0) { 616 pm_runtime_disable(dev); 617 pm_runtime_set_active(dev); 618 pm_runtime_enable(dev); 619 } 620 return rc; 621} 622 623static int tegra_ehci_runtime_suspend(struct device *dev) 624{ 625 return controller_suspend(dev); 626} 627 628static int tegra_ehci_runtime_resume(struct device *dev) 629{ 630 return controller_resume(dev); 631} 632 633static const struct dev_pm_ops tegra_ehci_pm_ops = { 634 .suspend = tegra_ehci_suspend, 635 .resume = tegra_ehci_resume, 636 .runtime_suspend = tegra_ehci_runtime_suspend, 637 .runtime_resume = tegra_ehci_runtime_resume, 638}; 639 640#endif 641 642static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32); 643 644static int tegra_ehci_probe(struct platform_device *pdev) 645{ 646 struct resource *res; 647 struct usb_hcd *hcd; 648 struct tegra_ehci_hcd *tegra; 649 struct tegra_ehci_platform_data *pdata; 650 int err = 0; 651 int irq; 652 int instance = pdev->id; 653 654 pdata = pdev->dev.platform_data; 655 if (!pdata) { 656 dev_err(&pdev->dev, "Platform data missing\n"); 657 return -EINVAL; 658 } 659 660 /* Right now device-tree probed devices don't get dma_mask set. 661 * Since shared usb code relies on it, set it here for now. 662 * Once we have dma capability bindings this can go away. 663 */ 664 if (!pdev->dev.dma_mask) 665 pdev->dev.dma_mask = &tegra_ehci_dma_mask; 666 667 setup_vbus_gpio(pdev); 668 669 tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); 670 if (!tegra) 671 return -ENOMEM; 672 673 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev, 674 dev_name(&pdev->dev)); 675 if (!hcd) { 676 dev_err(&pdev->dev, "Unable to create HCD\n"); 677 err = -ENOMEM; 678 goto fail_hcd; 679 } 680 681 platform_set_drvdata(pdev, tegra); 682 683 tegra->clk = clk_get(&pdev->dev, NULL); 684 if (IS_ERR(tegra->clk)) { 685 dev_err(&pdev->dev, "Can't get ehci clock\n"); 686 err = PTR_ERR(tegra->clk); 687 goto fail_clk; 688 } 689 690 err = clk_enable(tegra->clk); 691 if (err) 692 goto fail_clken; 693 694 tegra->emc_clk = clk_get(&pdev->dev, "emc"); 695 if (IS_ERR(tegra->emc_clk)) { 696 dev_err(&pdev->dev, "Can't get emc clock\n"); 697 err = PTR_ERR(tegra->emc_clk); 698 goto fail_emc_clk; 699 } 700 701 clk_enable(tegra->emc_clk); 702 clk_set_rate(tegra->emc_clk, 400000000); 703 704 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 705 if (!res) { 706 dev_err(&pdev->dev, "Failed to get I/O memory\n"); 707 err = -ENXIO; 708 goto fail_io; 709 } 710 hcd->rsrc_start = res->start; 711 hcd->rsrc_len = resource_size(res); 712 hcd->regs = ioremap(res->start, resource_size(res)); 713 if (!hcd->regs) { 714 dev_err(&pdev->dev, "Failed to remap I/O memory\n"); 715 err = -ENOMEM; 716 goto fail_io; 717 } 718 719 /* This is pretty ugly and needs to be fixed when we do only 720 * device-tree probing. Old code relies on the platform_device 721 * numbering that we lack for device-tree-instantiated devices. 722 */ 723 if (instance < 0) { 724 switch (res->start) { 725 case TEGRA_USB_BASE: 726 instance = 0; 727 break; 728 case TEGRA_USB2_BASE: 729 instance = 1; 730 break; 731 case TEGRA_USB3_BASE: 732 instance = 2; 733 break; 734 default: 735 err = -ENODEV; 736 dev_err(&pdev->dev, "unknown usb instance\n"); 737 goto fail_phy; 738 } 739 } 740 741 tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config, 742 TEGRA_USB_PHY_MODE_HOST); 743 if (IS_ERR(tegra->phy)) { 744 dev_err(&pdev->dev, "Failed to open USB phy\n"); 745 err = -ENXIO; 746 goto fail_phy; 747 } 748 749 err = tegra_usb_phy_power_on(tegra->phy); 750 if (err) { 751 dev_err(&pdev->dev, "Failed to power on the phy\n"); 752 goto fail; 753 } 754 755 tegra->host_resumed = 1; 756 tegra->ehci = hcd_to_ehci(hcd); 757 758 irq = platform_get_irq(pdev, 0); 759 if (!irq) { 760 dev_err(&pdev->dev, "Failed to get IRQ\n"); 761 err = -ENODEV; 762 goto fail; 763 } 764 765#ifdef CONFIG_USB_OTG_UTILS 766 if (pdata->operating_mode == TEGRA_USB_OTG) { 767 tegra->transceiver = usb_get_transceiver(); 768 if (tegra->transceiver) 769 otg_set_host(tegra->transceiver->otg, &hcd->self); 770 } 771#endif 772 773 err = usb_add_hcd(hcd, irq, IRQF_SHARED); 774 if (err) { 775 dev_err(&pdev->dev, "Failed to add USB HCD\n"); 776 goto fail; 777 } 778 779 pm_runtime_set_active(&pdev->dev); 780 pm_runtime_get_noresume(&pdev->dev); 781 782 /* Don't skip the pm_runtime_forbid call if wakeup isn't working */ 783 /* if (!pdata->power_down_on_bus_suspend) */ 784 pm_runtime_forbid(&pdev->dev); 785 pm_runtime_enable(&pdev->dev); 786 pm_runtime_put_sync(&pdev->dev); 787 return err; 788 789fail: 790#ifdef CONFIG_USB_OTG_UTILS 791 if (tegra->transceiver) { 792 otg_set_host(tegra->transceiver->otg, NULL); 793 usb_put_transceiver(tegra->transceiver); 794 } 795#endif 796 tegra_usb_phy_close(tegra->phy); 797fail_phy: 798 iounmap(hcd->regs); 799fail_io: 800 clk_disable(tegra->emc_clk); 801 clk_put(tegra->emc_clk); 802fail_emc_clk: 803 clk_disable(tegra->clk); 804fail_clken: 805 clk_put(tegra->clk); 806fail_clk: 807 usb_put_hcd(hcd); 808fail_hcd: 809 kfree(tegra); 810 return err; 811} 812 813static int tegra_ehci_remove(struct platform_device *pdev) 814{ 815 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); 816 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); 817 818 if (tegra == NULL || hcd == NULL) 819 return -EINVAL; 820 821 pm_runtime_get_sync(&pdev->dev); 822 pm_runtime_disable(&pdev->dev); 823 pm_runtime_put_noidle(&pdev->dev); 824 825#ifdef CONFIG_USB_OTG_UTILS 826 if (tegra->transceiver) { 827 otg_set_host(tegra->transceiver->otg, NULL); 828 usb_put_transceiver(tegra->transceiver); 829 } 830#endif 831 832 usb_remove_hcd(hcd); 833 usb_put_hcd(hcd); 834 835 tegra_usb_phy_close(tegra->phy); 836 iounmap(hcd->regs); 837 838 clk_disable(tegra->clk); 839 clk_put(tegra->clk); 840 841 clk_disable(tegra->emc_clk); 842 clk_put(tegra->emc_clk); 843 844 kfree(tegra); 845 return 0; 846} 847 848static void tegra_ehci_hcd_shutdown(struct platform_device *pdev) 849{ 850 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); 851 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); 852 853 if (hcd->driver->shutdown) 854 hcd->driver->shutdown(hcd); 855} 856 857static struct of_device_id tegra_ehci_of_match[] __devinitdata = { 858 { .compatible = "nvidia,tegra20-ehci", }, 859 { }, 860}; 861 862static struct platform_driver tegra_ehci_driver = { 863 .probe = tegra_ehci_probe, 864 .remove = tegra_ehci_remove, 865 .shutdown = tegra_ehci_hcd_shutdown, 866 .driver = { 867 .name = "tegra-ehci", 868 .of_match_table = tegra_ehci_of_match, 869#ifdef CONFIG_PM 870 .pm = &tegra_ehci_pm_ops, 871#endif 872 } 873}; 874