1/* 2 * Driver for the NXP ISP1760 chip 3 * 4 * However, the code might contain some bugs. What doesn't work for sure is: 5 * - ISO 6 * - OTG 7 e The interrupt line is configured as active low, level. 8 * 9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> 10 * 11 * (c) 2011 Arvid Brodin <arvid.brodin@enea.com> 12 * 13 */ 14#include <linux/module.h> 15#include <linux/kernel.h> 16#include <linux/slab.h> 17#include <linux/list.h> 18#include <linux/usb.h> 19#include <linux/usb/hcd.h> 20#include <linux/debugfs.h> 21#include <linux/uaccess.h> 22#include <linux/io.h> 23#include <linux/mm.h> 24#include <linux/timer.h> 25#include <asm/unaligned.h> 26#include <asm/cacheflush.h> 27#include <linux/gpio.h> 28 29#include "isp1760-hcd.h" 30 31static struct kmem_cache *qtd_cachep; 32static struct kmem_cache *qh_cachep; 33static struct kmem_cache *urb_listitem_cachep; 34 35enum queue_head_types { 36 QH_CONTROL, 37 QH_BULK, 38 QH_INTERRUPT, 39 QH_END 40}; 41 42struct isp1760_hcd { 43 u32 hcs_params; 44 spinlock_t lock; 45 struct slotinfo atl_slots[32]; 46 int atl_done_map; 47 struct slotinfo int_slots[32]; 48 int int_done_map; 49 struct memory_chunk memory_pool[BLOCKS]; 50 struct list_head qh_list[QH_END]; 51 52 /* periodic schedule support */ 53#define DEFAULT_I_TDPS 1024 54 unsigned periodic_size; 55 unsigned i_thresh; 56 unsigned long reset_done; 57 unsigned long next_statechange; 58 unsigned int devflags; 59 60 int rst_gpio; 61}; 62 63static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) 64{ 65 return (struct isp1760_hcd *) (hcd->hcd_priv); 66} 67 68/* Section 2.2 Host Controller Capability Registers */ 69#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ 70#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ 71#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ 72#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 73#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ 74#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ 75#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ 76 77/* Section 2.3 Host Controller Operational Registers */ 78#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ 79#define CMD_RESET (1<<1) /* reset HC not bus */ 80#define CMD_RUN (1<<0) /* start/stop HC */ 81#define STS_PCD (1<<2) /* port change detect */ 82#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ 83 84#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ 85#define PORT_POWER (1<<12) /* true: has power (see PPC) */ 86#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */ 87#define PORT_RESET (1<<8) /* reset port */ 88#define PORT_SUSPEND (1<<7) /* suspend port */ 89#define PORT_RESUME (1<<6) /* resume it */ 90#define PORT_PE (1<<2) /* port enable */ 91#define PORT_CSC (1<<1) /* connect status change */ 92#define PORT_CONNECT (1<<0) /* device connected */ 93#define PORT_RWC_BITS (PORT_CSC) 94 95struct isp1760_qtd { 96 u8 packet_type; 97 void *data_buffer; 98 u32 payload_addr; 99 100 /* the rest is HCD-private */ 101 struct list_head qtd_list; 102 struct urb *urb; 103 size_t length; 104 size_t actual_length; 105 106 /* QTD_ENQUEUED: waiting for transfer (inactive) */ 107 /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */ 108 /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only 109 interrupt handler may touch this qtd! */ 110 /* QTD_XFER_COMPLETE: payload has been transferred successfully */ 111 /* QTD_RETIRE: transfer error/abort qtd */ 112#define QTD_ENQUEUED 0 113#define QTD_PAYLOAD_ALLOC 1 114#define QTD_XFER_STARTED 2 115#define QTD_XFER_COMPLETE 3 116#define QTD_RETIRE 4 117 u32 status; 118}; 119 120/* Queue head, one for each active endpoint */ 121struct isp1760_qh { 122 struct list_head qh_list; 123 struct list_head qtd_list; 124 u32 toggle; 125 u32 ping; 126 int slot; 127 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */ 128}; 129 130struct urb_listitem { 131 struct list_head urb_list; 132 struct urb *urb; 133}; 134 135/* 136 * Access functions for isp176x registers (addresses 0..0x03FF). 137 */ 138static u32 reg_read32(void __iomem *base, u32 reg) 139{ 140 return readl(base + reg); 141} 142 143static void reg_write32(void __iomem *base, u32 reg, u32 val) 144{ 145 writel(val, base + reg); 146} 147 148/* 149 * Access functions for isp176x memory (offset >= 0x0400). 150 * 151 * bank_reads8() reads memory locations prefetched by an earlier write to 152 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- 153 * bank optimizations, you should use the more generic mem_reads8() below. 154 * 155 * For access to ptd memory, use the specialized ptd_read() and ptd_write() 156 * below. 157 * 158 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() 159 * doesn't quite work because some people have to enforce 32-bit access 160 */ 161static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, 162 __u32 *dst, u32 bytes) 163{ 164 __u32 __iomem *src; 165 u32 val; 166 __u8 *src_byteptr; 167 __u8 *dst_byteptr; 168 169 src = src_base + (bank_addr | src_offset); 170 171 if (src_offset < PAYLOAD_OFFSET) { 172 while (bytes >= 4) { 173 *dst = le32_to_cpu(__raw_readl(src)); 174 bytes -= 4; 175 src++; 176 dst++; 177 } 178 } else { 179 while (bytes >= 4) { 180 *dst = __raw_readl(src); 181 bytes -= 4; 182 src++; 183 dst++; 184 } 185 } 186 187 if (!bytes) 188 return; 189 190 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully 191 * allocated. 192 */ 193 if (src_offset < PAYLOAD_OFFSET) 194 val = le32_to_cpu(__raw_readl(src)); 195 else 196 val = __raw_readl(src); 197 198 dst_byteptr = (void *) dst; 199 src_byteptr = (void *) &val; 200 while (bytes > 0) { 201 *dst_byteptr = *src_byteptr; 202 dst_byteptr++; 203 src_byteptr++; 204 bytes--; 205 } 206} 207 208static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst, 209 u32 bytes) 210{ 211 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0)); 212 ndelay(90); 213 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes); 214} 215 216static void mem_writes8(void __iomem *dst_base, u32 dst_offset, 217 __u32 const *src, u32 bytes) 218{ 219 __u32 __iomem *dst; 220 221 dst = dst_base + dst_offset; 222 223 if (dst_offset < PAYLOAD_OFFSET) { 224 while (bytes >= 4) { 225 __raw_writel(cpu_to_le32(*src), dst); 226 bytes -= 4; 227 src++; 228 dst++; 229 } 230 } else { 231 while (bytes >= 4) { 232 __raw_writel(*src, dst); 233 bytes -= 4; 234 src++; 235 dst++; 236 } 237 } 238 239 if (!bytes) 240 return; 241 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the 242 * extra bytes should not be read by the HW. 243 */ 244 245 if (dst_offset < PAYLOAD_OFFSET) 246 __raw_writel(cpu_to_le32(*src), dst); 247 else 248 __raw_writel(*src, dst); 249} 250 251/* 252 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, 253 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. 254 */ 255static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot, 256 struct ptd *ptd) 257{ 258 reg_write32(base, HC_MEMORY_REG, 259 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd)); 260 ndelay(90); 261 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0), 262 (void *) ptd, sizeof(*ptd)); 263} 264 265static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, 266 struct ptd *ptd) 267{ 268 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), 269 &ptd->dw1, 7*sizeof(ptd->dw1)); 270 /* Make sure dw0 gets written last (after other dw's and after payload) 271 since it contains the enable bit */ 272 wmb(); 273 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0, 274 sizeof(ptd->dw0)); 275} 276 277 278/* memory management of the 60kb on the chip from 0x1000 to 0xffff */ 279static void init_memory(struct isp1760_hcd *priv) 280{ 281 int i, curr; 282 u32 payload_addr; 283 284 payload_addr = PAYLOAD_OFFSET; 285 for (i = 0; i < BLOCK_1_NUM; i++) { 286 priv->memory_pool[i].start = payload_addr; 287 priv->memory_pool[i].size = BLOCK_1_SIZE; 288 priv->memory_pool[i].free = 1; 289 payload_addr += priv->memory_pool[i].size; 290 } 291 292 curr = i; 293 for (i = 0; i < BLOCK_2_NUM; i++) { 294 priv->memory_pool[curr + i].start = payload_addr; 295 priv->memory_pool[curr + i].size = BLOCK_2_SIZE; 296 priv->memory_pool[curr + i].free = 1; 297 payload_addr += priv->memory_pool[curr + i].size; 298 } 299 300 curr = i; 301 for (i = 0; i < BLOCK_3_NUM; i++) { 302 priv->memory_pool[curr + i].start = payload_addr; 303 priv->memory_pool[curr + i].size = BLOCK_3_SIZE; 304 priv->memory_pool[curr + i].free = 1; 305 payload_addr += priv->memory_pool[curr + i].size; 306 } 307 308 WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE); 309} 310 311static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) 312{ 313 struct isp1760_hcd *priv = hcd_to_priv(hcd); 314 int i; 315 316 WARN_ON(qtd->payload_addr); 317 318 if (!qtd->length) 319 return; 320 321 for (i = 0; i < BLOCKS; i++) { 322 if (priv->memory_pool[i].size >= qtd->length && 323 priv->memory_pool[i].free) { 324 priv->memory_pool[i].free = 0; 325 qtd->payload_addr = priv->memory_pool[i].start; 326 return; 327 } 328 } 329} 330 331static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) 332{ 333 struct isp1760_hcd *priv = hcd_to_priv(hcd); 334 int i; 335 336 if (!qtd->payload_addr) 337 return; 338 339 for (i = 0; i < BLOCKS; i++) { 340 if (priv->memory_pool[i].start == qtd->payload_addr) { 341 WARN_ON(priv->memory_pool[i].free); 342 priv->memory_pool[i].free = 1; 343 qtd->payload_addr = 0; 344 return; 345 } 346 } 347 348 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n", 349 __func__, qtd->payload_addr); 350 WARN_ON(1); 351 qtd->payload_addr = 0; 352} 353 354static int handshake(struct usb_hcd *hcd, u32 reg, 355 u32 mask, u32 done, int usec) 356{ 357 u32 result; 358 359 do { 360 result = reg_read32(hcd->regs, reg); 361 if (result == ~0) 362 return -ENODEV; 363 result &= mask; 364 if (result == done) 365 return 0; 366 udelay(1); 367 usec--; 368 } while (usec > 0); 369 return -ETIMEDOUT; 370} 371 372/* reset a non-running (STS_HALT == 1) controller */ 373static int ehci_reset(struct usb_hcd *hcd) 374{ 375 int retval; 376 struct isp1760_hcd *priv = hcd_to_priv(hcd); 377 378 u32 command = reg_read32(hcd->regs, HC_USBCMD); 379 380 command |= CMD_RESET; 381 reg_write32(hcd->regs, HC_USBCMD, command); 382 hcd->state = HC_STATE_HALT; 383 priv->next_statechange = jiffies; 384 retval = handshake(hcd, HC_USBCMD, 385 CMD_RESET, 0, 250 * 1000); 386 return retval; 387} 388 389static struct isp1760_qh *qh_alloc(gfp_t flags) 390{ 391 struct isp1760_qh *qh; 392 393 qh = kmem_cache_zalloc(qh_cachep, flags); 394 if (!qh) 395 return NULL; 396 397 INIT_LIST_HEAD(&qh->qh_list); 398 INIT_LIST_HEAD(&qh->qtd_list); 399 qh->slot = -1; 400 401 return qh; 402} 403 404static void qh_free(struct isp1760_qh *qh) 405{ 406 WARN_ON(!list_empty(&qh->qtd_list)); 407 WARN_ON(qh->slot > -1); 408 kmem_cache_free(qh_cachep, qh); 409} 410 411/* one-time init, only for memory state */ 412static int priv_init(struct usb_hcd *hcd) 413{ 414 struct isp1760_hcd *priv = hcd_to_priv(hcd); 415 u32 hcc_params; 416 int i; 417 418 spin_lock_init(&priv->lock); 419 420 for (i = 0; i < QH_END; i++) 421 INIT_LIST_HEAD(&priv->qh_list[i]); 422 423 /* 424 * hw default: 1K periodic list heads, one per frame. 425 * periodic_size can shrink by USBCMD update if hcc_params allows. 426 */ 427 priv->periodic_size = DEFAULT_I_TDPS; 428 429 /* controllers may cache some of the periodic schedule ... */ 430 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS); 431 /* full frame cache */ 432 if (HCC_ISOC_CACHE(hcc_params)) 433 priv->i_thresh = 8; 434 else /* N microframes cached */ 435 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 436 437 return 0; 438} 439 440static int isp1760_hc_setup(struct usb_hcd *hcd) 441{ 442 struct isp1760_hcd *priv = hcd_to_priv(hcd); 443 int result; 444 u32 scratch, hwmode; 445 446 /* low-level chip reset */ 447 if (gpio_is_valid(priv->rst_gpio)) { 448 unsigned int rst_lvl; 449 450 rst_lvl = (priv->devflags & 451 ISP1760_FLAG_RESET_ACTIVE_HIGH) ? 1 : 0; 452 453 gpio_set_value(priv->rst_gpio, rst_lvl); 454 mdelay(50); 455 gpio_set_value(priv->rst_gpio, !rst_lvl); 456 } 457 458 /* Setup HW Mode Control: This assumes a level active-low interrupt */ 459 hwmode = HW_DATA_BUS_32BIT; 460 461 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) 462 hwmode &= ~HW_DATA_BUS_32BIT; 463 if (priv->devflags & ISP1760_FLAG_ANALOG_OC) 464 hwmode |= HW_ANA_DIGI_OC; 465 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH) 466 hwmode |= HW_DACK_POL_HIGH; 467 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH) 468 hwmode |= HW_DREQ_POL_HIGH; 469 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH) 470 hwmode |= HW_INTR_HIGH_ACT; 471 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG) 472 hwmode |= HW_INTR_EDGE_TRIG; 473 474 /* 475 * We have to set this first in case we're in 16-bit mode. 476 * Write it twice to ensure correct upper bits if switching 477 * to 16-bit mode. 478 */ 479 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); 480 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); 481 482 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe); 483 /* Change bus pattern */ 484 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG); 485 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG); 486 if (scratch != 0xdeadbabe) { 487 dev_err(hcd->self.controller, "Scratch test failed.\n"); 488 return -ENODEV; 489 } 490 491 /* pre reset */ 492 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0); 493 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); 494 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); 495 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); 496 497 /* reset */ 498 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL); 499 mdelay(100); 500 501 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC); 502 mdelay(100); 503 504 result = ehci_reset(hcd); 505 if (result) 506 return result; 507 508 /* Step 11 passed */ 509 510 dev_info(hcd->self.controller, "bus width: %d, oc: %s\n", 511 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ? 512 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ? 513 "analog" : "digital"); 514 515 /* ATL reset */ 516 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET); 517 mdelay(10); 518 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); 519 520 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK); 521 522 /* 523 * PORT 1 Control register of the ISP1760 is the OTG control 524 * register on ISP1761. Since there is no OTG or device controller 525 * support in this driver, we use port 1 as a "normal" USB host port on 526 * both chips. 527 */ 528 reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2); 529 mdelay(10); 530 531 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS); 532 533 return priv_init(hcd); 534} 535 536static u32 base_to_chip(u32 base) 537{ 538 return ((base - 0x400) >> 3); 539} 540 541static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) 542{ 543 struct urb *urb; 544 545 if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) 546 return 1; 547 548 urb = qtd->urb; 549 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); 550 return (qtd->urb != urb); 551} 552 553/* magic numbers that can affect system performance */ 554#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 555#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 556#define EHCI_TUNE_RL_TT 0 557#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 558#define EHCI_TUNE_MULT_TT 1 559#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ 560 561static void create_ptd_atl(struct isp1760_qh *qh, 562 struct isp1760_qtd *qtd, struct ptd *ptd) 563{ 564 u32 maxpacket; 565 u32 multi; 566 u32 rl = RL_COUNTER; 567 u32 nak = NAK_COUNTER; 568 569 memset(ptd, 0, sizeof(*ptd)); 570 571 /* according to 3.6.2, max packet len can not be > 0x400 */ 572 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe, 573 usb_pipeout(qtd->urb->pipe)); 574 multi = 1 + ((maxpacket >> 11) & 0x3); 575 maxpacket &= 0x7ff; 576 577 /* DW0 */ 578 ptd->dw0 = DW0_VALID_BIT; 579 ptd->dw0 |= TO_DW0_LENGTH(qtd->length); 580 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); 581 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); 582 583 /* DW1 */ 584 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1; 585 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); 586 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); 587 588 if (usb_pipebulk(qtd->urb->pipe)) 589 ptd->dw1 |= DW1_TRANS_BULK; 590 else if (usb_pipeint(qtd->urb->pipe)) 591 ptd->dw1 |= DW1_TRANS_INT; 592 593 if (qtd->urb->dev->speed != USB_SPEED_HIGH) { 594 /* split transaction */ 595 596 ptd->dw1 |= DW1_TRANS_SPLIT; 597 if (qtd->urb->dev->speed == USB_SPEED_LOW) 598 ptd->dw1 |= DW1_SE_USB_LOSPEED; 599 600 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport); 601 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum); 602 603 /* SE bit for Split INT transfers */ 604 if (usb_pipeint(qtd->urb->pipe) && 605 (qtd->urb->dev->speed == USB_SPEED_LOW)) 606 ptd->dw1 |= 2 << 16; 607 608 rl = 0; 609 nak = 0; 610 } else { 611 ptd->dw0 |= TO_DW0_MULTI(multi); 612 if (usb_pipecontrol(qtd->urb->pipe) || 613 usb_pipebulk(qtd->urb->pipe)) 614 ptd->dw3 |= TO_DW3_PING(qh->ping); 615 } 616 /* DW2 */ 617 ptd->dw2 = 0; 618 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); 619 ptd->dw2 |= TO_DW2_RL(rl); 620 621 /* DW3 */ 622 ptd->dw3 |= TO_DW3_NAKCOUNT(nak); 623 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); 624 if (usb_pipecontrol(qtd->urb->pipe)) { 625 if (qtd->data_buffer == qtd->urb->setup_packet) 626 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); 627 else if (last_qtd_of_urb(qtd, qh)) 628 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); 629 } 630 631 ptd->dw3 |= DW3_ACTIVE_BIT; 632 /* Cerr */ 633 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); 634} 635 636static void transform_add_int(struct isp1760_qh *qh, 637 struct isp1760_qtd *qtd, struct ptd *ptd) 638{ 639 u32 usof; 640 u32 period; 641 642 /* 643 * Most of this is guessing. ISP1761 datasheet is quite unclear, and 644 * the algorithm from the original Philips driver code, which was 645 * pretty much used in this driver before as well, is quite horrendous 646 * and, i believe, incorrect. The code below follows the datasheet and 647 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much 648 * more reliable this way (fingers crossed...). 649 */ 650 651 if (qtd->urb->dev->speed == USB_SPEED_HIGH) { 652 /* urb->interval is in units of microframes (1/8 ms) */ 653 period = qtd->urb->interval >> 3; 654 655 if (qtd->urb->interval > 4) 656 usof = 0x01; /* One bit set => 657 interval 1 ms * uFrame-match */ 658 else if (qtd->urb->interval > 2) 659 usof = 0x22; /* Two bits set => interval 1/2 ms */ 660 else if (qtd->urb->interval > 1) 661 usof = 0x55; /* Four bits set => interval 1/4 ms */ 662 else 663 usof = 0xff; /* All bits set => interval 1/8 ms */ 664 } else { 665 /* urb->interval is in units of frames (1 ms) */ 666 period = qtd->urb->interval; 667 usof = 0x0f; /* Execute Start Split on any of the 668 four first uFrames */ 669 670 /* 671 * First 8 bits in dw5 is uSCS and "specifies which uSOF the 672 * complete split needs to be sent. Valid only for IN." Also, 673 * "All bits can be set to one for every transfer." (p 82, 674 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did 675 * that number come from? 0xff seems to work fine... 676 */ 677 /* ptd->dw5 = 0x1c; */ 678 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */ 679 } 680 681 period = period >> 1;/* Ensure equal or shorter period than requested */ 682 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ 683 684 ptd->dw2 |= period; 685 ptd->dw4 = usof; 686} 687 688static void create_ptd_int(struct isp1760_qh *qh, 689 struct isp1760_qtd *qtd, struct ptd *ptd) 690{ 691 create_ptd_atl(qh, qtd, ptd); 692 transform_add_int(qh, qtd, ptd); 693} 694 695static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) 696__releases(priv->lock) 697__acquires(priv->lock) 698{ 699 struct isp1760_hcd *priv = hcd_to_priv(hcd); 700 701 if (!urb->unlinked) { 702 if (urb->status == -EINPROGRESS) 703 urb->status = 0; 704 } 705 706 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { 707 void *ptr; 708 for (ptr = urb->transfer_buffer; 709 ptr < urb->transfer_buffer + urb->transfer_buffer_length; 710 ptr += PAGE_SIZE) 711 flush_dcache_page(virt_to_page(ptr)); 712 } 713 714 /* complete() can reenter this HCD */ 715 usb_hcd_unlink_urb_from_ep(hcd, urb); 716 spin_unlock(&priv->lock); 717 usb_hcd_giveback_urb(hcd, urb, urb->status); 718 spin_lock(&priv->lock); 719} 720 721static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, 722 u8 packet_type) 723{ 724 struct isp1760_qtd *qtd; 725 726 qtd = kmem_cache_zalloc(qtd_cachep, flags); 727 if (!qtd) 728 return NULL; 729 730 INIT_LIST_HEAD(&qtd->qtd_list); 731 qtd->urb = urb; 732 qtd->packet_type = packet_type; 733 qtd->status = QTD_ENQUEUED; 734 qtd->actual_length = 0; 735 736 return qtd; 737} 738 739static void qtd_free(struct isp1760_qtd *qtd) 740{ 741 WARN_ON(qtd->payload_addr); 742 kmem_cache_free(qtd_cachep, qtd); 743} 744 745static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, 746 struct slotinfo *slots, struct isp1760_qtd *qtd, 747 struct isp1760_qh *qh, struct ptd *ptd) 748{ 749 struct isp1760_hcd *priv = hcd_to_priv(hcd); 750 int skip_map; 751 752 WARN_ON((slot < 0) || (slot > 31)); 753 WARN_ON(qtd->length && !qtd->payload_addr); 754 WARN_ON(slots[slot].qtd); 755 WARN_ON(slots[slot].qh); 756 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); 757 758 /* Make sure done map has not triggered from some unlinked transfer */ 759 if (ptd_offset == ATL_PTD_OFFSET) { 760 priv->atl_done_map |= reg_read32(hcd->regs, 761 HC_ATL_PTD_DONEMAP_REG); 762 priv->atl_done_map &= ~(1 << slot); 763 } else { 764 priv->int_done_map |= reg_read32(hcd->regs, 765 HC_INT_PTD_DONEMAP_REG); 766 priv->int_done_map &= ~(1 << slot); 767 } 768 769 qh->slot = slot; 770 qtd->status = QTD_XFER_STARTED; 771 slots[slot].timestamp = jiffies; 772 slots[slot].qtd = qtd; 773 slots[slot].qh = qh; 774 ptd_write(hcd->regs, ptd_offset, slot, ptd); 775 776 if (ptd_offset == ATL_PTD_OFFSET) { 777 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); 778 skip_map &= ~(1 << qh->slot); 779 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); 780 } else { 781 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); 782 skip_map &= ~(1 << qh->slot); 783 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); 784 } 785} 786 787static int is_short_bulk(struct isp1760_qtd *qtd) 788{ 789 return (usb_pipebulk(qtd->urb->pipe) && 790 (qtd->actual_length < qtd->length)); 791} 792 793static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, 794 struct list_head *urb_list) 795{ 796 int last_qtd; 797 struct isp1760_qtd *qtd, *qtd_next; 798 struct urb_listitem *urb_listitem; 799 800 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { 801 if (qtd->status < QTD_XFER_COMPLETE) 802 break; 803 804 last_qtd = last_qtd_of_urb(qtd, qh); 805 806 if ((!last_qtd) && (qtd->status == QTD_RETIRE)) 807 qtd_next->status = QTD_RETIRE; 808 809 if (qtd->status == QTD_XFER_COMPLETE) { 810 if (qtd->actual_length) { 811 switch (qtd->packet_type) { 812 case IN_PID: 813 mem_reads8(hcd->regs, qtd->payload_addr, 814 qtd->data_buffer, 815 qtd->actual_length); 816 /* Fall through (?) */ 817 case OUT_PID: 818 qtd->urb->actual_length += 819 qtd->actual_length; 820 /* Fall through ... */ 821 case SETUP_PID: 822 break; 823 } 824 } 825 826 if (is_short_bulk(qtd)) { 827 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) 828 qtd->urb->status = -EREMOTEIO; 829 if (!last_qtd) 830 qtd_next->status = QTD_RETIRE; 831 } 832 } 833 834 if (qtd->payload_addr) 835 free_mem(hcd, qtd); 836 837 if (last_qtd) { 838 if ((qtd->status == QTD_RETIRE) && 839 (qtd->urb->status == -EINPROGRESS)) 840 qtd->urb->status = -EPIPE; 841 /* Defer calling of urb_done() since it releases lock */ 842 urb_listitem = kmem_cache_zalloc(urb_listitem_cachep, 843 GFP_ATOMIC); 844 if (unlikely(!urb_listitem)) 845 break; /* Try again on next call */ 846 urb_listitem->urb = qtd->urb; 847 list_add_tail(&urb_listitem->urb_list, urb_list); 848 } 849 850 list_del(&qtd->qtd_list); 851 qtd_free(qtd); 852 } 853} 854 855#define ENQUEUE_DEPTH 2 856static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) 857{ 858 struct isp1760_hcd *priv = hcd_to_priv(hcd); 859 int ptd_offset; 860 struct slotinfo *slots; 861 int curr_slot, free_slot; 862 int n; 863 struct ptd ptd; 864 struct isp1760_qtd *qtd; 865 866 if (unlikely(list_empty(&qh->qtd_list))) { 867 WARN_ON(1); 868 return; 869 } 870 871 /* Make sure this endpoint's TT buffer is clean before queueing ptds */ 872 if (qh->tt_buffer_dirty) 873 return; 874 875 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, 876 qtd_list)->urb->pipe)) { 877 ptd_offset = INT_PTD_OFFSET; 878 slots = priv->int_slots; 879 } else { 880 ptd_offset = ATL_PTD_OFFSET; 881 slots = priv->atl_slots; 882 } 883 884 free_slot = -1; 885 for (curr_slot = 0; curr_slot < 32; curr_slot++) { 886 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) 887 free_slot = curr_slot; 888 if (slots[curr_slot].qh == qh) 889 break; 890 } 891 892 n = 0; 893 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { 894 if (qtd->status == QTD_ENQUEUED) { 895 WARN_ON(qtd->payload_addr); 896 alloc_mem(hcd, qtd); 897 if ((qtd->length) && (!qtd->payload_addr)) 898 break; 899 900 if ((qtd->length) && 901 ((qtd->packet_type == SETUP_PID) || 902 (qtd->packet_type == OUT_PID))) { 903 mem_writes8(hcd->regs, qtd->payload_addr, 904 qtd->data_buffer, qtd->length); 905 } 906 907 qtd->status = QTD_PAYLOAD_ALLOC; 908 } 909 910 if (qtd->status == QTD_PAYLOAD_ALLOC) { 911/* 912 if ((curr_slot > 31) && (free_slot == -1)) 913 dev_dbg(hcd->self.controller, "%s: No slot " 914 "available for transfer\n", __func__); 915*/ 916 /* Start xfer for this endpoint if not already done */ 917 if ((curr_slot > 31) && (free_slot > -1)) { 918 if (usb_pipeint(qtd->urb->pipe)) 919 create_ptd_int(qh, qtd, &ptd); 920 else 921 create_ptd_atl(qh, qtd, &ptd); 922 923 start_bus_transfer(hcd, ptd_offset, free_slot, 924 slots, qtd, qh, &ptd); 925 curr_slot = free_slot; 926 } 927 928 n++; 929 if (n >= ENQUEUE_DEPTH) 930 break; 931 } 932 } 933} 934 935void schedule_ptds(struct usb_hcd *hcd) 936{ 937 struct isp1760_hcd *priv; 938 struct isp1760_qh *qh, *qh_next; 939 struct list_head *ep_queue; 940 LIST_HEAD(urb_list); 941 struct urb_listitem *urb_listitem, *urb_listitem_next; 942 int i; 943 944 if (!hcd) { 945 WARN_ON(1); 946 return; 947 } 948 949 priv = hcd_to_priv(hcd); 950 951 /* 952 * check finished/retired xfers, transfer payloads, call urb_done() 953 */ 954 for (i = 0; i < QH_END; i++) { 955 ep_queue = &priv->qh_list[i]; 956 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) { 957 collect_qtds(hcd, qh, &urb_list); 958 if (list_empty(&qh->qtd_list)) 959 list_del(&qh->qh_list); 960 } 961 } 962 963 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, 964 urb_list) { 965 isp1760_urb_done(hcd, urb_listitem->urb); 966 kmem_cache_free(urb_listitem_cachep, urb_listitem); 967 } 968 969 /* 970 * Schedule packets for transfer. 971 * 972 * According to USB2.0 specification: 973 * 974 * 1st prio: interrupt xfers, up to 80 % of bandwidth 975 * 2nd prio: control xfers 976 * 3rd prio: bulk xfers 977 * 978 * ... but let's use a simpler scheme here (mostly because ISP1761 doc 979 * is very unclear on how to prioritize traffic): 980 * 981 * 1) Enqueue any queued control transfers, as long as payload chip mem 982 * and PTD ATL slots are available. 983 * 2) Enqueue any queued INT transfers, as long as payload chip mem 984 * and PTD INT slots are available. 985 * 3) Enqueue any queued bulk transfers, as long as payload chip mem 986 * and PTD ATL slots are available. 987 * 988 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between 989 * conservation of chip mem and performance. 990 * 991 * I'm sure this scheme could be improved upon! 992 */ 993 for (i = 0; i < QH_END; i++) { 994 ep_queue = &priv->qh_list[i]; 995 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) 996 enqueue_qtds(hcd, qh); 997 } 998} 999 1000#define PTD_STATE_QTD_DONE 1 1001#define PTD_STATE_QTD_RELOAD 2 1002#define PTD_STATE_URB_RETIRE 3 1003 1004static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, 1005 struct urb *urb) 1006{ 1007 __dw dw4; 1008 int i; 1009 1010 dw4 = ptd->dw4; 1011 dw4 >>= 8; 1012 1013 /* FIXME: ISP1761 datasheet does not say what to do with these. Do we 1014 need to handle these errors? Is it done in hardware? */ 1015 1016 if (ptd->dw3 & DW3_HALT_BIT) { 1017 1018 urb->status = -EPROTO; /* Default unknown error */ 1019 1020 for (i = 0; i < 8; i++) { 1021 switch (dw4 & 0x7) { 1022 case INT_UNDERRUN: 1023 dev_dbg(hcd->self.controller, "%s: underrun " 1024 "during uFrame %d\n", 1025 __func__, i); 1026 urb->status = -ECOMM; /* Could not write data */ 1027 break; 1028 case INT_EXACT: 1029 dev_dbg(hcd->self.controller, "%s: transaction " 1030 "error during uFrame %d\n", 1031 __func__, i); 1032 urb->status = -EPROTO; /* timeout, bad CRC, PID 1033 error etc. */ 1034 break; 1035 case INT_BABBLE: 1036 dev_dbg(hcd->self.controller, "%s: babble " 1037 "error during uFrame %d\n", 1038 __func__, i); 1039 urb->status = -EOVERFLOW; 1040 break; 1041 } 1042 dw4 >>= 3; 1043 } 1044 1045 return PTD_STATE_URB_RETIRE; 1046 } 1047 1048 return PTD_STATE_QTD_DONE; 1049} 1050 1051static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, 1052 struct urb *urb) 1053{ 1054 WARN_ON(!ptd); 1055 if (ptd->dw3 & DW3_HALT_BIT) { 1056 if (ptd->dw3 & DW3_BABBLE_BIT) 1057 urb->status = -EOVERFLOW; 1058 else if (FROM_DW3_CERR(ptd->dw3)) 1059 urb->status = -EPIPE; /* Stall */ 1060 else if (ptd->dw3 & DW3_ERROR_BIT) 1061 urb->status = -EPROTO; /* XactErr */ 1062 else 1063 urb->status = -EPROTO; /* Unknown */ 1064/* 1065 dev_dbg(hcd->self.controller, "%s: ptd error:\n" 1066 " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" 1067 " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", 1068 __func__, 1069 ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, 1070 ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); 1071*/ 1072 return PTD_STATE_URB_RETIRE; 1073 } 1074 1075 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) { 1076 /* Transfer Error, *but* active and no HALT -> reload */ 1077 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n"); 1078 return PTD_STATE_QTD_RELOAD; 1079 } 1080 1081 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) { 1082 /* 1083 * NAKs are handled in HW by the chip. Usually if the 1084 * device is not able to send data fast enough. 1085 * This happens mostly on slower hardware. 1086 */ 1087 return PTD_STATE_QTD_RELOAD; 1088 } 1089 1090 return PTD_STATE_QTD_DONE; 1091} 1092 1093static void handle_done_ptds(struct usb_hcd *hcd) 1094{ 1095 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1096 struct ptd ptd; 1097 struct isp1760_qh *qh; 1098 int slot; 1099 int state; 1100 struct slotinfo *slots; 1101 u32 ptd_offset; 1102 struct isp1760_qtd *qtd; 1103 int modified; 1104 int skip_map; 1105 1106 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); 1107 priv->int_done_map &= ~skip_map; 1108 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); 1109 priv->atl_done_map &= ~skip_map; 1110 1111 modified = priv->int_done_map || priv->atl_done_map; 1112 1113 while (priv->int_done_map || priv->atl_done_map) { 1114 if (priv->int_done_map) { 1115 /* INT ptd */ 1116 slot = __ffs(priv->int_done_map); 1117 priv->int_done_map &= ~(1 << slot); 1118 slots = priv->int_slots; 1119 /* This should not trigger, and could be removed if 1120 noone have any problems with it triggering: */ 1121 if (!slots[slot].qh) { 1122 WARN_ON(1); 1123 continue; 1124 } 1125 ptd_offset = INT_PTD_OFFSET; 1126 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd); 1127 state = check_int_transfer(hcd, &ptd, 1128 slots[slot].qtd->urb); 1129 } else { 1130 /* ATL ptd */ 1131 slot = __ffs(priv->atl_done_map); 1132 priv->atl_done_map &= ~(1 << slot); 1133 slots = priv->atl_slots; 1134 /* This should not trigger, and could be removed if 1135 noone have any problems with it triggering: */ 1136 if (!slots[slot].qh) { 1137 WARN_ON(1); 1138 continue; 1139 } 1140 ptd_offset = ATL_PTD_OFFSET; 1141 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); 1142 state = check_atl_transfer(hcd, &ptd, 1143 slots[slot].qtd->urb); 1144 } 1145 1146 qtd = slots[slot].qtd; 1147 slots[slot].qtd = NULL; 1148 qh = slots[slot].qh; 1149 slots[slot].qh = NULL; 1150 qh->slot = -1; 1151 1152 WARN_ON(qtd->status != QTD_XFER_STARTED); 1153 1154 switch (state) { 1155 case PTD_STATE_QTD_DONE: 1156 if ((usb_pipeint(qtd->urb->pipe)) && 1157 (qtd->urb->dev->speed != USB_SPEED_HIGH)) 1158 qtd->actual_length = 1159 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); 1160 else 1161 qtd->actual_length = 1162 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); 1163 1164 qtd->status = QTD_XFER_COMPLETE; 1165 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || 1166 is_short_bulk(qtd)) 1167 qtd = NULL; 1168 else 1169 qtd = list_entry(qtd->qtd_list.next, 1170 typeof(*qtd), qtd_list); 1171 1172 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); 1173 qh->ping = FROM_DW3_PING(ptd.dw3); 1174 break; 1175 1176 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ 1177 qtd->status = QTD_PAYLOAD_ALLOC; 1178 ptd.dw0 |= DW0_VALID_BIT; 1179 /* RL counter = ERR counter */ 1180 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); 1181 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); 1182 ptd.dw3 &= ~TO_DW3_CERR(3); 1183 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); 1184 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); 1185 qh->ping = FROM_DW3_PING(ptd.dw3); 1186 break; 1187 1188 case PTD_STATE_URB_RETIRE: 1189 qtd->status = QTD_RETIRE; 1190 if ((qtd->urb->dev->speed != USB_SPEED_HIGH) && 1191 (qtd->urb->status != -EPIPE) && 1192 (qtd->urb->status != -EREMOTEIO)) { 1193 qh->tt_buffer_dirty = 1; 1194 if (usb_hub_clear_tt_buffer(qtd->urb)) 1195 /* Clear failed; let's hope things work 1196 anyway */ 1197 qh->tt_buffer_dirty = 0; 1198 } 1199 qtd = NULL; 1200 qh->toggle = 0; 1201 qh->ping = 0; 1202 break; 1203 1204 default: 1205 WARN_ON(1); 1206 continue; 1207 } 1208 1209 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) { 1210 if (slots == priv->int_slots) { 1211 if (state == PTD_STATE_QTD_RELOAD) 1212 dev_err(hcd->self.controller, 1213 "%s: PTD_STATE_QTD_RELOAD on " 1214 "interrupt packet\n", __func__); 1215 if (state != PTD_STATE_QTD_RELOAD) 1216 create_ptd_int(qh, qtd, &ptd); 1217 } else { 1218 if (state != PTD_STATE_QTD_RELOAD) 1219 create_ptd_atl(qh, qtd, &ptd); 1220 } 1221 1222 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, 1223 qh, &ptd); 1224 } 1225 } 1226 1227 if (modified) 1228 schedule_ptds(hcd); 1229} 1230 1231static irqreturn_t isp1760_irq(struct usb_hcd *hcd) 1232{ 1233 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1234 u32 imask; 1235 irqreturn_t irqret = IRQ_NONE; 1236 1237 spin_lock(&priv->lock); 1238 1239 if (!(hcd->state & HC_STATE_RUNNING)) 1240 goto leave; 1241 1242 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG); 1243 if (unlikely(!imask)) 1244 goto leave; 1245 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */ 1246 1247 priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG); 1248 priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG); 1249 1250 handle_done_ptds(hcd); 1251 1252 irqret = IRQ_HANDLED; 1253leave: 1254 spin_unlock(&priv->lock); 1255 1256 return irqret; 1257} 1258 1259/* 1260 * Workaround for problem described in chip errata 2: 1261 * 1262 * Sometimes interrupts are not generated when ATL (not INT?) completion occurs. 1263 * One solution suggested in the errata is to use SOF interrupts _instead_of_ 1264 * ATL done interrupts (the "instead of" might be important since it seems 1265 * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget" 1266 * to set the PTD's done bit in addition to not generating an interrupt!). 1267 * 1268 * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their 1269 * done bit is not being set. This is bad - it blocks the endpoint until reboot. 1270 * 1271 * If we use SOF interrupts only, we get latency between ptd completion and the 1272 * actual handling. This is very noticeable in testusb runs which takes several 1273 * minutes longer without ATL interrupts. 1274 * 1275 * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it 1276 * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the 1277 * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered 1278 * completed and its done map bit is set. 1279 * 1280 * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen 1281 * not to cause too much lag when this HW bug occurs, while still hopefully 1282 * ensuring that the check does not falsely trigger. 1283 */ 1284#define SLOT_TIMEOUT 300 1285#define SLOT_CHECK_PERIOD 200 1286static struct timer_list errata2_timer; 1287 1288void errata2_function(unsigned long data) 1289{ 1290 struct usb_hcd *hcd = (struct usb_hcd *) data; 1291 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1292 int slot; 1293 struct ptd ptd; 1294 unsigned long spinflags; 1295 1296 spin_lock_irqsave(&priv->lock, spinflags); 1297 1298 for (slot = 0; slot < 32; slot++) 1299 if (priv->atl_slots[slot].qh && time_after(jiffies, 1300 priv->atl_slots[slot].timestamp + 1301 SLOT_TIMEOUT * HZ / 1000)) { 1302 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); 1303 if (!FROM_DW0_VALID(ptd.dw0) && 1304 !FROM_DW3_ACTIVE(ptd.dw3)) 1305 priv->atl_done_map |= 1 << slot; 1306 } 1307 1308 if (priv->atl_done_map) 1309 handle_done_ptds(hcd); 1310 1311 spin_unlock_irqrestore(&priv->lock, spinflags); 1312 1313 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000; 1314 add_timer(&errata2_timer); 1315} 1316 1317static int isp1760_run(struct usb_hcd *hcd) 1318{ 1319 int retval; 1320 u32 temp; 1321 u32 command; 1322 u32 chipid; 1323 1324 hcd->uses_new_polling = 1; 1325 1326 hcd->state = HC_STATE_RUNNING; 1327 1328 /* Set PTD interrupt AND & OR maps */ 1329 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0); 1330 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff); 1331 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0); 1332 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff); 1333 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0); 1334 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff); 1335 /* step 23 passed */ 1336 1337 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); 1338 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN); 1339 1340 command = reg_read32(hcd->regs, HC_USBCMD); 1341 command &= ~(CMD_LRESET|CMD_RESET); 1342 command |= CMD_RUN; 1343 reg_write32(hcd->regs, HC_USBCMD, command); 1344 1345 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000); 1346 if (retval) 1347 return retval; 1348 1349 /* 1350 * XXX 1351 * Spec says to write FLAG_CF as last config action, priv code grabs 1352 * the semaphore while doing so. 1353 */ 1354 down_write(&ehci_cf_port_reset_rwsem); 1355 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF); 1356 1357 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000); 1358 up_write(&ehci_cf_port_reset_rwsem); 1359 if (retval) 1360 return retval; 1361 1362 init_timer(&errata2_timer); 1363 errata2_timer.function = errata2_function; 1364 errata2_timer.data = (unsigned long) hcd; 1365 errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000; 1366 add_timer(&errata2_timer); 1367 1368 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG); 1369 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n", 1370 chipid & 0xffff, chipid >> 16); 1371 1372 /* PTD Register Init Part 2, Step 28 */ 1373 1374 /* Setup registers controlling PTD checking */ 1375 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000); 1376 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000); 1377 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001); 1378 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff); 1379 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff); 1380 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff); 1381 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 1382 ATL_BUF_FILL | INT_BUF_FILL); 1383 1384 /* GRR this is run-once init(), being done every time the HC starts. 1385 * So long as they're part of class devices, we can't do it init() 1386 * since the class device isn't created that early. 1387 */ 1388 return 0; 1389} 1390 1391static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) 1392{ 1393 qtd->data_buffer = databuffer; 1394 1395 if (len > MAX_PAYLOAD_SIZE) 1396 len = MAX_PAYLOAD_SIZE; 1397 qtd->length = len; 1398 1399 return qtd->length; 1400} 1401 1402static void qtd_list_free(struct list_head *qtd_list) 1403{ 1404 struct isp1760_qtd *qtd, *qtd_next; 1405 1406 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { 1407 list_del(&qtd->qtd_list); 1408 qtd_free(qtd); 1409 } 1410} 1411 1412/* 1413 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. 1414 * Also calculate the PID type (SETUP/IN/OUT) for each packet. 1415 */ 1416#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) 1417static void packetize_urb(struct usb_hcd *hcd, 1418 struct urb *urb, struct list_head *head, gfp_t flags) 1419{ 1420 struct isp1760_qtd *qtd; 1421 void *buf; 1422 int len, maxpacketsize; 1423 u8 packet_type; 1424 1425 /* 1426 * URBs map to sequences of QTDs: one logical transaction 1427 */ 1428 1429 if (!urb->transfer_buffer && urb->transfer_buffer_length) { 1430 /* XXX This looks like usb storage / SCSI bug */ 1431 dev_err(hcd->self.controller, 1432 "buf is null, dma is %08lx len is %d\n", 1433 (long unsigned)urb->transfer_dma, 1434 urb->transfer_buffer_length); 1435 WARN_ON(1); 1436 } 1437 1438 if (usb_pipein(urb->pipe)) 1439 packet_type = IN_PID; 1440 else 1441 packet_type = OUT_PID; 1442 1443 if (usb_pipecontrol(urb->pipe)) { 1444 qtd = qtd_alloc(flags, urb, SETUP_PID); 1445 if (!qtd) 1446 goto cleanup; 1447 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); 1448 list_add_tail(&qtd->qtd_list, head); 1449 1450 /* for zero length DATA stages, STATUS is always IN */ 1451 if (urb->transfer_buffer_length == 0) 1452 packet_type = IN_PID; 1453 } 1454 1455 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe, 1456 usb_pipeout(urb->pipe))); 1457 1458 /* 1459 * buffer gets wrapped in one or more qtds; 1460 * last one may be "short" (including zero len) 1461 * and may serve as a control status ack 1462 */ 1463 buf = urb->transfer_buffer; 1464 len = urb->transfer_buffer_length; 1465 1466 for (;;) { 1467 int this_qtd_len; 1468 1469 qtd = qtd_alloc(flags, urb, packet_type); 1470 if (!qtd) 1471 goto cleanup; 1472 this_qtd_len = qtd_fill(qtd, buf, len); 1473 list_add_tail(&qtd->qtd_list, head); 1474 1475 len -= this_qtd_len; 1476 buf += this_qtd_len; 1477 1478 if (len <= 0) 1479 break; 1480 } 1481 1482 /* 1483 * control requests may need a terminating data "status" ack; 1484 * bulk ones may need a terminating short packet (zero length). 1485 */ 1486 if (urb->transfer_buffer_length != 0) { 1487 int one_more = 0; 1488 1489 if (usb_pipecontrol(urb->pipe)) { 1490 one_more = 1; 1491 if (packet_type == IN_PID) 1492 packet_type = OUT_PID; 1493 else 1494 packet_type = IN_PID; 1495 } else if (usb_pipebulk(urb->pipe) 1496 && (urb->transfer_flags & URB_ZERO_PACKET) 1497 && !(urb->transfer_buffer_length % 1498 maxpacketsize)) { 1499 one_more = 1; 1500 } 1501 if (one_more) { 1502 qtd = qtd_alloc(flags, urb, packet_type); 1503 if (!qtd) 1504 goto cleanup; 1505 1506 /* never any data in such packets */ 1507 qtd_fill(qtd, NULL, 0); 1508 list_add_tail(&qtd->qtd_list, head); 1509 } 1510 } 1511 1512 return; 1513 1514cleanup: 1515 qtd_list_free(head); 1516} 1517 1518static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 1519 gfp_t mem_flags) 1520{ 1521 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1522 struct list_head *ep_queue; 1523 struct isp1760_qh *qh, *qhit; 1524 unsigned long spinflags; 1525 LIST_HEAD(new_qtds); 1526 int retval; 1527 int qh_in_queue; 1528 1529 switch (usb_pipetype(urb->pipe)) { 1530 case PIPE_CONTROL: 1531 ep_queue = &priv->qh_list[QH_CONTROL]; 1532 break; 1533 case PIPE_BULK: 1534 ep_queue = &priv->qh_list[QH_BULK]; 1535 break; 1536 case PIPE_INTERRUPT: 1537 if (urb->interval < 0) 1538 return -EINVAL; 1539 /* FIXME: Check bandwidth */ 1540 ep_queue = &priv->qh_list[QH_INTERRUPT]; 1541 break; 1542 case PIPE_ISOCHRONOUS: 1543 dev_err(hcd->self.controller, "%s: isochronous USB packets " 1544 "not yet supported\n", 1545 __func__); 1546 return -EPIPE; 1547 default: 1548 dev_err(hcd->self.controller, "%s: unknown pipe type\n", 1549 __func__); 1550 return -EPIPE; 1551 } 1552 1553 if (usb_pipein(urb->pipe)) 1554 urb->actual_length = 0; 1555 1556 packetize_urb(hcd, urb, &new_qtds, mem_flags); 1557 if (list_empty(&new_qtds)) 1558 return -ENOMEM; 1559 1560 retval = 0; 1561 spin_lock_irqsave(&priv->lock, spinflags); 1562 1563 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { 1564 retval = -ESHUTDOWN; 1565 goto out; 1566 } 1567 retval = usb_hcd_link_urb_to_ep(hcd, urb); 1568 if (retval) 1569 goto out; 1570 1571 qh = urb->ep->hcpriv; 1572 if (qh) { 1573 qh_in_queue = 0; 1574 list_for_each_entry(qhit, ep_queue, qh_list) { 1575 if (qhit == qh) { 1576 qh_in_queue = 1; 1577 break; 1578 } 1579 } 1580 if (!qh_in_queue) 1581 list_add_tail(&qh->qh_list, ep_queue); 1582 } else { 1583 qh = qh_alloc(GFP_ATOMIC); 1584 if (!qh) { 1585 retval = -ENOMEM; 1586 usb_hcd_unlink_urb_from_ep(hcd, urb); 1587 goto out; 1588 } 1589 list_add_tail(&qh->qh_list, ep_queue); 1590 urb->ep->hcpriv = qh; 1591 } 1592 1593 list_splice_tail(&new_qtds, &qh->qtd_list); 1594 schedule_ptds(hcd); 1595 1596out: 1597 spin_unlock_irqrestore(&priv->lock, spinflags); 1598 return retval; 1599} 1600 1601static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, 1602 struct isp1760_qh *qh) 1603{ 1604 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1605 int skip_map; 1606 1607 WARN_ON(qh->slot == -1); 1608 1609 /* We need to forcefully reclaim the slot since some transfers never 1610 return, e.g. interrupt transfers and NAKed bulk transfers. */ 1611 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { 1612 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); 1613 skip_map |= (1 << qh->slot); 1614 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); 1615 priv->atl_slots[qh->slot].qh = NULL; 1616 priv->atl_slots[qh->slot].qtd = NULL; 1617 } else { 1618 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); 1619 skip_map |= (1 << qh->slot); 1620 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); 1621 priv->int_slots[qh->slot].qh = NULL; 1622 priv->int_slots[qh->slot].qtd = NULL; 1623 } 1624 1625 qh->slot = -1; 1626} 1627 1628/* 1629 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing 1630 * any active transfer belonging to the urb in the process. 1631 */ 1632static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, 1633 struct isp1760_qtd *qtd) 1634{ 1635 struct urb *urb; 1636 int urb_was_running; 1637 1638 urb = qtd->urb; 1639 urb_was_running = 0; 1640 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) { 1641 if (qtd->urb != urb) 1642 break; 1643 1644 if (qtd->status >= QTD_XFER_STARTED) 1645 urb_was_running = 1; 1646 if (last_qtd_of_urb(qtd, qh) && 1647 (qtd->status >= QTD_XFER_COMPLETE)) 1648 urb_was_running = 0; 1649 1650 if (qtd->status == QTD_XFER_STARTED) 1651 kill_transfer(hcd, urb, qh); 1652 qtd->status = QTD_RETIRE; 1653 } 1654 1655 if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) { 1656 qh->tt_buffer_dirty = 1; 1657 if (usb_hub_clear_tt_buffer(urb)) 1658 /* Clear failed; let's hope things work anyway */ 1659 qh->tt_buffer_dirty = 0; 1660 } 1661} 1662 1663static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 1664 int status) 1665{ 1666 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1667 unsigned long spinflags; 1668 struct isp1760_qh *qh; 1669 struct isp1760_qtd *qtd; 1670 int retval = 0; 1671 1672 spin_lock_irqsave(&priv->lock, spinflags); 1673 retval = usb_hcd_check_unlink_urb(hcd, urb, status); 1674 if (retval) 1675 goto out; 1676 1677 qh = urb->ep->hcpriv; 1678 if (!qh) { 1679 retval = -EINVAL; 1680 goto out; 1681 } 1682 1683 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) 1684 if (qtd->urb == urb) { 1685 dequeue_urb_from_qtd(hcd, qh, qtd); 1686 break; 1687 } 1688 1689 urb->status = status; 1690 schedule_ptds(hcd); 1691 1692out: 1693 spin_unlock_irqrestore(&priv->lock, spinflags); 1694 return retval; 1695} 1696 1697static void isp1760_endpoint_disable(struct usb_hcd *hcd, 1698 struct usb_host_endpoint *ep) 1699{ 1700 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1701 unsigned long spinflags; 1702 struct isp1760_qh *qh, *qh_iter; 1703 int i; 1704 1705 spin_lock_irqsave(&priv->lock, spinflags); 1706 1707 qh = ep->hcpriv; 1708 if (!qh) 1709 goto out; 1710 1711 WARN_ON(!list_empty(&qh->qtd_list)); 1712 1713 for (i = 0; i < QH_END; i++) 1714 list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list) 1715 if (qh_iter == qh) { 1716 list_del(&qh_iter->qh_list); 1717 i = QH_END; 1718 break; 1719 } 1720 qh_free(qh); 1721 ep->hcpriv = NULL; 1722 1723 schedule_ptds(hcd); 1724 1725out: 1726 spin_unlock_irqrestore(&priv->lock, spinflags); 1727} 1728 1729static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) 1730{ 1731 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1732 u32 temp, status = 0; 1733 u32 mask; 1734 int retval = 1; 1735 unsigned long flags; 1736 1737 /* if !USB_SUSPEND, root hub timers won't get shut down ... */ 1738 if (!HC_IS_RUNNING(hcd->state)) 1739 return 0; 1740 1741 /* init status to no-changes */ 1742 buf[0] = 0; 1743 mask = PORT_CSC; 1744 1745 spin_lock_irqsave(&priv->lock, flags); 1746 temp = reg_read32(hcd->regs, HC_PORTSC1); 1747 1748 if (temp & PORT_OWNER) { 1749 if (temp & PORT_CSC) { 1750 temp &= ~PORT_CSC; 1751 reg_write32(hcd->regs, HC_PORTSC1, temp); 1752 goto done; 1753 } 1754 } 1755 1756 /* 1757 * Return status information even for ports with OWNER set. 1758 * Otherwise khubd wouldn't see the disconnect event when a 1759 * high-speed device is switched over to the companion 1760 * controller by the user. 1761 */ 1762 1763 if ((temp & mask) != 0 1764 || ((temp & PORT_RESUME) != 0 1765 && time_after_eq(jiffies, 1766 priv->reset_done))) { 1767 buf [0] |= 1 << (0 + 1); 1768 status = STS_PCD; 1769 } 1770 /* FIXME autosuspend idle root hubs */ 1771done: 1772 spin_unlock_irqrestore(&priv->lock, flags); 1773 return status ? retval : 0; 1774} 1775 1776static void isp1760_hub_descriptor(struct isp1760_hcd *priv, 1777 struct usb_hub_descriptor *desc) 1778{ 1779 int ports = HCS_N_PORTS(priv->hcs_params); 1780 u16 temp; 1781 1782 desc->bDescriptorType = 0x29; 1783 /* priv 1.0, 2.3.9 says 20ms max */ 1784 desc->bPwrOn2PwrGood = 10; 1785 desc->bHubContrCurrent = 0; 1786 1787 desc->bNbrPorts = ports; 1788 temp = 1 + (ports / 8); 1789 desc->bDescLength = 7 + 2 * temp; 1790 1791 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ 1792 memset(&desc->u.hs.DeviceRemovable[0], 0, temp); 1793 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); 1794 1795 /* per-port overcurrent reporting */ 1796 temp = 0x0008; 1797 if (HCS_PPC(priv->hcs_params)) 1798 /* per-port power control */ 1799 temp |= 0x0001; 1800 else 1801 /* no power switching */ 1802 temp |= 0x0002; 1803 desc->wHubCharacteristics = cpu_to_le16(temp); 1804} 1805 1806#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) 1807 1808static int check_reset_complete(struct usb_hcd *hcd, int index, 1809 int port_status) 1810{ 1811 if (!(port_status & PORT_CONNECT)) 1812 return port_status; 1813 1814 /* if reset finished and it's still not enabled -- handoff */ 1815 if (!(port_status & PORT_PE)) { 1816 1817 dev_info(hcd->self.controller, 1818 "port %d full speed --> companion\n", 1819 index + 1); 1820 1821 port_status |= PORT_OWNER; 1822 port_status &= ~PORT_RWC_BITS; 1823 reg_write32(hcd->regs, HC_PORTSC1, port_status); 1824 1825 } else 1826 dev_info(hcd->self.controller, "port %d high speed\n", 1827 index + 1); 1828 1829 return port_status; 1830} 1831 1832static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, 1833 u16 wValue, u16 wIndex, char *buf, u16 wLength) 1834{ 1835 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1836 int ports = HCS_N_PORTS(priv->hcs_params); 1837 u32 temp, status; 1838 unsigned long flags; 1839 int retval = 0; 1840 unsigned selector; 1841 1842 /* 1843 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. 1844 * HCS_INDICATOR may say we can change LEDs to off/amber/green. 1845 * (track current state ourselves) ... blink for diagnostics, 1846 * power, "this is the one", etc. EHCI spec supports this. 1847 */ 1848 1849 spin_lock_irqsave(&priv->lock, flags); 1850 switch (typeReq) { 1851 case ClearHubFeature: 1852 switch (wValue) { 1853 case C_HUB_LOCAL_POWER: 1854 case C_HUB_OVER_CURRENT: 1855 /* no hub-wide feature/status flags */ 1856 break; 1857 default: 1858 goto error; 1859 } 1860 break; 1861 case ClearPortFeature: 1862 if (!wIndex || wIndex > ports) 1863 goto error; 1864 wIndex--; 1865 temp = reg_read32(hcd->regs, HC_PORTSC1); 1866 1867 /* 1868 * Even if OWNER is set, so the port is owned by the 1869 * companion controller, khubd needs to be able to clear 1870 * the port-change status bits (especially 1871 * USB_PORT_STAT_C_CONNECTION). 1872 */ 1873 1874 switch (wValue) { 1875 case USB_PORT_FEAT_ENABLE: 1876 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE); 1877 break; 1878 case USB_PORT_FEAT_C_ENABLE: 1879 /* XXX error? */ 1880 break; 1881 case USB_PORT_FEAT_SUSPEND: 1882 if (temp & PORT_RESET) 1883 goto error; 1884 1885 if (temp & PORT_SUSPEND) { 1886 if ((temp & PORT_PE) == 0) 1887 goto error; 1888 /* resume signaling for 20 msec */ 1889 temp &= ~(PORT_RWC_BITS); 1890 reg_write32(hcd->regs, HC_PORTSC1, 1891 temp | PORT_RESUME); 1892 priv->reset_done = jiffies + 1893 msecs_to_jiffies(20); 1894 } 1895 break; 1896 case USB_PORT_FEAT_C_SUSPEND: 1897 /* we auto-clear this feature */ 1898 break; 1899 case USB_PORT_FEAT_POWER: 1900 if (HCS_PPC(priv->hcs_params)) 1901 reg_write32(hcd->regs, HC_PORTSC1, 1902 temp & ~PORT_POWER); 1903 break; 1904 case USB_PORT_FEAT_C_CONNECTION: 1905 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC); 1906 break; 1907 case USB_PORT_FEAT_C_OVER_CURRENT: 1908 /* XXX error ?*/ 1909 break; 1910 case USB_PORT_FEAT_C_RESET: 1911 /* GetPortStatus clears reset */ 1912 break; 1913 default: 1914 goto error; 1915 } 1916 reg_read32(hcd->regs, HC_USBCMD); 1917 break; 1918 case GetHubDescriptor: 1919 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) 1920 buf); 1921 break; 1922 case GetHubStatus: 1923 /* no hub-wide feature/status flags */ 1924 memset(buf, 0, 4); 1925 break; 1926 case GetPortStatus: 1927 if (!wIndex || wIndex > ports) 1928 goto error; 1929 wIndex--; 1930 status = 0; 1931 temp = reg_read32(hcd->regs, HC_PORTSC1); 1932 1933 /* wPortChange bits */ 1934 if (temp & PORT_CSC) 1935 status |= USB_PORT_STAT_C_CONNECTION << 16; 1936 1937 1938 /* whoever resumes must GetPortStatus to complete it!! */ 1939 if (temp & PORT_RESUME) { 1940 dev_err(hcd->self.controller, "Port resume should be skipped.\n"); 1941 1942 /* Remote Wakeup received? */ 1943 if (!priv->reset_done) { 1944 /* resume signaling for 20 msec */ 1945 priv->reset_done = jiffies 1946 + msecs_to_jiffies(20); 1947 /* check the port again */ 1948 mod_timer(&hcd->rh_timer, priv->reset_done); 1949 } 1950 1951 /* resume completed? */ 1952 else if (time_after_eq(jiffies, 1953 priv->reset_done)) { 1954 status |= USB_PORT_STAT_C_SUSPEND << 16; 1955 priv->reset_done = 0; 1956 1957 /* stop resume signaling */ 1958 temp = reg_read32(hcd->regs, HC_PORTSC1); 1959 reg_write32(hcd->regs, HC_PORTSC1, 1960 temp & ~(PORT_RWC_BITS | PORT_RESUME)); 1961 retval = handshake(hcd, HC_PORTSC1, 1962 PORT_RESUME, 0, 2000 /* 2msec */); 1963 if (retval != 0) { 1964 dev_err(hcd->self.controller, 1965 "port %d resume error %d\n", 1966 wIndex + 1, retval); 1967 goto error; 1968 } 1969 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); 1970 } 1971 } 1972 1973 /* whoever resets must GetPortStatus to complete it!! */ 1974 if ((temp & PORT_RESET) 1975 && time_after_eq(jiffies, 1976 priv->reset_done)) { 1977 status |= USB_PORT_STAT_C_RESET << 16; 1978 priv->reset_done = 0; 1979 1980 /* force reset to complete */ 1981 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET); 1982 /* REVISIT: some hardware needs 550+ usec to clear 1983 * this bit; seems too long to spin routinely... 1984 */ 1985 retval = handshake(hcd, HC_PORTSC1, 1986 PORT_RESET, 0, 750); 1987 if (retval != 0) { 1988 dev_err(hcd->self.controller, "port %d reset error %d\n", 1989 wIndex + 1, retval); 1990 goto error; 1991 } 1992 1993 /* see what we found out */ 1994 temp = check_reset_complete(hcd, wIndex, 1995 reg_read32(hcd->regs, HC_PORTSC1)); 1996 } 1997 /* 1998 * Even if OWNER is set, there's no harm letting khubd 1999 * see the wPortStatus values (they should all be 0 except 2000 * for PORT_POWER anyway). 2001 */ 2002 2003 if (temp & PORT_OWNER) 2004 dev_err(hcd->self.controller, "PORT_OWNER is set\n"); 2005 2006 if (temp & PORT_CONNECT) { 2007 status |= USB_PORT_STAT_CONNECTION; 2008 /* status may be from integrated TT */ 2009 status |= USB_PORT_STAT_HIGH_SPEED; 2010 } 2011 if (temp & PORT_PE) 2012 status |= USB_PORT_STAT_ENABLE; 2013 if (temp & (PORT_SUSPEND|PORT_RESUME)) 2014 status |= USB_PORT_STAT_SUSPEND; 2015 if (temp & PORT_RESET) 2016 status |= USB_PORT_STAT_RESET; 2017 if (temp & PORT_POWER) 2018 status |= USB_PORT_STAT_POWER; 2019 2020 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 2021 break; 2022 case SetHubFeature: 2023 switch (wValue) { 2024 case C_HUB_LOCAL_POWER: 2025 case C_HUB_OVER_CURRENT: 2026 /* no hub-wide feature/status flags */ 2027 break; 2028 default: 2029 goto error; 2030 } 2031 break; 2032 case SetPortFeature: 2033 selector = wIndex >> 8; 2034 wIndex &= 0xff; 2035 if (!wIndex || wIndex > ports) 2036 goto error; 2037 wIndex--; 2038 temp = reg_read32(hcd->regs, HC_PORTSC1); 2039 if (temp & PORT_OWNER) 2040 break; 2041 2042/* temp &= ~PORT_RWC_BITS; */ 2043 switch (wValue) { 2044 case USB_PORT_FEAT_ENABLE: 2045 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE); 2046 break; 2047 2048 case USB_PORT_FEAT_SUSPEND: 2049 if ((temp & PORT_PE) == 0 2050 || (temp & PORT_RESET) != 0) 2051 goto error; 2052 2053 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND); 2054 break; 2055 case USB_PORT_FEAT_POWER: 2056 if (HCS_PPC(priv->hcs_params)) 2057 reg_write32(hcd->regs, HC_PORTSC1, 2058 temp | PORT_POWER); 2059 break; 2060 case USB_PORT_FEAT_RESET: 2061 if (temp & PORT_RESUME) 2062 goto error; 2063 /* line status bits may report this as low speed, 2064 * which can be fine if this root hub has a 2065 * transaction translator built in. 2066 */ 2067 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT 2068 && PORT_USB11(temp)) { 2069 temp |= PORT_OWNER; 2070 } else { 2071 temp |= PORT_RESET; 2072 temp &= ~PORT_PE; 2073 2074 /* 2075 * caller must wait, then call GetPortStatus 2076 * usb 2.0 spec says 50 ms resets on root 2077 */ 2078 priv->reset_done = jiffies + 2079 msecs_to_jiffies(50); 2080 } 2081 reg_write32(hcd->regs, HC_PORTSC1, temp); 2082 break; 2083 default: 2084 goto error; 2085 } 2086 reg_read32(hcd->regs, HC_USBCMD); 2087 break; 2088 2089 default: 2090error: 2091 /* "stall" on error */ 2092 retval = -EPIPE; 2093 } 2094 spin_unlock_irqrestore(&priv->lock, flags); 2095 return retval; 2096} 2097 2098static int isp1760_get_frame(struct usb_hcd *hcd) 2099{ 2100 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2101 u32 fr; 2102 2103 fr = reg_read32(hcd->regs, HC_FRINDEX); 2104 return (fr >> 3) % priv->periodic_size; 2105} 2106 2107static void isp1760_stop(struct usb_hcd *hcd) 2108{ 2109 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2110 u32 temp; 2111 2112 del_timer(&errata2_timer); 2113 2114 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1, 2115 NULL, 0); 2116 mdelay(20); 2117 2118 spin_lock_irq(&priv->lock); 2119 ehci_reset(hcd); 2120 /* Disable IRQ */ 2121 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); 2122 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); 2123 spin_unlock_irq(&priv->lock); 2124 2125 reg_write32(hcd->regs, HC_CONFIGFLAG, 0); 2126} 2127 2128static void isp1760_shutdown(struct usb_hcd *hcd) 2129{ 2130 u32 command, temp; 2131 2132 isp1760_stop(hcd); 2133 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); 2134 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); 2135 2136 command = reg_read32(hcd->regs, HC_USBCMD); 2137 command &= ~CMD_RUN; 2138 reg_write32(hcd->regs, HC_USBCMD, command); 2139} 2140 2141static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd, 2142 struct usb_host_endpoint *ep) 2143{ 2144 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2145 struct isp1760_qh *qh = ep->hcpriv; 2146 unsigned long spinflags; 2147 2148 if (!qh) 2149 return; 2150 2151 spin_lock_irqsave(&priv->lock, spinflags); 2152 qh->tt_buffer_dirty = 0; 2153 schedule_ptds(hcd); 2154 spin_unlock_irqrestore(&priv->lock, spinflags); 2155} 2156 2157 2158static const struct hc_driver isp1760_hc_driver = { 2159 .description = "isp1760-hcd", 2160 .product_desc = "NXP ISP1760 USB Host Controller", 2161 .hcd_priv_size = sizeof(struct isp1760_hcd), 2162 .irq = isp1760_irq, 2163 .flags = HCD_MEMORY | HCD_USB2, 2164 .reset = isp1760_hc_setup, 2165 .start = isp1760_run, 2166 .stop = isp1760_stop, 2167 .shutdown = isp1760_shutdown, 2168 .urb_enqueue = isp1760_urb_enqueue, 2169 .urb_dequeue = isp1760_urb_dequeue, 2170 .endpoint_disable = isp1760_endpoint_disable, 2171 .get_frame_number = isp1760_get_frame, 2172 .hub_status_data = isp1760_hub_status_data, 2173 .hub_control = isp1760_hub_control, 2174 .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete, 2175}; 2176 2177int __init init_kmem_once(void) 2178{ 2179 urb_listitem_cachep = kmem_cache_create("isp1760 urb_listitem", 2180 sizeof(struct urb_listitem), 0, SLAB_TEMPORARY | 2181 SLAB_MEM_SPREAD, NULL); 2182 2183 if (!urb_listitem_cachep) 2184 return -ENOMEM; 2185 2186 qtd_cachep = kmem_cache_create("isp1760_qtd", 2187 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | 2188 SLAB_MEM_SPREAD, NULL); 2189 2190 if (!qtd_cachep) 2191 return -ENOMEM; 2192 2193 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), 2194 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); 2195 2196 if (!qh_cachep) { 2197 kmem_cache_destroy(qtd_cachep); 2198 return -ENOMEM; 2199 } 2200 2201 return 0; 2202} 2203 2204void deinit_kmem_cache(void) 2205{ 2206 kmem_cache_destroy(qtd_cachep); 2207 kmem_cache_destroy(qh_cachep); 2208 kmem_cache_destroy(urb_listitem_cachep); 2209} 2210 2211struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, 2212 int irq, unsigned long irqflags, 2213 int rst_gpio, 2214 struct device *dev, const char *busname, 2215 unsigned int devflags) 2216{ 2217 struct usb_hcd *hcd; 2218 struct isp1760_hcd *priv; 2219 int ret; 2220 2221 if (usb_disabled()) 2222 return ERR_PTR(-ENODEV); 2223 2224 /* prevent usb-core allocating DMA pages */ 2225 dev->dma_mask = NULL; 2226 2227 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev)); 2228 if (!hcd) 2229 return ERR_PTR(-ENOMEM); 2230 2231 priv = hcd_to_priv(hcd); 2232 priv->devflags = devflags; 2233 priv->rst_gpio = rst_gpio; 2234 init_memory(priv); 2235 hcd->regs = ioremap(res_start, res_len); 2236 if (!hcd->regs) { 2237 ret = -EIO; 2238 goto err_put; 2239 } 2240 2241 hcd->irq = irq; 2242 hcd->rsrc_start = res_start; 2243 hcd->rsrc_len = res_len; 2244 2245 ret = usb_add_hcd(hcd, irq, irqflags); 2246 if (ret) 2247 goto err_unmap; 2248 2249 return hcd; 2250 2251err_unmap: 2252 iounmap(hcd->regs); 2253 2254err_put: 2255 usb_put_hcd(hcd); 2256 2257 return ERR_PTR(ret); 2258} 2259 2260MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP"); 2261MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>"); 2262MODULE_LICENSE("GPL v2"); 2263