1/* 2 * xHCI host controller driver 3 * 4 * Copyright (C) 2008 Intel Corp. 5 * 6 * Author: Sarah Sharp 7 * Some code borrowed from the Linux EHCI driver. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23#include <linux/gfp.h> 24#include <asm/unaligned.h> 25 26#include "xhci.h" 27 28#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 29#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ 30 PORT_RC | PORT_PLC | PORT_PE) 31 32/* usb 1.1 root hub device descriptor */ 33static u8 usb_bos_descriptor [] = { 34 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ 35 USB_DT_BOS, /* __u8 bDescriptorType */ 36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ 37 0x1, /* __u8 bNumDeviceCaps */ 38 /* First device capability */ 39 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ 40 USB_DT_DEVICE_CAPABILITY, /* Device Capability */ 41 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ 42 0x00, /* bmAttributes, LTM off by default */ 43 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ 44 0x03, /* bFunctionalitySupport, 45 USB 3.0 speed only */ 46 0x00, /* bU1DevExitLat, set later. */ 47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */ 48}; 49 50 51static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, 52 struct usb_hub_descriptor *desc, int ports) 53{ 54 u16 temp; 55 56 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ 57 desc->bHubContrCurrent = 0; 58 59 desc->bNbrPorts = ports; 60 temp = 0; 61 /* Bits 1:0 - support per-port power switching, or power always on */ 62 if (HCC_PPC(xhci->hcc_params)) 63 temp |= HUB_CHAR_INDV_PORT_LPSM; 64 else 65 temp |= HUB_CHAR_NO_LPSM; 66 /* Bit 2 - root hubs are not part of a compound device */ 67 /* Bits 4:3 - individual port over current protection */ 68 temp |= HUB_CHAR_INDV_PORT_OCPM; 69 /* Bits 6:5 - no TTs in root ports */ 70 /* Bit 7 - no port indicators */ 71 desc->wHubCharacteristics = cpu_to_le16(temp); 72} 73 74/* Fill in the USB 2.0 roothub descriptor */ 75static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 76 struct usb_hub_descriptor *desc) 77{ 78 int ports; 79 u16 temp; 80 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; 81 u32 portsc; 82 unsigned int i; 83 84 ports = xhci->num_usb2_ports; 85 86 xhci_common_hub_descriptor(xhci, desc, ports); 87 desc->bDescriptorType = USB_DT_HUB; 88 temp = 1 + (ports / 8); 89 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; 90 91 /* The Device Removable bits are reported on a byte granularity. 92 * If the port doesn't exist within that byte, the bit is set to 0. 93 */ 94 memset(port_removable, 0, sizeof(port_removable)); 95 for (i = 0; i < ports; i++) { 96 portsc = xhci_readl(xhci, xhci->usb2_ports[i]); 97 /* If a device is removable, PORTSC reports a 0, same as in the 98 * hub descriptor DeviceRemovable bits. 99 */ 100 if (portsc & PORT_DEV_REMOVE) 101 /* This math is hairy because bit 0 of DeviceRemovable 102 * is reserved, and bit 1 is for port 1, etc. 103 */ 104 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); 105 } 106 107 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN 108 * ports on it. The USB 2.0 specification says that there are two 109 * variable length fields at the end of the hub descriptor: 110 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than 111 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array 112 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to 113 * 0xFF, so we initialize the both arrays (DeviceRemovable and 114 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each 115 * set of ports that actually exist. 116 */ 117 memset(desc->u.hs.DeviceRemovable, 0xff, 118 sizeof(desc->u.hs.DeviceRemovable)); 119 memset(desc->u.hs.PortPwrCtrlMask, 0xff, 120 sizeof(desc->u.hs.PortPwrCtrlMask)); 121 122 for (i = 0; i < (ports + 1 + 7) / 8; i++) 123 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], 124 sizeof(__u8)); 125} 126 127/* Fill in the USB 3.0 roothub descriptor */ 128static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 129 struct usb_hub_descriptor *desc) 130{ 131 int ports; 132 u16 port_removable; 133 u32 portsc; 134 unsigned int i; 135 136 ports = xhci->num_usb3_ports; 137 xhci_common_hub_descriptor(xhci, desc, ports); 138 desc->bDescriptorType = USB_DT_SS_HUB; 139 desc->bDescLength = USB_DT_SS_HUB_SIZE; 140 141 /* header decode latency should be zero for roothubs, 142 * see section 4.23.5.2. 143 */ 144 desc->u.ss.bHubHdrDecLat = 0; 145 desc->u.ss.wHubDelay = 0; 146 147 port_removable = 0; 148 /* bit 0 is reserved, bit 1 is for port 1, etc. */ 149 for (i = 0; i < ports; i++) { 150 portsc = xhci_readl(xhci, xhci->usb3_ports[i]); 151 if (portsc & PORT_DEV_REMOVE) 152 port_removable |= 1 << (i + 1); 153 } 154 memset(&desc->u.ss.DeviceRemovable, 155 (__force __u16) cpu_to_le16(port_removable), 156 sizeof(__u16)); 157} 158 159static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, 160 struct usb_hub_descriptor *desc) 161{ 162 163 if (hcd->speed == HCD_USB3) 164 xhci_usb3_hub_descriptor(hcd, xhci, desc); 165 else 166 xhci_usb2_hub_descriptor(hcd, xhci, desc); 167 168} 169 170static unsigned int xhci_port_speed(unsigned int port_status) 171{ 172 if (DEV_LOWSPEED(port_status)) 173 return USB_PORT_STAT_LOW_SPEED; 174 if (DEV_HIGHSPEED(port_status)) 175 return USB_PORT_STAT_HIGH_SPEED; 176 /* 177 * FIXME: Yes, we should check for full speed, but the core uses that as 178 * a default in portspeed() in usb/core/hub.c (which is the only place 179 * USB_PORT_STAT_*_SPEED is used). 180 */ 181 return 0; 182} 183 184/* 185 * These bits are Read Only (RO) and should be saved and written to the 186 * registers: 0, 3, 10:13, 30 187 * connect status, over-current status, port speed, and device removable. 188 * connect status and port speed are also sticky - meaning they're in 189 * the AUX well and they aren't changed by a hot, warm, or cold reset. 190 */ 191#define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) 192/* 193 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: 194 * bits 5:8, 9, 14:15, 25:27 195 * link state, port power, port indicator state, "wake on" enable state 196 */ 197#define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) 198/* 199 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: 200 * bit 4 (port reset) 201 */ 202#define XHCI_PORT_RW1S ((1<<4)) 203/* 204 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: 205 * bits 1, 17, 18, 19, 20, 21, 22, 23 206 * port enable/disable, and 207 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), 208 * over-current, reset, link state, and L1 change 209 */ 210#define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) 211/* 212 * Bit 16 is RW, and writing a '1' to it causes the link state control to be 213 * latched in 214 */ 215#define XHCI_PORT_RW ((1<<16)) 216/* 217 * These bits are Reserved Zero (RsvdZ) and zero should be written to them: 218 * bits 2, 24, 28:31 219 */ 220#define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) 221 222/* 223 * Given a port state, this function returns a value that would result in the 224 * port being in the same state, if the value was written to the port status 225 * control register. 226 * Save Read Only (RO) bits and save read/write bits where 227 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 228 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 229 */ 230u32 xhci_port_state_to_neutral(u32 state) 231{ 232 /* Save read-only status and port state */ 233 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 234} 235 236/* 237 * find slot id based on port number. 238 * @port: The one-based port number from one of the two split roothubs. 239 */ 240int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 241 u16 port) 242{ 243 int slot_id; 244 int i; 245 enum usb_device_speed speed; 246 247 slot_id = 0; 248 for (i = 0; i < MAX_HC_SLOTS; i++) { 249 if (!xhci->devs[i]) 250 continue; 251 speed = xhci->devs[i]->udev->speed; 252 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3)) 253 && xhci->devs[i]->fake_port == port) { 254 slot_id = i; 255 break; 256 } 257 } 258 259 return slot_id; 260} 261 262/* 263 * Stop device 264 * It issues stop endpoint command for EP 0 to 30. And wait the last command 265 * to complete. 266 * suspend will set to 1, if suspend bit need to set in command. 267 */ 268static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) 269{ 270 struct xhci_virt_device *virt_dev; 271 struct xhci_command *cmd; 272 unsigned long flags; 273 int timeleft; 274 int ret; 275 int i; 276 277 ret = 0; 278 virt_dev = xhci->devs[slot_id]; 279 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); 280 if (!cmd) { 281 xhci_dbg(xhci, "Couldn't allocate command structure.\n"); 282 return -ENOMEM; 283 } 284 285 spin_lock_irqsave(&xhci->lock, flags); 286 for (i = LAST_EP_INDEX; i > 0; i--) { 287 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) 288 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend); 289 } 290 cmd->command_trb = xhci->cmd_ring->enqueue; 291 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list); 292 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend); 293 xhci_ring_cmd_db(xhci); 294 spin_unlock_irqrestore(&xhci->lock, flags); 295 296 /* Wait for last stop endpoint command to finish */ 297 timeleft = wait_for_completion_interruptible_timeout( 298 cmd->completion, 299 USB_CTRL_SET_TIMEOUT); 300 if (timeleft <= 0) { 301 xhci_warn(xhci, "%s while waiting for stop endpoint command\n", 302 timeleft == 0 ? "Timeout" : "Signal"); 303 spin_lock_irqsave(&xhci->lock, flags); 304 /* The timeout might have raced with the event ring handler, so 305 * only delete from the list if the item isn't poisoned. 306 */ 307 if (cmd->cmd_list.next != LIST_POISON1) 308 list_del(&cmd->cmd_list); 309 spin_unlock_irqrestore(&xhci->lock, flags); 310 ret = -ETIME; 311 goto command_cleanup; 312 } 313 314command_cleanup: 315 xhci_free_command(xhci, cmd); 316 return ret; 317} 318 319/* 320 * Ring device, it rings the all doorbells unconditionally. 321 */ 322void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) 323{ 324 int i; 325 326 for (i = 0; i < LAST_EP_INDEX + 1; i++) 327 if (xhci->devs[slot_id]->eps[i].ring && 328 xhci->devs[slot_id]->eps[i].ring->dequeue) 329 xhci_ring_ep_doorbell(xhci, slot_id, i, 0); 330 331 return; 332} 333 334static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 335 u16 wIndex, __le32 __iomem *addr, u32 port_status) 336{ 337 /* Don't allow the USB core to disable SuperSpeed ports. */ 338 if (hcd->speed == HCD_USB3) { 339 xhci_dbg(xhci, "Ignoring request to disable " 340 "SuperSpeed port.\n"); 341 return; 342 } 343 344 /* Write 1 to disable the port */ 345 xhci_writel(xhci, port_status | PORT_PE, addr); 346 port_status = xhci_readl(xhci, addr); 347 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", 348 wIndex, port_status); 349} 350 351static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, 352 u16 wIndex, __le32 __iomem *addr, u32 port_status) 353{ 354 char *port_change_bit; 355 u32 status; 356 357 switch (wValue) { 358 case USB_PORT_FEAT_C_RESET: 359 status = PORT_RC; 360 port_change_bit = "reset"; 361 break; 362 case USB_PORT_FEAT_C_BH_PORT_RESET: 363 status = PORT_WRC; 364 port_change_bit = "warm(BH) reset"; 365 break; 366 case USB_PORT_FEAT_C_CONNECTION: 367 status = PORT_CSC; 368 port_change_bit = "connect"; 369 break; 370 case USB_PORT_FEAT_C_OVER_CURRENT: 371 status = PORT_OCC; 372 port_change_bit = "over-current"; 373 break; 374 case USB_PORT_FEAT_C_ENABLE: 375 status = PORT_PEC; 376 port_change_bit = "enable/disable"; 377 break; 378 case USB_PORT_FEAT_C_SUSPEND: 379 status = PORT_PLC; 380 port_change_bit = "suspend/resume"; 381 break; 382 case USB_PORT_FEAT_C_PORT_LINK_STATE: 383 status = PORT_PLC; 384 port_change_bit = "link state"; 385 break; 386 default: 387 /* Should never happen */ 388 return; 389 } 390 /* Change bits are all write 1 to clear */ 391 xhci_writel(xhci, port_status | status, addr); 392 port_status = xhci_readl(xhci, addr); 393 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", 394 port_change_bit, wIndex, port_status); 395} 396 397static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array) 398{ 399 int max_ports; 400 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 401 402 if (hcd->speed == HCD_USB3) { 403 max_ports = xhci->num_usb3_ports; 404 *port_array = xhci->usb3_ports; 405 } else { 406 max_ports = xhci->num_usb2_ports; 407 *port_array = xhci->usb2_ports; 408 } 409 410 return max_ports; 411} 412 413void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 414 int port_id, u32 link_state) 415{ 416 u32 temp; 417 418 temp = xhci_readl(xhci, port_array[port_id]); 419 temp = xhci_port_state_to_neutral(temp); 420 temp &= ~PORT_PLS_MASK; 421 temp |= PORT_LINK_STROBE | link_state; 422 xhci_writel(xhci, temp, port_array[port_id]); 423} 424 425void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, 426 __le32 __iomem **port_array, int port_id, u16 wake_mask) 427{ 428 u32 temp; 429 430 temp = xhci_readl(xhci, port_array[port_id]); 431 temp = xhci_port_state_to_neutral(temp); 432 433 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) 434 temp |= PORT_WKCONN_E; 435 else 436 temp &= ~PORT_WKCONN_E; 437 438 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) 439 temp |= PORT_WKDISC_E; 440 else 441 temp &= ~PORT_WKDISC_E; 442 443 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) 444 temp |= PORT_WKOC_E; 445 else 446 temp &= ~PORT_WKOC_E; 447 448 xhci_writel(xhci, temp, port_array[port_id]); 449} 450 451/* Test and clear port RWC bit */ 452void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 453 int port_id, u32 port_bit) 454{ 455 u32 temp; 456 457 temp = xhci_readl(xhci, port_array[port_id]); 458 if (temp & port_bit) { 459 temp = xhci_port_state_to_neutral(temp); 460 temp |= port_bit; 461 xhci_writel(xhci, temp, port_array[port_id]); 462 } 463} 464 465/* Updates Link Status for super Speed port */ 466static void xhci_hub_report_link_state(u32 *status, u32 status_reg) 467{ 468 u32 pls = status_reg & PORT_PLS_MASK; 469 470 /* resume state is a xHCI internal state. 471 * Do not report it to usb core. 472 */ 473 if (pls == XDEV_RESUME) 474 return; 475 476 /* When the CAS bit is set then warm reset 477 * should be performed on port 478 */ 479 if (status_reg & PORT_CAS) { 480 /* The CAS bit can be set while the port is 481 * in any link state. 482 * Only roothubs have CAS bit, so we 483 * pretend to be in compliance mode 484 * unless we're already in compliance 485 * or the inactive state. 486 */ 487 if (pls != USB_SS_PORT_LS_COMP_MOD && 488 pls != USB_SS_PORT_LS_SS_INACTIVE) { 489 pls = USB_SS_PORT_LS_COMP_MOD; 490 } 491 /* Return also connection bit - 492 * hub state machine resets port 493 * when this bit is set. 494 */ 495 pls |= USB_PORT_STAT_CONNECTION; 496 } 497 /* update status field */ 498 *status |= pls; 499} 500 501int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 502 u16 wIndex, char *buf, u16 wLength) 503{ 504 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 505 int max_ports; 506 unsigned long flags; 507 u32 temp, status; 508 int retval = 0; 509 __le32 __iomem **port_array; 510 int slot_id; 511 struct xhci_bus_state *bus_state; 512 u16 link_state = 0; 513 u16 wake_mask = 0; 514 515 max_ports = xhci_get_ports(hcd, &port_array); 516 bus_state = &xhci->bus_state[hcd_index(hcd)]; 517 518 spin_lock_irqsave(&xhci->lock, flags); 519 switch (typeReq) { 520 case GetHubStatus: 521 /* No power source, over-current reported per port */ 522 memset(buf, 0, 4); 523 break; 524 case GetHubDescriptor: 525 /* Check to make sure userspace is asking for the USB 3.0 hub 526 * descriptor for the USB 3.0 roothub. If not, we stall the 527 * endpoint, like external hubs do. 528 */ 529 if (hcd->speed == HCD_USB3 && 530 (wLength < USB_DT_SS_HUB_SIZE || 531 wValue != (USB_DT_SS_HUB << 8))) { 532 xhci_dbg(xhci, "Wrong hub descriptor type for " 533 "USB 3.0 roothub.\n"); 534 goto error; 535 } 536 xhci_hub_descriptor(hcd, xhci, 537 (struct usb_hub_descriptor *) buf); 538 break; 539 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 540 if ((wValue & 0xff00) != (USB_DT_BOS << 8)) 541 goto error; 542 543 if (hcd->speed != HCD_USB3) 544 goto error; 545 546 memcpy(buf, &usb_bos_descriptor, 547 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE); 548 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3); 549 buf[12] = HCS_U1_LATENCY(temp); 550 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); 551 552 spin_unlock_irqrestore(&xhci->lock, flags); 553 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; 554 case GetPortStatus: 555 if (!wIndex || wIndex > max_ports) 556 goto error; 557 wIndex--; 558 status = 0; 559 temp = xhci_readl(xhci, port_array[wIndex]); 560 if (temp == 0xffffffff) { 561 retval = -ENODEV; 562 break; 563 } 564 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp); 565 566 /* wPortChange bits */ 567 if (temp & PORT_CSC) 568 status |= USB_PORT_STAT_C_CONNECTION << 16; 569 if (temp & PORT_PEC) 570 status |= USB_PORT_STAT_C_ENABLE << 16; 571 if ((temp & PORT_OCC)) 572 status |= USB_PORT_STAT_C_OVERCURRENT << 16; 573 if ((temp & PORT_RC)) 574 status |= USB_PORT_STAT_C_RESET << 16; 575 /* USB3.0 only */ 576 if (hcd->speed == HCD_USB3) { 577 if ((temp & PORT_PLC)) 578 status |= USB_PORT_STAT_C_LINK_STATE << 16; 579 if ((temp & PORT_WRC)) 580 status |= USB_PORT_STAT_C_BH_RESET << 16; 581 } 582 583 if (hcd->speed != HCD_USB3) { 584 if ((temp & PORT_PLS_MASK) == XDEV_U3 585 && (temp & PORT_POWER)) 586 status |= USB_PORT_STAT_SUSPEND; 587 } 588 if ((temp & PORT_PLS_MASK) == XDEV_RESUME && 589 !DEV_SUPERSPEED(temp)) { 590 if ((temp & PORT_RESET) || !(temp & PORT_PE)) 591 goto error; 592 if (time_after_eq(jiffies, 593 bus_state->resume_done[wIndex])) { 594 xhci_dbg(xhci, "Resume USB2 port %d\n", 595 wIndex + 1); 596 bus_state->resume_done[wIndex] = 0; 597 clear_bit(wIndex, &bus_state->resuming_ports); 598 xhci_set_link_state(xhci, port_array, wIndex, 599 XDEV_U0); 600 xhci_dbg(xhci, "set port %d resume\n", 601 wIndex + 1); 602 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 603 wIndex + 1); 604 if (!slot_id) { 605 xhci_dbg(xhci, "slot_id is zero\n"); 606 goto error; 607 } 608 xhci_ring_device(xhci, slot_id); 609 bus_state->port_c_suspend |= 1 << wIndex; 610 bus_state->suspended_ports &= ~(1 << wIndex); 611 } else { 612 /* 613 * The resume has been signaling for less than 614 * 20ms. Report the port status as SUSPEND, 615 * let the usbcore check port status again 616 * and clear resume signaling later. 617 */ 618 status |= USB_PORT_STAT_SUSPEND; 619 } 620 } 621 if ((temp & PORT_PLS_MASK) == XDEV_U0 622 && (temp & PORT_POWER) 623 && (bus_state->suspended_ports & (1 << wIndex))) { 624 bus_state->suspended_ports &= ~(1 << wIndex); 625 if (hcd->speed != HCD_USB3) 626 bus_state->port_c_suspend |= 1 << wIndex; 627 } 628 if (temp & PORT_CONNECT) { 629 status |= USB_PORT_STAT_CONNECTION; 630 status |= xhci_port_speed(temp); 631 } 632 if (temp & PORT_PE) 633 status |= USB_PORT_STAT_ENABLE; 634 if (temp & PORT_OC) 635 status |= USB_PORT_STAT_OVERCURRENT; 636 if (temp & PORT_RESET) 637 status |= USB_PORT_STAT_RESET; 638 if (temp & PORT_POWER) { 639 if (hcd->speed == HCD_USB3) 640 status |= USB_SS_PORT_STAT_POWER; 641 else 642 status |= USB_PORT_STAT_POWER; 643 } 644 /* Update Port Link State for super speed ports*/ 645 if (hcd->speed == HCD_USB3) { 646 xhci_hub_report_link_state(&status, temp); 647 } 648 if (bus_state->port_c_suspend & (1 << wIndex)) 649 status |= 1 << USB_PORT_FEAT_C_SUSPEND; 650 xhci_dbg(xhci, "Get port status returned 0x%x\n", status); 651 put_unaligned(cpu_to_le32(status), (__le32 *) buf); 652 break; 653 case SetPortFeature: 654 if (wValue == USB_PORT_FEAT_LINK_STATE) 655 link_state = (wIndex & 0xff00) >> 3; 656 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) 657 wake_mask = wIndex & 0xff00; 658 wIndex &= 0xff; 659 if (!wIndex || wIndex > max_ports) 660 goto error; 661 wIndex--; 662 temp = xhci_readl(xhci, port_array[wIndex]); 663 if (temp == 0xffffffff) { 664 retval = -ENODEV; 665 break; 666 } 667 temp = xhci_port_state_to_neutral(temp); 668 /* FIXME: What new port features do we need to support? */ 669 switch (wValue) { 670 case USB_PORT_FEAT_SUSPEND: 671 temp = xhci_readl(xhci, port_array[wIndex]); 672 if ((temp & PORT_PLS_MASK) != XDEV_U0) { 673 /* Resume the port to U0 first */ 674 xhci_set_link_state(xhci, port_array, wIndex, 675 XDEV_U0); 676 spin_unlock_irqrestore(&xhci->lock, flags); 677 msleep(10); 678 spin_lock_irqsave(&xhci->lock, flags); 679 } 680 /* In spec software should not attempt to suspend 681 * a port unless the port reports that it is in the 682 * enabled (PED = â1â,PLS < â3â) state. 683 */ 684 temp = xhci_readl(xhci, port_array[wIndex]); 685 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) 686 || (temp & PORT_PLS_MASK) >= XDEV_U3) { 687 xhci_warn(xhci, "USB core suspending device " 688 "not in U0/U1/U2.\n"); 689 goto error; 690 } 691 692 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 693 wIndex + 1); 694 if (!slot_id) { 695 xhci_warn(xhci, "slot_id is zero\n"); 696 goto error; 697 } 698 /* unlock to execute stop endpoint commands */ 699 spin_unlock_irqrestore(&xhci->lock, flags); 700 xhci_stop_device(xhci, slot_id, 1); 701 spin_lock_irqsave(&xhci->lock, flags); 702 703 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3); 704 705 spin_unlock_irqrestore(&xhci->lock, flags); 706 msleep(10); /* wait device to enter */ 707 spin_lock_irqsave(&xhci->lock, flags); 708 709 temp = xhci_readl(xhci, port_array[wIndex]); 710 bus_state->suspended_ports |= 1 << wIndex; 711 break; 712 case USB_PORT_FEAT_LINK_STATE: 713 temp = xhci_readl(xhci, port_array[wIndex]); 714 /* Software should not attempt to set 715 * port link state above '5' (Rx.Detect) and the port 716 * must be enabled. 717 */ 718 if ((temp & PORT_PE) == 0 || 719 (link_state > USB_SS_PORT_LS_RX_DETECT)) { 720 xhci_warn(xhci, "Cannot set link state.\n"); 721 goto error; 722 } 723 724 if (link_state == USB_SS_PORT_LS_U3) { 725 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 726 wIndex + 1); 727 if (slot_id) { 728 /* unlock to execute stop endpoint 729 * commands */ 730 spin_unlock_irqrestore(&xhci->lock, 731 flags); 732 xhci_stop_device(xhci, slot_id, 1); 733 spin_lock_irqsave(&xhci->lock, flags); 734 } 735 } 736 737 xhci_set_link_state(xhci, port_array, wIndex, 738 link_state); 739 740 spin_unlock_irqrestore(&xhci->lock, flags); 741 msleep(20); /* wait device to enter */ 742 spin_lock_irqsave(&xhci->lock, flags); 743 744 temp = xhci_readl(xhci, port_array[wIndex]); 745 if (link_state == USB_SS_PORT_LS_U3) 746 bus_state->suspended_ports |= 1 << wIndex; 747 break; 748 case USB_PORT_FEAT_POWER: 749 /* 750 * Turn on ports, even if there isn't per-port switching. 751 * HC will report connect events even before this is set. 752 * However, khubd will ignore the roothub events until 753 * the roothub is registered. 754 */ 755 xhci_writel(xhci, temp | PORT_POWER, 756 port_array[wIndex]); 757 758 temp = xhci_readl(xhci, port_array[wIndex]); 759 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); 760 break; 761 case USB_PORT_FEAT_RESET: 762 temp = (temp | PORT_RESET); 763 xhci_writel(xhci, temp, port_array[wIndex]); 764 765 temp = xhci_readl(xhci, port_array[wIndex]); 766 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); 767 break; 768 case USB_PORT_FEAT_REMOTE_WAKE_MASK: 769 xhci_set_remote_wake_mask(xhci, port_array, 770 wIndex, wake_mask); 771 temp = xhci_readl(xhci, port_array[wIndex]); 772 xhci_dbg(xhci, "set port remote wake mask, " 773 "actual port %d status = 0x%x\n", 774 wIndex, temp); 775 break; 776 case USB_PORT_FEAT_BH_PORT_RESET: 777 temp |= PORT_WR; 778 xhci_writel(xhci, temp, port_array[wIndex]); 779 780 temp = xhci_readl(xhci, port_array[wIndex]); 781 break; 782 default: 783 goto error; 784 } 785 /* unblock any posted writes */ 786 temp = xhci_readl(xhci, port_array[wIndex]); 787 break; 788 case ClearPortFeature: 789 if (!wIndex || wIndex > max_ports) 790 goto error; 791 wIndex--; 792 temp = xhci_readl(xhci, port_array[wIndex]); 793 if (temp == 0xffffffff) { 794 retval = -ENODEV; 795 break; 796 } 797 /* FIXME: What new port features do we need to support? */ 798 temp = xhci_port_state_to_neutral(temp); 799 switch (wValue) { 800 case USB_PORT_FEAT_SUSPEND: 801 temp = xhci_readl(xhci, port_array[wIndex]); 802 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); 803 xhci_dbg(xhci, "PORTSC %04x\n", temp); 804 if (temp & PORT_RESET) 805 goto error; 806 if ((temp & PORT_PLS_MASK) == XDEV_U3) { 807 if ((temp & PORT_PE) == 0) 808 goto error; 809 810 xhci_set_link_state(xhci, port_array, wIndex, 811 XDEV_RESUME); 812 spin_unlock_irqrestore(&xhci->lock, flags); 813 msleep(20); 814 spin_lock_irqsave(&xhci->lock, flags); 815 xhci_set_link_state(xhci, port_array, wIndex, 816 XDEV_U0); 817 } 818 bus_state->port_c_suspend |= 1 << wIndex; 819 820 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 821 wIndex + 1); 822 if (!slot_id) { 823 xhci_dbg(xhci, "slot_id is zero\n"); 824 goto error; 825 } 826 xhci_ring_device(xhci, slot_id); 827 break; 828 case USB_PORT_FEAT_C_SUSPEND: 829 bus_state->port_c_suspend &= ~(1 << wIndex); 830 case USB_PORT_FEAT_C_RESET: 831 case USB_PORT_FEAT_C_BH_PORT_RESET: 832 case USB_PORT_FEAT_C_CONNECTION: 833 case USB_PORT_FEAT_C_OVER_CURRENT: 834 case USB_PORT_FEAT_C_ENABLE: 835 case USB_PORT_FEAT_C_PORT_LINK_STATE: 836 xhci_clear_port_change_bit(xhci, wValue, wIndex, 837 port_array[wIndex], temp); 838 break; 839 case USB_PORT_FEAT_ENABLE: 840 xhci_disable_port(hcd, xhci, wIndex, 841 port_array[wIndex], temp); 842 break; 843 default: 844 goto error; 845 } 846 break; 847 default: 848error: 849 /* "stall" on error */ 850 retval = -EPIPE; 851 } 852 spin_unlock_irqrestore(&xhci->lock, flags); 853 return retval; 854} 855 856/* 857 * Returns 0 if the status hasn't changed, or the number of bytes in buf. 858 * Ports are 0-indexed from the HCD point of view, 859 * and 1-indexed from the USB core pointer of view. 860 * 861 * Note that the status change bits will be cleared as soon as a port status 862 * change event is generated, so we use the saved status from that event. 863 */ 864int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) 865{ 866 unsigned long flags; 867 u32 temp, status; 868 u32 mask; 869 int i, retval; 870 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 871 int max_ports; 872 __le32 __iomem **port_array; 873 struct xhci_bus_state *bus_state; 874 875 max_ports = xhci_get_ports(hcd, &port_array); 876 bus_state = &xhci->bus_state[hcd_index(hcd)]; 877 878 /* Initial status is no changes */ 879 retval = (max_ports + 8) / 8; 880 memset(buf, 0, retval); 881 882 /* 883 * Inform the usbcore about resume-in-progress by returning 884 * a non-zero value even if there are no status changes. 885 */ 886 status = bus_state->resuming_ports; 887 888 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC; 889 890 spin_lock_irqsave(&xhci->lock, flags); 891 /* For each port, did anything change? If so, set that bit in buf. */ 892 for (i = 0; i < max_ports; i++) { 893 temp = xhci_readl(xhci, port_array[i]); 894 if (temp == 0xffffffff) { 895 retval = -ENODEV; 896 break; 897 } 898 if ((temp & mask) != 0 || 899 (bus_state->port_c_suspend & 1 << i) || 900 (bus_state->resume_done[i] && time_after_eq( 901 jiffies, bus_state->resume_done[i]))) { 902 buf[(i + 1) / 8] |= 1 << (i + 1) % 8; 903 status = 1; 904 } 905 } 906 spin_unlock_irqrestore(&xhci->lock, flags); 907 return status ? retval : 0; 908} 909 910#ifdef CONFIG_PM 911 912int xhci_bus_suspend(struct usb_hcd *hcd) 913{ 914 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 915 int max_ports, port_index; 916 __le32 __iomem **port_array; 917 struct xhci_bus_state *bus_state; 918 unsigned long flags; 919 920 max_ports = xhci_get_ports(hcd, &port_array); 921 bus_state = &xhci->bus_state[hcd_index(hcd)]; 922 923 spin_lock_irqsave(&xhci->lock, flags); 924 925 if (hcd->self.root_hub->do_remote_wakeup) { 926 if (bus_state->resuming_ports) { 927 spin_unlock_irqrestore(&xhci->lock, flags); 928 xhci_dbg(xhci, "suspend failed because " 929 "a port is resuming\n"); 930 return -EBUSY; 931 } 932 } 933 934 port_index = max_ports; 935 bus_state->bus_suspended = 0; 936 while (port_index--) { 937 /* suspend the port if the port is not suspended */ 938 u32 t1, t2; 939 int slot_id; 940 941 t1 = xhci_readl(xhci, port_array[port_index]); 942 t2 = xhci_port_state_to_neutral(t1); 943 944 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { 945 xhci_dbg(xhci, "port %d not suspended\n", port_index); 946 slot_id = xhci_find_slot_id_by_port(hcd, xhci, 947 port_index + 1); 948 if (slot_id) { 949 spin_unlock_irqrestore(&xhci->lock, flags); 950 xhci_stop_device(xhci, slot_id, 1); 951 spin_lock_irqsave(&xhci->lock, flags); 952 } 953 t2 &= ~PORT_PLS_MASK; 954 t2 |= PORT_LINK_STROBE | XDEV_U3; 955 set_bit(port_index, &bus_state->bus_suspended); 956 } 957 /* USB core sets remote wake mask for USB 3.0 hubs, 958 * including the USB 3.0 roothub, but only if CONFIG_USB_SUSPEND 959 * is enabled, so also enable remote wake here. 960 */ 961 if (hcd->self.root_hub->do_remote_wakeup) { 962 if (t1 & PORT_CONNECT) { 963 t2 |= PORT_WKOC_E | PORT_WKDISC_E; 964 t2 &= ~PORT_WKCONN_E; 965 } else { 966 t2 |= PORT_WKOC_E | PORT_WKCONN_E; 967 t2 &= ~PORT_WKDISC_E; 968 } 969 } else 970 t2 &= ~PORT_WAKE_BITS; 971 972 t1 = xhci_port_state_to_neutral(t1); 973 if (t1 != t2) 974 xhci_writel(xhci, t2, port_array[port_index]); 975 976 if (hcd->speed != HCD_USB3) { 977 /* enable remote wake up for USB 2.0 */ 978 __le32 __iomem *addr; 979 u32 tmp; 980 981 /* Add one to the port status register address to get 982 * the port power control register address. 983 */ 984 addr = port_array[port_index] + 1; 985 tmp = xhci_readl(xhci, addr); 986 tmp |= PORT_RWE; 987 xhci_writel(xhci, tmp, addr); 988 } 989 } 990 hcd->state = HC_STATE_SUSPENDED; 991 bus_state->next_statechange = jiffies + msecs_to_jiffies(10); 992 spin_unlock_irqrestore(&xhci->lock, flags); 993 return 0; 994} 995 996int xhci_bus_resume(struct usb_hcd *hcd) 997{ 998 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 999 int max_ports, port_index; 1000 __le32 __iomem **port_array; 1001 struct xhci_bus_state *bus_state; 1002 u32 temp; 1003 unsigned long flags; 1004 1005 max_ports = xhci_get_ports(hcd, &port_array); 1006 bus_state = &xhci->bus_state[hcd_index(hcd)]; 1007 1008 if (time_before(jiffies, bus_state->next_statechange)) 1009 msleep(5); 1010 1011 spin_lock_irqsave(&xhci->lock, flags); 1012 if (!HCD_HW_ACCESSIBLE(hcd)) { 1013 spin_unlock_irqrestore(&xhci->lock, flags); 1014 return -ESHUTDOWN; 1015 } 1016 1017 /* delay the irqs */ 1018 temp = xhci_readl(xhci, &xhci->op_regs->command); 1019 temp &= ~CMD_EIE; 1020 xhci_writel(xhci, temp, &xhci->op_regs->command); 1021 1022 port_index = max_ports; 1023 while (port_index--) { 1024 /* Check whether need resume ports. If needed 1025 resume port and disable remote wakeup */ 1026 u32 temp; 1027 int slot_id; 1028 1029 temp = xhci_readl(xhci, port_array[port_index]); 1030 if (DEV_SUPERSPEED(temp)) 1031 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); 1032 else 1033 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); 1034 if (test_bit(port_index, &bus_state->bus_suspended) && 1035 (temp & PORT_PLS_MASK)) { 1036 if (DEV_SUPERSPEED(temp)) { 1037 xhci_set_link_state(xhci, port_array, 1038 port_index, XDEV_U0); 1039 } else { 1040 xhci_set_link_state(xhci, port_array, 1041 port_index, XDEV_RESUME); 1042 1043 spin_unlock_irqrestore(&xhci->lock, flags); 1044 msleep(20); 1045 spin_lock_irqsave(&xhci->lock, flags); 1046 1047 xhci_set_link_state(xhci, port_array, 1048 port_index, XDEV_U0); 1049 } 1050 /* wait for the port to enter U0 and report port link 1051 * state change. 1052 */ 1053 spin_unlock_irqrestore(&xhci->lock, flags); 1054 msleep(20); 1055 spin_lock_irqsave(&xhci->lock, flags); 1056 1057 /* Clear PLC */ 1058 xhci_test_and_clear_bit(xhci, port_array, port_index, 1059 PORT_PLC); 1060 1061 slot_id = xhci_find_slot_id_by_port(hcd, 1062 xhci, port_index + 1); 1063 if (slot_id) 1064 xhci_ring_device(xhci, slot_id); 1065 } else 1066 xhci_writel(xhci, temp, port_array[port_index]); 1067 1068 if (hcd->speed != HCD_USB3) { 1069 /* disable remote wake up for USB 2.0 */ 1070 __le32 __iomem *addr; 1071 u32 tmp; 1072 1073 /* Add one to the port status register address to get 1074 * the port power control register address. 1075 */ 1076 addr = port_array[port_index] + 1; 1077 tmp = xhci_readl(xhci, addr); 1078 tmp &= ~PORT_RWE; 1079 xhci_writel(xhci, tmp, addr); 1080 } 1081 } 1082 1083 (void) xhci_readl(xhci, &xhci->op_regs->command); 1084 1085 bus_state->next_statechange = jiffies + msecs_to_jiffies(5); 1086 /* re-enable irqs */ 1087 temp = xhci_readl(xhci, &xhci->op_regs->command); 1088 temp |= CMD_EIE; 1089 xhci_writel(xhci, temp, &xhci->op_regs->command); 1090 temp = xhci_readl(xhci, &xhci->op_regs->command); 1091 1092 spin_unlock_irqrestore(&xhci->lock, flags); 1093 return 0; 1094} 1095 1096#endif /* CONFIG_PM */ 1097