1/* 2 * MUSB OTG controller driver for Blackfin Processors 3 * 4 * Copyright 2006-2008 Analog Devices Inc. 5 * 6 * Enter bugs at http://blackfin.uclinux.org/ 7 * 8 * Licensed under the GPL-2 or later. 9 */ 10 11#include <linux/module.h> 12#include <linux/kernel.h> 13#include <linux/sched.h> 14#include <linux/init.h> 15#include <linux/list.h> 16#include <linux/gpio.h> 17#include <linux/io.h> 18#include <linux/platform_device.h> 19#include <linux/dma-mapping.h> 20#include <linux/prefetch.h> 21 22#include <asm/cacheflush.h> 23 24#include "musb_core.h" 25#include "musbhsdma.h" 26#include "blackfin.h" 27 28struct bfin_glue { 29 struct device *dev; 30 struct platform_device *musb; 31}; 32#define glue_to_musb(g) platform_get_drvdata(g->musb) 33 34/* 35 * Load an endpoint's FIFO 36 */ 37void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 38{ 39 struct musb *musb = hw_ep->musb; 40 void __iomem *fifo = hw_ep->fifo; 41 void __iomem *epio = hw_ep->regs; 42 u8 epnum = hw_ep->epnum; 43 44 prefetch((u8 *)src); 45 46 musb_writew(epio, MUSB_TXCOUNT, len); 47 48 dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n", 49 hw_ep->epnum, fifo, len, src, epio); 50 51 dump_fifo_data(src, len); 52 53 if (!ANOMALY_05000380 && epnum != 0) { 54 u16 dma_reg; 55 56 flush_dcache_range((unsigned long)src, 57 (unsigned long)(src + len)); 58 59 /* Setup DMA address register */ 60 dma_reg = (u32)src; 61 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg); 62 SSYNC(); 63 64 dma_reg = (u32)src >> 16; 65 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg); 66 SSYNC(); 67 68 /* Setup DMA count register */ 69 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len); 70 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0); 71 SSYNC(); 72 73 /* Enable the DMA */ 74 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION; 75 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg); 76 SSYNC(); 77 78 /* Wait for compelete */ 79 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum))) 80 cpu_relax(); 81 82 /* acknowledge dma interrupt */ 83 bfin_write_USB_DMA_INTERRUPT(1 << epnum); 84 SSYNC(); 85 86 /* Reset DMA */ 87 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0); 88 SSYNC(); 89 } else { 90 SSYNC(); 91 92 if (unlikely((unsigned long)src & 0x01)) 93 outsw_8((unsigned long)fifo, src, (len + 1) >> 1); 94 else 95 outsw((unsigned long)fifo, src, (len + 1) >> 1); 96 } 97} 98/* 99 * Unload an endpoint's FIFO 100 */ 101void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 102{ 103 struct musb *musb = hw_ep->musb; 104 void __iomem *fifo = hw_ep->fifo; 105 u8 epnum = hw_ep->epnum; 106 107 if (ANOMALY_05000467 && epnum != 0) { 108 u16 dma_reg; 109 110 invalidate_dcache_range((unsigned long)dst, 111 (unsigned long)(dst + len)); 112 113 /* Setup DMA address register */ 114 dma_reg = (u32)dst; 115 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg); 116 SSYNC(); 117 118 dma_reg = (u32)dst >> 16; 119 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg); 120 SSYNC(); 121 122 /* Setup DMA count register */ 123 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len); 124 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0); 125 SSYNC(); 126 127 /* Enable the DMA */ 128 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA; 129 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg); 130 SSYNC(); 131 132 /* Wait for compelete */ 133 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum))) 134 cpu_relax(); 135 136 /* acknowledge dma interrupt */ 137 bfin_write_USB_DMA_INTERRUPT(1 << epnum); 138 SSYNC(); 139 140 /* Reset DMA */ 141 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0); 142 SSYNC(); 143 } else { 144 SSYNC(); 145 /* Read the last byte of packet with odd size from address fifo + 4 146 * to trigger 1 byte access to EP0 FIFO. 147 */ 148 if (len == 1) 149 *dst = (u8)inw((unsigned long)fifo + 4); 150 else { 151 if (unlikely((unsigned long)dst & 0x01)) 152 insw_8((unsigned long)fifo, dst, len >> 1); 153 else 154 insw((unsigned long)fifo, dst, len >> 1); 155 156 if (len & 0x01) 157 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4); 158 } 159 } 160 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 161 'R', hw_ep->epnum, fifo, len, dst); 162 163 dump_fifo_data(dst, len); 164} 165 166static irqreturn_t blackfin_interrupt(int irq, void *__hci) 167{ 168 unsigned long flags; 169 irqreturn_t retval = IRQ_NONE; 170 struct musb *musb = __hci; 171 172 spin_lock_irqsave(&musb->lock, flags); 173 174 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 175 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 176 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 177 178 if (musb->int_usb || musb->int_tx || musb->int_rx) { 179 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb); 180 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx); 181 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx); 182 retval = musb_interrupt(musb); 183 } 184 185 /* Start sampling ID pin, when plug is removed from MUSB */ 186 if ((is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE 187 || musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) || 188 (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) { 189 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY); 190 musb->a_wait_bcon = TIMER_DELAY; 191 } 192 193 spin_unlock_irqrestore(&musb->lock, flags); 194 195 return retval; 196} 197 198static void musb_conn_timer_handler(unsigned long _musb) 199{ 200 struct musb *musb = (void *)_musb; 201 unsigned long flags; 202 u16 val; 203 static u8 toggle; 204 205 spin_lock_irqsave(&musb->lock, flags); 206 switch (musb->xceiv->state) { 207 case OTG_STATE_A_IDLE: 208 case OTG_STATE_A_WAIT_BCON: 209 /* Start a new session */ 210 val = musb_readw(musb->mregs, MUSB_DEVCTL); 211 val &= ~MUSB_DEVCTL_SESSION; 212 musb_writew(musb->mregs, MUSB_DEVCTL, val); 213 val |= MUSB_DEVCTL_SESSION; 214 musb_writew(musb->mregs, MUSB_DEVCTL, val); 215 /* Check if musb is host or peripheral. */ 216 val = musb_readw(musb->mregs, MUSB_DEVCTL); 217 218 if (!(val & MUSB_DEVCTL_BDEVICE)) { 219 gpio_set_value(musb->config->gpio_vrsel, 1); 220 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 221 } else { 222 gpio_set_value(musb->config->gpio_vrsel, 0); 223 /* Ignore VBUSERROR and SUSPEND IRQ */ 224 val = musb_readb(musb->mregs, MUSB_INTRUSBE); 225 val &= ~MUSB_INTR_VBUSERROR; 226 musb_writeb(musb->mregs, MUSB_INTRUSBE, val); 227 228 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR; 229 musb_writeb(musb->mregs, MUSB_INTRUSB, val); 230 if (is_otg_enabled(musb)) 231 musb->xceiv->state = OTG_STATE_B_IDLE; 232 else 233 musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB); 234 } 235 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY); 236 break; 237 case OTG_STATE_B_IDLE: 238 239 if (!is_peripheral_enabled(musb)) 240 break; 241 /* Start a new session. It seems that MUSB needs taking 242 * some time to recognize the type of the plug inserted? 243 */ 244 val = musb_readw(musb->mregs, MUSB_DEVCTL); 245 val |= MUSB_DEVCTL_SESSION; 246 musb_writew(musb->mregs, MUSB_DEVCTL, val); 247 val = musb_readw(musb->mregs, MUSB_DEVCTL); 248 249 if (!(val & MUSB_DEVCTL_BDEVICE)) { 250 gpio_set_value(musb->config->gpio_vrsel, 1); 251 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 252 } else { 253 gpio_set_value(musb->config->gpio_vrsel, 0); 254 255 /* Ignore VBUSERROR and SUSPEND IRQ */ 256 val = musb_readb(musb->mregs, MUSB_INTRUSBE); 257 val &= ~MUSB_INTR_VBUSERROR; 258 musb_writeb(musb->mregs, MUSB_INTRUSBE, val); 259 260 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR; 261 musb_writeb(musb->mregs, MUSB_INTRUSB, val); 262 263 /* Toggle the Soft Conn bit, so that we can response to 264 * the inserting of either A-plug or B-plug. 265 */ 266 if (toggle) { 267 val = musb_readb(musb->mregs, MUSB_POWER); 268 val &= ~MUSB_POWER_SOFTCONN; 269 musb_writeb(musb->mregs, MUSB_POWER, val); 270 toggle = 0; 271 } else { 272 val = musb_readb(musb->mregs, MUSB_POWER); 273 val |= MUSB_POWER_SOFTCONN; 274 musb_writeb(musb->mregs, MUSB_POWER, val); 275 toggle = 1; 276 } 277 /* The delay time is set to 1/4 second by default, 278 * shortening it, if accelerating A-plug detection 279 * is needed in OTG mode. 280 */ 281 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4); 282 } 283 break; 284 default: 285 dev_dbg(musb->controller, "%s state not handled\n", 286 otg_state_string(musb->xceiv->state)); 287 break; 288 } 289 spin_unlock_irqrestore(&musb->lock, flags); 290 291 dev_dbg(musb->controller, "state is %s\n", 292 otg_state_string(musb->xceiv->state)); 293} 294 295static void bfin_musb_enable(struct musb *musb) 296{ 297 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 298 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY); 299 musb->a_wait_bcon = TIMER_DELAY; 300 } 301} 302 303static void bfin_musb_disable(struct musb *musb) 304{ 305} 306 307static void bfin_musb_set_vbus(struct musb *musb, int is_on) 308{ 309 int value = musb->config->gpio_vrsel_active; 310 if (!is_on) 311 value = !value; 312 gpio_set_value(musb->config->gpio_vrsel, value); 313 314 dev_dbg(musb->controller, "VBUS %s, devctl %02x " 315 /* otg %3x conf %08x prcm %08x */ "\n", 316 otg_state_string(musb->xceiv->state), 317 musb_readb(musb->mregs, MUSB_DEVCTL)); 318} 319 320static int bfin_musb_set_power(struct usb_phy *x, unsigned mA) 321{ 322 return 0; 323} 324 325static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout) 326{ 327 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 328 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY); 329} 330 331static int bfin_musb_vbus_status(struct musb *musb) 332{ 333 return 0; 334} 335 336static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode) 337{ 338 return -EIO; 339} 340 341static int bfin_musb_adjust_channel_params(struct dma_channel *channel, 342 u16 packet_sz, u8 *mode, 343 dma_addr_t *dma_addr, u32 *len) 344{ 345 struct musb_dma_channel *musb_channel = channel->private_data; 346 347 /* 348 * Anomaly 05000450 might cause data corruption when using DMA 349 * MODE 1 transmits with short packet. So to work around this, 350 * we truncate all MODE 1 transfers down to a multiple of the 351 * max packet size, and then do the last short packet transfer 352 * (if there is any) using MODE 0. 353 */ 354 if (ANOMALY_05000450) { 355 if (musb_channel->transmit && *mode == 1) 356 *len = *len - (*len % packet_sz); 357 } 358 359 return 0; 360} 361 362static void bfin_musb_reg_init(struct musb *musb) 363{ 364 if (ANOMALY_05000346) { 365 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value); 366 SSYNC(); 367 } 368 369 if (ANOMALY_05000347) { 370 bfin_write_USB_APHY_CNTRL(0x0); 371 SSYNC(); 372 } 373 374 /* Configure PLL oscillator register */ 375 bfin_write_USB_PLLOSC_CTRL(0x3080 | 376 ((480/musb->config->clkin) << 1)); 377 SSYNC(); 378 379 bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1); 380 SSYNC(); 381 382 bfin_write_USB_EP_NI0_RXMAXP(64); 383 SSYNC(); 384 385 bfin_write_USB_EP_NI0_TXMAXP(64); 386 SSYNC(); 387 388 /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/ 389 bfin_write_USB_GLOBINTR(0x7); 390 SSYNC(); 391 392 bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA | 393 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA | 394 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA | 395 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA | 396 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA); 397 SSYNC(); 398} 399 400static int bfin_musb_init(struct musb *musb) 401{ 402 403 /* 404 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE 405 * and OTG HOST modes, while rev 1.1 and greater require PE7 to 406 * be low for DEVICE mode and high for HOST mode. We set it high 407 * here because we are in host mode 408 */ 409 410 if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) { 411 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n", 412 musb->config->gpio_vrsel); 413 return -ENODEV; 414 } 415 gpio_direction_output(musb->config->gpio_vrsel, 0); 416 417 usb_nop_xceiv_register(); 418 musb->xceiv = usb_get_transceiver(); 419 if (!musb->xceiv) { 420 gpio_free(musb->config->gpio_vrsel); 421 return -ENODEV; 422 } 423 424 bfin_musb_reg_init(musb); 425 426 if (is_host_enabled(musb)) { 427 setup_timer(&musb_conn_timer, 428 musb_conn_timer_handler, (unsigned long) musb); 429 } 430 if (is_peripheral_enabled(musb)) 431 musb->xceiv->set_power = bfin_musb_set_power; 432 433 musb->isr = blackfin_interrupt; 434 musb->double_buffer_not_ok = true; 435 436 return 0; 437} 438 439static int bfin_musb_exit(struct musb *musb) 440{ 441 gpio_free(musb->config->gpio_vrsel); 442 443 usb_put_transceiver(musb->xceiv); 444 usb_nop_xceiv_unregister(); 445 return 0; 446} 447 448static const struct musb_platform_ops bfin_ops = { 449 .init = bfin_musb_init, 450 .exit = bfin_musb_exit, 451 452 .enable = bfin_musb_enable, 453 .disable = bfin_musb_disable, 454 455 .set_mode = bfin_musb_set_mode, 456 .try_idle = bfin_musb_try_idle, 457 458 .vbus_status = bfin_musb_vbus_status, 459 .set_vbus = bfin_musb_set_vbus, 460 461 .adjust_channel_params = bfin_musb_adjust_channel_params, 462}; 463 464static u64 bfin_dmamask = DMA_BIT_MASK(32); 465 466static int __devinit bfin_probe(struct platform_device *pdev) 467{ 468 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; 469 struct platform_device *musb; 470 struct bfin_glue *glue; 471 472 int ret = -ENOMEM; 473 474 glue = kzalloc(sizeof(*glue), GFP_KERNEL); 475 if (!glue) { 476 dev_err(&pdev->dev, "failed to allocate glue context\n"); 477 goto err0; 478 } 479 480 musb = platform_device_alloc("musb-hdrc", -1); 481 if (!musb) { 482 dev_err(&pdev->dev, "failed to allocate musb device\n"); 483 goto err1; 484 } 485 486 musb->dev.parent = &pdev->dev; 487 musb->dev.dma_mask = &bfin_dmamask; 488 musb->dev.coherent_dma_mask = bfin_dmamask; 489 490 glue->dev = &pdev->dev; 491 glue->musb = musb; 492 493 pdata->platform_ops = &bfin_ops; 494 495 platform_set_drvdata(pdev, glue); 496 497 ret = platform_device_add_resources(musb, pdev->resource, 498 pdev->num_resources); 499 if (ret) { 500 dev_err(&pdev->dev, "failed to add resources\n"); 501 goto err2; 502 } 503 504 ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); 505 if (ret) { 506 dev_err(&pdev->dev, "failed to add platform_data\n"); 507 goto err2; 508 } 509 510 ret = platform_device_add(musb); 511 if (ret) { 512 dev_err(&pdev->dev, "failed to register musb device\n"); 513 goto err2; 514 } 515 516 return 0; 517 518err2: 519 platform_device_put(musb); 520 521err1: 522 kfree(glue); 523 524err0: 525 return ret; 526} 527 528static int __devexit bfin_remove(struct platform_device *pdev) 529{ 530 struct bfin_glue *glue = platform_get_drvdata(pdev); 531 532 platform_device_del(glue->musb); 533 platform_device_put(glue->musb); 534 kfree(glue); 535 536 return 0; 537} 538 539#ifdef CONFIG_PM 540static int bfin_suspend(struct device *dev) 541{ 542 struct bfin_glue *glue = dev_get_drvdata(dev); 543 struct musb *musb = glue_to_musb(glue); 544 545 if (is_host_active(musb)) 546 /* 547 * During hibernate gpio_vrsel will change from high to low 548 * low which will generate wakeup event resume the system 549 * immediately. Set it to 0 before hibernate to avoid this 550 * wakeup event. 551 */ 552 gpio_set_value(musb->config->gpio_vrsel, 0); 553 554 return 0; 555} 556 557static int bfin_resume(struct device *dev) 558{ 559 struct bfin_glue *glue = dev_get_drvdata(dev); 560 struct musb *musb = glue_to_musb(glue); 561 562 bfin_musb_reg_init(musb); 563 564 return 0; 565} 566 567static struct dev_pm_ops bfin_pm_ops = { 568 .suspend = bfin_suspend, 569 .resume = bfin_resume, 570}; 571 572#define DEV_PM_OPS &bfin_pm_ops 573#else 574#define DEV_PM_OPS NULL 575#endif 576 577static struct platform_driver bfin_driver = { 578 .probe = bfin_probe, 579 .remove = __exit_p(bfin_remove), 580 .driver = { 581 .name = "musb-blackfin", 582 .pm = DEV_PM_OPS, 583 }, 584}; 585 586MODULE_DESCRIPTION("Blackfin MUSB Glue Layer"); 587MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>"); 588MODULE_LICENSE("GPL v2"); 589 590static int __init bfin_init(void) 591{ 592 return platform_driver_register(&bfin_driver); 593} 594module_init(bfin_init); 595 596static void __exit bfin_exit(void) 597{ 598 platform_driver_unregister(&bfin_driver); 599} 600module_exit(bfin_exit); 601