1/* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35/* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82/* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92#include <linux/module.h> 93#include <linux/kernel.h> 94#include <linux/sched.h> 95#include <linux/slab.h> 96#include <linux/init.h> 97#include <linux/list.h> 98#include <linux/kobject.h> 99#include <linux/prefetch.h> 100#include <linux/platform_device.h> 101#include <linux/io.h> 102 103#include "musb_core.h" 104 105#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 106 107 108#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 109#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 110 111#define MUSB_VERSION "6.0" 112 113#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 114 115#define MUSB_DRIVER_NAME "musb-hdrc" 116const char musb_driver_name[] = MUSB_DRIVER_NAME; 117 118MODULE_DESCRIPTION(DRIVER_INFO); 119MODULE_AUTHOR(DRIVER_AUTHOR); 120MODULE_LICENSE("GPL"); 121MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 122 123 124/*-------------------------------------------------------------------------*/ 125 126static inline struct musb *dev_to_musb(struct device *dev) 127{ 128 return dev_get_drvdata(dev); 129} 130 131/*-------------------------------------------------------------------------*/ 132 133#ifndef CONFIG_BLACKFIN 134static int musb_ulpi_read(struct usb_phy *phy, u32 offset) 135{ 136 void __iomem *addr = phy->io_priv; 137 int i = 0; 138 u8 r; 139 u8 power; 140 int ret; 141 142 pm_runtime_get_sync(phy->io_dev); 143 144 /* Make sure the transceiver is not in low power mode */ 145 power = musb_readb(addr, MUSB_POWER); 146 power &= ~MUSB_POWER_SUSPENDM; 147 musb_writeb(addr, MUSB_POWER, power); 148 149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 151 */ 152 153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 156 157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 158 & MUSB_ULPI_REG_CMPLT)) { 159 i++; 160 if (i == 10000) { 161 ret = -ETIMEDOUT; 162 goto out; 163 } 164 165 } 166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 167 r &= ~MUSB_ULPI_REG_CMPLT; 168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 169 170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA); 171 172out: 173 pm_runtime_put(phy->io_dev); 174 175 return ret; 176} 177 178static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) 179{ 180 void __iomem *addr = phy->io_priv; 181 int i = 0; 182 u8 r = 0; 183 u8 power; 184 int ret = 0; 185 186 pm_runtime_get_sync(phy->io_dev); 187 188 /* Make sure the transceiver is not in low power mode */ 189 power = musb_readb(addr, MUSB_POWER); 190 power &= ~MUSB_POWER_SUSPENDM; 191 musb_writeb(addr, MUSB_POWER, power); 192 193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 196 197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 198 & MUSB_ULPI_REG_CMPLT)) { 199 i++; 200 if (i == 10000) { 201 ret = -ETIMEDOUT; 202 goto out; 203 } 204 } 205 206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 207 r &= ~MUSB_ULPI_REG_CMPLT; 208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 209 210out: 211 pm_runtime_put(phy->io_dev); 212 213 return ret; 214} 215#else 216#define musb_ulpi_read NULL 217#define musb_ulpi_write NULL 218#endif 219 220static struct usb_phy_io_ops musb_ulpi_access = { 221 .read = musb_ulpi_read, 222 .write = musb_ulpi_write, 223}; 224 225/*-------------------------------------------------------------------------*/ 226 227#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) 228 229/* 230 * Load an endpoint's FIFO 231 */ 232void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 233{ 234 struct musb *musb = hw_ep->musb; 235 void __iomem *fifo = hw_ep->fifo; 236 237 prefetch((u8 *)src); 238 239 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 240 'T', hw_ep->epnum, fifo, len, src); 241 242 /* we can't assume unaligned reads work */ 243 if (likely((0x01 & (unsigned long) src) == 0)) { 244 u16 index = 0; 245 246 /* best case is 32bit-aligned source address */ 247 if ((0x02 & (unsigned long) src) == 0) { 248 if (len >= 4) { 249 writesl(fifo, src + index, len >> 2); 250 index += len & ~0x03; 251 } 252 if (len & 0x02) { 253 musb_writew(fifo, 0, *(u16 *)&src[index]); 254 index += 2; 255 } 256 } else { 257 if (len >= 2) { 258 writesw(fifo, src + index, len >> 1); 259 index += len & ~0x01; 260 } 261 } 262 if (len & 0x01) 263 musb_writeb(fifo, 0, src[index]); 264 } else { 265 /* byte aligned */ 266 writesb(fifo, src, len); 267 } 268} 269 270#if !defined(CONFIG_USB_MUSB_AM35X) 271/* 272 * Unload an endpoint's FIFO 273 */ 274void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 275{ 276 struct musb *musb = hw_ep->musb; 277 void __iomem *fifo = hw_ep->fifo; 278 279 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 280 'R', hw_ep->epnum, fifo, len, dst); 281 282 /* we can't assume unaligned writes work */ 283 if (likely((0x01 & (unsigned long) dst) == 0)) { 284 u16 index = 0; 285 286 /* best case is 32bit-aligned destination address */ 287 if ((0x02 & (unsigned long) dst) == 0) { 288 if (len >= 4) { 289 readsl(fifo, dst, len >> 2); 290 index = len & ~0x03; 291 } 292 if (len & 0x02) { 293 *(u16 *)&dst[index] = musb_readw(fifo, 0); 294 index += 2; 295 } 296 } else { 297 if (len >= 2) { 298 readsw(fifo, dst, len >> 1); 299 index = len & ~0x01; 300 } 301 } 302 if (len & 0x01) 303 dst[index] = musb_readb(fifo, 0); 304 } else { 305 /* byte aligned */ 306 readsb(fifo, dst, len); 307 } 308} 309#endif 310 311#endif /* normal PIO */ 312 313 314/*-------------------------------------------------------------------------*/ 315 316/* for high speed test mode; see USB 2.0 spec 7.1.20 */ 317static const u8 musb_test_packet[53] = { 318 /* implicit SYNC then DATA0 to start */ 319 320 /* JKJKJKJK x9 */ 321 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 322 /* JJKKJJKK x8 */ 323 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 324 /* JJJJKKKK x8 */ 325 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 326 /* JJJJJJJKKKKKKK x8 */ 327 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 328 /* JJJJJJJK x8 */ 329 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 330 /* JKKKKKKK x10, JK */ 331 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 332 333 /* implicit CRC16 then EOP to end */ 334}; 335 336void musb_load_testpacket(struct musb *musb) 337{ 338 void __iomem *regs = musb->endpoints[0].regs; 339 340 musb_ep_select(musb->mregs, 0); 341 musb_write_fifo(musb->control_ep, 342 sizeof(musb_test_packet), musb_test_packet); 343 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 344} 345 346/*-------------------------------------------------------------------------*/ 347 348/* 349 * Handles OTG hnp timeouts, such as b_ase0_brst 350 */ 351void musb_otg_timer_func(unsigned long data) 352{ 353 struct musb *musb = (struct musb *)data; 354 unsigned long flags; 355 356 spin_lock_irqsave(&musb->lock, flags); 357 switch (musb->xceiv->state) { 358 case OTG_STATE_B_WAIT_ACON: 359 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 360 musb_g_disconnect(musb); 361 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 362 musb->is_active = 0; 363 break; 364 case OTG_STATE_A_SUSPEND: 365 case OTG_STATE_A_WAIT_BCON: 366 dev_dbg(musb->controller, "HNP: %s timeout\n", 367 otg_state_string(musb->xceiv->state)); 368 musb_platform_set_vbus(musb, 0); 369 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 370 break; 371 default: 372 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", 373 otg_state_string(musb->xceiv->state)); 374 } 375 musb->ignore_disconnect = 0; 376 spin_unlock_irqrestore(&musb->lock, flags); 377} 378 379/* 380 * Stops the HNP transition. Caller must take care of locking. 381 */ 382void musb_hnp_stop(struct musb *musb) 383{ 384 struct usb_hcd *hcd = musb_to_hcd(musb); 385 void __iomem *mbase = musb->mregs; 386 u8 reg; 387 388 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); 389 390 switch (musb->xceiv->state) { 391 case OTG_STATE_A_PERIPHERAL: 392 musb_g_disconnect(musb); 393 dev_dbg(musb->controller, "HNP: back to %s\n", 394 otg_state_string(musb->xceiv->state)); 395 break; 396 case OTG_STATE_B_HOST: 397 dev_dbg(musb->controller, "HNP: Disabling HR\n"); 398 hcd->self.is_b_host = 0; 399 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 400 MUSB_DEV_MODE(musb); 401 reg = musb_readb(mbase, MUSB_POWER); 402 reg |= MUSB_POWER_SUSPENDM; 403 musb_writeb(mbase, MUSB_POWER, reg); 404 /* REVISIT: Start SESSION_REQUEST here? */ 405 break; 406 default: 407 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", 408 otg_state_string(musb->xceiv->state)); 409 } 410 411 /* 412 * When returning to A state after HNP, avoid hub_port_rebounce(), 413 * which cause occasional OPT A "Did not receive reset after connect" 414 * errors. 415 */ 416 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 417} 418 419/* 420 * Interrupt Service Routine to record USB "global" interrupts. 421 * Since these do not happen often and signify things of 422 * paramount importance, it seems OK to check them individually; 423 * the order of the tests is specified in the manual 424 * 425 * @param musb instance pointer 426 * @param int_usb register contents 427 * @param devctl 428 * @param power 429 */ 430 431static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 432 u8 devctl, u8 power) 433{ 434 struct usb_otg *otg = musb->xceiv->otg; 435 irqreturn_t handled = IRQ_NONE; 436 437 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 438 int_usb); 439 440 /* in host mode, the peripheral may issue remote wakeup. 441 * in peripheral mode, the host may resume the link. 442 * spurious RESUME irqs happen too, paired with SUSPEND. 443 */ 444 if (int_usb & MUSB_INTR_RESUME) { 445 handled = IRQ_HANDLED; 446 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); 447 448 if (devctl & MUSB_DEVCTL_HM) { 449 void __iomem *mbase = musb->mregs; 450 451 switch (musb->xceiv->state) { 452 case OTG_STATE_A_SUSPEND: 453 /* remote wakeup? later, GetPortStatus 454 * will stop RESUME signaling 455 */ 456 457 if (power & MUSB_POWER_SUSPENDM) { 458 /* spurious */ 459 musb->int_usb &= ~MUSB_INTR_SUSPEND; 460 dev_dbg(musb->controller, "Spurious SUSPENDM\n"); 461 break; 462 } 463 464 power &= ~MUSB_POWER_SUSPENDM; 465 musb_writeb(mbase, MUSB_POWER, 466 power | MUSB_POWER_RESUME); 467 468 musb->port1_status |= 469 (USB_PORT_STAT_C_SUSPEND << 16) 470 | MUSB_PORT_STAT_RESUME; 471 musb->rh_timer = jiffies 472 + msecs_to_jiffies(20); 473 474 musb->xceiv->state = OTG_STATE_A_HOST; 475 musb->is_active = 1; 476 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 477 break; 478 case OTG_STATE_B_WAIT_ACON: 479 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 480 musb->is_active = 1; 481 MUSB_DEV_MODE(musb); 482 break; 483 default: 484 WARNING("bogus %s RESUME (%s)\n", 485 "host", 486 otg_state_string(musb->xceiv->state)); 487 } 488 } else { 489 switch (musb->xceiv->state) { 490 case OTG_STATE_A_SUSPEND: 491 /* possibly DISCONNECT is upcoming */ 492 musb->xceiv->state = OTG_STATE_A_HOST; 493 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 494 break; 495 case OTG_STATE_B_WAIT_ACON: 496 case OTG_STATE_B_PERIPHERAL: 497 /* disconnect while suspended? we may 498 * not get a disconnect irq... 499 */ 500 if ((devctl & MUSB_DEVCTL_VBUS) 501 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 502 ) { 503 musb->int_usb |= MUSB_INTR_DISCONNECT; 504 musb->int_usb &= ~MUSB_INTR_SUSPEND; 505 break; 506 } 507 musb_g_resume(musb); 508 break; 509 case OTG_STATE_B_IDLE: 510 musb->int_usb &= ~MUSB_INTR_SUSPEND; 511 break; 512 default: 513 WARNING("bogus %s RESUME (%s)\n", 514 "peripheral", 515 otg_state_string(musb->xceiv->state)); 516 } 517 } 518 } 519 520 /* see manual for the order of the tests */ 521 if (int_usb & MUSB_INTR_SESSREQ) { 522 void __iomem *mbase = musb->mregs; 523 524 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 525 && (devctl & MUSB_DEVCTL_BDEVICE)) { 526 dev_dbg(musb->controller, "SessReq while on B state\n"); 527 return IRQ_HANDLED; 528 } 529 530 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", 531 otg_state_string(musb->xceiv->state)); 532 533 /* IRQ arrives from ID pin sense or (later, if VBUS power 534 * is removed) SRP. responses are time critical: 535 * - turn on VBUS (with silicon-specific mechanism) 536 * - go through A_WAIT_VRISE 537 * - ... to A_WAIT_BCON. 538 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 539 */ 540 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 541 musb->ep0_stage = MUSB_EP0_START; 542 musb->xceiv->state = OTG_STATE_A_IDLE; 543 MUSB_HST_MODE(musb); 544 musb_platform_set_vbus(musb, 1); 545 546 handled = IRQ_HANDLED; 547 } 548 549 if (int_usb & MUSB_INTR_VBUSERROR) { 550 int ignore = 0; 551 552 /* During connection as an A-Device, we may see a short 553 * current spikes causing voltage drop, because of cable 554 * and peripheral capacitance combined with vbus draw. 555 * (So: less common with truly self-powered devices, where 556 * vbus doesn't act like a power supply.) 557 * 558 * Such spikes are short; usually less than ~500 usec, max 559 * of ~2 msec. That is, they're not sustained overcurrent 560 * errors, though they're reported using VBUSERROR irqs. 561 * 562 * Workarounds: (a) hardware: use self powered devices. 563 * (b) software: ignore non-repeated VBUS errors. 564 * 565 * REVISIT: do delays from lots of DEBUG_KERNEL checks 566 * make trouble here, keeping VBUS < 4.4V ? 567 */ 568 switch (musb->xceiv->state) { 569 case OTG_STATE_A_HOST: 570 /* recovery is dicey once we've gotten past the 571 * initial stages of enumeration, but if VBUS 572 * stayed ok at the other end of the link, and 573 * another reset is due (at least for high speed, 574 * to redo the chirp etc), it might work OK... 575 */ 576 case OTG_STATE_A_WAIT_BCON: 577 case OTG_STATE_A_WAIT_VRISE: 578 if (musb->vbuserr_retry) { 579 void __iomem *mbase = musb->mregs; 580 581 musb->vbuserr_retry--; 582 ignore = 1; 583 devctl |= MUSB_DEVCTL_SESSION; 584 musb_writeb(mbase, MUSB_DEVCTL, devctl); 585 } else { 586 musb->port1_status |= 587 USB_PORT_STAT_OVERCURRENT 588 | (USB_PORT_STAT_C_OVERCURRENT << 16); 589 } 590 break; 591 default: 592 break; 593 } 594 595 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 596 otg_state_string(musb->xceiv->state), 597 devctl, 598 ({ char *s; 599 switch (devctl & MUSB_DEVCTL_VBUS) { 600 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 601 s = "<SessEnd"; break; 602 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 603 s = "<AValid"; break; 604 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 605 s = "<VBusValid"; break; 606 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 607 default: 608 s = "VALID"; break; 609 }; s; }), 610 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 611 musb->port1_status); 612 613 /* go through A_WAIT_VFALL then start a new session */ 614 if (!ignore) 615 musb_platform_set_vbus(musb, 0); 616 handled = IRQ_HANDLED; 617 } 618 619 if (int_usb & MUSB_INTR_SUSPEND) { 620 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", 621 otg_state_string(musb->xceiv->state), devctl, power); 622 handled = IRQ_HANDLED; 623 624 switch (musb->xceiv->state) { 625 case OTG_STATE_A_PERIPHERAL: 626 /* We also come here if the cable is removed, since 627 * this silicon doesn't report ID-no-longer-grounded. 628 * 629 * We depend on T(a_wait_bcon) to shut us down, and 630 * hope users don't do anything dicey during this 631 * undesired detour through A_WAIT_BCON. 632 */ 633 musb_hnp_stop(musb); 634 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 635 musb_root_disconnect(musb); 636 musb_platform_try_idle(musb, jiffies 637 + msecs_to_jiffies(musb->a_wait_bcon 638 ? : OTG_TIME_A_WAIT_BCON)); 639 640 break; 641 case OTG_STATE_B_IDLE: 642 if (!musb->is_active) 643 break; 644 case OTG_STATE_B_PERIPHERAL: 645 musb_g_suspend(musb); 646 musb->is_active = is_otg_enabled(musb) 647 && otg->gadget->b_hnp_enable; 648 if (musb->is_active) { 649 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 650 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); 651 mod_timer(&musb->otg_timer, jiffies 652 + msecs_to_jiffies( 653 OTG_TIME_B_ASE0_BRST)); 654 } 655 break; 656 case OTG_STATE_A_WAIT_BCON: 657 if (musb->a_wait_bcon != 0) 658 musb_platform_try_idle(musb, jiffies 659 + msecs_to_jiffies(musb->a_wait_bcon)); 660 break; 661 case OTG_STATE_A_HOST: 662 musb->xceiv->state = OTG_STATE_A_SUSPEND; 663 musb->is_active = is_otg_enabled(musb) 664 && otg->host->b_hnp_enable; 665 break; 666 case OTG_STATE_B_HOST: 667 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 668 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); 669 break; 670 default: 671 /* "should not happen" */ 672 musb->is_active = 0; 673 break; 674 } 675 } 676 677 if (int_usb & MUSB_INTR_CONNECT) { 678 struct usb_hcd *hcd = musb_to_hcd(musb); 679 680 handled = IRQ_HANDLED; 681 musb->is_active = 1; 682 683 musb->ep0_stage = MUSB_EP0_START; 684 685 /* flush endpoints when transitioning from Device Mode */ 686 if (is_peripheral_active(musb)) { 687 /* REVISIT HNP; just force disconnect */ 688 } 689 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); 690 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); 691 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 692 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 693 |USB_PORT_STAT_HIGH_SPEED 694 |USB_PORT_STAT_ENABLE 695 ); 696 musb->port1_status |= USB_PORT_STAT_CONNECTION 697 |(USB_PORT_STAT_C_CONNECTION << 16); 698 699 /* high vs full speed is just a guess until after reset */ 700 if (devctl & MUSB_DEVCTL_LSDEV) 701 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 702 703 /* indicate new connection to OTG machine */ 704 switch (musb->xceiv->state) { 705 case OTG_STATE_B_PERIPHERAL: 706 if (int_usb & MUSB_INTR_SUSPEND) { 707 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); 708 int_usb &= ~MUSB_INTR_SUSPEND; 709 goto b_host; 710 } else 711 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); 712 break; 713 case OTG_STATE_B_WAIT_ACON: 714 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); 715b_host: 716 musb->xceiv->state = OTG_STATE_B_HOST; 717 hcd->self.is_b_host = 1; 718 musb->ignore_disconnect = 0; 719 del_timer(&musb->otg_timer); 720 break; 721 default: 722 if ((devctl & MUSB_DEVCTL_VBUS) 723 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 724 musb->xceiv->state = OTG_STATE_A_HOST; 725 hcd->self.is_b_host = 0; 726 } 727 break; 728 } 729 730 /* poke the root hub */ 731 MUSB_HST_MODE(musb); 732 if (hcd->status_urb) 733 usb_hcd_poll_rh_status(hcd); 734 else 735 usb_hcd_resume_root_hub(hcd); 736 737 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", 738 otg_state_string(musb->xceiv->state), devctl); 739 } 740 741 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 742 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", 743 otg_state_string(musb->xceiv->state), 744 MUSB_MODE(musb), devctl); 745 handled = IRQ_HANDLED; 746 747 switch (musb->xceiv->state) { 748 case OTG_STATE_A_HOST: 749 case OTG_STATE_A_SUSPEND: 750 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 751 musb_root_disconnect(musb); 752 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 753 musb_platform_try_idle(musb, jiffies 754 + msecs_to_jiffies(musb->a_wait_bcon)); 755 break; 756 case OTG_STATE_B_HOST: 757 /* REVISIT this behaves for "real disconnect" 758 * cases; make sure the other transitions from 759 * from B_HOST act right too. The B_HOST code 760 * in hnp_stop() is currently not used... 761 */ 762 musb_root_disconnect(musb); 763 musb_to_hcd(musb)->self.is_b_host = 0; 764 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 765 MUSB_DEV_MODE(musb); 766 musb_g_disconnect(musb); 767 break; 768 case OTG_STATE_A_PERIPHERAL: 769 musb_hnp_stop(musb); 770 musb_root_disconnect(musb); 771 /* FALLTHROUGH */ 772 case OTG_STATE_B_WAIT_ACON: 773 /* FALLTHROUGH */ 774 case OTG_STATE_B_PERIPHERAL: 775 case OTG_STATE_B_IDLE: 776 musb_g_disconnect(musb); 777 break; 778 default: 779 WARNING("unhandled DISCONNECT transition (%s)\n", 780 otg_state_string(musb->xceiv->state)); 781 break; 782 } 783 } 784 785 /* mentor saves a bit: bus reset and babble share the same irq. 786 * only host sees babble; only peripheral sees bus reset. 787 */ 788 if (int_usb & MUSB_INTR_RESET) { 789 handled = IRQ_HANDLED; 790 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 791 /* 792 * Looks like non-HS BABBLE can be ignored, but 793 * HS BABBLE is an error condition. For HS the solution 794 * is to avoid babble in the first place and fix what 795 * caused BABBLE. When HS BABBLE happens we can only 796 * stop the session. 797 */ 798 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 799 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); 800 else { 801 ERR("Stopping host session -- babble\n"); 802 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 803 } 804 } else if (is_peripheral_capable()) { 805 dev_dbg(musb->controller, "BUS RESET as %s\n", 806 otg_state_string(musb->xceiv->state)); 807 switch (musb->xceiv->state) { 808 case OTG_STATE_A_SUSPEND: 809 /* We need to ignore disconnect on suspend 810 * otherwise tusb 2.0 won't reconnect after a 811 * power cycle, which breaks otg compliance. 812 */ 813 musb->ignore_disconnect = 1; 814 musb_g_reset(musb); 815 /* FALLTHROUGH */ 816 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 817 /* never use invalid T(a_wait_bcon) */ 818 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", 819 otg_state_string(musb->xceiv->state), 820 TA_WAIT_BCON(musb)); 821 mod_timer(&musb->otg_timer, jiffies 822 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 823 break; 824 case OTG_STATE_A_PERIPHERAL: 825 musb->ignore_disconnect = 0; 826 del_timer(&musb->otg_timer); 827 musb_g_reset(musb); 828 break; 829 case OTG_STATE_B_WAIT_ACON: 830 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", 831 otg_state_string(musb->xceiv->state)); 832 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 833 musb_g_reset(musb); 834 break; 835 case OTG_STATE_B_IDLE: 836 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 837 /* FALLTHROUGH */ 838 case OTG_STATE_B_PERIPHERAL: 839 musb_g_reset(musb); 840 break; 841 default: 842 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", 843 otg_state_string(musb->xceiv->state)); 844 } 845 } 846 } 847 848#if 0 849/* REVISIT ... this would be for multiplexing periodic endpoints, or 850 * supporting transfer phasing to prevent exceeding ISO bandwidth 851 * limits of a given frame or microframe. 852 * 853 * It's not needed for peripheral side, which dedicates endpoints; 854 * though it _might_ use SOF irqs for other purposes. 855 * 856 * And it's not currently needed for host side, which also dedicates 857 * endpoints, relies on TX/RX interval registers, and isn't claimed 858 * to support ISO transfers yet. 859 */ 860 if (int_usb & MUSB_INTR_SOF) { 861 void __iomem *mbase = musb->mregs; 862 struct musb_hw_ep *ep; 863 u8 epnum; 864 u16 frame; 865 866 dev_dbg(musb->controller, "START_OF_FRAME\n"); 867 handled = IRQ_HANDLED; 868 869 /* start any periodic Tx transfers waiting for current frame */ 870 frame = musb_readw(mbase, MUSB_FRAME); 871 ep = musb->endpoints; 872 for (epnum = 1; (epnum < musb->nr_endpoints) 873 && (musb->epmask >= (1 << epnum)); 874 epnum++, ep++) { 875 /* 876 * FIXME handle framecounter wraps (12 bits) 877 * eliminate duplicated StartUrb logic 878 */ 879 if (ep->dwWaitFrame >= frame) { 880 ep->dwWaitFrame = 0; 881 pr_debug("SOF --> periodic TX%s on %d\n", 882 ep->tx_channel ? " DMA" : "", 883 epnum); 884 if (!ep->tx_channel) 885 musb_h_tx_start(musb, epnum); 886 else 887 cppi_hostdma_start(musb, epnum); 888 } 889 } /* end of for loop */ 890 } 891#endif 892 893 schedule_work(&musb->irq_work); 894 895 return handled; 896} 897 898/*-------------------------------------------------------------------------*/ 899 900/* 901* Program the HDRC to start (enable interrupts, dma, etc.). 902*/ 903void musb_start(struct musb *musb) 904{ 905 void __iomem *regs = musb->mregs; 906 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 907 908 dev_dbg(musb->controller, "<== devctl %02x\n", devctl); 909 910 /* Set INT enable registers, enable interrupts */ 911 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 912 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 913 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 914 915 musb_writeb(regs, MUSB_TESTMODE, 0); 916 917 /* put into basic highspeed mode and start session */ 918 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 919 | MUSB_POWER_HSENAB 920 /* ENSUSPEND wedges tusb */ 921 /* | MUSB_POWER_ENSUSPEND */ 922 ); 923 924 musb->is_active = 0; 925 devctl = musb_readb(regs, MUSB_DEVCTL); 926 devctl &= ~MUSB_DEVCTL_SESSION; 927 928 if (is_otg_enabled(musb)) { 929 /* session started after: 930 * (a) ID-grounded irq, host mode; 931 * (b) vbus present/connect IRQ, peripheral mode; 932 * (c) peripheral initiates, using SRP 933 */ 934 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 935 musb->is_active = 1; 936 else 937 devctl |= MUSB_DEVCTL_SESSION; 938 939 } else if (is_host_enabled(musb)) { 940 /* assume ID pin is hard-wired to ground */ 941 devctl |= MUSB_DEVCTL_SESSION; 942 943 } else /* peripheral is enabled */ { 944 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 945 musb->is_active = 1; 946 } 947 musb_platform_enable(musb); 948 musb_writeb(regs, MUSB_DEVCTL, devctl); 949} 950 951 952static void musb_generic_disable(struct musb *musb) 953{ 954 void __iomem *mbase = musb->mregs; 955 u16 temp; 956 957 /* disable interrupts */ 958 musb_writeb(mbase, MUSB_INTRUSBE, 0); 959 musb_writew(mbase, MUSB_INTRTXE, 0); 960 musb_writew(mbase, MUSB_INTRRXE, 0); 961 962 /* off */ 963 musb_writeb(mbase, MUSB_DEVCTL, 0); 964 965 /* flush pending interrupts */ 966 temp = musb_readb(mbase, MUSB_INTRUSB); 967 temp = musb_readw(mbase, MUSB_INTRTX); 968 temp = musb_readw(mbase, MUSB_INTRRX); 969 970} 971 972/* 973 * Make the HDRC stop (disable interrupts, etc.); 974 * reversible by musb_start 975 * called on gadget driver unregister 976 * with controller locked, irqs blocked 977 * acts as a NOP unless some role activated the hardware 978 */ 979void musb_stop(struct musb *musb) 980{ 981 /* stop IRQs, timers, ... */ 982 musb_platform_disable(musb); 983 musb_generic_disable(musb); 984 dev_dbg(musb->controller, "HDRC disabled\n"); 985 986 /* FIXME 987 * - mark host and/or peripheral drivers unusable/inactive 988 * - disable DMA (and enable it in HdrcStart) 989 * - make sure we can musb_start() after musb_stop(); with 990 * OTG mode, gadget driver module rmmod/modprobe cycles that 991 * - ... 992 */ 993 musb_platform_try_idle(musb, 0); 994} 995 996static void musb_shutdown(struct platform_device *pdev) 997{ 998 struct musb *musb = dev_to_musb(&pdev->dev); 999 unsigned long flags; 1000 1001 pm_runtime_get_sync(musb->controller); 1002 1003 musb_gadget_cleanup(musb); 1004 1005 spin_lock_irqsave(&musb->lock, flags); 1006 musb_platform_disable(musb); 1007 musb_generic_disable(musb); 1008 spin_unlock_irqrestore(&musb->lock, flags); 1009 1010 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 1011 usb_remove_hcd(musb_to_hcd(musb)); 1012 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1013 musb_platform_exit(musb); 1014 1015 pm_runtime_put(musb->controller); 1016 /* FIXME power down */ 1017} 1018 1019 1020/*-------------------------------------------------------------------------*/ 1021 1022/* 1023 * The silicon either has hard-wired endpoint configurations, or else 1024 * "dynamic fifo" sizing. The driver has support for both, though at this 1025 * writing only the dynamic sizing is very well tested. Since we switched 1026 * away from compile-time hardware parameters, we can no longer rely on 1027 * dead code elimination to leave only the relevant one in the object file. 1028 * 1029 * We don't currently use dynamic fifo setup capability to do anything 1030 * more than selecting one of a bunch of predefined configurations. 1031 */ 1032#if defined(CONFIG_USB_MUSB_TUSB6010) \ 1033 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ 1034 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ 1035 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ 1036 || defined(CONFIG_USB_MUSB_AM35X) \ 1037 || defined(CONFIG_USB_MUSB_AM35X_MODULE) 1038static ushort __devinitdata fifo_mode = 4; 1039#elif defined(CONFIG_USB_MUSB_UX500) \ 1040 || defined(CONFIG_USB_MUSB_UX500_MODULE) 1041static ushort __devinitdata fifo_mode = 5; 1042#else 1043static ushort __devinitdata fifo_mode = 2; 1044#endif 1045 1046/* "modprobe ... fifo_mode=1" etc */ 1047module_param(fifo_mode, ushort, 0); 1048MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1049 1050/* 1051 * tables defining fifo_mode values. define more if you like. 1052 * for host side, make sure both halves of ep1 are set up. 1053 */ 1054 1055/* mode 0 - fits in 2KB */ 1056static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = { 1057{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1058{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1059{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1060{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1061{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1062}; 1063 1064/* mode 1 - fits in 4KB */ 1065static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = { 1066{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1067{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1068{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1069{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1070{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1071}; 1072 1073/* mode 2 - fits in 4KB */ 1074static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = { 1075{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1076{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1077{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1078{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1079{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1080{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1081}; 1082 1083/* mode 3 - fits in 4KB */ 1084static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = { 1085{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1086{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1087{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1088{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1089{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1090{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1091}; 1092 1093/* mode 4 - fits in 16KB */ 1094static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = { 1095{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1096{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1097{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1098{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1099{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1100{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1101{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1102{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1103{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1104{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1105{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1106{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1107{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1108{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1109{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1110{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1111{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1112{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1113{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1114{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1115{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1116{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1117{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1118{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1119{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1120{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1121{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1122}; 1123 1124/* mode 5 - fits in 8KB */ 1125static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = { 1126{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1127{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1128{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1129{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1130{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1131{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1132{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1133{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1134{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1135{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1136{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1137{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1138{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1139{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1140{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1141{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1142{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1143{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1144{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1145{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1146{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1147{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1148{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1149{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1150{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1151{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1152{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1153}; 1154 1155/* 1156 * configure a fifo; for non-shared endpoints, this may be called 1157 * once for a tx fifo and once for an rx fifo. 1158 * 1159 * returns negative errno or offset for next fifo. 1160 */ 1161static int __devinit 1162fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1163 const struct musb_fifo_cfg *cfg, u16 offset) 1164{ 1165 void __iomem *mbase = musb->mregs; 1166 int size = 0; 1167 u16 maxpacket = cfg->maxpacket; 1168 u16 c_off = offset >> 3; 1169 u8 c_size; 1170 1171 /* expect hw_ep has already been zero-initialized */ 1172 1173 size = ffs(max(maxpacket, (u16) 8)) - 1; 1174 maxpacket = 1 << size; 1175 1176 c_size = size - 3; 1177 if (cfg->mode == BUF_DOUBLE) { 1178 if ((offset + (maxpacket << 1)) > 1179 (1 << (musb->config->ram_bits + 2))) 1180 return -EMSGSIZE; 1181 c_size |= MUSB_FIFOSZ_DPB; 1182 } else { 1183 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1184 return -EMSGSIZE; 1185 } 1186 1187 /* configure the FIFO */ 1188 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1189 1190 /* EP0 reserved endpoint for control, bidirectional; 1191 * EP1 reserved for bulk, two unidirection halves. 1192 */ 1193 if (hw_ep->epnum == 1) 1194 musb->bulk_ep = hw_ep; 1195 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1196 switch (cfg->style) { 1197 case FIFO_TX: 1198 musb_write_txfifosz(mbase, c_size); 1199 musb_write_txfifoadd(mbase, c_off); 1200 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1201 hw_ep->max_packet_sz_tx = maxpacket; 1202 break; 1203 case FIFO_RX: 1204 musb_write_rxfifosz(mbase, c_size); 1205 musb_write_rxfifoadd(mbase, c_off); 1206 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1207 hw_ep->max_packet_sz_rx = maxpacket; 1208 break; 1209 case FIFO_RXTX: 1210 musb_write_txfifosz(mbase, c_size); 1211 musb_write_txfifoadd(mbase, c_off); 1212 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1213 hw_ep->max_packet_sz_rx = maxpacket; 1214 1215 musb_write_rxfifosz(mbase, c_size); 1216 musb_write_rxfifoadd(mbase, c_off); 1217 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1218 hw_ep->max_packet_sz_tx = maxpacket; 1219 1220 hw_ep->is_shared_fifo = true; 1221 break; 1222 } 1223 1224 /* NOTE rx and tx endpoint irqs aren't managed separately, 1225 * which happens to be ok 1226 */ 1227 musb->epmask |= (1 << hw_ep->epnum); 1228 1229 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1230} 1231 1232static struct musb_fifo_cfg __devinitdata ep0_cfg = { 1233 .style = FIFO_RXTX, .maxpacket = 64, 1234}; 1235 1236static int __devinit ep_config_from_table(struct musb *musb) 1237{ 1238 const struct musb_fifo_cfg *cfg; 1239 unsigned i, n; 1240 int offset; 1241 struct musb_hw_ep *hw_ep = musb->endpoints; 1242 1243 if (musb->config->fifo_cfg) { 1244 cfg = musb->config->fifo_cfg; 1245 n = musb->config->fifo_cfg_size; 1246 goto done; 1247 } 1248 1249 switch (fifo_mode) { 1250 default: 1251 fifo_mode = 0; 1252 /* FALLTHROUGH */ 1253 case 0: 1254 cfg = mode_0_cfg; 1255 n = ARRAY_SIZE(mode_0_cfg); 1256 break; 1257 case 1: 1258 cfg = mode_1_cfg; 1259 n = ARRAY_SIZE(mode_1_cfg); 1260 break; 1261 case 2: 1262 cfg = mode_2_cfg; 1263 n = ARRAY_SIZE(mode_2_cfg); 1264 break; 1265 case 3: 1266 cfg = mode_3_cfg; 1267 n = ARRAY_SIZE(mode_3_cfg); 1268 break; 1269 case 4: 1270 cfg = mode_4_cfg; 1271 n = ARRAY_SIZE(mode_4_cfg); 1272 break; 1273 case 5: 1274 cfg = mode_5_cfg; 1275 n = ARRAY_SIZE(mode_5_cfg); 1276 break; 1277 } 1278 1279 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1280 musb_driver_name, fifo_mode); 1281 1282 1283done: 1284 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1285 /* assert(offset > 0) */ 1286 1287 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1288 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1289 */ 1290 1291 for (i = 0; i < n; i++) { 1292 u8 epn = cfg->hw_ep_num; 1293 1294 if (epn >= musb->config->num_eps) { 1295 pr_debug("%s: invalid ep %d\n", 1296 musb_driver_name, epn); 1297 return -EINVAL; 1298 } 1299 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1300 if (offset < 0) { 1301 pr_debug("%s: mem overrun, ep %d\n", 1302 musb_driver_name, epn); 1303 return -EINVAL; 1304 } 1305 epn++; 1306 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1307 } 1308 1309 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1310 musb_driver_name, 1311 n + 1, musb->config->num_eps * 2 - 1, 1312 offset, (1 << (musb->config->ram_bits + 2))); 1313 1314 if (!musb->bulk_ep) { 1315 pr_debug("%s: missing bulk\n", musb_driver_name); 1316 return -EINVAL; 1317 } 1318 1319 return 0; 1320} 1321 1322 1323/* 1324 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1325 * @param musb the controller 1326 */ 1327static int __devinit ep_config_from_hw(struct musb *musb) 1328{ 1329 u8 epnum = 0; 1330 struct musb_hw_ep *hw_ep; 1331 void *mbase = musb->mregs; 1332 int ret = 0; 1333 1334 dev_dbg(musb->controller, "<== static silicon ep config\n"); 1335 1336 /* FIXME pick up ep0 maxpacket size */ 1337 1338 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1339 musb_ep_select(mbase, epnum); 1340 hw_ep = musb->endpoints + epnum; 1341 1342 ret = musb_read_fifosize(musb, hw_ep, epnum); 1343 if (ret < 0) 1344 break; 1345 1346 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1347 1348 /* pick an RX/TX endpoint for bulk */ 1349 if (hw_ep->max_packet_sz_tx < 512 1350 || hw_ep->max_packet_sz_rx < 512) 1351 continue; 1352 1353 /* REVISIT: this algorithm is lazy, we should at least 1354 * try to pick a double buffered endpoint. 1355 */ 1356 if (musb->bulk_ep) 1357 continue; 1358 musb->bulk_ep = hw_ep; 1359 } 1360 1361 if (!musb->bulk_ep) { 1362 pr_debug("%s: missing bulk\n", musb_driver_name); 1363 return -EINVAL; 1364 } 1365 1366 return 0; 1367} 1368 1369enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1370 1371/* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1372 * configure endpoints, or take their config from silicon 1373 */ 1374static int __devinit musb_core_init(u16 musb_type, struct musb *musb) 1375{ 1376 u8 reg; 1377 char *type; 1378 char aInfo[90], aRevision[32], aDate[12]; 1379 void __iomem *mbase = musb->mregs; 1380 int status = 0; 1381 int i; 1382 1383 /* log core options (read using indexed model) */ 1384 reg = musb_read_configdata(mbase); 1385 1386 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1387 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1388 strcat(aInfo, ", dyn FIFOs"); 1389 musb->dyn_fifo = true; 1390 } 1391 if (reg & MUSB_CONFIGDATA_MPRXE) { 1392 strcat(aInfo, ", bulk combine"); 1393 musb->bulk_combine = true; 1394 } 1395 if (reg & MUSB_CONFIGDATA_MPTXE) { 1396 strcat(aInfo, ", bulk split"); 1397 musb->bulk_split = true; 1398 } 1399 if (reg & MUSB_CONFIGDATA_HBRXE) { 1400 strcat(aInfo, ", HB-ISO Rx"); 1401 musb->hb_iso_rx = true; 1402 } 1403 if (reg & MUSB_CONFIGDATA_HBTXE) { 1404 strcat(aInfo, ", HB-ISO Tx"); 1405 musb->hb_iso_tx = true; 1406 } 1407 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1408 strcat(aInfo, ", SoftConn"); 1409 1410 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1411 musb_driver_name, reg, aInfo); 1412 1413 aDate[0] = 0; 1414 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1415 musb->is_multipoint = 1; 1416 type = "M"; 1417 } else { 1418 musb->is_multipoint = 0; 1419 type = ""; 1420#ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1421 printk(KERN_ERR 1422 "%s: kernel must blacklist external hubs\n", 1423 musb_driver_name); 1424#endif 1425 } 1426 1427 /* log release info */ 1428 musb->hwvers = musb_read_hwvers(mbase); 1429 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1430 MUSB_HWVERS_MINOR(musb->hwvers), 1431 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1432 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1433 musb_driver_name, type, aRevision, aDate); 1434 1435 /* configure ep0 */ 1436 musb_configure_ep0(musb); 1437 1438 /* discover endpoint configuration */ 1439 musb->nr_endpoints = 1; 1440 musb->epmask = 1; 1441 1442 if (musb->dyn_fifo) 1443 status = ep_config_from_table(musb); 1444 else 1445 status = ep_config_from_hw(musb); 1446 1447 if (status < 0) 1448 return status; 1449 1450 /* finish init, and print endpoint config */ 1451 for (i = 0; i < musb->nr_endpoints; i++) { 1452 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1453 1454 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1455#if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) 1456 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1457 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1458 hw_ep->fifo_sync_va = 1459 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1460 1461 if (i == 0) 1462 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1463 else 1464 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1465#endif 1466 1467 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1468 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1469 hw_ep->rx_reinit = 1; 1470 hw_ep->tx_reinit = 1; 1471 1472 if (hw_ep->max_packet_sz_tx) { 1473 dev_dbg(musb->controller, 1474 "%s: hw_ep %d%s, %smax %d\n", 1475 musb_driver_name, i, 1476 hw_ep->is_shared_fifo ? "shared" : "tx", 1477 hw_ep->tx_double_buffered 1478 ? "doublebuffer, " : "", 1479 hw_ep->max_packet_sz_tx); 1480 } 1481 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1482 dev_dbg(musb->controller, 1483 "%s: hw_ep %d%s, %smax %d\n", 1484 musb_driver_name, i, 1485 "rx", 1486 hw_ep->rx_double_buffered 1487 ? "doublebuffer, " : "", 1488 hw_ep->max_packet_sz_rx); 1489 } 1490 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1491 dev_dbg(musb->controller, "hw_ep %d not configured\n", i); 1492 } 1493 1494 return 0; 1495} 1496 1497/*-------------------------------------------------------------------------*/ 1498 1499#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ 1500 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) 1501 1502static irqreturn_t generic_interrupt(int irq, void *__hci) 1503{ 1504 unsigned long flags; 1505 irqreturn_t retval = IRQ_NONE; 1506 struct musb *musb = __hci; 1507 1508 spin_lock_irqsave(&musb->lock, flags); 1509 1510 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1511 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1512 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1513 1514 if (musb->int_usb || musb->int_tx || musb->int_rx) 1515 retval = musb_interrupt(musb); 1516 1517 spin_unlock_irqrestore(&musb->lock, flags); 1518 1519 return retval; 1520} 1521 1522#else 1523#define generic_interrupt NULL 1524#endif 1525 1526/* 1527 * handle all the irqs defined by the HDRC core. for now we expect: other 1528 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1529 * will be assigned, and the irq will already have been acked. 1530 * 1531 * called in irq context with spinlock held, irqs blocked 1532 */ 1533irqreturn_t musb_interrupt(struct musb *musb) 1534{ 1535 irqreturn_t retval = IRQ_NONE; 1536 u8 devctl, power; 1537 int ep_num; 1538 u32 reg; 1539 1540 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1541 power = musb_readb(musb->mregs, MUSB_POWER); 1542 1543 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", 1544 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1545 musb->int_usb, musb->int_tx, musb->int_rx); 1546 1547 /* the core can interrupt us for multiple reasons; docs have 1548 * a generic interrupt flowchart to follow 1549 */ 1550 if (musb->int_usb) 1551 retval |= musb_stage0_irq(musb, musb->int_usb, 1552 devctl, power); 1553 1554 /* "stage 1" is handling endpoint irqs */ 1555 1556 /* handle endpoint 0 first */ 1557 if (musb->int_tx & 1) { 1558 if (devctl & MUSB_DEVCTL_HM) 1559 retval |= musb_h_ep0_irq(musb); 1560 else 1561 retval |= musb_g_ep0_irq(musb); 1562 } 1563 1564 /* RX on endpoints 1-15 */ 1565 reg = musb->int_rx >> 1; 1566 ep_num = 1; 1567 while (reg) { 1568 if (reg & 1) { 1569 /* musb_ep_select(musb->mregs, ep_num); */ 1570 /* REVISIT just retval = ep->rx_irq(...) */ 1571 retval = IRQ_HANDLED; 1572 if (devctl & MUSB_DEVCTL_HM) { 1573 if (is_host_capable()) 1574 musb_host_rx(musb, ep_num); 1575 } else { 1576 if (is_peripheral_capable()) 1577 musb_g_rx(musb, ep_num); 1578 } 1579 } 1580 1581 reg >>= 1; 1582 ep_num++; 1583 } 1584 1585 /* TX on endpoints 1-15 */ 1586 reg = musb->int_tx >> 1; 1587 ep_num = 1; 1588 while (reg) { 1589 if (reg & 1) { 1590 /* musb_ep_select(musb->mregs, ep_num); */ 1591 /* REVISIT just retval |= ep->tx_irq(...) */ 1592 retval = IRQ_HANDLED; 1593 if (devctl & MUSB_DEVCTL_HM) { 1594 if (is_host_capable()) 1595 musb_host_tx(musb, ep_num); 1596 } else { 1597 if (is_peripheral_capable()) 1598 musb_g_tx(musb, ep_num); 1599 } 1600 } 1601 reg >>= 1; 1602 ep_num++; 1603 } 1604 1605 return retval; 1606} 1607EXPORT_SYMBOL_GPL(musb_interrupt); 1608 1609#ifndef CONFIG_MUSB_PIO_ONLY 1610static bool __devinitdata use_dma = 1; 1611 1612/* "modprobe ... use_dma=0" etc */ 1613module_param(use_dma, bool, 0); 1614MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1615 1616void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1617{ 1618 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1619 1620 /* called with controller lock already held */ 1621 1622 if (!epnum) { 1623#ifndef CONFIG_USB_TUSB_OMAP_DMA 1624 if (!is_cppi_enabled()) { 1625 /* endpoint 0 */ 1626 if (devctl & MUSB_DEVCTL_HM) 1627 musb_h_ep0_irq(musb); 1628 else 1629 musb_g_ep0_irq(musb); 1630 } 1631#endif 1632 } else { 1633 /* endpoints 1..15 */ 1634 if (transmit) { 1635 if (devctl & MUSB_DEVCTL_HM) { 1636 if (is_host_capable()) 1637 musb_host_tx(musb, epnum); 1638 } else { 1639 if (is_peripheral_capable()) 1640 musb_g_tx(musb, epnum); 1641 } 1642 } else { 1643 /* receive */ 1644 if (devctl & MUSB_DEVCTL_HM) { 1645 if (is_host_capable()) 1646 musb_host_rx(musb, epnum); 1647 } else { 1648 if (is_peripheral_capable()) 1649 musb_g_rx(musb, epnum); 1650 } 1651 } 1652 } 1653} 1654EXPORT_SYMBOL_GPL(musb_dma_completion); 1655 1656#else 1657#define use_dma 0 1658#endif 1659 1660/*-------------------------------------------------------------------------*/ 1661 1662#ifdef CONFIG_SYSFS 1663 1664static ssize_t 1665musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1666{ 1667 struct musb *musb = dev_to_musb(dev); 1668 unsigned long flags; 1669 int ret = -EINVAL; 1670 1671 spin_lock_irqsave(&musb->lock, flags); 1672 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); 1673 spin_unlock_irqrestore(&musb->lock, flags); 1674 1675 return ret; 1676} 1677 1678static ssize_t 1679musb_mode_store(struct device *dev, struct device_attribute *attr, 1680 const char *buf, size_t n) 1681{ 1682 struct musb *musb = dev_to_musb(dev); 1683 unsigned long flags; 1684 int status; 1685 1686 spin_lock_irqsave(&musb->lock, flags); 1687 if (sysfs_streq(buf, "host")) 1688 status = musb_platform_set_mode(musb, MUSB_HOST); 1689 else if (sysfs_streq(buf, "peripheral")) 1690 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1691 else if (sysfs_streq(buf, "otg")) 1692 status = musb_platform_set_mode(musb, MUSB_OTG); 1693 else 1694 status = -EINVAL; 1695 spin_unlock_irqrestore(&musb->lock, flags); 1696 1697 return (status == 0) ? n : status; 1698} 1699static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1700 1701static ssize_t 1702musb_vbus_store(struct device *dev, struct device_attribute *attr, 1703 const char *buf, size_t n) 1704{ 1705 struct musb *musb = dev_to_musb(dev); 1706 unsigned long flags; 1707 unsigned long val; 1708 1709 if (sscanf(buf, "%lu", &val) < 1) { 1710 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1711 return -EINVAL; 1712 } 1713 1714 spin_lock_irqsave(&musb->lock, flags); 1715 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1716 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1717 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1718 musb->is_active = 0; 1719 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1720 spin_unlock_irqrestore(&musb->lock, flags); 1721 1722 return n; 1723} 1724 1725static ssize_t 1726musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1727{ 1728 struct musb *musb = dev_to_musb(dev); 1729 unsigned long flags; 1730 unsigned long val; 1731 int vbus; 1732 1733 spin_lock_irqsave(&musb->lock, flags); 1734 val = musb->a_wait_bcon; 1735 /* FIXME get_vbus_status() is normally #defined as false... 1736 * and is effectively TUSB-specific. 1737 */ 1738 vbus = musb_platform_get_vbus_status(musb); 1739 spin_unlock_irqrestore(&musb->lock, flags); 1740 1741 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1742 vbus ? "on" : "off", val); 1743} 1744static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1745 1746/* Gadget drivers can't know that a host is connected so they might want 1747 * to start SRP, but users can. This allows userspace to trigger SRP. 1748 */ 1749static ssize_t 1750musb_srp_store(struct device *dev, struct device_attribute *attr, 1751 const char *buf, size_t n) 1752{ 1753 struct musb *musb = dev_to_musb(dev); 1754 unsigned short srp; 1755 1756 if (sscanf(buf, "%hu", &srp) != 1 1757 || (srp != 1)) { 1758 dev_err(dev, "SRP: Value must be 1\n"); 1759 return -EINVAL; 1760 } 1761 1762 if (srp == 1) 1763 musb_g_wakeup(musb); 1764 1765 return n; 1766} 1767static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1768 1769static struct attribute *musb_attributes[] = { 1770 &dev_attr_mode.attr, 1771 &dev_attr_vbus.attr, 1772 &dev_attr_srp.attr, 1773 NULL 1774}; 1775 1776static const struct attribute_group musb_attr_group = { 1777 .attrs = musb_attributes, 1778}; 1779 1780#endif /* sysfs */ 1781 1782/* Only used to provide driver mode change events */ 1783static void musb_irq_work(struct work_struct *data) 1784{ 1785 struct musb *musb = container_of(data, struct musb, irq_work); 1786 static int old_state; 1787 1788 if (musb->xceiv->state != old_state) { 1789 old_state = musb->xceiv->state; 1790 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1791 } 1792} 1793 1794/* -------------------------------------------------------------------------- 1795 * Init support 1796 */ 1797 1798static struct musb *__devinit 1799allocate_instance(struct device *dev, 1800 struct musb_hdrc_config *config, void __iomem *mbase) 1801{ 1802 struct musb *musb; 1803 struct musb_hw_ep *ep; 1804 int epnum; 1805 struct usb_hcd *hcd; 1806 1807 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1808 if (!hcd) 1809 return NULL; 1810 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1811 1812 musb = hcd_to_musb(hcd); 1813 INIT_LIST_HEAD(&musb->control); 1814 INIT_LIST_HEAD(&musb->in_bulk); 1815 INIT_LIST_HEAD(&musb->out_bulk); 1816 1817 hcd->uses_new_polling = 1; 1818 hcd->has_tt = 1; 1819 1820 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1821 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1822 dev_set_drvdata(dev, musb); 1823 musb->mregs = mbase; 1824 musb->ctrl_base = mbase; 1825 musb->nIrq = -ENODEV; 1826 musb->config = config; 1827 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1828 for (epnum = 0, ep = musb->endpoints; 1829 epnum < musb->config->num_eps; 1830 epnum++, ep++) { 1831 ep->musb = musb; 1832 ep->epnum = epnum; 1833 } 1834 1835 musb->controller = dev; 1836 1837 return musb; 1838} 1839 1840static void musb_free(struct musb *musb) 1841{ 1842 /* this has multiple entry modes. it handles fault cleanup after 1843 * probe(), where things may be partially set up, as well as rmmod 1844 * cleanup after everything's been de-activated. 1845 */ 1846 1847#ifdef CONFIG_SYSFS 1848 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1849#endif 1850 1851 if (musb->nIrq >= 0) { 1852 if (musb->irq_wake) 1853 disable_irq_wake(musb->nIrq); 1854 free_irq(musb->nIrq, musb); 1855 } 1856 if (is_dma_capable() && musb->dma_controller) { 1857 struct dma_controller *c = musb->dma_controller; 1858 1859 (void) c->stop(c); 1860 dma_controller_destroy(c); 1861 } 1862 1863 kfree(musb); 1864} 1865 1866/* 1867 * Perform generic per-controller initialization. 1868 * 1869 * @pDevice: the controller (already clocked, etc) 1870 * @nIrq: irq 1871 * @mregs: virtual address of controller registers, 1872 * not yet corrected for platform-specific offsets 1873 */ 1874static int __devinit 1875musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1876{ 1877 int status; 1878 struct musb *musb; 1879 struct musb_hdrc_platform_data *plat = dev->platform_data; 1880 1881 /* The driver might handle more features than the board; OK. 1882 * Fail when the board needs a feature that's not enabled. 1883 */ 1884 if (!plat) { 1885 dev_dbg(dev, "no platform_data?\n"); 1886 status = -ENODEV; 1887 goto fail0; 1888 } 1889 1890 /* allocate */ 1891 musb = allocate_instance(dev, plat->config, ctrl); 1892 if (!musb) { 1893 status = -ENOMEM; 1894 goto fail0; 1895 } 1896 1897 pm_runtime_use_autosuspend(musb->controller); 1898 pm_runtime_set_autosuspend_delay(musb->controller, 200); 1899 pm_runtime_enable(musb->controller); 1900 1901 spin_lock_init(&musb->lock); 1902 musb->board_mode = plat->mode; 1903 musb->board_set_power = plat->set_power; 1904 musb->min_power = plat->min_power; 1905 musb->ops = plat->platform_ops; 1906 1907 /* The musb_platform_init() call: 1908 * - adjusts musb->mregs and musb->isr if needed, 1909 * - may initialize an integrated tranceiver 1910 * - initializes musb->xceiv, usually by otg_get_transceiver() 1911 * - stops powering VBUS 1912 * 1913 * There are various transceiver configurations. Blackfin, 1914 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1915 * external/discrete ones in various flavors (twl4030 family, 1916 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1917 */ 1918 musb->isr = generic_interrupt; 1919 status = musb_platform_init(musb); 1920 if (status < 0) 1921 goto fail1; 1922 1923 if (!musb->isr) { 1924 status = -ENODEV; 1925 goto fail2; 1926 } 1927 1928 if (!musb->xceiv->io_ops) { 1929 musb->xceiv->io_dev = musb->controller; 1930 musb->xceiv->io_priv = musb->mregs; 1931 musb->xceiv->io_ops = &musb_ulpi_access; 1932 } 1933 1934 pm_runtime_get_sync(musb->controller); 1935 1936#ifndef CONFIG_MUSB_PIO_ONLY 1937 if (use_dma && dev->dma_mask) { 1938 struct dma_controller *c; 1939 1940 c = dma_controller_create(musb, musb->mregs); 1941 musb->dma_controller = c; 1942 if (c) 1943 (void) c->start(c); 1944 } 1945#endif 1946 /* ideally this would be abstracted in platform setup */ 1947 if (!is_dma_capable() || !musb->dma_controller) 1948 dev->dma_mask = NULL; 1949 1950 /* be sure interrupts are disabled before connecting ISR */ 1951 musb_platform_disable(musb); 1952 musb_generic_disable(musb); 1953 1954 /* setup musb parts of the core (especially endpoints) */ 1955 status = musb_core_init(plat->config->multipoint 1956 ? MUSB_CONTROLLER_MHDRC 1957 : MUSB_CONTROLLER_HDRC, musb); 1958 if (status < 0) 1959 goto fail3; 1960 1961 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 1962 1963 /* Init IRQ workqueue before request_irq */ 1964 INIT_WORK(&musb->irq_work, musb_irq_work); 1965 1966 /* attach to the IRQ */ 1967 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 1968 dev_err(dev, "request_irq %d failed!\n", nIrq); 1969 status = -ENODEV; 1970 goto fail3; 1971 } 1972 musb->nIrq = nIrq; 1973/* FIXME this handles wakeup irqs wrong */ 1974 if (enable_irq_wake(nIrq) == 0) { 1975 musb->irq_wake = 1; 1976 device_init_wakeup(dev, 1); 1977 } else { 1978 musb->irq_wake = 0; 1979 } 1980 1981 /* host side needs more setup */ 1982 if (is_host_enabled(musb)) { 1983 struct usb_hcd *hcd = musb_to_hcd(musb); 1984 1985 otg_set_host(musb->xceiv->otg, &hcd->self); 1986 1987 if (is_otg_enabled(musb)) 1988 hcd->self.otg_port = 1; 1989 musb->xceiv->otg->host = &hcd->self; 1990 hcd->power_budget = 2 * (plat->power ? : 250); 1991 1992 /* program PHY to use external vBus if required */ 1993 if (plat->extvbus) { 1994 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 1995 busctl |= MUSB_ULPI_USE_EXTVBUS; 1996 musb_write_ulpi_buscontrol(musb->mregs, busctl); 1997 } 1998 } 1999 2000 /* For the host-only role, we can activate right away. 2001 * (We expect the ID pin to be forcibly grounded!!) 2002 * Otherwise, wait till the gadget driver hooks up. 2003 */ 2004 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2005 struct usb_hcd *hcd = musb_to_hcd(musb); 2006 2007 MUSB_HST_MODE(musb); 2008 musb->xceiv->otg->default_a = 1; 2009 musb->xceiv->state = OTG_STATE_A_IDLE; 2010 2011 status = usb_add_hcd(musb_to_hcd(musb), 0, 0); 2012 2013 hcd->self.uses_pio_for_control = 1; 2014 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n", 2015 "HOST", status, 2016 musb_readb(musb->mregs, MUSB_DEVCTL), 2017 (musb_readb(musb->mregs, MUSB_DEVCTL) 2018 & MUSB_DEVCTL_BDEVICE 2019 ? 'B' : 'A')); 2020 2021 } else /* peripheral is enabled */ { 2022 MUSB_DEV_MODE(musb); 2023 musb->xceiv->otg->default_a = 0; 2024 musb->xceiv->state = OTG_STATE_B_IDLE; 2025 2026 status = musb_gadget_setup(musb); 2027 2028 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n", 2029 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2030 status, 2031 musb_readb(musb->mregs, MUSB_DEVCTL)); 2032 2033 } 2034 if (status < 0) 2035 goto fail3; 2036 2037 status = musb_init_debugfs(musb); 2038 if (status < 0) 2039 goto fail4; 2040 2041#ifdef CONFIG_SYSFS 2042 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2043 if (status) 2044 goto fail5; 2045#endif 2046 2047 pm_runtime_put(musb->controller); 2048 2049 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", 2050 ({char *s; 2051 switch (musb->board_mode) { 2052 case MUSB_HOST: s = "Host"; break; 2053 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2054 default: s = "OTG"; break; 2055 }; s; }), 2056 ctrl, 2057 (is_dma_capable() && musb->dma_controller) 2058 ? "DMA" : "PIO", 2059 musb->nIrq); 2060 2061 return 0; 2062 2063fail5: 2064 musb_exit_debugfs(musb); 2065 2066fail4: 2067 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 2068 usb_remove_hcd(musb_to_hcd(musb)); 2069 else 2070 musb_gadget_cleanup(musb); 2071 2072fail3: 2073 pm_runtime_put_sync(musb->controller); 2074 2075fail2: 2076 if (musb->irq_wake) 2077 device_init_wakeup(dev, 0); 2078 musb_platform_exit(musb); 2079 2080fail1: 2081 dev_err(musb->controller, 2082 "musb_init_controller failed with status %d\n", status); 2083 2084 musb_free(musb); 2085 2086fail0: 2087 2088 return status; 2089 2090} 2091 2092/*-------------------------------------------------------------------------*/ 2093 2094/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2095 * bridge to a platform device; this driver then suffices. 2096 */ 2097 2098#ifndef CONFIG_MUSB_PIO_ONLY 2099static u64 *orig_dma_mask; 2100#endif 2101 2102static int __devinit musb_probe(struct platform_device *pdev) 2103{ 2104 struct device *dev = &pdev->dev; 2105 int irq = platform_get_irq_byname(pdev, "mc"); 2106 int status; 2107 struct resource *iomem; 2108 void __iomem *base; 2109 2110 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2111 if (!iomem || irq <= 0) 2112 return -ENODEV; 2113 2114 base = ioremap(iomem->start, resource_size(iomem)); 2115 if (!base) { 2116 dev_err(dev, "ioremap failed\n"); 2117 return -ENOMEM; 2118 } 2119 2120#ifndef CONFIG_MUSB_PIO_ONLY 2121 /* clobbered by use_dma=n */ 2122 orig_dma_mask = dev->dma_mask; 2123#endif 2124 status = musb_init_controller(dev, irq, base); 2125 if (status < 0) 2126 iounmap(base); 2127 2128 return status; 2129} 2130 2131static int __devexit musb_remove(struct platform_device *pdev) 2132{ 2133 struct musb *musb = dev_to_musb(&pdev->dev); 2134 void __iomem *ctrl_base = musb->ctrl_base; 2135 2136 /* this gets called on rmmod. 2137 * - Host mode: host may still be active 2138 * - Peripheral mode: peripheral is deactivated (or never-activated) 2139 * - OTG mode: both roles are deactivated (or never-activated) 2140 */ 2141 musb_exit_debugfs(musb); 2142 musb_shutdown(pdev); 2143 2144 musb_free(musb); 2145 iounmap(ctrl_base); 2146 device_init_wakeup(&pdev->dev, 0); 2147#ifndef CONFIG_MUSB_PIO_ONLY 2148 pdev->dev.dma_mask = orig_dma_mask; 2149#endif 2150 return 0; 2151} 2152 2153#ifdef CONFIG_PM 2154 2155static void musb_save_context(struct musb *musb) 2156{ 2157 int i; 2158 void __iomem *musb_base = musb->mregs; 2159 void __iomem *epio; 2160 2161 if (is_host_enabled(musb)) { 2162 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2163 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2164 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2165 } 2166 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2167 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2168 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2169 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2170 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2171 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2172 2173 for (i = 0; i < musb->config->num_eps; ++i) { 2174 struct musb_hw_ep *hw_ep; 2175 2176 hw_ep = &musb->endpoints[i]; 2177 if (!hw_ep) 2178 continue; 2179 2180 epio = hw_ep->regs; 2181 if (!epio) 2182 continue; 2183 2184 musb_writeb(musb_base, MUSB_INDEX, i); 2185 musb->context.index_regs[i].txmaxp = 2186 musb_readw(epio, MUSB_TXMAXP); 2187 musb->context.index_regs[i].txcsr = 2188 musb_readw(epio, MUSB_TXCSR); 2189 musb->context.index_regs[i].rxmaxp = 2190 musb_readw(epio, MUSB_RXMAXP); 2191 musb->context.index_regs[i].rxcsr = 2192 musb_readw(epio, MUSB_RXCSR); 2193 2194 if (musb->dyn_fifo) { 2195 musb->context.index_regs[i].txfifoadd = 2196 musb_read_txfifoadd(musb_base); 2197 musb->context.index_regs[i].rxfifoadd = 2198 musb_read_rxfifoadd(musb_base); 2199 musb->context.index_regs[i].txfifosz = 2200 musb_read_txfifosz(musb_base); 2201 musb->context.index_regs[i].rxfifosz = 2202 musb_read_rxfifosz(musb_base); 2203 } 2204 if (is_host_enabled(musb)) { 2205 musb->context.index_regs[i].txtype = 2206 musb_readb(epio, MUSB_TXTYPE); 2207 musb->context.index_regs[i].txinterval = 2208 musb_readb(epio, MUSB_TXINTERVAL); 2209 musb->context.index_regs[i].rxtype = 2210 musb_readb(epio, MUSB_RXTYPE); 2211 musb->context.index_regs[i].rxinterval = 2212 musb_readb(epio, MUSB_RXINTERVAL); 2213 2214 musb->context.index_regs[i].txfunaddr = 2215 musb_read_txfunaddr(musb_base, i); 2216 musb->context.index_regs[i].txhubaddr = 2217 musb_read_txhubaddr(musb_base, i); 2218 musb->context.index_regs[i].txhubport = 2219 musb_read_txhubport(musb_base, i); 2220 2221 musb->context.index_regs[i].rxfunaddr = 2222 musb_read_rxfunaddr(musb_base, i); 2223 musb->context.index_regs[i].rxhubaddr = 2224 musb_read_rxhubaddr(musb_base, i); 2225 musb->context.index_regs[i].rxhubport = 2226 musb_read_rxhubport(musb_base, i); 2227 } 2228 } 2229} 2230 2231static void musb_restore_context(struct musb *musb) 2232{ 2233 int i; 2234 void __iomem *musb_base = musb->mregs; 2235 void __iomem *ep_target_regs; 2236 void __iomem *epio; 2237 2238 if (is_host_enabled(musb)) { 2239 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2240 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2241 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2242 } 2243 musb_writeb(musb_base, MUSB_POWER, musb->context.power); 2244 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); 2245 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); 2246 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2247 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2248 2249 for (i = 0; i < musb->config->num_eps; ++i) { 2250 struct musb_hw_ep *hw_ep; 2251 2252 hw_ep = &musb->endpoints[i]; 2253 if (!hw_ep) 2254 continue; 2255 2256 epio = hw_ep->regs; 2257 if (!epio) 2258 continue; 2259 2260 musb_writeb(musb_base, MUSB_INDEX, i); 2261 musb_writew(epio, MUSB_TXMAXP, 2262 musb->context.index_regs[i].txmaxp); 2263 musb_writew(epio, MUSB_TXCSR, 2264 musb->context.index_regs[i].txcsr); 2265 musb_writew(epio, MUSB_RXMAXP, 2266 musb->context.index_regs[i].rxmaxp); 2267 musb_writew(epio, MUSB_RXCSR, 2268 musb->context.index_regs[i].rxcsr); 2269 2270 if (musb->dyn_fifo) { 2271 musb_write_txfifosz(musb_base, 2272 musb->context.index_regs[i].txfifosz); 2273 musb_write_rxfifosz(musb_base, 2274 musb->context.index_regs[i].rxfifosz); 2275 musb_write_txfifoadd(musb_base, 2276 musb->context.index_regs[i].txfifoadd); 2277 musb_write_rxfifoadd(musb_base, 2278 musb->context.index_regs[i].rxfifoadd); 2279 } 2280 2281 if (is_host_enabled(musb)) { 2282 musb_writeb(epio, MUSB_TXTYPE, 2283 musb->context.index_regs[i].txtype); 2284 musb_writeb(epio, MUSB_TXINTERVAL, 2285 musb->context.index_regs[i].txinterval); 2286 musb_writeb(epio, MUSB_RXTYPE, 2287 musb->context.index_regs[i].rxtype); 2288 musb_writeb(epio, MUSB_RXINTERVAL, 2289 2290 musb->context.index_regs[i].rxinterval); 2291 musb_write_txfunaddr(musb_base, i, 2292 musb->context.index_regs[i].txfunaddr); 2293 musb_write_txhubaddr(musb_base, i, 2294 musb->context.index_regs[i].txhubaddr); 2295 musb_write_txhubport(musb_base, i, 2296 musb->context.index_regs[i].txhubport); 2297 2298 ep_target_regs = 2299 musb_read_target_reg_base(i, musb_base); 2300 2301 musb_write_rxfunaddr(ep_target_regs, 2302 musb->context.index_regs[i].rxfunaddr); 2303 musb_write_rxhubaddr(ep_target_regs, 2304 musb->context.index_regs[i].rxhubaddr); 2305 musb_write_rxhubport(ep_target_regs, 2306 musb->context.index_regs[i].rxhubport); 2307 } 2308 } 2309 musb_writeb(musb_base, MUSB_INDEX, musb->context.index); 2310} 2311 2312static int musb_suspend(struct device *dev) 2313{ 2314 struct musb *musb = dev_to_musb(dev); 2315 unsigned long flags; 2316 2317 spin_lock_irqsave(&musb->lock, flags); 2318 2319 if (is_peripheral_active(musb)) { 2320 /* FIXME force disconnect unless we know USB will wake 2321 * the system up quickly enough to respond ... 2322 */ 2323 } else if (is_host_active(musb)) { 2324 /* we know all the children are suspended; sometimes 2325 * they will even be wakeup-enabled. 2326 */ 2327 } 2328 2329 spin_unlock_irqrestore(&musb->lock, flags); 2330 return 0; 2331} 2332 2333static int musb_resume_noirq(struct device *dev) 2334{ 2335 /* for static cmos like DaVinci, register values were preserved 2336 * unless for some reason the whole soc powered down or the USB 2337 * module got reset through the PSC (vs just being disabled). 2338 */ 2339 return 0; 2340} 2341 2342static int musb_runtime_suspend(struct device *dev) 2343{ 2344 struct musb *musb = dev_to_musb(dev); 2345 2346 musb_save_context(musb); 2347 2348 return 0; 2349} 2350 2351static int musb_runtime_resume(struct device *dev) 2352{ 2353 struct musb *musb = dev_to_musb(dev); 2354 static int first = 1; 2355 2356 /* 2357 * When pm_runtime_get_sync called for the first time in driver 2358 * init, some of the structure is still not initialized which is 2359 * used in restore function. But clock needs to be 2360 * enabled before any register access, so 2361 * pm_runtime_get_sync has to be called. 2362 * Also context restore without save does not make 2363 * any sense 2364 */ 2365 if (!first) 2366 musb_restore_context(musb); 2367 first = 0; 2368 2369 return 0; 2370} 2371 2372static const struct dev_pm_ops musb_dev_pm_ops = { 2373 .suspend = musb_suspend, 2374 .resume_noirq = musb_resume_noirq, 2375 .runtime_suspend = musb_runtime_suspend, 2376 .runtime_resume = musb_runtime_resume, 2377}; 2378 2379#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2380#else 2381#define MUSB_DEV_PM_OPS NULL 2382#endif 2383 2384static struct platform_driver musb_driver = { 2385 .driver = { 2386 .name = (char *)musb_driver_name, 2387 .bus = &platform_bus_type, 2388 .owner = THIS_MODULE, 2389 .pm = MUSB_DEV_PM_OPS, 2390 }, 2391 .probe = musb_probe, 2392 .remove = __devexit_p(musb_remove), 2393 .shutdown = musb_shutdown, 2394}; 2395 2396/*-------------------------------------------------------------------------*/ 2397 2398static int __init musb_init(void) 2399{ 2400 if (usb_disabled()) 2401 return 0; 2402 2403 pr_info("%s: version " MUSB_VERSION ", " 2404 "?dma?" 2405 ", " 2406 "otg (peripheral+host)", 2407 musb_driver_name); 2408 return platform_driver_register(&musb_driver); 2409} 2410module_init(musb_init); 2411 2412static void __exit musb_cleanup(void) 2413{ 2414 platform_driver_unregister(&musb_driver); 2415} 2416module_exit(musb_cleanup); 2417