musb_core.c revision 2bb14cbf04ded4b9e394a6ba9e4f06b82fbac8b2
1/* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35/* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82/* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92#include <linux/module.h> 93#include <linux/kernel.h> 94#include <linux/sched.h> 95#include <linux/slab.h> 96#include <linux/init.h> 97#include <linux/list.h> 98#include <linux/kobject.h> 99#include <linux/platform_device.h> 100#include <linux/io.h> 101 102#ifdef CONFIG_ARM 103#include <mach/hardware.h> 104#include <mach/memory.h> 105#include <asm/mach-types.h> 106#endif 107 108#include "musb_core.h" 109 110 111#ifdef CONFIG_ARCH_DAVINCI 112#include "davinci.h" 113#endif 114 115#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 116 117 118unsigned musb_debug; 119module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR); 120MODULE_PARM_DESC(debug, "Debug message level. Default = 0"); 121 122#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 123#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 124 125#define MUSB_VERSION "6.0" 126 127#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 128 129#define MUSB_DRIVER_NAME "musb_hdrc" 130const char musb_driver_name[] = MUSB_DRIVER_NAME; 131 132MODULE_DESCRIPTION(DRIVER_INFO); 133MODULE_AUTHOR(DRIVER_AUTHOR); 134MODULE_LICENSE("GPL"); 135MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 136 137 138/*-------------------------------------------------------------------------*/ 139 140static inline struct musb *dev_to_musb(struct device *dev) 141{ 142#ifdef CONFIG_USB_MUSB_HDRC_HCD 143 /* usbcore insists dev->driver_data is a "struct hcd *" */ 144 return hcd_to_musb(dev_get_drvdata(dev)); 145#else 146 return dev_get_drvdata(dev); 147#endif 148} 149 150/*-------------------------------------------------------------------------*/ 151 152#ifndef CONFIG_BLACKFIN 153static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset) 154{ 155 void __iomem *addr = otg->io_priv; 156 int i = 0; 157 u8 r; 158 u8 power; 159 160 /* Make sure the transceiver is not in low power mode */ 161 power = musb_readb(addr, MUSB_POWER); 162 power &= ~MUSB_POWER_SUSPENDM; 163 musb_writeb(addr, MUSB_POWER, power); 164 165 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 166 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 167 */ 168 169 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 171 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 172 173 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 174 & MUSB_ULPI_REG_CMPLT)) { 175 i++; 176 if (i == 10000) { 177 DBG(3, "ULPI read timed out\n"); 178 return -ETIMEDOUT; 179 } 180 181 } 182 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 183 r &= ~MUSB_ULPI_REG_CMPLT; 184 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 185 186 return musb_readb(addr, MUSB_ULPI_REG_DATA); 187} 188 189static int musb_ulpi_write(struct otg_transceiver *otg, 190 u32 offset, u32 data) 191{ 192 void __iomem *addr = otg->io_priv; 193 int i = 0; 194 u8 r = 0; 195 u8 power; 196 197 /* Make sure the transceiver is not in low power mode */ 198 power = musb_readb(addr, MUSB_POWER); 199 power &= ~MUSB_POWER_SUSPENDM; 200 musb_writeb(addr, MUSB_POWER, power); 201 202 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 203 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 205 206 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 207 & MUSB_ULPI_REG_CMPLT)) { 208 i++; 209 if (i == 10000) { 210 DBG(3, "ULPI write timed out\n"); 211 return -ETIMEDOUT; 212 } 213 } 214 215 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 216 r &= ~MUSB_ULPI_REG_CMPLT; 217 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 218 219 return 0; 220} 221#else 222#define musb_ulpi_read(a, b) NULL 223#define musb_ulpi_write(a, b, c) NULL 224#endif 225 226static struct otg_io_access_ops musb_ulpi_access = { 227 .read = musb_ulpi_read, 228 .write = musb_ulpi_write, 229}; 230 231/*-------------------------------------------------------------------------*/ 232 233#if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN) 234 235/* 236 * Load an endpoint's FIFO 237 */ 238void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 239{ 240 void __iomem *fifo = hw_ep->fifo; 241 242 prefetch((u8 *)src); 243 244 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 245 'T', hw_ep->epnum, fifo, len, src); 246 247 /* we can't assume unaligned reads work */ 248 if (likely((0x01 & (unsigned long) src) == 0)) { 249 u16 index = 0; 250 251 /* best case is 32bit-aligned source address */ 252 if ((0x02 & (unsigned long) src) == 0) { 253 if (len >= 4) { 254 writesl(fifo, src + index, len >> 2); 255 index += len & ~0x03; 256 } 257 if (len & 0x02) { 258 musb_writew(fifo, 0, *(u16 *)&src[index]); 259 index += 2; 260 } 261 } else { 262 if (len >= 2) { 263 writesw(fifo, src + index, len >> 1); 264 index += len & ~0x01; 265 } 266 } 267 if (len & 0x01) 268 musb_writeb(fifo, 0, src[index]); 269 } else { 270 /* byte aligned */ 271 writesb(fifo, src, len); 272 } 273} 274 275/* 276 * Unload an endpoint's FIFO 277 */ 278void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 279{ 280 void __iomem *fifo = hw_ep->fifo; 281 282 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 283 'R', hw_ep->epnum, fifo, len, dst); 284 285 /* we can't assume unaligned writes work */ 286 if (likely((0x01 & (unsigned long) dst) == 0)) { 287 u16 index = 0; 288 289 /* best case is 32bit-aligned destination address */ 290 if ((0x02 & (unsigned long) dst) == 0) { 291 if (len >= 4) { 292 readsl(fifo, dst, len >> 2); 293 index = len & ~0x03; 294 } 295 if (len & 0x02) { 296 *(u16 *)&dst[index] = musb_readw(fifo, 0); 297 index += 2; 298 } 299 } else { 300 if (len >= 2) { 301 readsw(fifo, dst, len >> 1); 302 index = len & ~0x01; 303 } 304 } 305 if (len & 0x01) 306 dst[index] = musb_readb(fifo, 0); 307 } else { 308 /* byte aligned */ 309 readsb(fifo, dst, len); 310 } 311} 312 313#endif /* normal PIO */ 314 315 316/*-------------------------------------------------------------------------*/ 317 318/* for high speed test mode; see USB 2.0 spec 7.1.20 */ 319static const u8 musb_test_packet[53] = { 320 /* implicit SYNC then DATA0 to start */ 321 322 /* JKJKJKJK x9 */ 323 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 324 /* JJKKJJKK x8 */ 325 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 326 /* JJJJKKKK x8 */ 327 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 328 /* JJJJJJJKKKKKKK x8 */ 329 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 330 /* JJJJJJJK x8 */ 331 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 332 /* JKKKKKKK x10, JK */ 333 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 334 335 /* implicit CRC16 then EOP to end */ 336}; 337 338void musb_load_testpacket(struct musb *musb) 339{ 340 void __iomem *regs = musb->endpoints[0].regs; 341 342 musb_ep_select(musb->mregs, 0); 343 musb_write_fifo(musb->control_ep, 344 sizeof(musb_test_packet), musb_test_packet); 345 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 346} 347 348/*-------------------------------------------------------------------------*/ 349 350const char *otg_state_string(struct musb *musb) 351{ 352 switch (musb->xceiv->state) { 353 case OTG_STATE_A_IDLE: return "a_idle"; 354 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; 355 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; 356 case OTG_STATE_A_HOST: return "a_host"; 357 case OTG_STATE_A_SUSPEND: return "a_suspend"; 358 case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; 359 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; 360 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; 361 case OTG_STATE_B_IDLE: return "b_idle"; 362 case OTG_STATE_B_SRP_INIT: return "b_srp_init"; 363 case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; 364 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; 365 case OTG_STATE_B_HOST: return "b_host"; 366 default: return "UNDEFINED"; 367 } 368} 369 370#ifdef CONFIG_USB_MUSB_OTG 371 372/* 373 * Handles OTG hnp timeouts, such as b_ase0_brst 374 */ 375void musb_otg_timer_func(unsigned long data) 376{ 377 struct musb *musb = (struct musb *)data; 378 unsigned long flags; 379 380 spin_lock_irqsave(&musb->lock, flags); 381 switch (musb->xceiv->state) { 382 case OTG_STATE_B_WAIT_ACON: 383 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 384 musb_g_disconnect(musb); 385 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 386 musb->is_active = 0; 387 break; 388 case OTG_STATE_A_SUSPEND: 389 case OTG_STATE_A_WAIT_BCON: 390 DBG(1, "HNP: %s timeout\n", otg_state_string(musb)); 391 musb_set_vbus(musb, 0); 392 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 393 break; 394 default: 395 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb)); 396 } 397 musb->ignore_disconnect = 0; 398 spin_unlock_irqrestore(&musb->lock, flags); 399} 400 401/* 402 * Stops the HNP transition. Caller must take care of locking. 403 */ 404void musb_hnp_stop(struct musb *musb) 405{ 406 struct usb_hcd *hcd = musb_to_hcd(musb); 407 void __iomem *mbase = musb->mregs; 408 u8 reg; 409 410 DBG(1, "HNP: stop from %s\n", otg_state_string(musb)); 411 412 switch (musb->xceiv->state) { 413 case OTG_STATE_A_PERIPHERAL: 414 musb_g_disconnect(musb); 415 DBG(1, "HNP: back to %s\n", otg_state_string(musb)); 416 break; 417 case OTG_STATE_B_HOST: 418 DBG(1, "HNP: Disabling HR\n"); 419 hcd->self.is_b_host = 0; 420 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 421 MUSB_DEV_MODE(musb); 422 reg = musb_readb(mbase, MUSB_POWER); 423 reg |= MUSB_POWER_SUSPENDM; 424 musb_writeb(mbase, MUSB_POWER, reg); 425 /* REVISIT: Start SESSION_REQUEST here? */ 426 break; 427 default: 428 DBG(1, "HNP: Stopping in unknown state %s\n", 429 otg_state_string(musb)); 430 } 431 432 /* 433 * When returning to A state after HNP, avoid hub_port_rebounce(), 434 * which cause occasional OPT A "Did not receive reset after connect" 435 * errors. 436 */ 437 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 438} 439 440#endif 441 442/* 443 * Interrupt Service Routine to record USB "global" interrupts. 444 * Since these do not happen often and signify things of 445 * paramount importance, it seems OK to check them individually; 446 * the order of the tests is specified in the manual 447 * 448 * @param musb instance pointer 449 * @param int_usb register contents 450 * @param devctl 451 * @param power 452 */ 453 454#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \ 455 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \ 456 | MUSB_INTR_RESET) 457 458static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 459 u8 devctl, u8 power) 460{ 461 irqreturn_t handled = IRQ_NONE; 462 463 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 464 int_usb); 465 466 /* in host mode, the peripheral may issue remote wakeup. 467 * in peripheral mode, the host may resume the link. 468 * spurious RESUME irqs happen too, paired with SUSPEND. 469 */ 470 if (int_usb & MUSB_INTR_RESUME) { 471 handled = IRQ_HANDLED; 472 DBG(3, "RESUME (%s)\n", otg_state_string(musb)); 473 474 if (devctl & MUSB_DEVCTL_HM) { 475#ifdef CONFIG_USB_MUSB_HDRC_HCD 476 void __iomem *mbase = musb->mregs; 477 478 switch (musb->xceiv->state) { 479 case OTG_STATE_A_SUSPEND: 480 /* remote wakeup? later, GetPortStatus 481 * will stop RESUME signaling 482 */ 483 484 if (power & MUSB_POWER_SUSPENDM) { 485 /* spurious */ 486 musb->int_usb &= ~MUSB_INTR_SUSPEND; 487 DBG(2, "Spurious SUSPENDM\n"); 488 break; 489 } 490 491 power &= ~MUSB_POWER_SUSPENDM; 492 musb_writeb(mbase, MUSB_POWER, 493 power | MUSB_POWER_RESUME); 494 495 musb->port1_status |= 496 (USB_PORT_STAT_C_SUSPEND << 16) 497 | MUSB_PORT_STAT_RESUME; 498 musb->rh_timer = jiffies 499 + msecs_to_jiffies(20); 500 501 musb->xceiv->state = OTG_STATE_A_HOST; 502 musb->is_active = 1; 503 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 504 break; 505 case OTG_STATE_B_WAIT_ACON: 506 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 507 musb->is_active = 1; 508 MUSB_DEV_MODE(musb); 509 break; 510 default: 511 WARNING("bogus %s RESUME (%s)\n", 512 "host", 513 otg_state_string(musb)); 514 } 515#endif 516 } else { 517 switch (musb->xceiv->state) { 518#ifdef CONFIG_USB_MUSB_HDRC_HCD 519 case OTG_STATE_A_SUSPEND: 520 /* possibly DISCONNECT is upcoming */ 521 musb->xceiv->state = OTG_STATE_A_HOST; 522 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 523 break; 524#endif 525#ifdef CONFIG_USB_GADGET_MUSB_HDRC 526 case OTG_STATE_B_WAIT_ACON: 527 case OTG_STATE_B_PERIPHERAL: 528 /* disconnect while suspended? we may 529 * not get a disconnect irq... 530 */ 531 if ((devctl & MUSB_DEVCTL_VBUS) 532 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 533 ) { 534 musb->int_usb |= MUSB_INTR_DISCONNECT; 535 musb->int_usb &= ~MUSB_INTR_SUSPEND; 536 break; 537 } 538 musb_g_resume(musb); 539 break; 540 case OTG_STATE_B_IDLE: 541 musb->int_usb &= ~MUSB_INTR_SUSPEND; 542 break; 543#endif 544 default: 545 WARNING("bogus %s RESUME (%s)\n", 546 "peripheral", 547 otg_state_string(musb)); 548 } 549 } 550 } 551 552#ifdef CONFIG_USB_MUSB_HDRC_HCD 553 /* see manual for the order of the tests */ 554 if (int_usb & MUSB_INTR_SESSREQ) { 555 void __iomem *mbase = musb->mregs; 556 557 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); 558 559 /* IRQ arrives from ID pin sense or (later, if VBUS power 560 * is removed) SRP. responses are time critical: 561 * - turn on VBUS (with silicon-specific mechanism) 562 * - go through A_WAIT_VRISE 563 * - ... to A_WAIT_BCON. 564 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 565 */ 566 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 567 musb->ep0_stage = MUSB_EP0_START; 568 musb->xceiv->state = OTG_STATE_A_IDLE; 569 MUSB_HST_MODE(musb); 570 musb_set_vbus(musb, 1); 571 572 handled = IRQ_HANDLED; 573 } 574 575 if (int_usb & MUSB_INTR_VBUSERROR) { 576 int ignore = 0; 577 578 /* During connection as an A-Device, we may see a short 579 * current spikes causing voltage drop, because of cable 580 * and peripheral capacitance combined with vbus draw. 581 * (So: less common with truly self-powered devices, where 582 * vbus doesn't act like a power supply.) 583 * 584 * Such spikes are short; usually less than ~500 usec, max 585 * of ~2 msec. That is, they're not sustained overcurrent 586 * errors, though they're reported using VBUSERROR irqs. 587 * 588 * Workarounds: (a) hardware: use self powered devices. 589 * (b) software: ignore non-repeated VBUS errors. 590 * 591 * REVISIT: do delays from lots of DEBUG_KERNEL checks 592 * make trouble here, keeping VBUS < 4.4V ? 593 */ 594 switch (musb->xceiv->state) { 595 case OTG_STATE_A_HOST: 596 /* recovery is dicey once we've gotten past the 597 * initial stages of enumeration, but if VBUS 598 * stayed ok at the other end of the link, and 599 * another reset is due (at least for high speed, 600 * to redo the chirp etc), it might work OK... 601 */ 602 case OTG_STATE_A_WAIT_BCON: 603 case OTG_STATE_A_WAIT_VRISE: 604 if (musb->vbuserr_retry) { 605 void __iomem *mbase = musb->mregs; 606 607 musb->vbuserr_retry--; 608 ignore = 1; 609 devctl |= MUSB_DEVCTL_SESSION; 610 musb_writeb(mbase, MUSB_DEVCTL, devctl); 611 } else { 612 musb->port1_status |= 613 USB_PORT_STAT_OVERCURRENT 614 | (USB_PORT_STAT_C_OVERCURRENT << 16); 615 } 616 break; 617 default: 618 break; 619 } 620 621 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 622 otg_state_string(musb), 623 devctl, 624 ({ char *s; 625 switch (devctl & MUSB_DEVCTL_VBUS) { 626 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 627 s = "<SessEnd"; break; 628 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 629 s = "<AValid"; break; 630 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 631 s = "<VBusValid"; break; 632 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 633 default: 634 s = "VALID"; break; 635 }; s; }), 636 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 637 musb->port1_status); 638 639 /* go through A_WAIT_VFALL then start a new session */ 640 if (!ignore) 641 musb_set_vbus(musb, 0); 642 handled = IRQ_HANDLED; 643 } 644 645#endif 646 if (int_usb & MUSB_INTR_SUSPEND) { 647 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", 648 otg_state_string(musb), devctl, power); 649 handled = IRQ_HANDLED; 650 651 switch (musb->xceiv->state) { 652#ifdef CONFIG_USB_MUSB_OTG 653 case OTG_STATE_A_PERIPHERAL: 654 /* We also come here if the cable is removed, since 655 * this silicon doesn't report ID-no-longer-grounded. 656 * 657 * We depend on T(a_wait_bcon) to shut us down, and 658 * hope users don't do anything dicey during this 659 * undesired detour through A_WAIT_BCON. 660 */ 661 musb_hnp_stop(musb); 662 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 663 musb_root_disconnect(musb); 664 musb_platform_try_idle(musb, jiffies 665 + msecs_to_jiffies(musb->a_wait_bcon 666 ? : OTG_TIME_A_WAIT_BCON)); 667 668 break; 669#endif 670 case OTG_STATE_B_IDLE: 671 if (!musb->is_active) 672 break; 673 case OTG_STATE_B_PERIPHERAL: 674 musb_g_suspend(musb); 675 musb->is_active = is_otg_enabled(musb) 676 && musb->xceiv->gadget->b_hnp_enable; 677 if (musb->is_active) { 678#ifdef CONFIG_USB_MUSB_OTG 679 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 680 DBG(1, "HNP: Setting timer for b_ase0_brst\n"); 681 mod_timer(&musb->otg_timer, jiffies 682 + msecs_to_jiffies( 683 OTG_TIME_B_ASE0_BRST)); 684#endif 685 } 686 break; 687 case OTG_STATE_A_WAIT_BCON: 688 if (musb->a_wait_bcon != 0) 689 musb_platform_try_idle(musb, jiffies 690 + msecs_to_jiffies(musb->a_wait_bcon)); 691 break; 692 case OTG_STATE_A_HOST: 693 musb->xceiv->state = OTG_STATE_A_SUSPEND; 694 musb->is_active = is_otg_enabled(musb) 695 && musb->xceiv->host->b_hnp_enable; 696 break; 697 case OTG_STATE_B_HOST: 698 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 699 DBG(1, "REVISIT: SUSPEND as B_HOST\n"); 700 break; 701 default: 702 /* "should not happen" */ 703 musb->is_active = 0; 704 break; 705 } 706 } 707 708#ifdef CONFIG_USB_MUSB_HDRC_HCD 709 if (int_usb & MUSB_INTR_CONNECT) { 710 struct usb_hcd *hcd = musb_to_hcd(musb); 711 void __iomem *mbase = musb->mregs; 712 713 handled = IRQ_HANDLED; 714 musb->is_active = 1; 715 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); 716 717 musb->ep0_stage = MUSB_EP0_START; 718 719#ifdef CONFIG_USB_MUSB_OTG 720 /* flush endpoints when transitioning from Device Mode */ 721 if (is_peripheral_active(musb)) { 722 /* REVISIT HNP; just force disconnect */ 723 } 724 musb_writew(mbase, MUSB_INTRTXE, musb->epmask); 725 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe); 726 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7); 727#endif 728 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 729 |USB_PORT_STAT_HIGH_SPEED 730 |USB_PORT_STAT_ENABLE 731 ); 732 musb->port1_status |= USB_PORT_STAT_CONNECTION 733 |(USB_PORT_STAT_C_CONNECTION << 16); 734 735 /* high vs full speed is just a guess until after reset */ 736 if (devctl & MUSB_DEVCTL_LSDEV) 737 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 738 739 /* indicate new connection to OTG machine */ 740 switch (musb->xceiv->state) { 741 case OTG_STATE_B_PERIPHERAL: 742 if (int_usb & MUSB_INTR_SUSPEND) { 743 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); 744 int_usb &= ~MUSB_INTR_SUSPEND; 745 goto b_host; 746 } else 747 DBG(1, "CONNECT as b_peripheral???\n"); 748 break; 749 case OTG_STATE_B_WAIT_ACON: 750 DBG(1, "HNP: CONNECT, now b_host\n"); 751b_host: 752 musb->xceiv->state = OTG_STATE_B_HOST; 753 hcd->self.is_b_host = 1; 754 musb->ignore_disconnect = 0; 755 del_timer(&musb->otg_timer); 756 break; 757 default: 758 if ((devctl & MUSB_DEVCTL_VBUS) 759 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 760 musb->xceiv->state = OTG_STATE_A_HOST; 761 hcd->self.is_b_host = 0; 762 } 763 break; 764 } 765 766 /* poke the root hub */ 767 MUSB_HST_MODE(musb); 768 if (hcd->status_urb) 769 usb_hcd_poll_rh_status(hcd); 770 else 771 usb_hcd_resume_root_hub(hcd); 772 773 DBG(1, "CONNECT (%s) devctl %02x\n", 774 otg_state_string(musb), devctl); 775 } 776#endif /* CONFIG_USB_MUSB_HDRC_HCD */ 777 778 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 779 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n", 780 otg_state_string(musb), 781 MUSB_MODE(musb), devctl); 782 handled = IRQ_HANDLED; 783 784 switch (musb->xceiv->state) { 785#ifdef CONFIG_USB_MUSB_HDRC_HCD 786 case OTG_STATE_A_HOST: 787 case OTG_STATE_A_SUSPEND: 788 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 789 musb_root_disconnect(musb); 790 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 791 musb_platform_try_idle(musb, jiffies 792 + msecs_to_jiffies(musb->a_wait_bcon)); 793 break; 794#endif /* HOST */ 795#ifdef CONFIG_USB_MUSB_OTG 796 case OTG_STATE_B_HOST: 797 /* REVISIT this behaves for "real disconnect" 798 * cases; make sure the other transitions from 799 * from B_HOST act right too. The B_HOST code 800 * in hnp_stop() is currently not used... 801 */ 802 musb_root_disconnect(musb); 803 musb_to_hcd(musb)->self.is_b_host = 0; 804 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 805 MUSB_DEV_MODE(musb); 806 musb_g_disconnect(musb); 807 break; 808 case OTG_STATE_A_PERIPHERAL: 809 musb_hnp_stop(musb); 810 musb_root_disconnect(musb); 811 /* FALLTHROUGH */ 812 case OTG_STATE_B_WAIT_ACON: 813 /* FALLTHROUGH */ 814#endif /* OTG */ 815#ifdef CONFIG_USB_GADGET_MUSB_HDRC 816 case OTG_STATE_B_PERIPHERAL: 817 case OTG_STATE_B_IDLE: 818 musb_g_disconnect(musb); 819 break; 820#endif /* GADGET */ 821 default: 822 WARNING("unhandled DISCONNECT transition (%s)\n", 823 otg_state_string(musb)); 824 break; 825 } 826 } 827 828 /* mentor saves a bit: bus reset and babble share the same irq. 829 * only host sees babble; only peripheral sees bus reset. 830 */ 831 if (int_usb & MUSB_INTR_RESET) { 832 handled = IRQ_HANDLED; 833 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 834 /* 835 * Looks like non-HS BABBLE can be ignored, but 836 * HS BABBLE is an error condition. For HS the solution 837 * is to avoid babble in the first place and fix what 838 * caused BABBLE. When HS BABBLE happens we can only 839 * stop the session. 840 */ 841 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 842 DBG(1, "BABBLE devctl: %02x\n", devctl); 843 else { 844 ERR("Stopping host session -- babble\n"); 845 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 846 } 847 } else if (is_peripheral_capable()) { 848 DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); 849 switch (musb->xceiv->state) { 850#ifdef CONFIG_USB_OTG 851 case OTG_STATE_A_SUSPEND: 852 /* We need to ignore disconnect on suspend 853 * otherwise tusb 2.0 won't reconnect after a 854 * power cycle, which breaks otg compliance. 855 */ 856 musb->ignore_disconnect = 1; 857 musb_g_reset(musb); 858 /* FALLTHROUGH */ 859 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 860 /* never use invalid T(a_wait_bcon) */ 861 DBG(1, "HNP: in %s, %d msec timeout\n", 862 otg_state_string(musb), 863 TA_WAIT_BCON(musb)); 864 mod_timer(&musb->otg_timer, jiffies 865 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 866 break; 867 case OTG_STATE_A_PERIPHERAL: 868 musb->ignore_disconnect = 0; 869 del_timer(&musb->otg_timer); 870 musb_g_reset(musb); 871 break; 872 case OTG_STATE_B_WAIT_ACON: 873 DBG(1, "HNP: RESET (%s), to b_peripheral\n", 874 otg_state_string(musb)); 875 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 876 musb_g_reset(musb); 877 break; 878#endif 879 case OTG_STATE_B_IDLE: 880 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 881 /* FALLTHROUGH */ 882 case OTG_STATE_B_PERIPHERAL: 883 musb_g_reset(musb); 884 break; 885 default: 886 DBG(1, "Unhandled BUS RESET as %s\n", 887 otg_state_string(musb)); 888 } 889 } 890 } 891 892#if 0 893/* REVISIT ... this would be for multiplexing periodic endpoints, or 894 * supporting transfer phasing to prevent exceeding ISO bandwidth 895 * limits of a given frame or microframe. 896 * 897 * It's not needed for peripheral side, which dedicates endpoints; 898 * though it _might_ use SOF irqs for other purposes. 899 * 900 * And it's not currently needed for host side, which also dedicates 901 * endpoints, relies on TX/RX interval registers, and isn't claimed 902 * to support ISO transfers yet. 903 */ 904 if (int_usb & MUSB_INTR_SOF) { 905 void __iomem *mbase = musb->mregs; 906 struct musb_hw_ep *ep; 907 u8 epnum; 908 u16 frame; 909 910 DBG(6, "START_OF_FRAME\n"); 911 handled = IRQ_HANDLED; 912 913 /* start any periodic Tx transfers waiting for current frame */ 914 frame = musb_readw(mbase, MUSB_FRAME); 915 ep = musb->endpoints; 916 for (epnum = 1; (epnum < musb->nr_endpoints) 917 && (musb->epmask >= (1 << epnum)); 918 epnum++, ep++) { 919 /* 920 * FIXME handle framecounter wraps (12 bits) 921 * eliminate duplicated StartUrb logic 922 */ 923 if (ep->dwWaitFrame >= frame) { 924 ep->dwWaitFrame = 0; 925 pr_debug("SOF --> periodic TX%s on %d\n", 926 ep->tx_channel ? " DMA" : "", 927 epnum); 928 if (!ep->tx_channel) 929 musb_h_tx_start(musb, epnum); 930 else 931 cppi_hostdma_start(musb, epnum); 932 } 933 } /* end of for loop */ 934 } 935#endif 936 937 schedule_work(&musb->irq_work); 938 939 return handled; 940} 941 942/*-------------------------------------------------------------------------*/ 943 944/* 945* Program the HDRC to start (enable interrupts, dma, etc.). 946*/ 947void musb_start(struct musb *musb) 948{ 949 void __iomem *regs = musb->mregs; 950 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 951 952 DBG(2, "<== devctl %02x\n", devctl); 953 954 /* Set INT enable registers, enable interrupts */ 955 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 956 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 957 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 958 959 musb_writeb(regs, MUSB_TESTMODE, 0); 960 961 /* put into basic highspeed mode and start session */ 962 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 963 | MUSB_POWER_SOFTCONN 964 | MUSB_POWER_HSENAB 965 /* ENSUSPEND wedges tusb */ 966 /* | MUSB_POWER_ENSUSPEND */ 967 ); 968 969 musb->is_active = 0; 970 devctl = musb_readb(regs, MUSB_DEVCTL); 971 devctl &= ~MUSB_DEVCTL_SESSION; 972 973 if (is_otg_enabled(musb)) { 974 /* session started after: 975 * (a) ID-grounded irq, host mode; 976 * (b) vbus present/connect IRQ, peripheral mode; 977 * (c) peripheral initiates, using SRP 978 */ 979 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 980 musb->is_active = 1; 981 else 982 devctl |= MUSB_DEVCTL_SESSION; 983 984 } else if (is_host_enabled(musb)) { 985 /* assume ID pin is hard-wired to ground */ 986 devctl |= MUSB_DEVCTL_SESSION; 987 988 } else /* peripheral is enabled */ { 989 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 990 musb->is_active = 1; 991 } 992 musb_platform_enable(musb); 993 musb_writeb(regs, MUSB_DEVCTL, devctl); 994} 995 996 997static void musb_generic_disable(struct musb *musb) 998{ 999 void __iomem *mbase = musb->mregs; 1000 u16 temp; 1001 1002 /* disable interrupts */ 1003 musb_writeb(mbase, MUSB_INTRUSBE, 0); 1004 musb_writew(mbase, MUSB_INTRTXE, 0); 1005 musb_writew(mbase, MUSB_INTRRXE, 0); 1006 1007 /* off */ 1008 musb_writeb(mbase, MUSB_DEVCTL, 0); 1009 1010 /* flush pending interrupts */ 1011 temp = musb_readb(mbase, MUSB_INTRUSB); 1012 temp = musb_readw(mbase, MUSB_INTRTX); 1013 temp = musb_readw(mbase, MUSB_INTRRX); 1014 1015} 1016 1017/* 1018 * Make the HDRC stop (disable interrupts, etc.); 1019 * reversible by musb_start 1020 * called on gadget driver unregister 1021 * with controller locked, irqs blocked 1022 * acts as a NOP unless some role activated the hardware 1023 */ 1024void musb_stop(struct musb *musb) 1025{ 1026 /* stop IRQs, timers, ... */ 1027 musb_platform_disable(musb); 1028 musb_generic_disable(musb); 1029 DBG(3, "HDRC disabled\n"); 1030 1031 /* FIXME 1032 * - mark host and/or peripheral drivers unusable/inactive 1033 * - disable DMA (and enable it in HdrcStart) 1034 * - make sure we can musb_start() after musb_stop(); with 1035 * OTG mode, gadget driver module rmmod/modprobe cycles that 1036 * - ... 1037 */ 1038 musb_platform_try_idle(musb, 0); 1039} 1040 1041static void musb_shutdown(struct platform_device *pdev) 1042{ 1043 struct musb *musb = dev_to_musb(&pdev->dev); 1044 unsigned long flags; 1045 1046 spin_lock_irqsave(&musb->lock, flags); 1047 musb_platform_disable(musb); 1048 musb_generic_disable(musb); 1049 if (musb->clock) 1050 clk_put(musb->clock); 1051 spin_unlock_irqrestore(&musb->lock, flags); 1052 1053 /* FIXME power down */ 1054} 1055 1056 1057/*-------------------------------------------------------------------------*/ 1058 1059/* 1060 * The silicon either has hard-wired endpoint configurations, or else 1061 * "dynamic fifo" sizing. The driver has support for both, though at this 1062 * writing only the dynamic sizing is very well tested. Since we switched 1063 * away from compile-time hardware parameters, we can no longer rely on 1064 * dead code elimination to leave only the relevant one in the object file. 1065 * 1066 * We don't currently use dynamic fifo setup capability to do anything 1067 * more than selecting one of a bunch of predefined configurations. 1068 */ 1069#if defined(CONFIG_USB_TUSB6010) || \ 1070 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ 1071 || defined(CONFIG_ARCH_OMAP4) 1072static ushort __initdata fifo_mode = 4; 1073#else 1074static ushort __initdata fifo_mode = 2; 1075#endif 1076 1077/* "modprobe ... fifo_mode=1" etc */ 1078module_param(fifo_mode, ushort, 0); 1079MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1080 1081/* 1082 * tables defining fifo_mode values. define more if you like. 1083 * for host side, make sure both halves of ep1 are set up. 1084 */ 1085 1086/* mode 0 - fits in 2KB */ 1087static struct musb_fifo_cfg __initdata mode_0_cfg[] = { 1088{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1089{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1090{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1091{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1092{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1093}; 1094 1095/* mode 1 - fits in 4KB */ 1096static struct musb_fifo_cfg __initdata mode_1_cfg[] = { 1097{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1098{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1099{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1100{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1101{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1102}; 1103 1104/* mode 2 - fits in 4KB */ 1105static struct musb_fifo_cfg __initdata mode_2_cfg[] = { 1106{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1107{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1108{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1109{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1110{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1111{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1112}; 1113 1114/* mode 3 - fits in 4KB */ 1115static struct musb_fifo_cfg __initdata mode_3_cfg[] = { 1116{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1117{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1118{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1119{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1120{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1121{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1122}; 1123 1124/* mode 4 - fits in 16KB */ 1125static struct musb_fifo_cfg __initdata mode_4_cfg[] = { 1126{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1127{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1128{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1129{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1130{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1131{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1132{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1133{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1134{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1135{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1136{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1137{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1138{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1139{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1140{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1141{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1142{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1143{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1144{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1145{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1146{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1147{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1148{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1149{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1150{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1151{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1152{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1153}; 1154 1155/* mode 5 - fits in 8KB */ 1156static struct musb_fifo_cfg __initdata mode_5_cfg[] = { 1157{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1158{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1159{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1160{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1161{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1162{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1163{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1164{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1165{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1166{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1167{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1168{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1169{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1170{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1171{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1172{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1173{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1174{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1175{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1176{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1177{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1178{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1179{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1180{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1181{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1182{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1183{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1184}; 1185 1186/* 1187 * configure a fifo; for non-shared endpoints, this may be called 1188 * once for a tx fifo and once for an rx fifo. 1189 * 1190 * returns negative errno or offset for next fifo. 1191 */ 1192static int __init 1193fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1194 const struct musb_fifo_cfg *cfg, u16 offset) 1195{ 1196 void __iomem *mbase = musb->mregs; 1197 int size = 0; 1198 u16 maxpacket = cfg->maxpacket; 1199 u16 c_off = offset >> 3; 1200 u8 c_size; 1201 1202 /* expect hw_ep has already been zero-initialized */ 1203 1204 size = ffs(max(maxpacket, (u16) 8)) - 1; 1205 maxpacket = 1 << size; 1206 1207 c_size = size - 3; 1208 if (cfg->mode == BUF_DOUBLE) { 1209 if ((offset + (maxpacket << 1)) > 1210 (1 << (musb->config->ram_bits + 2))) 1211 return -EMSGSIZE; 1212 c_size |= MUSB_FIFOSZ_DPB; 1213 } else { 1214 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1215 return -EMSGSIZE; 1216 } 1217 1218 /* configure the FIFO */ 1219 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1220 1221#ifdef CONFIG_USB_MUSB_HDRC_HCD 1222 /* EP0 reserved endpoint for control, bidirectional; 1223 * EP1 reserved for bulk, two unidirection halves. 1224 */ 1225 if (hw_ep->epnum == 1) 1226 musb->bulk_ep = hw_ep; 1227 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1228#endif 1229 switch (cfg->style) { 1230 case FIFO_TX: 1231 musb_write_txfifosz(mbase, c_size); 1232 musb_write_txfifoadd(mbase, c_off); 1233 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1234 hw_ep->max_packet_sz_tx = maxpacket; 1235 break; 1236 case FIFO_RX: 1237 musb_write_rxfifosz(mbase, c_size); 1238 musb_write_rxfifoadd(mbase, c_off); 1239 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1240 hw_ep->max_packet_sz_rx = maxpacket; 1241 break; 1242 case FIFO_RXTX: 1243 musb_write_txfifosz(mbase, c_size); 1244 musb_write_txfifoadd(mbase, c_off); 1245 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1246 hw_ep->max_packet_sz_rx = maxpacket; 1247 1248 musb_write_rxfifosz(mbase, c_size); 1249 musb_write_rxfifoadd(mbase, c_off); 1250 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1251 hw_ep->max_packet_sz_tx = maxpacket; 1252 1253 hw_ep->is_shared_fifo = true; 1254 break; 1255 } 1256 1257 /* NOTE rx and tx endpoint irqs aren't managed separately, 1258 * which happens to be ok 1259 */ 1260 musb->epmask |= (1 << hw_ep->epnum); 1261 1262 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1263} 1264 1265static struct musb_fifo_cfg __initdata ep0_cfg = { 1266 .style = FIFO_RXTX, .maxpacket = 64, 1267}; 1268 1269static int __init ep_config_from_table(struct musb *musb) 1270{ 1271 const struct musb_fifo_cfg *cfg; 1272 unsigned i, n; 1273 int offset; 1274 struct musb_hw_ep *hw_ep = musb->endpoints; 1275 1276 if (musb->config->fifo_cfg) { 1277 cfg = musb->config->fifo_cfg; 1278 n = musb->config->fifo_cfg_size; 1279 goto done; 1280 } 1281 1282 switch (fifo_mode) { 1283 default: 1284 fifo_mode = 0; 1285 /* FALLTHROUGH */ 1286 case 0: 1287 cfg = mode_0_cfg; 1288 n = ARRAY_SIZE(mode_0_cfg); 1289 break; 1290 case 1: 1291 cfg = mode_1_cfg; 1292 n = ARRAY_SIZE(mode_1_cfg); 1293 break; 1294 case 2: 1295 cfg = mode_2_cfg; 1296 n = ARRAY_SIZE(mode_2_cfg); 1297 break; 1298 case 3: 1299 cfg = mode_3_cfg; 1300 n = ARRAY_SIZE(mode_3_cfg); 1301 break; 1302 case 4: 1303 cfg = mode_4_cfg; 1304 n = ARRAY_SIZE(mode_4_cfg); 1305 break; 1306 case 5: 1307 cfg = mode_5_cfg; 1308 n = ARRAY_SIZE(mode_5_cfg); 1309 break; 1310 } 1311 1312 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1313 musb_driver_name, fifo_mode); 1314 1315 1316done: 1317 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1318 /* assert(offset > 0) */ 1319 1320 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1321 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1322 */ 1323 1324 for (i = 0; i < n; i++) { 1325 u8 epn = cfg->hw_ep_num; 1326 1327 if (epn >= musb->config->num_eps) { 1328 pr_debug("%s: invalid ep %d\n", 1329 musb_driver_name, epn); 1330 return -EINVAL; 1331 } 1332 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1333 if (offset < 0) { 1334 pr_debug("%s: mem overrun, ep %d\n", 1335 musb_driver_name, epn); 1336 return -EINVAL; 1337 } 1338 epn++; 1339 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1340 } 1341 1342 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1343 musb_driver_name, 1344 n + 1, musb->config->num_eps * 2 - 1, 1345 offset, (1 << (musb->config->ram_bits + 2))); 1346 1347#ifdef CONFIG_USB_MUSB_HDRC_HCD 1348 if (!musb->bulk_ep) { 1349 pr_debug("%s: missing bulk\n", musb_driver_name); 1350 return -EINVAL; 1351 } 1352#endif 1353 1354 return 0; 1355} 1356 1357 1358/* 1359 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1360 * @param musb the controller 1361 */ 1362static int __init ep_config_from_hw(struct musb *musb) 1363{ 1364 u8 epnum = 0; 1365 struct musb_hw_ep *hw_ep; 1366 void *mbase = musb->mregs; 1367 int ret = 0; 1368 1369 DBG(2, "<== static silicon ep config\n"); 1370 1371 /* FIXME pick up ep0 maxpacket size */ 1372 1373 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1374 musb_ep_select(mbase, epnum); 1375 hw_ep = musb->endpoints + epnum; 1376 1377 ret = musb_read_fifosize(musb, hw_ep, epnum); 1378 if (ret < 0) 1379 break; 1380 1381 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1382 1383#ifdef CONFIG_USB_MUSB_HDRC_HCD 1384 /* pick an RX/TX endpoint for bulk */ 1385 if (hw_ep->max_packet_sz_tx < 512 1386 || hw_ep->max_packet_sz_rx < 512) 1387 continue; 1388 1389 /* REVISIT: this algorithm is lazy, we should at least 1390 * try to pick a double buffered endpoint. 1391 */ 1392 if (musb->bulk_ep) 1393 continue; 1394 musb->bulk_ep = hw_ep; 1395#endif 1396 } 1397 1398#ifdef CONFIG_USB_MUSB_HDRC_HCD 1399 if (!musb->bulk_ep) { 1400 pr_debug("%s: missing bulk\n", musb_driver_name); 1401 return -EINVAL; 1402 } 1403#endif 1404 1405 return 0; 1406} 1407 1408enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1409 1410/* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1411 * configure endpoints, or take their config from silicon 1412 */ 1413static int __init musb_core_init(u16 musb_type, struct musb *musb) 1414{ 1415 u8 reg; 1416 char *type; 1417 char aInfo[90], aRevision[32], aDate[12]; 1418 void __iomem *mbase = musb->mregs; 1419 int status = 0; 1420 int i; 1421 1422 /* log core options (read using indexed model) */ 1423 reg = musb_read_configdata(mbase); 1424 1425 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1426 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1427 strcat(aInfo, ", dyn FIFOs"); 1428 musb->dyn_fifo = true; 1429 } 1430 if (reg & MUSB_CONFIGDATA_MPRXE) { 1431 strcat(aInfo, ", bulk combine"); 1432 musb->bulk_combine = true; 1433 } 1434 if (reg & MUSB_CONFIGDATA_MPTXE) { 1435 strcat(aInfo, ", bulk split"); 1436 musb->bulk_split = true; 1437 } 1438 if (reg & MUSB_CONFIGDATA_HBRXE) { 1439 strcat(aInfo, ", HB-ISO Rx"); 1440 musb->hb_iso_rx = true; 1441 } 1442 if (reg & MUSB_CONFIGDATA_HBTXE) { 1443 strcat(aInfo, ", HB-ISO Tx"); 1444 musb->hb_iso_tx = true; 1445 } 1446 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1447 strcat(aInfo, ", SoftConn"); 1448 1449 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1450 musb_driver_name, reg, aInfo); 1451 1452 aDate[0] = 0; 1453 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1454 musb->is_multipoint = 1; 1455 type = "M"; 1456 } else { 1457 musb->is_multipoint = 0; 1458 type = ""; 1459#ifdef CONFIG_USB_MUSB_HDRC_HCD 1460#ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1461 printk(KERN_ERR 1462 "%s: kernel must blacklist external hubs\n", 1463 musb_driver_name); 1464#endif 1465#endif 1466 } 1467 1468 /* log release info */ 1469 musb->hwvers = musb_read_hwvers(mbase); 1470 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1471 MUSB_HWVERS_MINOR(musb->hwvers), 1472 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1473 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1474 musb_driver_name, type, aRevision, aDate); 1475 1476 /* configure ep0 */ 1477 musb_configure_ep0(musb); 1478 1479 /* discover endpoint configuration */ 1480 musb->nr_endpoints = 1; 1481 musb->epmask = 1; 1482 1483 if (musb->dyn_fifo) 1484 status = ep_config_from_table(musb); 1485 else 1486 status = ep_config_from_hw(musb); 1487 1488 if (status < 0) 1489 return status; 1490 1491 /* finish init, and print endpoint config */ 1492 for (i = 0; i < musb->nr_endpoints; i++) { 1493 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1494 1495 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1496#ifdef CONFIG_USB_TUSB6010 1497 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1498 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1499 hw_ep->fifo_sync_va = 1500 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1501 1502 if (i == 0) 1503 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1504 else 1505 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1506#endif 1507 1508 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1509#ifdef CONFIG_USB_MUSB_HDRC_HCD 1510 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1511 hw_ep->rx_reinit = 1; 1512 hw_ep->tx_reinit = 1; 1513#endif 1514 1515 if (hw_ep->max_packet_sz_tx) { 1516 DBG(1, 1517 "%s: hw_ep %d%s, %smax %d\n", 1518 musb_driver_name, i, 1519 hw_ep->is_shared_fifo ? "shared" : "tx", 1520 hw_ep->tx_double_buffered 1521 ? "doublebuffer, " : "", 1522 hw_ep->max_packet_sz_tx); 1523 } 1524 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1525 DBG(1, 1526 "%s: hw_ep %d%s, %smax %d\n", 1527 musb_driver_name, i, 1528 "rx", 1529 hw_ep->rx_double_buffered 1530 ? "doublebuffer, " : "", 1531 hw_ep->max_packet_sz_rx); 1532 } 1533 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1534 DBG(1, "hw_ep %d not configured\n", i); 1535 } 1536 1537 return 0; 1538} 1539 1540/*-------------------------------------------------------------------------*/ 1541 1542#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \ 1543 defined(CONFIG_ARCH_OMAP4) 1544 1545static irqreturn_t generic_interrupt(int irq, void *__hci) 1546{ 1547 unsigned long flags; 1548 irqreturn_t retval = IRQ_NONE; 1549 struct musb *musb = __hci; 1550 1551 spin_lock_irqsave(&musb->lock, flags); 1552 1553 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1554 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1555 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1556 1557 if (musb->int_usb || musb->int_tx || musb->int_rx) 1558 retval = musb_interrupt(musb); 1559 1560 spin_unlock_irqrestore(&musb->lock, flags); 1561 1562 return retval; 1563} 1564 1565#else 1566#define generic_interrupt NULL 1567#endif 1568 1569/* 1570 * handle all the irqs defined by the HDRC core. for now we expect: other 1571 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1572 * will be assigned, and the irq will already have been acked. 1573 * 1574 * called in irq context with spinlock held, irqs blocked 1575 */ 1576irqreturn_t musb_interrupt(struct musb *musb) 1577{ 1578 irqreturn_t retval = IRQ_NONE; 1579 u8 devctl, power; 1580 int ep_num; 1581 u32 reg; 1582 1583 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1584 power = musb_readb(musb->mregs, MUSB_POWER); 1585 1586 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n", 1587 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1588 musb->int_usb, musb->int_tx, musb->int_rx); 1589 1590#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1591 if (is_otg_enabled(musb) || is_peripheral_enabled(musb)) 1592 if (!musb->gadget_driver) { 1593 DBG(5, "No gadget driver loaded\n"); 1594 return IRQ_HANDLED; 1595 } 1596#endif 1597 1598 /* the core can interrupt us for multiple reasons; docs have 1599 * a generic interrupt flowchart to follow 1600 */ 1601 if (musb->int_usb & STAGE0_MASK) 1602 retval |= musb_stage0_irq(musb, musb->int_usb, 1603 devctl, power); 1604 1605 /* "stage 1" is handling endpoint irqs */ 1606 1607 /* handle endpoint 0 first */ 1608 if (musb->int_tx & 1) { 1609 if (devctl & MUSB_DEVCTL_HM) 1610 retval |= musb_h_ep0_irq(musb); 1611 else 1612 retval |= musb_g_ep0_irq(musb); 1613 } 1614 1615 /* RX on endpoints 1-15 */ 1616 reg = musb->int_rx >> 1; 1617 ep_num = 1; 1618 while (reg) { 1619 if (reg & 1) { 1620 /* musb_ep_select(musb->mregs, ep_num); */ 1621 /* REVISIT just retval = ep->rx_irq(...) */ 1622 retval = IRQ_HANDLED; 1623 if (devctl & MUSB_DEVCTL_HM) { 1624 if (is_host_capable()) 1625 musb_host_rx(musb, ep_num); 1626 } else { 1627 if (is_peripheral_capable()) 1628 musb_g_rx(musb, ep_num); 1629 } 1630 } 1631 1632 reg >>= 1; 1633 ep_num++; 1634 } 1635 1636 /* TX on endpoints 1-15 */ 1637 reg = musb->int_tx >> 1; 1638 ep_num = 1; 1639 while (reg) { 1640 if (reg & 1) { 1641 /* musb_ep_select(musb->mregs, ep_num); */ 1642 /* REVISIT just retval |= ep->tx_irq(...) */ 1643 retval = IRQ_HANDLED; 1644 if (devctl & MUSB_DEVCTL_HM) { 1645 if (is_host_capable()) 1646 musb_host_tx(musb, ep_num); 1647 } else { 1648 if (is_peripheral_capable()) 1649 musb_g_tx(musb, ep_num); 1650 } 1651 } 1652 reg >>= 1; 1653 ep_num++; 1654 } 1655 1656 return retval; 1657} 1658 1659 1660#ifndef CONFIG_MUSB_PIO_ONLY 1661static int __initdata use_dma = 1; 1662 1663/* "modprobe ... use_dma=0" etc */ 1664module_param(use_dma, bool, 0); 1665MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1666 1667void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1668{ 1669 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1670 1671 /* called with controller lock already held */ 1672 1673 if (!epnum) { 1674#ifndef CONFIG_USB_TUSB_OMAP_DMA 1675 if (!is_cppi_enabled()) { 1676 /* endpoint 0 */ 1677 if (devctl & MUSB_DEVCTL_HM) 1678 musb_h_ep0_irq(musb); 1679 else 1680 musb_g_ep0_irq(musb); 1681 } 1682#endif 1683 } else { 1684 /* endpoints 1..15 */ 1685 if (transmit) { 1686 if (devctl & MUSB_DEVCTL_HM) { 1687 if (is_host_capable()) 1688 musb_host_tx(musb, epnum); 1689 } else { 1690 if (is_peripheral_capable()) 1691 musb_g_tx(musb, epnum); 1692 } 1693 } else { 1694 /* receive */ 1695 if (devctl & MUSB_DEVCTL_HM) { 1696 if (is_host_capable()) 1697 musb_host_rx(musb, epnum); 1698 } else { 1699 if (is_peripheral_capable()) 1700 musb_g_rx(musb, epnum); 1701 } 1702 } 1703 } 1704} 1705 1706#else 1707#define use_dma 0 1708#endif 1709 1710/*-------------------------------------------------------------------------*/ 1711 1712#ifdef CONFIG_SYSFS 1713 1714static ssize_t 1715musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1716{ 1717 struct musb *musb = dev_to_musb(dev); 1718 unsigned long flags; 1719 int ret = -EINVAL; 1720 1721 spin_lock_irqsave(&musb->lock, flags); 1722 ret = sprintf(buf, "%s\n", otg_state_string(musb)); 1723 spin_unlock_irqrestore(&musb->lock, flags); 1724 1725 return ret; 1726} 1727 1728static ssize_t 1729musb_mode_store(struct device *dev, struct device_attribute *attr, 1730 const char *buf, size_t n) 1731{ 1732 struct musb *musb = dev_to_musb(dev); 1733 unsigned long flags; 1734 int status; 1735 1736 spin_lock_irqsave(&musb->lock, flags); 1737 if (sysfs_streq(buf, "host")) 1738 status = musb_platform_set_mode(musb, MUSB_HOST); 1739 else if (sysfs_streq(buf, "peripheral")) 1740 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1741 else if (sysfs_streq(buf, "otg")) 1742 status = musb_platform_set_mode(musb, MUSB_OTG); 1743 else 1744 status = -EINVAL; 1745 spin_unlock_irqrestore(&musb->lock, flags); 1746 1747 return (status == 0) ? n : status; 1748} 1749static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1750 1751static ssize_t 1752musb_vbus_store(struct device *dev, struct device_attribute *attr, 1753 const char *buf, size_t n) 1754{ 1755 struct musb *musb = dev_to_musb(dev); 1756 unsigned long flags; 1757 unsigned long val; 1758 1759 if (sscanf(buf, "%lu", &val) < 1) { 1760 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1761 return -EINVAL; 1762 } 1763 1764 spin_lock_irqsave(&musb->lock, flags); 1765 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1766 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1767 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1768 musb->is_active = 0; 1769 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1770 spin_unlock_irqrestore(&musb->lock, flags); 1771 1772 return n; 1773} 1774 1775static ssize_t 1776musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1777{ 1778 struct musb *musb = dev_to_musb(dev); 1779 unsigned long flags; 1780 unsigned long val; 1781 int vbus; 1782 1783 spin_lock_irqsave(&musb->lock, flags); 1784 val = musb->a_wait_bcon; 1785 /* FIXME get_vbus_status() is normally #defined as false... 1786 * and is effectively TUSB-specific. 1787 */ 1788 vbus = musb_platform_get_vbus_status(musb); 1789 spin_unlock_irqrestore(&musb->lock, flags); 1790 1791 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1792 vbus ? "on" : "off", val); 1793} 1794static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1795 1796#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1797 1798/* Gadget drivers can't know that a host is connected so they might want 1799 * to start SRP, but users can. This allows userspace to trigger SRP. 1800 */ 1801static ssize_t 1802musb_srp_store(struct device *dev, struct device_attribute *attr, 1803 const char *buf, size_t n) 1804{ 1805 struct musb *musb = dev_to_musb(dev); 1806 unsigned short srp; 1807 1808 if (sscanf(buf, "%hu", &srp) != 1 1809 || (srp != 1)) { 1810 dev_err(dev, "SRP: Value must be 1\n"); 1811 return -EINVAL; 1812 } 1813 1814 if (srp == 1) 1815 musb_g_wakeup(musb); 1816 1817 return n; 1818} 1819static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1820 1821#endif /* CONFIG_USB_GADGET_MUSB_HDRC */ 1822 1823static struct attribute *musb_attributes[] = { 1824 &dev_attr_mode.attr, 1825 &dev_attr_vbus.attr, 1826#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1827 &dev_attr_srp.attr, 1828#endif 1829 NULL 1830}; 1831 1832static const struct attribute_group musb_attr_group = { 1833 .attrs = musb_attributes, 1834}; 1835 1836#endif /* sysfs */ 1837 1838/* Only used to provide driver mode change events */ 1839static void musb_irq_work(struct work_struct *data) 1840{ 1841 struct musb *musb = container_of(data, struct musb, irq_work); 1842 static int old_state; 1843 1844 if (musb->xceiv->state != old_state) { 1845 old_state = musb->xceiv->state; 1846 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1847 } 1848} 1849 1850/* -------------------------------------------------------------------------- 1851 * Init support 1852 */ 1853 1854static struct musb *__init 1855allocate_instance(struct device *dev, 1856 struct musb_hdrc_config *config, void __iomem *mbase) 1857{ 1858 struct musb *musb; 1859 struct musb_hw_ep *ep; 1860 int epnum; 1861#ifdef CONFIG_USB_MUSB_HDRC_HCD 1862 struct usb_hcd *hcd; 1863 1864 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1865 if (!hcd) 1866 return NULL; 1867 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1868 1869 musb = hcd_to_musb(hcd); 1870 INIT_LIST_HEAD(&musb->control); 1871 INIT_LIST_HEAD(&musb->in_bulk); 1872 INIT_LIST_HEAD(&musb->out_bulk); 1873 1874 hcd->uses_new_polling = 1; 1875 1876 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1877 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1878#else 1879 musb = kzalloc(sizeof *musb, GFP_KERNEL); 1880 if (!musb) 1881 return NULL; 1882 dev_set_drvdata(dev, musb); 1883 1884#endif 1885 1886 musb->mregs = mbase; 1887 musb->ctrl_base = mbase; 1888 musb->nIrq = -ENODEV; 1889 musb->config = config; 1890 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1891 for (epnum = 0, ep = musb->endpoints; 1892 epnum < musb->config->num_eps; 1893 epnum++, ep++) { 1894 ep->musb = musb; 1895 ep->epnum = epnum; 1896 } 1897 1898 musb->controller = dev; 1899 return musb; 1900} 1901 1902static void musb_free(struct musb *musb) 1903{ 1904 /* this has multiple entry modes. it handles fault cleanup after 1905 * probe(), where things may be partially set up, as well as rmmod 1906 * cleanup after everything's been de-activated. 1907 */ 1908 1909#ifdef CONFIG_SYSFS 1910 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1911#endif 1912 1913#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1914 musb_gadget_cleanup(musb); 1915#endif 1916 1917 if (musb->nIrq >= 0) { 1918 if (musb->irq_wake) 1919 disable_irq_wake(musb->nIrq); 1920 free_irq(musb->nIrq, musb); 1921 } 1922 if (is_dma_capable() && musb->dma_controller) { 1923 struct dma_controller *c = musb->dma_controller; 1924 1925 (void) c->stop(c); 1926 dma_controller_destroy(c); 1927 } 1928 1929#ifdef CONFIG_USB_MUSB_OTG 1930 put_device(musb->xceiv->dev); 1931#endif 1932 1933#ifdef CONFIG_USB_MUSB_HDRC_HCD 1934 usb_put_hcd(musb_to_hcd(musb)); 1935#else 1936 kfree(musb); 1937#endif 1938} 1939 1940/* 1941 * Perform generic per-controller initialization. 1942 * 1943 * @pDevice: the controller (already clocked, etc) 1944 * @nIrq: irq 1945 * @mregs: virtual address of controller registers, 1946 * not yet corrected for platform-specific offsets 1947 */ 1948static int __init 1949musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1950{ 1951 int status; 1952 struct musb *musb; 1953 struct musb_hdrc_platform_data *plat = dev->platform_data; 1954 1955 /* The driver might handle more features than the board; OK. 1956 * Fail when the board needs a feature that's not enabled. 1957 */ 1958 if (!plat) { 1959 dev_dbg(dev, "no platform_data?\n"); 1960 status = -ENODEV; 1961 goto fail0; 1962 } 1963 1964 switch (plat->mode) { 1965 case MUSB_HOST: 1966#ifdef CONFIG_USB_MUSB_HDRC_HCD 1967 break; 1968#else 1969 goto bad_config; 1970#endif 1971 case MUSB_PERIPHERAL: 1972#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1973 break; 1974#else 1975 goto bad_config; 1976#endif 1977 case MUSB_OTG: 1978#ifdef CONFIG_USB_MUSB_OTG 1979 break; 1980#else 1981bad_config: 1982#endif 1983 default: 1984 dev_err(dev, "incompatible Kconfig role setting\n"); 1985 status = -EINVAL; 1986 goto fail0; 1987 } 1988 1989 /* allocate */ 1990 musb = allocate_instance(dev, plat->config, ctrl); 1991 if (!musb) { 1992 status = -ENOMEM; 1993 goto fail0; 1994 } 1995 1996 spin_lock_init(&musb->lock); 1997 musb->board_mode = plat->mode; 1998 musb->board_set_power = plat->set_power; 1999 musb->set_clock = plat->set_clock; 2000 musb->min_power = plat->min_power; 2001 2002 /* Clock usage is chip-specific ... functional clock (DaVinci, 2003 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core 2004 * code does is make sure a clock handle is available; platform 2005 * code manages it during start/stop and suspend/resume. 2006 */ 2007 if (plat->clock) { 2008 musb->clock = clk_get(dev, plat->clock); 2009 if (IS_ERR(musb->clock)) { 2010 status = PTR_ERR(musb->clock); 2011 musb->clock = NULL; 2012 goto fail1; 2013 } 2014 } 2015 2016 /* The musb_platform_init() call: 2017 * - adjusts musb->mregs and musb->isr if needed, 2018 * - may initialize an integrated tranceiver 2019 * - initializes musb->xceiv, usually by otg_get_transceiver() 2020 * - activates clocks. 2021 * - stops powering VBUS 2022 * - assigns musb->board_set_vbus if host mode is enabled 2023 * 2024 * There are various transciever configurations. Blackfin, 2025 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 2026 * external/discrete ones in various flavors (twl4030 family, 2027 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 2028 */ 2029 musb->isr = generic_interrupt; 2030 status = musb_platform_init(musb, plat->board_data); 2031 if (status < 0) 2032 goto fail2; 2033 2034 if (!musb->isr) { 2035 status = -ENODEV; 2036 goto fail3; 2037 } 2038 2039 if (!musb->xceiv->io_ops) { 2040 musb->xceiv->io_priv = musb->mregs; 2041 musb->xceiv->io_ops = &musb_ulpi_access; 2042 } 2043 2044#ifndef CONFIG_MUSB_PIO_ONLY 2045 if (use_dma && dev->dma_mask) { 2046 struct dma_controller *c; 2047 2048 c = dma_controller_create(musb, musb->mregs); 2049 musb->dma_controller = c; 2050 if (c) 2051 (void) c->start(c); 2052 } 2053#endif 2054 /* ideally this would be abstracted in platform setup */ 2055 if (!is_dma_capable() || !musb->dma_controller) 2056 dev->dma_mask = NULL; 2057 2058 /* be sure interrupts are disabled before connecting ISR */ 2059 musb_platform_disable(musb); 2060 musb_generic_disable(musb); 2061 2062 /* setup musb parts of the core (especially endpoints) */ 2063 status = musb_core_init(plat->config->multipoint 2064 ? MUSB_CONTROLLER_MHDRC 2065 : MUSB_CONTROLLER_HDRC, musb); 2066 if (status < 0) 2067 goto fail3; 2068 2069#ifdef CONFIG_USB_MUSB_OTG 2070 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 2071#endif 2072 2073 /* Init IRQ workqueue before request_irq */ 2074 INIT_WORK(&musb->irq_work, musb_irq_work); 2075 2076 /* attach to the IRQ */ 2077 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 2078 dev_err(dev, "request_irq %d failed!\n", nIrq); 2079 status = -ENODEV; 2080 goto fail3; 2081 } 2082 musb->nIrq = nIrq; 2083/* FIXME this handles wakeup irqs wrong */ 2084 if (enable_irq_wake(nIrq) == 0) { 2085 musb->irq_wake = 1; 2086 device_init_wakeup(dev, 1); 2087 } else { 2088 musb->irq_wake = 0; 2089 } 2090 2091 /* host side needs more setup */ 2092 if (is_host_enabled(musb)) { 2093 struct usb_hcd *hcd = musb_to_hcd(musb); 2094 2095 otg_set_host(musb->xceiv, &hcd->self); 2096 2097 if (is_otg_enabled(musb)) 2098 hcd->self.otg_port = 1; 2099 musb->xceiv->host = &hcd->self; 2100 hcd->power_budget = 2 * (plat->power ? : 250); 2101 2102 /* program PHY to use external vBus if required */ 2103 if (plat->extvbus) { 2104 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2105 busctl |= MUSB_ULPI_USE_EXTVBUS; 2106 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2107 } 2108 } 2109 2110 /* For the host-only role, we can activate right away. 2111 * (We expect the ID pin to be forcibly grounded!!) 2112 * Otherwise, wait till the gadget driver hooks up. 2113 */ 2114 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2115 MUSB_HST_MODE(musb); 2116 musb->xceiv->default_a = 1; 2117 musb->xceiv->state = OTG_STATE_A_IDLE; 2118 2119 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 2120 2121 DBG(1, "%s mode, status %d, devctl %02x %c\n", 2122 "HOST", status, 2123 musb_readb(musb->mregs, MUSB_DEVCTL), 2124 (musb_readb(musb->mregs, MUSB_DEVCTL) 2125 & MUSB_DEVCTL_BDEVICE 2126 ? 'B' : 'A')); 2127 2128 } else /* peripheral is enabled */ { 2129 MUSB_DEV_MODE(musb); 2130 musb->xceiv->default_a = 0; 2131 musb->xceiv->state = OTG_STATE_B_IDLE; 2132 2133 status = musb_gadget_setup(musb); 2134 2135 DBG(1, "%s mode, status %d, dev%02x\n", 2136 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2137 status, 2138 musb_readb(musb->mregs, MUSB_DEVCTL)); 2139 2140 } 2141 if (status < 0) 2142 goto fail3; 2143 2144 status = musb_init_debugfs(musb); 2145 if (status < 0) 2146 goto fail4; 2147 2148#ifdef CONFIG_SYSFS 2149 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2150 if (status) 2151 goto fail5; 2152#endif 2153 2154 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", 2155 ({char *s; 2156 switch (musb->board_mode) { 2157 case MUSB_HOST: s = "Host"; break; 2158 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2159 default: s = "OTG"; break; 2160 }; s; }), 2161 ctrl, 2162 (is_dma_capable() && musb->dma_controller) 2163 ? "DMA" : "PIO", 2164 musb->nIrq); 2165 2166 return 0; 2167 2168fail5: 2169 musb_exit_debugfs(musb); 2170 2171fail4: 2172 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 2173 usb_remove_hcd(musb_to_hcd(musb)); 2174 else 2175 musb_gadget_cleanup(musb); 2176 2177fail3: 2178 if (musb->irq_wake) 2179 device_init_wakeup(dev, 0); 2180 musb_platform_exit(musb); 2181 2182fail2: 2183 if (musb->clock) 2184 clk_put(musb->clock); 2185 2186fail1: 2187 dev_err(musb->controller, 2188 "musb_init_controller failed with status %d\n", status); 2189 2190 musb_free(musb); 2191 2192fail0: 2193 2194 return status; 2195 2196} 2197 2198/*-------------------------------------------------------------------------*/ 2199 2200/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2201 * bridge to a platform device; this driver then suffices. 2202 */ 2203 2204#ifndef CONFIG_MUSB_PIO_ONLY 2205static u64 *orig_dma_mask; 2206#endif 2207 2208static int __init musb_probe(struct platform_device *pdev) 2209{ 2210 struct device *dev = &pdev->dev; 2211 int irq = platform_get_irq(pdev, 0); 2212 int status; 2213 struct resource *iomem; 2214 void __iomem *base; 2215 2216 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2217 if (!iomem || irq == 0) 2218 return -ENODEV; 2219 2220 base = ioremap(iomem->start, resource_size(iomem)); 2221 if (!base) { 2222 dev_err(dev, "ioremap failed\n"); 2223 return -ENOMEM; 2224 } 2225 2226#ifndef CONFIG_MUSB_PIO_ONLY 2227 /* clobbered by use_dma=n */ 2228 orig_dma_mask = dev->dma_mask; 2229#endif 2230 status = musb_init_controller(dev, irq, base); 2231 if (status < 0) 2232 iounmap(base); 2233 2234 return status; 2235} 2236 2237static int __exit musb_remove(struct platform_device *pdev) 2238{ 2239 struct musb *musb = dev_to_musb(&pdev->dev); 2240 void __iomem *ctrl_base = musb->ctrl_base; 2241 2242 /* this gets called on rmmod. 2243 * - Host mode: host may still be active 2244 * - Peripheral mode: peripheral is deactivated (or never-activated) 2245 * - OTG mode: both roles are deactivated (or never-activated) 2246 */ 2247 musb_exit_debugfs(musb); 2248 musb_shutdown(pdev); 2249#ifdef CONFIG_USB_MUSB_HDRC_HCD 2250 if (musb->board_mode == MUSB_HOST) 2251 usb_remove_hcd(musb_to_hcd(musb)); 2252#endif 2253 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2254 musb_platform_exit(musb); 2255 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2256 2257 musb_free(musb); 2258 iounmap(ctrl_base); 2259 device_init_wakeup(&pdev->dev, 0); 2260#ifndef CONFIG_MUSB_PIO_ONLY 2261 pdev->dev.dma_mask = orig_dma_mask; 2262#endif 2263 return 0; 2264} 2265 2266#ifdef CONFIG_PM 2267 2268static struct musb_context_registers musb_context; 2269 2270void musb_save_context(struct musb *musb) 2271{ 2272 int i; 2273 void __iomem *musb_base = musb->mregs; 2274 2275 if (is_host_enabled(musb)) { 2276 musb_context.frame = musb_readw(musb_base, MUSB_FRAME); 2277 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2278 musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2279 } 2280 musb_context.power = musb_readb(musb_base, MUSB_POWER); 2281 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2282 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2283 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2284 musb_context.index = musb_readb(musb_base, MUSB_INDEX); 2285 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2286 2287 for (i = 0; i < MUSB_C_NUM_EPS; ++i) { 2288 musb_writeb(musb_base, MUSB_INDEX, i); 2289 musb_context.index_regs[i].txmaxp = 2290 musb_readw(musb_base, 0x10 + MUSB_TXMAXP); 2291 musb_context.index_regs[i].txcsr = 2292 musb_readw(musb_base, 0x10 + MUSB_TXCSR); 2293 musb_context.index_regs[i].rxmaxp = 2294 musb_readw(musb_base, 0x10 + MUSB_RXMAXP); 2295 musb_context.index_regs[i].rxcsr = 2296 musb_readw(musb_base, 0x10 + MUSB_RXCSR); 2297 2298 if (musb->dyn_fifo) { 2299 musb_context.index_regs[i].txfifoadd = 2300 musb_read_txfifoadd(musb_base); 2301 musb_context.index_regs[i].rxfifoadd = 2302 musb_read_rxfifoadd(musb_base); 2303 musb_context.index_regs[i].txfifosz = 2304 musb_read_txfifosz(musb_base); 2305 musb_context.index_regs[i].rxfifosz = 2306 musb_read_rxfifosz(musb_base); 2307 } 2308 if (is_host_enabled(musb)) { 2309 musb_context.index_regs[i].txtype = 2310 musb_readb(musb_base, 0x10 + MUSB_TXTYPE); 2311 musb_context.index_regs[i].txinterval = 2312 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL); 2313 musb_context.index_regs[i].rxtype = 2314 musb_readb(musb_base, 0x10 + MUSB_RXTYPE); 2315 musb_context.index_regs[i].rxinterval = 2316 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL); 2317 2318 musb_context.index_regs[i].txfunaddr = 2319 musb_read_txfunaddr(musb_base, i); 2320 musb_context.index_regs[i].txhubaddr = 2321 musb_read_txhubaddr(musb_base, i); 2322 musb_context.index_regs[i].txhubport = 2323 musb_read_txhubport(musb_base, i); 2324 2325 musb_context.index_regs[i].rxfunaddr = 2326 musb_read_rxfunaddr(musb_base, i); 2327 musb_context.index_regs[i].rxhubaddr = 2328 musb_read_rxhubaddr(musb_base, i); 2329 musb_context.index_regs[i].rxhubport = 2330 musb_read_rxhubport(musb_base, i); 2331 } 2332 } 2333 2334 musb_writeb(musb_base, MUSB_INDEX, musb_context.index); 2335 2336 musb_platform_save_context(musb, &musb_context); 2337} 2338 2339void musb_restore_context(struct musb *musb) 2340{ 2341 int i; 2342 void __iomem *musb_base = musb->mregs; 2343 void __iomem *ep_target_regs; 2344 2345 musb_platform_restore_context(musb, &musb_context); 2346 2347 if (is_host_enabled(musb)) { 2348 musb_writew(musb_base, MUSB_FRAME, musb_context.frame); 2349 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode); 2350 musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl); 2351 } 2352 musb_writeb(musb_base, MUSB_POWER, musb_context.power); 2353 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe); 2354 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe); 2355 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe); 2356 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl); 2357 2358 for (i = 0; i < MUSB_C_NUM_EPS; ++i) { 2359 musb_writeb(musb_base, MUSB_INDEX, i); 2360 musb_writew(musb_base, 0x10 + MUSB_TXMAXP, 2361 musb_context.index_regs[i].txmaxp); 2362 musb_writew(musb_base, 0x10 + MUSB_TXCSR, 2363 musb_context.index_regs[i].txcsr); 2364 musb_writew(musb_base, 0x10 + MUSB_RXMAXP, 2365 musb_context.index_regs[i].rxmaxp); 2366 musb_writew(musb_base, 0x10 + MUSB_RXCSR, 2367 musb_context.index_regs[i].rxcsr); 2368 2369 if (musb->dyn_fifo) { 2370 musb_write_txfifosz(musb_base, 2371 musb_context.index_regs[i].txfifosz); 2372 musb_write_rxfifosz(musb_base, 2373 musb_context.index_regs[i].rxfifosz); 2374 musb_write_txfifoadd(musb_base, 2375 musb_context.index_regs[i].txfifoadd); 2376 musb_write_rxfifoadd(musb_base, 2377 musb_context.index_regs[i].rxfifoadd); 2378 } 2379 2380 if (is_host_enabled(musb)) { 2381 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE, 2382 musb_context.index_regs[i].txtype); 2383 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL, 2384 musb_context.index_regs[i].txinterval); 2385 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE, 2386 musb_context.index_regs[i].rxtype); 2387 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL, 2388 2389 musb_context.index_regs[i].rxinterval); 2390 musb_write_txfunaddr(musb_base, i, 2391 musb_context.index_regs[i].txfunaddr); 2392 musb_write_txhubaddr(musb_base, i, 2393 musb_context.index_regs[i].txhubaddr); 2394 musb_write_txhubport(musb_base, i, 2395 musb_context.index_regs[i].txhubport); 2396 2397 ep_target_regs = 2398 musb_read_target_reg_base(i, musb_base); 2399 2400 musb_write_rxfunaddr(ep_target_regs, 2401 musb_context.index_regs[i].rxfunaddr); 2402 musb_write_rxhubaddr(ep_target_regs, 2403 musb_context.index_regs[i].rxhubaddr); 2404 musb_write_rxhubport(ep_target_regs, 2405 musb_context.index_regs[i].rxhubport); 2406 } 2407 } 2408 2409 musb_writeb(musb_base, MUSB_INDEX, musb_context.index); 2410} 2411 2412static int musb_suspend(struct device *dev) 2413{ 2414 struct platform_device *pdev = to_platform_device(dev); 2415 unsigned long flags; 2416 struct musb *musb = dev_to_musb(&pdev->dev); 2417 2418 if (!musb->clock) 2419 return 0; 2420 2421 spin_lock_irqsave(&musb->lock, flags); 2422 2423 if (is_peripheral_active(musb)) { 2424 /* FIXME force disconnect unless we know USB will wake 2425 * the system up quickly enough to respond ... 2426 */ 2427 } else if (is_host_active(musb)) { 2428 /* we know all the children are suspended; sometimes 2429 * they will even be wakeup-enabled. 2430 */ 2431 } 2432 2433 musb_save_context(musb); 2434 2435 if (musb->set_clock) 2436 musb->set_clock(musb->clock, 0); 2437 else 2438 clk_disable(musb->clock); 2439 spin_unlock_irqrestore(&musb->lock, flags); 2440 return 0; 2441} 2442 2443static int musb_resume_noirq(struct device *dev) 2444{ 2445 struct platform_device *pdev = to_platform_device(dev); 2446 struct musb *musb = dev_to_musb(&pdev->dev); 2447 2448 if (!musb->clock) 2449 return 0; 2450 2451 if (musb->set_clock) 2452 musb->set_clock(musb->clock, 1); 2453 else 2454 clk_enable(musb->clock); 2455 2456 musb_restore_context(musb); 2457 2458 /* for static cmos like DaVinci, register values were preserved 2459 * unless for some reason the whole soc powered down or the USB 2460 * module got reset through the PSC (vs just being disabled). 2461 */ 2462 return 0; 2463} 2464 2465static const struct dev_pm_ops musb_dev_pm_ops = { 2466 .suspend = musb_suspend, 2467 .resume_noirq = musb_resume_noirq, 2468}; 2469 2470#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2471#else 2472#define MUSB_DEV_PM_OPS NULL 2473#endif 2474 2475static struct platform_driver musb_driver = { 2476 .driver = { 2477 .name = (char *)musb_driver_name, 2478 .bus = &platform_bus_type, 2479 .owner = THIS_MODULE, 2480 .pm = MUSB_DEV_PM_OPS, 2481 }, 2482 .remove = __exit_p(musb_remove), 2483 .shutdown = musb_shutdown, 2484}; 2485 2486/*-------------------------------------------------------------------------*/ 2487 2488static int __init musb_init(void) 2489{ 2490#ifdef CONFIG_USB_MUSB_HDRC_HCD 2491 if (usb_disabled()) 2492 return 0; 2493#endif 2494 2495 pr_info("%s: version " MUSB_VERSION ", " 2496#ifdef CONFIG_MUSB_PIO_ONLY 2497 "pio" 2498#elif defined(CONFIG_USB_TI_CPPI_DMA) 2499 "cppi-dma" 2500#elif defined(CONFIG_USB_INVENTRA_DMA) 2501 "musb-dma" 2502#elif defined(CONFIG_USB_TUSB_OMAP_DMA) 2503 "tusb-omap-dma" 2504#else 2505 "?dma?" 2506#endif 2507 ", " 2508#ifdef CONFIG_USB_MUSB_OTG 2509 "otg (peripheral+host)" 2510#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 2511 "peripheral" 2512#elif defined(CONFIG_USB_MUSB_HDRC_HCD) 2513 "host" 2514#endif 2515 ", debug=%d\n", 2516 musb_driver_name, musb_debug); 2517 return platform_driver_probe(&musb_driver, musb_probe); 2518} 2519 2520/* make us init after usbcore and i2c (transceivers, regulators, etc) 2521 * and before usb gadget and host-side drivers start to register 2522 */ 2523fs_initcall(musb_init); 2524 2525static void __exit musb_cleanup(void) 2526{ 2527 platform_driver_unregister(&musb_driver); 2528} 2529module_exit(musb_cleanup); 2530