musb_core.c revision 461972d8a4c94bc44f11a13046041c78a7cf18dd
1/* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35/* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82/* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92#include <linux/module.h> 93#include <linux/kernel.h> 94#include <linux/sched.h> 95#include <linux/slab.h> 96#include <linux/init.h> 97#include <linux/list.h> 98#include <linux/kobject.h> 99#include <linux/platform_device.h> 100#include <linux/io.h> 101 102#ifdef CONFIG_ARM 103#include <mach/hardware.h> 104#include <mach/memory.h> 105#include <asm/mach-types.h> 106#endif 107 108#include "musb_core.h" 109 110 111#ifdef CONFIG_ARCH_DAVINCI 112#include "davinci.h" 113#endif 114 115#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 116 117 118unsigned musb_debug; 119module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR); 120MODULE_PARM_DESC(debug, "Debug message level. Default = 0"); 121 122#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 123#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 124 125#define MUSB_VERSION "6.0" 126 127#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 128 129#define MUSB_DRIVER_NAME "musb_hdrc" 130const char musb_driver_name[] = MUSB_DRIVER_NAME; 131 132MODULE_DESCRIPTION(DRIVER_INFO); 133MODULE_AUTHOR(DRIVER_AUTHOR); 134MODULE_LICENSE("GPL"); 135MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 136 137 138/*-------------------------------------------------------------------------*/ 139 140static inline struct musb *dev_to_musb(struct device *dev) 141{ 142#ifdef CONFIG_USB_MUSB_HDRC_HCD 143 /* usbcore insists dev->driver_data is a "struct hcd *" */ 144 return hcd_to_musb(dev_get_drvdata(dev)); 145#else 146 return dev_get_drvdata(dev); 147#endif 148} 149 150/*-------------------------------------------------------------------------*/ 151 152#if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN) 153 154/* 155 * Load an endpoint's FIFO 156 */ 157void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 158{ 159 void __iomem *fifo = hw_ep->fifo; 160 161 prefetch((u8 *)src); 162 163 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 164 'T', hw_ep->epnum, fifo, len, src); 165 166 /* we can't assume unaligned reads work */ 167 if (likely((0x01 & (unsigned long) src) == 0)) { 168 u16 index = 0; 169 170 /* best case is 32bit-aligned source address */ 171 if ((0x02 & (unsigned long) src) == 0) { 172 if (len >= 4) { 173 writesl(fifo, src + index, len >> 2); 174 index += len & ~0x03; 175 } 176 if (len & 0x02) { 177 musb_writew(fifo, 0, *(u16 *)&src[index]); 178 index += 2; 179 } 180 } else { 181 if (len >= 2) { 182 writesw(fifo, src + index, len >> 1); 183 index += len & ~0x01; 184 } 185 } 186 if (len & 0x01) 187 musb_writeb(fifo, 0, src[index]); 188 } else { 189 /* byte aligned */ 190 writesb(fifo, src, len); 191 } 192} 193 194/* 195 * Unload an endpoint's FIFO 196 */ 197void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 198{ 199 void __iomem *fifo = hw_ep->fifo; 200 201 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 202 'R', hw_ep->epnum, fifo, len, dst); 203 204 /* we can't assume unaligned writes work */ 205 if (likely((0x01 & (unsigned long) dst) == 0)) { 206 u16 index = 0; 207 208 /* best case is 32bit-aligned destination address */ 209 if ((0x02 & (unsigned long) dst) == 0) { 210 if (len >= 4) { 211 readsl(fifo, dst, len >> 2); 212 index = len & ~0x03; 213 } 214 if (len & 0x02) { 215 *(u16 *)&dst[index] = musb_readw(fifo, 0); 216 index += 2; 217 } 218 } else { 219 if (len >= 2) { 220 readsw(fifo, dst, len >> 1); 221 index = len & ~0x01; 222 } 223 } 224 if (len & 0x01) 225 dst[index] = musb_readb(fifo, 0); 226 } else { 227 /* byte aligned */ 228 readsb(fifo, dst, len); 229 } 230} 231 232#endif /* normal PIO */ 233 234 235/*-------------------------------------------------------------------------*/ 236 237/* for high speed test mode; see USB 2.0 spec 7.1.20 */ 238static const u8 musb_test_packet[53] = { 239 /* implicit SYNC then DATA0 to start */ 240 241 /* JKJKJKJK x9 */ 242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 243 /* JJKKJJKK x8 */ 244 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 245 /* JJJJKKKK x8 */ 246 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 247 /* JJJJJJJKKKKKKK x8 */ 248 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 249 /* JJJJJJJK x8 */ 250 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 251 /* JKKKKKKK x10, JK */ 252 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 253 254 /* implicit CRC16 then EOP to end */ 255}; 256 257void musb_load_testpacket(struct musb *musb) 258{ 259 void __iomem *regs = musb->endpoints[0].regs; 260 261 musb_ep_select(musb->mregs, 0); 262 musb_write_fifo(musb->control_ep, 263 sizeof(musb_test_packet), musb_test_packet); 264 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 265} 266 267/*-------------------------------------------------------------------------*/ 268 269const char *otg_state_string(struct musb *musb) 270{ 271 switch (musb->xceiv->state) { 272 case OTG_STATE_A_IDLE: return "a_idle"; 273 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; 274 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; 275 case OTG_STATE_A_HOST: return "a_host"; 276 case OTG_STATE_A_SUSPEND: return "a_suspend"; 277 case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; 278 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; 279 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; 280 case OTG_STATE_B_IDLE: return "b_idle"; 281 case OTG_STATE_B_SRP_INIT: return "b_srp_init"; 282 case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; 283 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; 284 case OTG_STATE_B_HOST: return "b_host"; 285 default: return "UNDEFINED"; 286 } 287} 288 289#ifdef CONFIG_USB_MUSB_OTG 290 291/* 292 * Handles OTG hnp timeouts, such as b_ase0_brst 293 */ 294void musb_otg_timer_func(unsigned long data) 295{ 296 struct musb *musb = (struct musb *)data; 297 unsigned long flags; 298 299 spin_lock_irqsave(&musb->lock, flags); 300 switch (musb->xceiv->state) { 301 case OTG_STATE_B_WAIT_ACON: 302 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 303 musb_g_disconnect(musb); 304 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 305 musb->is_active = 0; 306 break; 307 case OTG_STATE_A_SUSPEND: 308 case OTG_STATE_A_WAIT_BCON: 309 DBG(1, "HNP: %s timeout\n", otg_state_string(musb)); 310 musb_set_vbus(musb, 0); 311 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 312 break; 313 default: 314 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb)); 315 } 316 musb->ignore_disconnect = 0; 317 spin_unlock_irqrestore(&musb->lock, flags); 318} 319 320/* 321 * Stops the HNP transition. Caller must take care of locking. 322 */ 323void musb_hnp_stop(struct musb *musb) 324{ 325 struct usb_hcd *hcd = musb_to_hcd(musb); 326 void __iomem *mbase = musb->mregs; 327 u8 reg; 328 329 DBG(1, "HNP: stop from %s\n", otg_state_string(musb)); 330 331 switch (musb->xceiv->state) { 332 case OTG_STATE_A_PERIPHERAL: 333 musb_g_disconnect(musb); 334 DBG(1, "HNP: back to %s\n", otg_state_string(musb)); 335 break; 336 case OTG_STATE_B_HOST: 337 DBG(1, "HNP: Disabling HR\n"); 338 hcd->self.is_b_host = 0; 339 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 340 MUSB_DEV_MODE(musb); 341 reg = musb_readb(mbase, MUSB_POWER); 342 reg |= MUSB_POWER_SUSPENDM; 343 musb_writeb(mbase, MUSB_POWER, reg); 344 /* REVISIT: Start SESSION_REQUEST here? */ 345 break; 346 default: 347 DBG(1, "HNP: Stopping in unknown state %s\n", 348 otg_state_string(musb)); 349 } 350 351 /* 352 * When returning to A state after HNP, avoid hub_port_rebounce(), 353 * which cause occasional OPT A "Did not receive reset after connect" 354 * errors. 355 */ 356 musb->port1_status &= 357 ~(1 << USB_PORT_FEAT_C_CONNECTION); 358} 359 360#endif 361 362/* 363 * Interrupt Service Routine to record USB "global" interrupts. 364 * Since these do not happen often and signify things of 365 * paramount importance, it seems OK to check them individually; 366 * the order of the tests is specified in the manual 367 * 368 * @param musb instance pointer 369 * @param int_usb register contents 370 * @param devctl 371 * @param power 372 */ 373 374#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \ 375 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \ 376 | MUSB_INTR_RESET) 377 378static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 379 u8 devctl, u8 power) 380{ 381 irqreturn_t handled = IRQ_NONE; 382 383 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 384 int_usb); 385 386 /* in host mode, the peripheral may issue remote wakeup. 387 * in peripheral mode, the host may resume the link. 388 * spurious RESUME irqs happen too, paired with SUSPEND. 389 */ 390 if (int_usb & MUSB_INTR_RESUME) { 391 handled = IRQ_HANDLED; 392 DBG(3, "RESUME (%s)\n", otg_state_string(musb)); 393 394 if (devctl & MUSB_DEVCTL_HM) { 395#ifdef CONFIG_USB_MUSB_HDRC_HCD 396 void __iomem *mbase = musb->mregs; 397 398 switch (musb->xceiv->state) { 399 case OTG_STATE_A_SUSPEND: 400 /* remote wakeup? later, GetPortStatus 401 * will stop RESUME signaling 402 */ 403 404 if (power & MUSB_POWER_SUSPENDM) { 405 /* spurious */ 406 musb->int_usb &= ~MUSB_INTR_SUSPEND; 407 DBG(2, "Spurious SUSPENDM\n"); 408 break; 409 } 410 411 power &= ~MUSB_POWER_SUSPENDM; 412 musb_writeb(mbase, MUSB_POWER, 413 power | MUSB_POWER_RESUME); 414 415 musb->port1_status |= 416 (USB_PORT_STAT_C_SUSPEND << 16) 417 | MUSB_PORT_STAT_RESUME; 418 musb->rh_timer = jiffies 419 + msecs_to_jiffies(20); 420 421 musb->xceiv->state = OTG_STATE_A_HOST; 422 musb->is_active = 1; 423 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 424 break; 425 case OTG_STATE_B_WAIT_ACON: 426 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 427 musb->is_active = 1; 428 MUSB_DEV_MODE(musb); 429 break; 430 default: 431 WARNING("bogus %s RESUME (%s)\n", 432 "host", 433 otg_state_string(musb)); 434 } 435#endif 436 } else { 437 switch (musb->xceiv->state) { 438#ifdef CONFIG_USB_MUSB_HDRC_HCD 439 case OTG_STATE_A_SUSPEND: 440 /* possibly DISCONNECT is upcoming */ 441 musb->xceiv->state = OTG_STATE_A_HOST; 442 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 443 break; 444#endif 445#ifdef CONFIG_USB_GADGET_MUSB_HDRC 446 case OTG_STATE_B_WAIT_ACON: 447 case OTG_STATE_B_PERIPHERAL: 448 /* disconnect while suspended? we may 449 * not get a disconnect irq... 450 */ 451 if ((devctl & MUSB_DEVCTL_VBUS) 452 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 453 ) { 454 musb->int_usb |= MUSB_INTR_DISCONNECT; 455 musb->int_usb &= ~MUSB_INTR_SUSPEND; 456 break; 457 } 458 musb_g_resume(musb); 459 break; 460 case OTG_STATE_B_IDLE: 461 musb->int_usb &= ~MUSB_INTR_SUSPEND; 462 break; 463#endif 464 default: 465 WARNING("bogus %s RESUME (%s)\n", 466 "peripheral", 467 otg_state_string(musb)); 468 } 469 } 470 } 471 472#ifdef CONFIG_USB_MUSB_HDRC_HCD 473 /* see manual for the order of the tests */ 474 if (int_usb & MUSB_INTR_SESSREQ) { 475 void __iomem *mbase = musb->mregs; 476 477 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); 478 479 /* IRQ arrives from ID pin sense or (later, if VBUS power 480 * is removed) SRP. responses are time critical: 481 * - turn on VBUS (with silicon-specific mechanism) 482 * - go through A_WAIT_VRISE 483 * - ... to A_WAIT_BCON. 484 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 485 */ 486 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 487 musb->ep0_stage = MUSB_EP0_START; 488 musb->xceiv->state = OTG_STATE_A_IDLE; 489 MUSB_HST_MODE(musb); 490 musb_set_vbus(musb, 1); 491 492 handled = IRQ_HANDLED; 493 } 494 495 if (int_usb & MUSB_INTR_VBUSERROR) { 496 int ignore = 0; 497 498 /* During connection as an A-Device, we may see a short 499 * current spikes causing voltage drop, because of cable 500 * and peripheral capacitance combined with vbus draw. 501 * (So: less common with truly self-powered devices, where 502 * vbus doesn't act like a power supply.) 503 * 504 * Such spikes are short; usually less than ~500 usec, max 505 * of ~2 msec. That is, they're not sustained overcurrent 506 * errors, though they're reported using VBUSERROR irqs. 507 * 508 * Workarounds: (a) hardware: use self powered devices. 509 * (b) software: ignore non-repeated VBUS errors. 510 * 511 * REVISIT: do delays from lots of DEBUG_KERNEL checks 512 * make trouble here, keeping VBUS < 4.4V ? 513 */ 514 switch (musb->xceiv->state) { 515 case OTG_STATE_A_HOST: 516 /* recovery is dicey once we've gotten past the 517 * initial stages of enumeration, but if VBUS 518 * stayed ok at the other end of the link, and 519 * another reset is due (at least for high speed, 520 * to redo the chirp etc), it might work OK... 521 */ 522 case OTG_STATE_A_WAIT_BCON: 523 case OTG_STATE_A_WAIT_VRISE: 524 if (musb->vbuserr_retry) { 525 void __iomem *mbase = musb->mregs; 526 527 musb->vbuserr_retry--; 528 ignore = 1; 529 devctl |= MUSB_DEVCTL_SESSION; 530 musb_writeb(mbase, MUSB_DEVCTL, devctl); 531 } else { 532 musb->port1_status |= 533 (1 << USB_PORT_FEAT_OVER_CURRENT) 534 | (1 << USB_PORT_FEAT_C_OVER_CURRENT); 535 } 536 break; 537 default: 538 break; 539 } 540 541 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 542 otg_state_string(musb), 543 devctl, 544 ({ char *s; 545 switch (devctl & MUSB_DEVCTL_VBUS) { 546 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 547 s = "<SessEnd"; break; 548 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 549 s = "<AValid"; break; 550 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 551 s = "<VBusValid"; break; 552 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 553 default: 554 s = "VALID"; break; 555 }; s; }), 556 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 557 musb->port1_status); 558 559 /* go through A_WAIT_VFALL then start a new session */ 560 if (!ignore) 561 musb_set_vbus(musb, 0); 562 handled = IRQ_HANDLED; 563 } 564 565 566 if (int_usb & MUSB_INTR_SUSPEND) { 567 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", 568 otg_state_string(musb), devctl, power); 569 handled = IRQ_HANDLED; 570 571 switch (musb->xceiv->state) { 572#ifdef CONFIG_USB_MUSB_OTG 573 case OTG_STATE_A_PERIPHERAL: 574 /* We also come here if the cable is removed, since 575 * this silicon doesn't report ID-no-longer-grounded. 576 * 577 * We depend on T(a_wait_bcon) to shut us down, and 578 * hope users don't do anything dicey during this 579 * undesired detour through A_WAIT_BCON. 580 */ 581 musb_hnp_stop(musb); 582 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 583 musb_root_disconnect(musb); 584 musb_platform_try_idle(musb, jiffies 585 + msecs_to_jiffies(musb->a_wait_bcon 586 ? : OTG_TIME_A_WAIT_BCON)); 587 588 break; 589#endif 590 case OTG_STATE_B_IDLE: 591 if (!musb->is_active) 592 break; 593 case OTG_STATE_B_PERIPHERAL: 594 musb_g_suspend(musb); 595 musb->is_active = is_otg_enabled(musb) 596 && musb->xceiv->gadget->b_hnp_enable; 597 if (musb->is_active) { 598#ifdef CONFIG_USB_MUSB_OTG 599 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 600 DBG(1, "HNP: Setting timer for b_ase0_brst\n"); 601 mod_timer(&musb->otg_timer, jiffies 602 + msecs_to_jiffies( 603 OTG_TIME_B_ASE0_BRST)); 604#endif 605 } 606 break; 607 case OTG_STATE_A_WAIT_BCON: 608 if (musb->a_wait_bcon != 0) 609 musb_platform_try_idle(musb, jiffies 610 + msecs_to_jiffies(musb->a_wait_bcon)); 611 break; 612 case OTG_STATE_A_HOST: 613 musb->xceiv->state = OTG_STATE_A_SUSPEND; 614 musb->is_active = is_otg_enabled(musb) 615 && musb->xceiv->host->b_hnp_enable; 616 break; 617 case OTG_STATE_B_HOST: 618 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 619 DBG(1, "REVISIT: SUSPEND as B_HOST\n"); 620 break; 621 default: 622 /* "should not happen" */ 623 musb->is_active = 0; 624 break; 625 } 626 } 627 628 if (int_usb & MUSB_INTR_CONNECT) { 629 struct usb_hcd *hcd = musb_to_hcd(musb); 630 void __iomem *mbase = musb->mregs; 631 632 handled = IRQ_HANDLED; 633 musb->is_active = 1; 634 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); 635 636 musb->ep0_stage = MUSB_EP0_START; 637 638#ifdef CONFIG_USB_MUSB_OTG 639 /* flush endpoints when transitioning from Device Mode */ 640 if (is_peripheral_active(musb)) { 641 /* REVISIT HNP; just force disconnect */ 642 } 643 musb_writew(mbase, MUSB_INTRTXE, musb->epmask); 644 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe); 645 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7); 646#endif 647 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 648 |USB_PORT_STAT_HIGH_SPEED 649 |USB_PORT_STAT_ENABLE 650 ); 651 musb->port1_status |= USB_PORT_STAT_CONNECTION 652 |(USB_PORT_STAT_C_CONNECTION << 16); 653 654 /* high vs full speed is just a guess until after reset */ 655 if (devctl & MUSB_DEVCTL_LSDEV) 656 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 657 658 /* indicate new connection to OTG machine */ 659 switch (musb->xceiv->state) { 660 case OTG_STATE_B_PERIPHERAL: 661 if (int_usb & MUSB_INTR_SUSPEND) { 662 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); 663 int_usb &= ~MUSB_INTR_SUSPEND; 664 goto b_host; 665 } else 666 DBG(1, "CONNECT as b_peripheral???\n"); 667 break; 668 case OTG_STATE_B_WAIT_ACON: 669 DBG(1, "HNP: CONNECT, now b_host\n"); 670b_host: 671 musb->xceiv->state = OTG_STATE_B_HOST; 672 hcd->self.is_b_host = 1; 673 musb->ignore_disconnect = 0; 674 del_timer(&musb->otg_timer); 675 break; 676 default: 677 if ((devctl & MUSB_DEVCTL_VBUS) 678 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 679 musb->xceiv->state = OTG_STATE_A_HOST; 680 hcd->self.is_b_host = 0; 681 } 682 break; 683 } 684 685 /* poke the root hub */ 686 MUSB_HST_MODE(musb); 687 if (hcd->status_urb) 688 usb_hcd_poll_rh_status(hcd); 689 else 690 usb_hcd_resume_root_hub(hcd); 691 692 DBG(1, "CONNECT (%s) devctl %02x\n", 693 otg_state_string(musb), devctl); 694 } 695#endif /* CONFIG_USB_MUSB_HDRC_HCD */ 696 697 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 698 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n", 699 otg_state_string(musb), 700 MUSB_MODE(musb), devctl); 701 handled = IRQ_HANDLED; 702 703 switch (musb->xceiv->state) { 704#ifdef CONFIG_USB_MUSB_HDRC_HCD 705 case OTG_STATE_A_HOST: 706 case OTG_STATE_A_SUSPEND: 707 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 708 musb_root_disconnect(musb); 709 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 710 musb_platform_try_idle(musb, jiffies 711 + msecs_to_jiffies(musb->a_wait_bcon)); 712 break; 713#endif /* HOST */ 714#ifdef CONFIG_USB_MUSB_OTG 715 case OTG_STATE_B_HOST: 716 /* REVISIT this behaves for "real disconnect" 717 * cases; make sure the other transitions from 718 * from B_HOST act right too. The B_HOST code 719 * in hnp_stop() is currently not used... 720 */ 721 musb_root_disconnect(musb); 722 musb_to_hcd(musb)->self.is_b_host = 0; 723 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 724 MUSB_DEV_MODE(musb); 725 musb_g_disconnect(musb); 726 break; 727 case OTG_STATE_A_PERIPHERAL: 728 musb_hnp_stop(musb); 729 musb_root_disconnect(musb); 730 /* FALLTHROUGH */ 731 case OTG_STATE_B_WAIT_ACON: 732 /* FALLTHROUGH */ 733#endif /* OTG */ 734#ifdef CONFIG_USB_GADGET_MUSB_HDRC 735 case OTG_STATE_B_PERIPHERAL: 736 case OTG_STATE_B_IDLE: 737 musb_g_disconnect(musb); 738 break; 739#endif /* GADGET */ 740 default: 741 WARNING("unhandled DISCONNECT transition (%s)\n", 742 otg_state_string(musb)); 743 break; 744 } 745 } 746 747 /* mentor saves a bit: bus reset and babble share the same irq. 748 * only host sees babble; only peripheral sees bus reset. 749 */ 750 if (int_usb & MUSB_INTR_RESET) { 751 handled = IRQ_HANDLED; 752 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 753 /* 754 * Looks like non-HS BABBLE can be ignored, but 755 * HS BABBLE is an error condition. For HS the solution 756 * is to avoid babble in the first place and fix what 757 * caused BABBLE. When HS BABBLE happens we can only 758 * stop the session. 759 */ 760 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 761 DBG(1, "BABBLE devctl: %02x\n", devctl); 762 else { 763 ERR("Stopping host session -- babble\n"); 764 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 765 } 766 } else if (is_peripheral_capable()) { 767 DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); 768 switch (musb->xceiv->state) { 769#ifdef CONFIG_USB_OTG 770 case OTG_STATE_A_SUSPEND: 771 /* We need to ignore disconnect on suspend 772 * otherwise tusb 2.0 won't reconnect after a 773 * power cycle, which breaks otg compliance. 774 */ 775 musb->ignore_disconnect = 1; 776 musb_g_reset(musb); 777 /* FALLTHROUGH */ 778 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 779 /* never use invalid T(a_wait_bcon) */ 780 DBG(1, "HNP: in %s, %d msec timeout\n", 781 otg_state_string(musb), 782 TA_WAIT_BCON(musb)); 783 mod_timer(&musb->otg_timer, jiffies 784 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 785 break; 786 case OTG_STATE_A_PERIPHERAL: 787 musb->ignore_disconnect = 0; 788 del_timer(&musb->otg_timer); 789 musb_g_reset(musb); 790 break; 791 case OTG_STATE_B_WAIT_ACON: 792 DBG(1, "HNP: RESET (%s), to b_peripheral\n", 793 otg_state_string(musb)); 794 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 795 musb_g_reset(musb); 796 break; 797#endif 798 case OTG_STATE_B_IDLE: 799 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 800 /* FALLTHROUGH */ 801 case OTG_STATE_B_PERIPHERAL: 802 musb_g_reset(musb); 803 break; 804 default: 805 DBG(1, "Unhandled BUS RESET as %s\n", 806 otg_state_string(musb)); 807 } 808 } 809 } 810 811#if 0 812/* REVISIT ... this would be for multiplexing periodic endpoints, or 813 * supporting transfer phasing to prevent exceeding ISO bandwidth 814 * limits of a given frame or microframe. 815 * 816 * It's not needed for peripheral side, which dedicates endpoints; 817 * though it _might_ use SOF irqs for other purposes. 818 * 819 * And it's not currently needed for host side, which also dedicates 820 * endpoints, relies on TX/RX interval registers, and isn't claimed 821 * to support ISO transfers yet. 822 */ 823 if (int_usb & MUSB_INTR_SOF) { 824 void __iomem *mbase = musb->mregs; 825 struct musb_hw_ep *ep; 826 u8 epnum; 827 u16 frame; 828 829 DBG(6, "START_OF_FRAME\n"); 830 handled = IRQ_HANDLED; 831 832 /* start any periodic Tx transfers waiting for current frame */ 833 frame = musb_readw(mbase, MUSB_FRAME); 834 ep = musb->endpoints; 835 for (epnum = 1; (epnum < musb->nr_endpoints) 836 && (musb->epmask >= (1 << epnum)); 837 epnum++, ep++) { 838 /* 839 * FIXME handle framecounter wraps (12 bits) 840 * eliminate duplicated StartUrb logic 841 */ 842 if (ep->dwWaitFrame >= frame) { 843 ep->dwWaitFrame = 0; 844 pr_debug("SOF --> periodic TX%s on %d\n", 845 ep->tx_channel ? " DMA" : "", 846 epnum); 847 if (!ep->tx_channel) 848 musb_h_tx_start(musb, epnum); 849 else 850 cppi_hostdma_start(musb, epnum); 851 } 852 } /* end of for loop */ 853 } 854#endif 855 856 schedule_work(&musb->irq_work); 857 858 return handled; 859} 860 861/*-------------------------------------------------------------------------*/ 862 863/* 864* Program the HDRC to start (enable interrupts, dma, etc.). 865*/ 866void musb_start(struct musb *musb) 867{ 868 void __iomem *regs = musb->mregs; 869 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 870 871 DBG(2, "<== devctl %02x\n", devctl); 872 873 /* Set INT enable registers, enable interrupts */ 874 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 875 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 876 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 877 878 musb_writeb(regs, MUSB_TESTMODE, 0); 879 880 /* put into basic highspeed mode and start session */ 881 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 882 | MUSB_POWER_SOFTCONN 883 | MUSB_POWER_HSENAB 884 /* ENSUSPEND wedges tusb */ 885 /* | MUSB_POWER_ENSUSPEND */ 886 ); 887 888 musb->is_active = 0; 889 devctl = musb_readb(regs, MUSB_DEVCTL); 890 devctl &= ~MUSB_DEVCTL_SESSION; 891 892 if (is_otg_enabled(musb)) { 893 /* session started after: 894 * (a) ID-grounded irq, host mode; 895 * (b) vbus present/connect IRQ, peripheral mode; 896 * (c) peripheral initiates, using SRP 897 */ 898 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 899 musb->is_active = 1; 900 else 901 devctl |= MUSB_DEVCTL_SESSION; 902 903 } else if (is_host_enabled(musb)) { 904 /* assume ID pin is hard-wired to ground */ 905 devctl |= MUSB_DEVCTL_SESSION; 906 907 } else /* peripheral is enabled */ { 908 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 909 musb->is_active = 1; 910 } 911 musb_platform_enable(musb); 912 musb_writeb(regs, MUSB_DEVCTL, devctl); 913} 914 915 916static void musb_generic_disable(struct musb *musb) 917{ 918 void __iomem *mbase = musb->mregs; 919 u16 temp; 920 921 /* disable interrupts */ 922 musb_writeb(mbase, MUSB_INTRUSBE, 0); 923 musb_writew(mbase, MUSB_INTRTXE, 0); 924 musb_writew(mbase, MUSB_INTRRXE, 0); 925 926 /* off */ 927 musb_writeb(mbase, MUSB_DEVCTL, 0); 928 929 /* flush pending interrupts */ 930 temp = musb_readb(mbase, MUSB_INTRUSB); 931 temp = musb_readw(mbase, MUSB_INTRTX); 932 temp = musb_readw(mbase, MUSB_INTRRX); 933 934} 935 936/* 937 * Make the HDRC stop (disable interrupts, etc.); 938 * reversible by musb_start 939 * called on gadget driver unregister 940 * with controller locked, irqs blocked 941 * acts as a NOP unless some role activated the hardware 942 */ 943void musb_stop(struct musb *musb) 944{ 945 /* stop IRQs, timers, ... */ 946 musb_platform_disable(musb); 947 musb_generic_disable(musb); 948 DBG(3, "HDRC disabled\n"); 949 950 /* FIXME 951 * - mark host and/or peripheral drivers unusable/inactive 952 * - disable DMA (and enable it in HdrcStart) 953 * - make sure we can musb_start() after musb_stop(); with 954 * OTG mode, gadget driver module rmmod/modprobe cycles that 955 * - ... 956 */ 957 musb_platform_try_idle(musb, 0); 958} 959 960static void musb_shutdown(struct platform_device *pdev) 961{ 962 struct musb *musb = dev_to_musb(&pdev->dev); 963 unsigned long flags; 964 965 spin_lock_irqsave(&musb->lock, flags); 966 musb_platform_disable(musb); 967 musb_generic_disable(musb); 968 if (musb->clock) 969 clk_put(musb->clock); 970 spin_unlock_irqrestore(&musb->lock, flags); 971 972 /* FIXME power down */ 973} 974 975 976/*-------------------------------------------------------------------------*/ 977 978/* 979 * The silicon either has hard-wired endpoint configurations, or else 980 * "dynamic fifo" sizing. The driver has support for both, though at this 981 * writing only the dynamic sizing is very well tested. Since we switched 982 * away from compile-time hardware parameters, we can no longer rely on 983 * dead code elimination to leave only the relevant one in the object file. 984 * 985 * We don't currently use dynamic fifo setup capability to do anything 986 * more than selecting one of a bunch of predefined configurations. 987 */ 988#if defined(CONFIG_USB_TUSB6010) || \ 989 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) 990static ushort __initdata fifo_mode = 4; 991#else 992static ushort __initdata fifo_mode = 2; 993#endif 994 995/* "modprobe ... fifo_mode=1" etc */ 996module_param(fifo_mode, ushort, 0); 997MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 998 999 1000enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed)); 1001enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed)); 1002 1003struct fifo_cfg { 1004 u8 hw_ep_num; 1005 enum fifo_style style; 1006 enum buf_mode mode; 1007 u16 maxpacket; 1008}; 1009 1010/* 1011 * tables defining fifo_mode values. define more if you like. 1012 * for host side, make sure both halves of ep1 are set up. 1013 */ 1014 1015/* mode 0 - fits in 2KB */ 1016static struct fifo_cfg __initdata mode_0_cfg[] = { 1017{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1018{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1019{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1020{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1021{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1022}; 1023 1024/* mode 1 - fits in 4KB */ 1025static struct fifo_cfg __initdata mode_1_cfg[] = { 1026{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1027{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1028{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1029{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1030{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1031}; 1032 1033/* mode 2 - fits in 4KB */ 1034static struct fifo_cfg __initdata mode_2_cfg[] = { 1035{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1036{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1037{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1038{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1039{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1040{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1041}; 1042 1043/* mode 3 - fits in 4KB */ 1044static struct fifo_cfg __initdata mode_3_cfg[] = { 1045{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1046{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1047{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1048{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1049{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1050{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1051}; 1052 1053/* mode 4 - fits in 16KB */ 1054static struct fifo_cfg __initdata mode_4_cfg[] = { 1055{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1056{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1057{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1058{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1059{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1060{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1061{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1062{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1063{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1064{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1065{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1066{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1067{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1068{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1069{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1070{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1071{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1072{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1073{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1074{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1075{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1076{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1077{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1078{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1079{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1080{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1081{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1082}; 1083 1084/* mode 5 - fits in 8KB */ 1085static struct fifo_cfg __initdata mode_5_cfg[] = { 1086{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1087{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1088{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1089{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1090{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1091{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1092{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1093{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1094{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1095{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1096{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1097{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1098{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1099{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1100{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1101{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1102{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1103{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1104{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1105{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1106{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1107{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1108{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1109{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1110{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1111{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1112{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1113}; 1114 1115/* 1116 * configure a fifo; for non-shared endpoints, this may be called 1117 * once for a tx fifo and once for an rx fifo. 1118 * 1119 * returns negative errno or offset for next fifo. 1120 */ 1121static int __init 1122fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1123 const struct fifo_cfg *cfg, u16 offset) 1124{ 1125 void __iomem *mbase = musb->mregs; 1126 int size = 0; 1127 u16 maxpacket = cfg->maxpacket; 1128 u16 c_off = offset >> 3; 1129 u8 c_size; 1130 1131 /* expect hw_ep has already been zero-initialized */ 1132 1133 size = ffs(max(maxpacket, (u16) 8)) - 1; 1134 maxpacket = 1 << size; 1135 1136 c_size = size - 3; 1137 if (cfg->mode == BUF_DOUBLE) { 1138 if ((offset + (maxpacket << 1)) > 1139 (1 << (musb->config->ram_bits + 2))) 1140 return -EMSGSIZE; 1141 c_size |= MUSB_FIFOSZ_DPB; 1142 } else { 1143 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1144 return -EMSGSIZE; 1145 } 1146 1147 /* configure the FIFO */ 1148 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1149 1150#ifdef CONFIG_USB_MUSB_HDRC_HCD 1151 /* EP0 reserved endpoint for control, bidirectional; 1152 * EP1 reserved for bulk, two unidirection halves. 1153 */ 1154 if (hw_ep->epnum == 1) 1155 musb->bulk_ep = hw_ep; 1156 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1157#endif 1158 switch (cfg->style) { 1159 case FIFO_TX: 1160 musb_write_txfifosz(mbase, c_size); 1161 musb_write_txfifoadd(mbase, c_off); 1162 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1163 hw_ep->max_packet_sz_tx = maxpacket; 1164 break; 1165 case FIFO_RX: 1166 musb_write_rxfifosz(mbase, c_size); 1167 musb_write_rxfifoadd(mbase, c_off); 1168 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1169 hw_ep->max_packet_sz_rx = maxpacket; 1170 break; 1171 case FIFO_RXTX: 1172 musb_write_txfifosz(mbase, c_size); 1173 musb_write_txfifoadd(mbase, c_off); 1174 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1175 hw_ep->max_packet_sz_rx = maxpacket; 1176 1177 musb_write_rxfifosz(mbase, c_size); 1178 musb_write_rxfifoadd(mbase, c_off); 1179 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1180 hw_ep->max_packet_sz_tx = maxpacket; 1181 1182 hw_ep->is_shared_fifo = true; 1183 break; 1184 } 1185 1186 /* NOTE rx and tx endpoint irqs aren't managed separately, 1187 * which happens to be ok 1188 */ 1189 musb->epmask |= (1 << hw_ep->epnum); 1190 1191 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1192} 1193 1194static struct fifo_cfg __initdata ep0_cfg = { 1195 .style = FIFO_RXTX, .maxpacket = 64, 1196}; 1197 1198static int __init ep_config_from_table(struct musb *musb) 1199{ 1200 const struct fifo_cfg *cfg; 1201 unsigned i, n; 1202 int offset; 1203 struct musb_hw_ep *hw_ep = musb->endpoints; 1204 1205 switch (fifo_mode) { 1206 default: 1207 fifo_mode = 0; 1208 /* FALLTHROUGH */ 1209 case 0: 1210 cfg = mode_0_cfg; 1211 n = ARRAY_SIZE(mode_0_cfg); 1212 break; 1213 case 1: 1214 cfg = mode_1_cfg; 1215 n = ARRAY_SIZE(mode_1_cfg); 1216 break; 1217 case 2: 1218 cfg = mode_2_cfg; 1219 n = ARRAY_SIZE(mode_2_cfg); 1220 break; 1221 case 3: 1222 cfg = mode_3_cfg; 1223 n = ARRAY_SIZE(mode_3_cfg); 1224 break; 1225 case 4: 1226 cfg = mode_4_cfg; 1227 n = ARRAY_SIZE(mode_4_cfg); 1228 break; 1229 case 5: 1230 cfg = mode_5_cfg; 1231 n = ARRAY_SIZE(mode_5_cfg); 1232 break; 1233 } 1234 1235 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1236 musb_driver_name, fifo_mode); 1237 1238 1239 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1240 /* assert(offset > 0) */ 1241 1242 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1243 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1244 */ 1245 1246 for (i = 0; i < n; i++) { 1247 u8 epn = cfg->hw_ep_num; 1248 1249 if (epn >= musb->config->num_eps) { 1250 pr_debug("%s: invalid ep %d\n", 1251 musb_driver_name, epn); 1252 return -EINVAL; 1253 } 1254 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1255 if (offset < 0) { 1256 pr_debug("%s: mem overrun, ep %d\n", 1257 musb_driver_name, epn); 1258 return -EINVAL; 1259 } 1260 epn++; 1261 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1262 } 1263 1264 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1265 musb_driver_name, 1266 n + 1, musb->config->num_eps * 2 - 1, 1267 offset, (1 << (musb->config->ram_bits + 2))); 1268 1269#ifdef CONFIG_USB_MUSB_HDRC_HCD 1270 if (!musb->bulk_ep) { 1271 pr_debug("%s: missing bulk\n", musb_driver_name); 1272 return -EINVAL; 1273 } 1274#endif 1275 1276 return 0; 1277} 1278 1279 1280/* 1281 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1282 * @param musb the controller 1283 */ 1284static int __init ep_config_from_hw(struct musb *musb) 1285{ 1286 u8 epnum = 0; 1287 struct musb_hw_ep *hw_ep; 1288 void *mbase = musb->mregs; 1289 int ret = 0; 1290 1291 DBG(2, "<== static silicon ep config\n"); 1292 1293 /* FIXME pick up ep0 maxpacket size */ 1294 1295 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1296 musb_ep_select(mbase, epnum); 1297 hw_ep = musb->endpoints + epnum; 1298 1299 ret = musb_read_fifosize(musb, hw_ep, epnum); 1300 if (ret < 0) 1301 break; 1302 1303 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1304 1305#ifdef CONFIG_USB_MUSB_HDRC_HCD 1306 /* pick an RX/TX endpoint for bulk */ 1307 if (hw_ep->max_packet_sz_tx < 512 1308 || hw_ep->max_packet_sz_rx < 512) 1309 continue; 1310 1311 /* REVISIT: this algorithm is lazy, we should at least 1312 * try to pick a double buffered endpoint. 1313 */ 1314 if (musb->bulk_ep) 1315 continue; 1316 musb->bulk_ep = hw_ep; 1317#endif 1318 } 1319 1320#ifdef CONFIG_USB_MUSB_HDRC_HCD 1321 if (!musb->bulk_ep) { 1322 pr_debug("%s: missing bulk\n", musb_driver_name); 1323 return -EINVAL; 1324 } 1325#endif 1326 1327 return 0; 1328} 1329 1330enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1331 1332/* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1333 * configure endpoints, or take their config from silicon 1334 */ 1335static int __init musb_core_init(u16 musb_type, struct musb *musb) 1336{ 1337 u8 reg; 1338 char *type; 1339 char aInfo[90], aRevision[32], aDate[12]; 1340 void __iomem *mbase = musb->mregs; 1341 int status = 0; 1342 int i; 1343 1344 /* log core options (read using indexed model) */ 1345 reg = musb_read_configdata(mbase); 1346 1347 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1348 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1349 strcat(aInfo, ", dyn FIFOs"); 1350 musb->dyn_fifo = true; 1351 } 1352 if (reg & MUSB_CONFIGDATA_MPRXE) { 1353 strcat(aInfo, ", bulk combine"); 1354 musb->bulk_combine = true; 1355 } 1356 if (reg & MUSB_CONFIGDATA_MPTXE) { 1357 strcat(aInfo, ", bulk split"); 1358 musb->bulk_split = true; 1359 } 1360 if (reg & MUSB_CONFIGDATA_HBRXE) { 1361 strcat(aInfo, ", HB-ISO Rx"); 1362 musb->hb_iso_rx = true; 1363 } 1364 if (reg & MUSB_CONFIGDATA_HBTXE) { 1365 strcat(aInfo, ", HB-ISO Tx"); 1366 musb->hb_iso_tx = true; 1367 } 1368 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1369 strcat(aInfo, ", SoftConn"); 1370 1371 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1372 musb_driver_name, reg, aInfo); 1373 1374 aDate[0] = 0; 1375 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1376 musb->is_multipoint = 1; 1377 type = "M"; 1378 } else { 1379 musb->is_multipoint = 0; 1380 type = ""; 1381#ifdef CONFIG_USB_MUSB_HDRC_HCD 1382#ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1383 printk(KERN_ERR 1384 "%s: kernel must blacklist external hubs\n", 1385 musb_driver_name); 1386#endif 1387#endif 1388 } 1389 1390 /* log release info */ 1391 musb->hwvers = musb_read_hwvers(mbase); 1392 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1393 MUSB_HWVERS_MINOR(musb->hwvers), 1394 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1395 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1396 musb_driver_name, type, aRevision, aDate); 1397 1398 /* configure ep0 */ 1399 musb_configure_ep0(musb); 1400 1401 /* discover endpoint configuration */ 1402 musb->nr_endpoints = 1; 1403 musb->epmask = 1; 1404 1405 if (musb->dyn_fifo) 1406 status = ep_config_from_table(musb); 1407 else 1408 status = ep_config_from_hw(musb); 1409 1410 if (status < 0) 1411 return status; 1412 1413 /* finish init, and print endpoint config */ 1414 for (i = 0; i < musb->nr_endpoints; i++) { 1415 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1416 1417 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1418#ifdef CONFIG_USB_TUSB6010 1419 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1420 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1421 hw_ep->fifo_sync_va = 1422 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1423 1424 if (i == 0) 1425 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1426 else 1427 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1428#endif 1429 1430 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1431#ifdef CONFIG_USB_MUSB_HDRC_HCD 1432 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1433 hw_ep->rx_reinit = 1; 1434 hw_ep->tx_reinit = 1; 1435#endif 1436 1437 if (hw_ep->max_packet_sz_tx) { 1438 DBG(1, 1439 "%s: hw_ep %d%s, %smax %d\n", 1440 musb_driver_name, i, 1441 hw_ep->is_shared_fifo ? "shared" : "tx", 1442 hw_ep->tx_double_buffered 1443 ? "doublebuffer, " : "", 1444 hw_ep->max_packet_sz_tx); 1445 } 1446 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1447 DBG(1, 1448 "%s: hw_ep %d%s, %smax %d\n", 1449 musb_driver_name, i, 1450 "rx", 1451 hw_ep->rx_double_buffered 1452 ? "doublebuffer, " : "", 1453 hw_ep->max_packet_sz_rx); 1454 } 1455 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1456 DBG(1, "hw_ep %d not configured\n", i); 1457 } 1458 1459 return 0; 1460} 1461 1462/*-------------------------------------------------------------------------*/ 1463 1464#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) 1465 1466static irqreturn_t generic_interrupt(int irq, void *__hci) 1467{ 1468 unsigned long flags; 1469 irqreturn_t retval = IRQ_NONE; 1470 struct musb *musb = __hci; 1471 1472 spin_lock_irqsave(&musb->lock, flags); 1473 1474 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1475 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1476 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1477 1478 if (musb->int_usb || musb->int_tx || musb->int_rx) 1479 retval = musb_interrupt(musb); 1480 1481 spin_unlock_irqrestore(&musb->lock, flags); 1482 1483 return retval; 1484} 1485 1486#else 1487#define generic_interrupt NULL 1488#endif 1489 1490/* 1491 * handle all the irqs defined by the HDRC core. for now we expect: other 1492 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1493 * will be assigned, and the irq will already have been acked. 1494 * 1495 * called in irq context with spinlock held, irqs blocked 1496 */ 1497irqreturn_t musb_interrupt(struct musb *musb) 1498{ 1499 irqreturn_t retval = IRQ_NONE; 1500 u8 devctl, power; 1501 int ep_num; 1502 u32 reg; 1503 1504 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1505 power = musb_readb(musb->mregs, MUSB_POWER); 1506 1507 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n", 1508 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1509 musb->int_usb, musb->int_tx, musb->int_rx); 1510 1511#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1512 if (is_otg_enabled(musb) || is_peripheral_enabled(musb)) 1513 if (!musb->gadget_driver) { 1514 DBG(5, "No gadget driver loaded\n"); 1515 return IRQ_HANDLED; 1516 } 1517#endif 1518 1519 /* the core can interrupt us for multiple reasons; docs have 1520 * a generic interrupt flowchart to follow 1521 */ 1522 if (musb->int_usb & STAGE0_MASK) 1523 retval |= musb_stage0_irq(musb, musb->int_usb, 1524 devctl, power); 1525 1526 /* "stage 1" is handling endpoint irqs */ 1527 1528 /* handle endpoint 0 first */ 1529 if (musb->int_tx & 1) { 1530 if (devctl & MUSB_DEVCTL_HM) 1531 retval |= musb_h_ep0_irq(musb); 1532 else 1533 retval |= musb_g_ep0_irq(musb); 1534 } 1535 1536 /* RX on endpoints 1-15 */ 1537 reg = musb->int_rx >> 1; 1538 ep_num = 1; 1539 while (reg) { 1540 if (reg & 1) { 1541 /* musb_ep_select(musb->mregs, ep_num); */ 1542 /* REVISIT just retval = ep->rx_irq(...) */ 1543 retval = IRQ_HANDLED; 1544 if (devctl & MUSB_DEVCTL_HM) { 1545 if (is_host_capable()) 1546 musb_host_rx(musb, ep_num); 1547 } else { 1548 if (is_peripheral_capable()) 1549 musb_g_rx(musb, ep_num); 1550 } 1551 } 1552 1553 reg >>= 1; 1554 ep_num++; 1555 } 1556 1557 /* TX on endpoints 1-15 */ 1558 reg = musb->int_tx >> 1; 1559 ep_num = 1; 1560 while (reg) { 1561 if (reg & 1) { 1562 /* musb_ep_select(musb->mregs, ep_num); */ 1563 /* REVISIT just retval |= ep->tx_irq(...) */ 1564 retval = IRQ_HANDLED; 1565 if (devctl & MUSB_DEVCTL_HM) { 1566 if (is_host_capable()) 1567 musb_host_tx(musb, ep_num); 1568 } else { 1569 if (is_peripheral_capable()) 1570 musb_g_tx(musb, ep_num); 1571 } 1572 } 1573 reg >>= 1; 1574 ep_num++; 1575 } 1576 1577 return retval; 1578} 1579 1580 1581#ifndef CONFIG_MUSB_PIO_ONLY 1582static int __initdata use_dma = 1; 1583 1584/* "modprobe ... use_dma=0" etc */ 1585module_param(use_dma, bool, 0); 1586MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1587 1588void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1589{ 1590 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1591 1592 /* called with controller lock already held */ 1593 1594 if (!epnum) { 1595#ifndef CONFIG_USB_TUSB_OMAP_DMA 1596 if (!is_cppi_enabled()) { 1597 /* endpoint 0 */ 1598 if (devctl & MUSB_DEVCTL_HM) 1599 musb_h_ep0_irq(musb); 1600 else 1601 musb_g_ep0_irq(musb); 1602 } 1603#endif 1604 } else { 1605 /* endpoints 1..15 */ 1606 if (transmit) { 1607 if (devctl & MUSB_DEVCTL_HM) { 1608 if (is_host_capable()) 1609 musb_host_tx(musb, epnum); 1610 } else { 1611 if (is_peripheral_capable()) 1612 musb_g_tx(musb, epnum); 1613 } 1614 } else { 1615 /* receive */ 1616 if (devctl & MUSB_DEVCTL_HM) { 1617 if (is_host_capable()) 1618 musb_host_rx(musb, epnum); 1619 } else { 1620 if (is_peripheral_capable()) 1621 musb_g_rx(musb, epnum); 1622 } 1623 } 1624 } 1625} 1626 1627#else 1628#define use_dma 0 1629#endif 1630 1631/*-------------------------------------------------------------------------*/ 1632 1633#ifdef CONFIG_SYSFS 1634 1635static ssize_t 1636musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1637{ 1638 struct musb *musb = dev_to_musb(dev); 1639 unsigned long flags; 1640 int ret = -EINVAL; 1641 1642 spin_lock_irqsave(&musb->lock, flags); 1643 ret = sprintf(buf, "%s\n", otg_state_string(musb)); 1644 spin_unlock_irqrestore(&musb->lock, flags); 1645 1646 return ret; 1647} 1648 1649static ssize_t 1650musb_mode_store(struct device *dev, struct device_attribute *attr, 1651 const char *buf, size_t n) 1652{ 1653 struct musb *musb = dev_to_musb(dev); 1654 unsigned long flags; 1655 int status; 1656 1657 spin_lock_irqsave(&musb->lock, flags); 1658 if (sysfs_streq(buf, "host")) 1659 status = musb_platform_set_mode(musb, MUSB_HOST); 1660 else if (sysfs_streq(buf, "peripheral")) 1661 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1662 else if (sysfs_streq(buf, "otg")) 1663 status = musb_platform_set_mode(musb, MUSB_OTG); 1664 else 1665 status = -EINVAL; 1666 spin_unlock_irqrestore(&musb->lock, flags); 1667 1668 return (status == 0) ? n : status; 1669} 1670static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1671 1672static ssize_t 1673musb_vbus_store(struct device *dev, struct device_attribute *attr, 1674 const char *buf, size_t n) 1675{ 1676 struct musb *musb = dev_to_musb(dev); 1677 unsigned long flags; 1678 unsigned long val; 1679 1680 if (sscanf(buf, "%lu", &val) < 1) { 1681 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1682 return -EINVAL; 1683 } 1684 1685 spin_lock_irqsave(&musb->lock, flags); 1686 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1687 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1688 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1689 musb->is_active = 0; 1690 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1691 spin_unlock_irqrestore(&musb->lock, flags); 1692 1693 return n; 1694} 1695 1696static ssize_t 1697musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1698{ 1699 struct musb *musb = dev_to_musb(dev); 1700 unsigned long flags; 1701 unsigned long val; 1702 int vbus; 1703 1704 spin_lock_irqsave(&musb->lock, flags); 1705 val = musb->a_wait_bcon; 1706 /* FIXME get_vbus_status() is normally #defined as false... 1707 * and is effectively TUSB-specific. 1708 */ 1709 vbus = musb_platform_get_vbus_status(musb); 1710 spin_unlock_irqrestore(&musb->lock, flags); 1711 1712 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1713 vbus ? "on" : "off", val); 1714} 1715static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1716 1717#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1718 1719/* Gadget drivers can't know that a host is connected so they might want 1720 * to start SRP, but users can. This allows userspace to trigger SRP. 1721 */ 1722static ssize_t 1723musb_srp_store(struct device *dev, struct device_attribute *attr, 1724 const char *buf, size_t n) 1725{ 1726 struct musb *musb = dev_to_musb(dev); 1727 unsigned short srp; 1728 1729 if (sscanf(buf, "%hu", &srp) != 1 1730 || (srp != 1)) { 1731 dev_err(dev, "SRP: Value must be 1\n"); 1732 return -EINVAL; 1733 } 1734 1735 if (srp == 1) 1736 musb_g_wakeup(musb); 1737 1738 return n; 1739} 1740static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1741 1742#endif /* CONFIG_USB_GADGET_MUSB_HDRC */ 1743 1744static struct attribute *musb_attributes[] = { 1745 &dev_attr_mode.attr, 1746 &dev_attr_vbus.attr, 1747#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1748 &dev_attr_srp.attr, 1749#endif 1750 NULL 1751}; 1752 1753static const struct attribute_group musb_attr_group = { 1754 .attrs = musb_attributes, 1755}; 1756 1757#endif /* sysfs */ 1758 1759/* Only used to provide driver mode change events */ 1760static void musb_irq_work(struct work_struct *data) 1761{ 1762 struct musb *musb = container_of(data, struct musb, irq_work); 1763 static int old_state; 1764 1765 if (musb->xceiv->state != old_state) { 1766 old_state = musb->xceiv->state; 1767 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1768 } 1769} 1770 1771/* -------------------------------------------------------------------------- 1772 * Init support 1773 */ 1774 1775static struct musb *__init 1776allocate_instance(struct device *dev, 1777 struct musb_hdrc_config *config, void __iomem *mbase) 1778{ 1779 struct musb *musb; 1780 struct musb_hw_ep *ep; 1781 int epnum; 1782#ifdef CONFIG_USB_MUSB_HDRC_HCD 1783 struct usb_hcd *hcd; 1784 1785 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1786 if (!hcd) 1787 return NULL; 1788 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1789 1790 musb = hcd_to_musb(hcd); 1791 INIT_LIST_HEAD(&musb->control); 1792 INIT_LIST_HEAD(&musb->in_bulk); 1793 INIT_LIST_HEAD(&musb->out_bulk); 1794 1795 hcd->uses_new_polling = 1; 1796 1797 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1798 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1799#else 1800 musb = kzalloc(sizeof *musb, GFP_KERNEL); 1801 if (!musb) 1802 return NULL; 1803 dev_set_drvdata(dev, musb); 1804 1805#endif 1806 1807 musb->mregs = mbase; 1808 musb->ctrl_base = mbase; 1809 musb->nIrq = -ENODEV; 1810 musb->config = config; 1811 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1812 for (epnum = 0, ep = musb->endpoints; 1813 epnum < musb->config->num_eps; 1814 epnum++, ep++) { 1815 ep->musb = musb; 1816 ep->epnum = epnum; 1817 } 1818 1819 musb->controller = dev; 1820 return musb; 1821} 1822 1823static void musb_free(struct musb *musb) 1824{ 1825 /* this has multiple entry modes. it handles fault cleanup after 1826 * probe(), where things may be partially set up, as well as rmmod 1827 * cleanup after everything's been de-activated. 1828 */ 1829 1830#ifdef CONFIG_SYSFS 1831 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1832#endif 1833 1834#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1835 musb_gadget_cleanup(musb); 1836#endif 1837 1838 if (musb->nIrq >= 0) { 1839 if (musb->irq_wake) 1840 disable_irq_wake(musb->nIrq); 1841 free_irq(musb->nIrq, musb); 1842 } 1843 if (is_dma_capable() && musb->dma_controller) { 1844 struct dma_controller *c = musb->dma_controller; 1845 1846 (void) c->stop(c); 1847 dma_controller_destroy(c); 1848 } 1849 1850#ifdef CONFIG_USB_MUSB_OTG 1851 put_device(musb->xceiv->dev); 1852#endif 1853 1854#ifdef CONFIG_USB_MUSB_HDRC_HCD 1855 usb_put_hcd(musb_to_hcd(musb)); 1856#else 1857 kfree(musb); 1858#endif 1859} 1860 1861/* 1862 * Perform generic per-controller initialization. 1863 * 1864 * @pDevice: the controller (already clocked, etc) 1865 * @nIrq: irq 1866 * @mregs: virtual address of controller registers, 1867 * not yet corrected for platform-specific offsets 1868 */ 1869static int __init 1870musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1871{ 1872 int status; 1873 struct musb *musb; 1874 struct musb_hdrc_platform_data *plat = dev->platform_data; 1875 1876 /* The driver might handle more features than the board; OK. 1877 * Fail when the board needs a feature that's not enabled. 1878 */ 1879 if (!plat) { 1880 dev_dbg(dev, "no platform_data?\n"); 1881 return -ENODEV; 1882 } 1883 switch (plat->mode) { 1884 case MUSB_HOST: 1885#ifdef CONFIG_USB_MUSB_HDRC_HCD 1886 break; 1887#else 1888 goto bad_config; 1889#endif 1890 case MUSB_PERIPHERAL: 1891#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1892 break; 1893#else 1894 goto bad_config; 1895#endif 1896 case MUSB_OTG: 1897#ifdef CONFIG_USB_MUSB_OTG 1898 break; 1899#else 1900bad_config: 1901#endif 1902 default: 1903 dev_err(dev, "incompatible Kconfig role setting\n"); 1904 return -EINVAL; 1905 } 1906 1907 /* allocate */ 1908 musb = allocate_instance(dev, plat->config, ctrl); 1909 if (!musb) 1910 return -ENOMEM; 1911 1912 spin_lock_init(&musb->lock); 1913 musb->board_mode = plat->mode; 1914 musb->board_set_power = plat->set_power; 1915 musb->set_clock = plat->set_clock; 1916 musb->min_power = plat->min_power; 1917 1918 /* Clock usage is chip-specific ... functional clock (DaVinci, 1919 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core 1920 * code does is make sure a clock handle is available; platform 1921 * code manages it during start/stop and suspend/resume. 1922 */ 1923 if (plat->clock) { 1924 musb->clock = clk_get(dev, plat->clock); 1925 if (IS_ERR(musb->clock)) { 1926 status = PTR_ERR(musb->clock); 1927 musb->clock = NULL; 1928 goto fail; 1929 } 1930 } 1931 1932 /* The musb_platform_init() call: 1933 * - adjusts musb->mregs and musb->isr if needed, 1934 * - may initialize an integrated tranceiver 1935 * - initializes musb->xceiv, usually by otg_get_transceiver() 1936 * - activates clocks. 1937 * - stops powering VBUS 1938 * - assigns musb->board_set_vbus if host mode is enabled 1939 * 1940 * There are various transciever configurations. Blackfin, 1941 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1942 * external/discrete ones in various flavors (twl4030 family, 1943 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1944 */ 1945 musb->isr = generic_interrupt; 1946 status = musb_platform_init(musb); 1947 1948 if (status < 0) 1949 goto fail; 1950 if (!musb->isr) { 1951 status = -ENODEV; 1952 goto fail2; 1953 } 1954 1955#ifndef CONFIG_MUSB_PIO_ONLY 1956 if (use_dma && dev->dma_mask) { 1957 struct dma_controller *c; 1958 1959 c = dma_controller_create(musb, musb->mregs); 1960 musb->dma_controller = c; 1961 if (c) 1962 (void) c->start(c); 1963 } 1964#endif 1965 /* ideally this would be abstracted in platform setup */ 1966 if (!is_dma_capable() || !musb->dma_controller) 1967 dev->dma_mask = NULL; 1968 1969 /* be sure interrupts are disabled before connecting ISR */ 1970 musb_platform_disable(musb); 1971 musb_generic_disable(musb); 1972 1973 /* setup musb parts of the core (especially endpoints) */ 1974 status = musb_core_init(plat->config->multipoint 1975 ? MUSB_CONTROLLER_MHDRC 1976 : MUSB_CONTROLLER_HDRC, musb); 1977 if (status < 0) 1978 goto fail2; 1979 1980#ifdef CONFIG_USB_MUSB_OTG 1981 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 1982#endif 1983 1984 /* Init IRQ workqueue before request_irq */ 1985 INIT_WORK(&musb->irq_work, musb_irq_work); 1986 1987 /* attach to the IRQ */ 1988 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 1989 dev_err(dev, "request_irq %d failed!\n", nIrq); 1990 status = -ENODEV; 1991 goto fail2; 1992 } 1993 musb->nIrq = nIrq; 1994/* FIXME this handles wakeup irqs wrong */ 1995 if (enable_irq_wake(nIrq) == 0) { 1996 musb->irq_wake = 1; 1997 device_init_wakeup(dev, 1); 1998 } else { 1999 musb->irq_wake = 0; 2000 } 2001 2002 /* host side needs more setup */ 2003 if (is_host_enabled(musb)) { 2004 struct usb_hcd *hcd = musb_to_hcd(musb); 2005 2006 otg_set_host(musb->xceiv, &hcd->self); 2007 2008 if (is_otg_enabled(musb)) 2009 hcd->self.otg_port = 1; 2010 musb->xceiv->host = &hcd->self; 2011 hcd->power_budget = 2 * (plat->power ? : 250); 2012 2013 /* program PHY to use external vBus if required */ 2014 if (plat->extvbus) { 2015 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2016 busctl |= MUSB_ULPI_USE_EXTVBUS; 2017 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2018 } 2019 } 2020 2021 /* For the host-only role, we can activate right away. 2022 * (We expect the ID pin to be forcibly grounded!!) 2023 * Otherwise, wait till the gadget driver hooks up. 2024 */ 2025 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2026 MUSB_HST_MODE(musb); 2027 musb->xceiv->default_a = 1; 2028 musb->xceiv->state = OTG_STATE_A_IDLE; 2029 2030 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 2031 2032 DBG(1, "%s mode, status %d, devctl %02x %c\n", 2033 "HOST", status, 2034 musb_readb(musb->mregs, MUSB_DEVCTL), 2035 (musb_readb(musb->mregs, MUSB_DEVCTL) 2036 & MUSB_DEVCTL_BDEVICE 2037 ? 'B' : 'A')); 2038 2039 } else /* peripheral is enabled */ { 2040 MUSB_DEV_MODE(musb); 2041 musb->xceiv->default_a = 0; 2042 musb->xceiv->state = OTG_STATE_B_IDLE; 2043 2044 status = musb_gadget_setup(musb); 2045 2046 DBG(1, "%s mode, status %d, dev%02x\n", 2047 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2048 status, 2049 musb_readb(musb->mregs, MUSB_DEVCTL)); 2050 2051 } 2052 if (status < 0) 2053 goto fail2; 2054 2055#ifdef CONFIG_SYSFS 2056 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2057 if (status) 2058 goto fail2; 2059#endif 2060 2061 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", 2062 ({char *s; 2063 switch (musb->board_mode) { 2064 case MUSB_HOST: s = "Host"; break; 2065 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2066 default: s = "OTG"; break; 2067 }; s; }), 2068 ctrl, 2069 (is_dma_capable() && musb->dma_controller) 2070 ? "DMA" : "PIO", 2071 musb->nIrq); 2072 2073 return 0; 2074 2075fail2: 2076 musb_platform_exit(musb); 2077fail: 2078 dev_err(musb->controller, 2079 "musb_init_controller failed with status %d\n", status); 2080 2081 if (musb->clock) 2082 clk_put(musb->clock); 2083 device_init_wakeup(dev, 0); 2084 musb_free(musb); 2085 2086 return status; 2087 2088} 2089 2090/*-------------------------------------------------------------------------*/ 2091 2092/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2093 * bridge to a platform device; this driver then suffices. 2094 */ 2095 2096#ifndef CONFIG_MUSB_PIO_ONLY 2097static u64 *orig_dma_mask; 2098#endif 2099 2100static int __init musb_probe(struct platform_device *pdev) 2101{ 2102 struct device *dev = &pdev->dev; 2103 int irq = platform_get_irq(pdev, 0); 2104 int status; 2105 struct resource *iomem; 2106 void __iomem *base; 2107 2108 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2109 if (!iomem || irq == 0) 2110 return -ENODEV; 2111 2112 base = ioremap(iomem->start, resource_size(iomem)); 2113 if (!base) { 2114 dev_err(dev, "ioremap failed\n"); 2115 return -ENOMEM; 2116 } 2117 2118#ifndef CONFIG_MUSB_PIO_ONLY 2119 /* clobbered by use_dma=n */ 2120 orig_dma_mask = dev->dma_mask; 2121#endif 2122 status = musb_init_controller(dev, irq, base); 2123 if (status < 0) 2124 iounmap(base); 2125 2126 return status; 2127} 2128 2129static int __exit musb_remove(struct platform_device *pdev) 2130{ 2131 struct musb *musb = dev_to_musb(&pdev->dev); 2132 void __iomem *ctrl_base = musb->ctrl_base; 2133 2134 /* this gets called on rmmod. 2135 * - Host mode: host may still be active 2136 * - Peripheral mode: peripheral is deactivated (or never-activated) 2137 * - OTG mode: both roles are deactivated (or never-activated) 2138 */ 2139 musb_shutdown(pdev); 2140#ifdef CONFIG_USB_MUSB_HDRC_HCD 2141 if (musb->board_mode == MUSB_HOST) 2142 usb_remove_hcd(musb_to_hcd(musb)); 2143#endif 2144 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2145 musb_platform_exit(musb); 2146 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2147 2148 musb_free(musb); 2149 iounmap(ctrl_base); 2150 device_init_wakeup(&pdev->dev, 0); 2151#ifndef CONFIG_MUSB_PIO_ONLY 2152 pdev->dev.dma_mask = orig_dma_mask; 2153#endif 2154 return 0; 2155} 2156 2157#ifdef CONFIG_PM 2158 2159static struct musb_context_registers musb_context; 2160 2161void musb_save_context(struct musb *musb) 2162{ 2163 int i; 2164 void __iomem *musb_base = musb->mregs; 2165 2166 if (is_host_enabled(musb)) { 2167 musb_context.frame = musb_readw(musb_base, MUSB_FRAME); 2168 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2169 musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2170 } 2171 musb_context.power = musb_readb(musb_base, MUSB_POWER); 2172 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2173 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2174 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2175 musb_context.index = musb_readb(musb_base, MUSB_INDEX); 2176 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2177 2178 for (i = 0; i < MUSB_C_NUM_EPS; ++i) { 2179 musb_writeb(musb_base, MUSB_INDEX, i); 2180 musb_context.index_regs[i].txmaxp = 2181 musb_readw(musb_base, 0x10 + MUSB_TXMAXP); 2182 musb_context.index_regs[i].txcsr = 2183 musb_readw(musb_base, 0x10 + MUSB_TXCSR); 2184 musb_context.index_regs[i].rxmaxp = 2185 musb_readw(musb_base, 0x10 + MUSB_RXMAXP); 2186 musb_context.index_regs[i].rxcsr = 2187 musb_readw(musb_base, 0x10 + MUSB_RXCSR); 2188 2189 if (musb->dyn_fifo) { 2190 musb_context.index_regs[i].txfifoadd = 2191 musb_read_txfifoadd(musb_base); 2192 musb_context.index_regs[i].rxfifoadd = 2193 musb_read_rxfifoadd(musb_base); 2194 musb_context.index_regs[i].txfifosz = 2195 musb_read_txfifosz(musb_base); 2196 musb_context.index_regs[i].rxfifosz = 2197 musb_read_rxfifosz(musb_base); 2198 } 2199 if (is_host_enabled(musb)) { 2200 musb_context.index_regs[i].txtype = 2201 musb_readb(musb_base, 0x10 + MUSB_TXTYPE); 2202 musb_context.index_regs[i].txinterval = 2203 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL); 2204 musb_context.index_regs[i].rxtype = 2205 musb_readb(musb_base, 0x10 + MUSB_RXTYPE); 2206 musb_context.index_regs[i].rxinterval = 2207 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL); 2208 2209 musb_context.index_regs[i].txfunaddr = 2210 musb_read_txfunaddr(musb_base, i); 2211 musb_context.index_regs[i].txhubaddr = 2212 musb_read_txhubaddr(musb_base, i); 2213 musb_context.index_regs[i].txhubport = 2214 musb_read_txhubport(musb_base, i); 2215 2216 musb_context.index_regs[i].rxfunaddr = 2217 musb_read_rxfunaddr(musb_base, i); 2218 musb_context.index_regs[i].rxhubaddr = 2219 musb_read_rxhubaddr(musb_base, i); 2220 musb_context.index_regs[i].rxhubport = 2221 musb_read_rxhubport(musb_base, i); 2222 } 2223 } 2224 2225 musb_writeb(musb_base, MUSB_INDEX, musb_context.index); 2226 2227 musb_platform_save_context(musb, &musb_context); 2228} 2229 2230void musb_restore_context(struct musb *musb) 2231{ 2232 int i; 2233 void __iomem *musb_base = musb->mregs; 2234 void __iomem *ep_target_regs; 2235 2236 musb_platform_restore_context(musb, &musb_context); 2237 2238 if (is_host_enabled(musb)) { 2239 musb_writew(musb_base, MUSB_FRAME, musb_context.frame); 2240 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode); 2241 musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl); 2242 } 2243 musb_writeb(musb_base, MUSB_POWER, musb_context.power); 2244 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe); 2245 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe); 2246 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe); 2247 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl); 2248 2249 for (i = 0; i < MUSB_C_NUM_EPS; ++i) { 2250 musb_writeb(musb_base, MUSB_INDEX, i); 2251 musb_writew(musb_base, 0x10 + MUSB_TXMAXP, 2252 musb_context.index_regs[i].txmaxp); 2253 musb_writew(musb_base, 0x10 + MUSB_TXCSR, 2254 musb_context.index_regs[i].txcsr); 2255 musb_writew(musb_base, 0x10 + MUSB_RXMAXP, 2256 musb_context.index_regs[i].rxmaxp); 2257 musb_writew(musb_base, 0x10 + MUSB_RXCSR, 2258 musb_context.index_regs[i].rxcsr); 2259 2260 if (musb->dyn_fifo) { 2261 musb_write_txfifosz(musb_base, 2262 musb_context.index_regs[i].txfifosz); 2263 musb_write_rxfifosz(musb_base, 2264 musb_context.index_regs[i].rxfifosz); 2265 musb_write_txfifoadd(musb_base, 2266 musb_context.index_regs[i].txfifoadd); 2267 musb_write_rxfifoadd(musb_base, 2268 musb_context.index_regs[i].rxfifoadd); 2269 } 2270 2271 if (is_host_enabled(musb)) { 2272 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE, 2273 musb_context.index_regs[i].txtype); 2274 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL, 2275 musb_context.index_regs[i].txinterval); 2276 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE, 2277 musb_context.index_regs[i].rxtype); 2278 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL, 2279 2280 musb_context.index_regs[i].rxinterval); 2281 musb_write_txfunaddr(musb_base, i, 2282 musb_context.index_regs[i].txfunaddr); 2283 musb_write_txhubaddr(musb_base, i, 2284 musb_context.index_regs[i].txhubaddr); 2285 musb_write_txhubport(musb_base, i, 2286 musb_context.index_regs[i].txhubport); 2287 2288 ep_target_regs = 2289 musb_read_target_reg_base(i, musb_base); 2290 2291 musb_write_rxfunaddr(ep_target_regs, 2292 musb_context.index_regs[i].rxfunaddr); 2293 musb_write_rxhubaddr(ep_target_regs, 2294 musb_context.index_regs[i].rxhubaddr); 2295 musb_write_rxhubport(ep_target_regs, 2296 musb_context.index_regs[i].rxhubport); 2297 } 2298 } 2299 2300 musb_writeb(musb_base, MUSB_INDEX, musb_context.index); 2301} 2302 2303static int musb_suspend(struct device *dev) 2304{ 2305 struct platform_device *pdev = to_platform_device(dev); 2306 unsigned long flags; 2307 struct musb *musb = dev_to_musb(&pdev->dev); 2308 2309 if (!musb->clock) 2310 return 0; 2311 2312 spin_lock_irqsave(&musb->lock, flags); 2313 2314 if (is_peripheral_active(musb)) { 2315 /* FIXME force disconnect unless we know USB will wake 2316 * the system up quickly enough to respond ... 2317 */ 2318 } else if (is_host_active(musb)) { 2319 /* we know all the children are suspended; sometimes 2320 * they will even be wakeup-enabled. 2321 */ 2322 } 2323 2324 musb_save_context(musb); 2325 2326 if (musb->set_clock) 2327 musb->set_clock(musb->clock, 0); 2328 else 2329 clk_disable(musb->clock); 2330 spin_unlock_irqrestore(&musb->lock, flags); 2331 return 0; 2332} 2333 2334static int musb_resume_noirq(struct device *dev) 2335{ 2336 struct platform_device *pdev = to_platform_device(dev); 2337 struct musb *musb = dev_to_musb(&pdev->dev); 2338 2339 if (!musb->clock) 2340 return 0; 2341 2342 if (musb->set_clock) 2343 musb->set_clock(musb->clock, 1); 2344 else 2345 clk_enable(musb->clock); 2346 2347 musb_restore_context(musb); 2348 2349 /* for static cmos like DaVinci, register values were preserved 2350 * unless for some reason the whole soc powered down or the USB 2351 * module got reset through the PSC (vs just being disabled). 2352 */ 2353 return 0; 2354} 2355 2356static const struct dev_pm_ops musb_dev_pm_ops = { 2357 .suspend = musb_suspend, 2358 .resume_noirq = musb_resume_noirq, 2359}; 2360 2361#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2362#else 2363#define MUSB_DEV_PM_OPS NULL 2364#endif 2365 2366static struct platform_driver musb_driver = { 2367 .driver = { 2368 .name = (char *)musb_driver_name, 2369 .bus = &platform_bus_type, 2370 .owner = THIS_MODULE, 2371 .pm = MUSB_DEV_PM_OPS, 2372 }, 2373 .remove = __exit_p(musb_remove), 2374 .shutdown = musb_shutdown, 2375}; 2376 2377/*-------------------------------------------------------------------------*/ 2378 2379static int __init musb_init(void) 2380{ 2381#ifdef CONFIG_USB_MUSB_HDRC_HCD 2382 if (usb_disabled()) 2383 return 0; 2384#endif 2385 2386 pr_info("%s: version " MUSB_VERSION ", " 2387#ifdef CONFIG_MUSB_PIO_ONLY 2388 "pio" 2389#elif defined(CONFIG_USB_TI_CPPI_DMA) 2390 "cppi-dma" 2391#elif defined(CONFIG_USB_INVENTRA_DMA) 2392 "musb-dma" 2393#elif defined(CONFIG_USB_TUSB_OMAP_DMA) 2394 "tusb-omap-dma" 2395#else 2396 "?dma?" 2397#endif 2398 ", " 2399#ifdef CONFIG_USB_MUSB_OTG 2400 "otg (peripheral+host)" 2401#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 2402 "peripheral" 2403#elif defined(CONFIG_USB_MUSB_HDRC_HCD) 2404 "host" 2405#endif 2406 ", debug=%d\n", 2407 musb_driver_name, musb_debug); 2408 return platform_driver_probe(&musb_driver, musb_probe); 2409} 2410 2411/* make us init after usbcore and i2c (transceivers, regulators, etc) 2412 * and before usb gadget and host-side drivers start to register 2413 */ 2414fs_initcall(musb_init); 2415 2416static void __exit musb_cleanup(void) 2417{ 2418 platform_driver_unregister(&musb_driver); 2419} 2420module_exit(musb_cleanup); 2421