musb_core.c revision 541079de88735152a993ff93e90096643730a054
1/* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35/* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82/* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92#include <linux/module.h> 93#include <linux/kernel.h> 94#include <linux/sched.h> 95#include <linux/slab.h> 96#include <linux/init.h> 97#include <linux/list.h> 98#include <linux/kobject.h> 99#include <linux/platform_device.h> 100#include <linux/io.h> 101 102#include "musb_core.h" 103 104#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 105 106 107unsigned musb_debug; 108module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR); 109MODULE_PARM_DESC(debug, "Debug message level. Default = 0"); 110 111#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 112#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 113 114#define MUSB_VERSION "6.0" 115 116#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 117 118#define MUSB_DRIVER_NAME "musb-hdrc" 119const char musb_driver_name[] = MUSB_DRIVER_NAME; 120 121MODULE_DESCRIPTION(DRIVER_INFO); 122MODULE_AUTHOR(DRIVER_AUTHOR); 123MODULE_LICENSE("GPL"); 124MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 125 126 127/*-------------------------------------------------------------------------*/ 128 129static inline struct musb *dev_to_musb(struct device *dev) 130{ 131 return dev_get_drvdata(dev); 132} 133 134/*-------------------------------------------------------------------------*/ 135 136#ifndef CONFIG_BLACKFIN 137static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset) 138{ 139 void __iomem *addr = otg->io_priv; 140 int i = 0; 141 u8 r; 142 u8 power; 143 144 /* Make sure the transceiver is not in low power mode */ 145 power = musb_readb(addr, MUSB_POWER); 146 power &= ~MUSB_POWER_SUSPENDM; 147 musb_writeb(addr, MUSB_POWER, power); 148 149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 151 */ 152 153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 156 157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 158 & MUSB_ULPI_REG_CMPLT)) { 159 i++; 160 if (i == 10000) { 161 DBG(3, "ULPI read timed out\n"); 162 return -ETIMEDOUT; 163 } 164 165 } 166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 167 r &= ~MUSB_ULPI_REG_CMPLT; 168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 169 170 return musb_readb(addr, MUSB_ULPI_REG_DATA); 171} 172 173static int musb_ulpi_write(struct otg_transceiver *otg, 174 u32 offset, u32 data) 175{ 176 void __iomem *addr = otg->io_priv; 177 int i = 0; 178 u8 r = 0; 179 u8 power; 180 181 /* Make sure the transceiver is not in low power mode */ 182 power = musb_readb(addr, MUSB_POWER); 183 power &= ~MUSB_POWER_SUSPENDM; 184 musb_writeb(addr, MUSB_POWER, power); 185 186 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 187 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 188 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 189 190 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 191 & MUSB_ULPI_REG_CMPLT)) { 192 i++; 193 if (i == 10000) { 194 DBG(3, "ULPI write timed out\n"); 195 return -ETIMEDOUT; 196 } 197 } 198 199 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 200 r &= ~MUSB_ULPI_REG_CMPLT; 201 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 202 203 return 0; 204} 205#else 206#define musb_ulpi_read NULL 207#define musb_ulpi_write NULL 208#endif 209 210static struct otg_io_access_ops musb_ulpi_access = { 211 .read = musb_ulpi_read, 212 .write = musb_ulpi_write, 213}; 214 215/*-------------------------------------------------------------------------*/ 216 217#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) 218 219/* 220 * Load an endpoint's FIFO 221 */ 222void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 223{ 224 void __iomem *fifo = hw_ep->fifo; 225 226 prefetch((u8 *)src); 227 228 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 229 'T', hw_ep->epnum, fifo, len, src); 230 231 /* we can't assume unaligned reads work */ 232 if (likely((0x01 & (unsigned long) src) == 0)) { 233 u16 index = 0; 234 235 /* best case is 32bit-aligned source address */ 236 if ((0x02 & (unsigned long) src) == 0) { 237 if (len >= 4) { 238 writesl(fifo, src + index, len >> 2); 239 index += len & ~0x03; 240 } 241 if (len & 0x02) { 242 musb_writew(fifo, 0, *(u16 *)&src[index]); 243 index += 2; 244 } 245 } else { 246 if (len >= 2) { 247 writesw(fifo, src + index, len >> 1); 248 index += len & ~0x01; 249 } 250 } 251 if (len & 0x01) 252 musb_writeb(fifo, 0, src[index]); 253 } else { 254 /* byte aligned */ 255 writesb(fifo, src, len); 256 } 257} 258 259#if !defined(CONFIG_USB_MUSB_AM35X) 260/* 261 * Unload an endpoint's FIFO 262 */ 263void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 264{ 265 void __iomem *fifo = hw_ep->fifo; 266 267 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 268 'R', hw_ep->epnum, fifo, len, dst); 269 270 /* we can't assume unaligned writes work */ 271 if (likely((0x01 & (unsigned long) dst) == 0)) { 272 u16 index = 0; 273 274 /* best case is 32bit-aligned destination address */ 275 if ((0x02 & (unsigned long) dst) == 0) { 276 if (len >= 4) { 277 readsl(fifo, dst, len >> 2); 278 index = len & ~0x03; 279 } 280 if (len & 0x02) { 281 *(u16 *)&dst[index] = musb_readw(fifo, 0); 282 index += 2; 283 } 284 } else { 285 if (len >= 2) { 286 readsw(fifo, dst, len >> 1); 287 index = len & ~0x01; 288 } 289 } 290 if (len & 0x01) 291 dst[index] = musb_readb(fifo, 0); 292 } else { 293 /* byte aligned */ 294 readsb(fifo, dst, len); 295 } 296} 297#endif 298 299#endif /* normal PIO */ 300 301 302/*-------------------------------------------------------------------------*/ 303 304/* for high speed test mode; see USB 2.0 spec 7.1.20 */ 305static const u8 musb_test_packet[53] = { 306 /* implicit SYNC then DATA0 to start */ 307 308 /* JKJKJKJK x9 */ 309 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 310 /* JJKKJJKK x8 */ 311 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 312 /* JJJJKKKK x8 */ 313 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 314 /* JJJJJJJKKKKKKK x8 */ 315 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 316 /* JJJJJJJK x8 */ 317 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 318 /* JKKKKKKK x10, JK */ 319 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 320 321 /* implicit CRC16 then EOP to end */ 322}; 323 324void musb_load_testpacket(struct musb *musb) 325{ 326 void __iomem *regs = musb->endpoints[0].regs; 327 328 musb_ep_select(musb->mregs, 0); 329 musb_write_fifo(musb->control_ep, 330 sizeof(musb_test_packet), musb_test_packet); 331 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 332} 333 334/*-------------------------------------------------------------------------*/ 335 336const char *otg_state_string(struct musb *musb) 337{ 338 switch (musb->xceiv->state) { 339 case OTG_STATE_A_IDLE: return "a_idle"; 340 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; 341 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; 342 case OTG_STATE_A_HOST: return "a_host"; 343 case OTG_STATE_A_SUSPEND: return "a_suspend"; 344 case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; 345 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; 346 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; 347 case OTG_STATE_B_IDLE: return "b_idle"; 348 case OTG_STATE_B_SRP_INIT: return "b_srp_init"; 349 case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; 350 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; 351 case OTG_STATE_B_HOST: return "b_host"; 352 default: return "UNDEFINED"; 353 } 354} 355 356#ifdef CONFIG_USB_MUSB_OTG 357 358/* 359 * Handles OTG hnp timeouts, such as b_ase0_brst 360 */ 361void musb_otg_timer_func(unsigned long data) 362{ 363 struct musb *musb = (struct musb *)data; 364 unsigned long flags; 365 366 spin_lock_irqsave(&musb->lock, flags); 367 switch (musb->xceiv->state) { 368 case OTG_STATE_B_WAIT_ACON: 369 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 370 musb_g_disconnect(musb); 371 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 372 musb->is_active = 0; 373 break; 374 case OTG_STATE_A_SUSPEND: 375 case OTG_STATE_A_WAIT_BCON: 376 DBG(1, "HNP: %s timeout\n", otg_state_string(musb)); 377 musb_platform_set_vbus(musb, 0); 378 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 379 break; 380 default: 381 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb)); 382 } 383 musb->ignore_disconnect = 0; 384 spin_unlock_irqrestore(&musb->lock, flags); 385} 386 387/* 388 * Stops the HNP transition. Caller must take care of locking. 389 */ 390void musb_hnp_stop(struct musb *musb) 391{ 392 struct usb_hcd *hcd = musb_to_hcd(musb); 393 void __iomem *mbase = musb->mregs; 394 u8 reg; 395 396 DBG(1, "HNP: stop from %s\n", otg_state_string(musb)); 397 398 switch (musb->xceiv->state) { 399 case OTG_STATE_A_PERIPHERAL: 400 musb_g_disconnect(musb); 401 DBG(1, "HNP: back to %s\n", otg_state_string(musb)); 402 break; 403 case OTG_STATE_B_HOST: 404 DBG(1, "HNP: Disabling HR\n"); 405 hcd->self.is_b_host = 0; 406 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 407 MUSB_DEV_MODE(musb); 408 reg = musb_readb(mbase, MUSB_POWER); 409 reg |= MUSB_POWER_SUSPENDM; 410 musb_writeb(mbase, MUSB_POWER, reg); 411 /* REVISIT: Start SESSION_REQUEST here? */ 412 break; 413 default: 414 DBG(1, "HNP: Stopping in unknown state %s\n", 415 otg_state_string(musb)); 416 } 417 418 /* 419 * When returning to A state after HNP, avoid hub_port_rebounce(), 420 * which cause occasional OPT A "Did not receive reset after connect" 421 * errors. 422 */ 423 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 424} 425 426#endif 427 428/* 429 * Interrupt Service Routine to record USB "global" interrupts. 430 * Since these do not happen often and signify things of 431 * paramount importance, it seems OK to check them individually; 432 * the order of the tests is specified in the manual 433 * 434 * @param musb instance pointer 435 * @param int_usb register contents 436 * @param devctl 437 * @param power 438 */ 439 440static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 441 u8 devctl, u8 power) 442{ 443 irqreturn_t handled = IRQ_NONE; 444 445 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 446 int_usb); 447 448 /* in host mode, the peripheral may issue remote wakeup. 449 * in peripheral mode, the host may resume the link. 450 * spurious RESUME irqs happen too, paired with SUSPEND. 451 */ 452 if (int_usb & MUSB_INTR_RESUME) { 453 handled = IRQ_HANDLED; 454 DBG(3, "RESUME (%s)\n", otg_state_string(musb)); 455 456 if (devctl & MUSB_DEVCTL_HM) { 457#ifdef CONFIG_USB_MUSB_HDRC_HCD 458 void __iomem *mbase = musb->mregs; 459 460 switch (musb->xceiv->state) { 461 case OTG_STATE_A_SUSPEND: 462 /* remote wakeup? later, GetPortStatus 463 * will stop RESUME signaling 464 */ 465 466 if (power & MUSB_POWER_SUSPENDM) { 467 /* spurious */ 468 musb->int_usb &= ~MUSB_INTR_SUSPEND; 469 DBG(2, "Spurious SUSPENDM\n"); 470 break; 471 } 472 473 power &= ~MUSB_POWER_SUSPENDM; 474 musb_writeb(mbase, MUSB_POWER, 475 power | MUSB_POWER_RESUME); 476 477 musb->port1_status |= 478 (USB_PORT_STAT_C_SUSPEND << 16) 479 | MUSB_PORT_STAT_RESUME; 480 musb->rh_timer = jiffies 481 + msecs_to_jiffies(20); 482 483 musb->xceiv->state = OTG_STATE_A_HOST; 484 musb->is_active = 1; 485 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 486 break; 487 case OTG_STATE_B_WAIT_ACON: 488 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 489 musb->is_active = 1; 490 MUSB_DEV_MODE(musb); 491 break; 492 default: 493 WARNING("bogus %s RESUME (%s)\n", 494 "host", 495 otg_state_string(musb)); 496 } 497#endif 498 } else { 499 switch (musb->xceiv->state) { 500#ifdef CONFIG_USB_MUSB_HDRC_HCD 501 case OTG_STATE_A_SUSPEND: 502 /* possibly DISCONNECT is upcoming */ 503 musb->xceiv->state = OTG_STATE_A_HOST; 504 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 505 break; 506#endif 507#ifdef CONFIG_USB_GADGET_MUSB_HDRC 508 case OTG_STATE_B_WAIT_ACON: 509 case OTG_STATE_B_PERIPHERAL: 510 /* disconnect while suspended? we may 511 * not get a disconnect irq... 512 */ 513 if ((devctl & MUSB_DEVCTL_VBUS) 514 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 515 ) { 516 musb->int_usb |= MUSB_INTR_DISCONNECT; 517 musb->int_usb &= ~MUSB_INTR_SUSPEND; 518 break; 519 } 520 musb_g_resume(musb); 521 break; 522 case OTG_STATE_B_IDLE: 523 musb->int_usb &= ~MUSB_INTR_SUSPEND; 524 break; 525#endif 526 default: 527 WARNING("bogus %s RESUME (%s)\n", 528 "peripheral", 529 otg_state_string(musb)); 530 } 531 } 532 } 533 534#ifdef CONFIG_USB_MUSB_HDRC_HCD 535 /* see manual for the order of the tests */ 536 if (int_usb & MUSB_INTR_SESSREQ) { 537 void __iomem *mbase = musb->mregs; 538 539 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS 540 && (devctl & MUSB_DEVCTL_BDEVICE)) { 541 DBG(3, "SessReq while on B state\n"); 542 return IRQ_HANDLED; 543 } 544 545 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); 546 547 /* IRQ arrives from ID pin sense or (later, if VBUS power 548 * is removed) SRP. responses are time critical: 549 * - turn on VBUS (with silicon-specific mechanism) 550 * - go through A_WAIT_VRISE 551 * - ... to A_WAIT_BCON. 552 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 553 */ 554 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 555 musb->ep0_stage = MUSB_EP0_START; 556 musb->xceiv->state = OTG_STATE_A_IDLE; 557 MUSB_HST_MODE(musb); 558 musb_platform_set_vbus(musb, 1); 559 560 handled = IRQ_HANDLED; 561 } 562 563 if (int_usb & MUSB_INTR_VBUSERROR) { 564 int ignore = 0; 565 566 /* During connection as an A-Device, we may see a short 567 * current spikes causing voltage drop, because of cable 568 * and peripheral capacitance combined with vbus draw. 569 * (So: less common with truly self-powered devices, where 570 * vbus doesn't act like a power supply.) 571 * 572 * Such spikes are short; usually less than ~500 usec, max 573 * of ~2 msec. That is, they're not sustained overcurrent 574 * errors, though they're reported using VBUSERROR irqs. 575 * 576 * Workarounds: (a) hardware: use self powered devices. 577 * (b) software: ignore non-repeated VBUS errors. 578 * 579 * REVISIT: do delays from lots of DEBUG_KERNEL checks 580 * make trouble here, keeping VBUS < 4.4V ? 581 */ 582 switch (musb->xceiv->state) { 583 case OTG_STATE_A_HOST: 584 /* recovery is dicey once we've gotten past the 585 * initial stages of enumeration, but if VBUS 586 * stayed ok at the other end of the link, and 587 * another reset is due (at least for high speed, 588 * to redo the chirp etc), it might work OK... 589 */ 590 case OTG_STATE_A_WAIT_BCON: 591 case OTG_STATE_A_WAIT_VRISE: 592 if (musb->vbuserr_retry) { 593 void __iomem *mbase = musb->mregs; 594 595 musb->vbuserr_retry--; 596 ignore = 1; 597 devctl |= MUSB_DEVCTL_SESSION; 598 musb_writeb(mbase, MUSB_DEVCTL, devctl); 599 } else { 600 musb->port1_status |= 601 USB_PORT_STAT_OVERCURRENT 602 | (USB_PORT_STAT_C_OVERCURRENT << 16); 603 } 604 break; 605 default: 606 break; 607 } 608 609 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 610 otg_state_string(musb), 611 devctl, 612 ({ char *s; 613 switch (devctl & MUSB_DEVCTL_VBUS) { 614 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 615 s = "<SessEnd"; break; 616 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 617 s = "<AValid"; break; 618 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 619 s = "<VBusValid"; break; 620 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 621 default: 622 s = "VALID"; break; 623 }; s; }), 624 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 625 musb->port1_status); 626 627 /* go through A_WAIT_VFALL then start a new session */ 628 if (!ignore) 629 musb_platform_set_vbus(musb, 0); 630 handled = IRQ_HANDLED; 631 } 632 633#endif 634 if (int_usb & MUSB_INTR_SUSPEND) { 635 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", 636 otg_state_string(musb), devctl, power); 637 handled = IRQ_HANDLED; 638 639 switch (musb->xceiv->state) { 640#ifdef CONFIG_USB_MUSB_OTG 641 case OTG_STATE_A_PERIPHERAL: 642 /* We also come here if the cable is removed, since 643 * this silicon doesn't report ID-no-longer-grounded. 644 * 645 * We depend on T(a_wait_bcon) to shut us down, and 646 * hope users don't do anything dicey during this 647 * undesired detour through A_WAIT_BCON. 648 */ 649 musb_hnp_stop(musb); 650 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 651 musb_root_disconnect(musb); 652 musb_platform_try_idle(musb, jiffies 653 + msecs_to_jiffies(musb->a_wait_bcon 654 ? : OTG_TIME_A_WAIT_BCON)); 655 656 break; 657#endif 658 case OTG_STATE_B_IDLE: 659 if (!musb->is_active) 660 break; 661 case OTG_STATE_B_PERIPHERAL: 662 musb_g_suspend(musb); 663 musb->is_active = is_otg_enabled(musb) 664 && musb->xceiv->gadget->b_hnp_enable; 665 if (musb->is_active) { 666#ifdef CONFIG_USB_MUSB_OTG 667 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 668 DBG(1, "HNP: Setting timer for b_ase0_brst\n"); 669 mod_timer(&musb->otg_timer, jiffies 670 + msecs_to_jiffies( 671 OTG_TIME_B_ASE0_BRST)); 672#endif 673 } 674 break; 675 case OTG_STATE_A_WAIT_BCON: 676 if (musb->a_wait_bcon != 0) 677 musb_platform_try_idle(musb, jiffies 678 + msecs_to_jiffies(musb->a_wait_bcon)); 679 break; 680 case OTG_STATE_A_HOST: 681 musb->xceiv->state = OTG_STATE_A_SUSPEND; 682 musb->is_active = is_otg_enabled(musb) 683 && musb->xceiv->host->b_hnp_enable; 684 break; 685 case OTG_STATE_B_HOST: 686 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 687 DBG(1, "REVISIT: SUSPEND as B_HOST\n"); 688 break; 689 default: 690 /* "should not happen" */ 691 musb->is_active = 0; 692 break; 693 } 694 } 695 696#ifdef CONFIG_USB_MUSB_HDRC_HCD 697 if (int_usb & MUSB_INTR_CONNECT) { 698 struct usb_hcd *hcd = musb_to_hcd(musb); 699 700 handled = IRQ_HANDLED; 701 musb->is_active = 1; 702 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); 703 704 musb->ep0_stage = MUSB_EP0_START; 705 706#ifdef CONFIG_USB_MUSB_OTG 707 /* flush endpoints when transitioning from Device Mode */ 708 if (is_peripheral_active(musb)) { 709 /* REVISIT HNP; just force disconnect */ 710 } 711 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); 712 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); 713 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 714#endif 715 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 716 |USB_PORT_STAT_HIGH_SPEED 717 |USB_PORT_STAT_ENABLE 718 ); 719 musb->port1_status |= USB_PORT_STAT_CONNECTION 720 |(USB_PORT_STAT_C_CONNECTION << 16); 721 722 /* high vs full speed is just a guess until after reset */ 723 if (devctl & MUSB_DEVCTL_LSDEV) 724 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 725 726 /* indicate new connection to OTG machine */ 727 switch (musb->xceiv->state) { 728 case OTG_STATE_B_PERIPHERAL: 729 if (int_usb & MUSB_INTR_SUSPEND) { 730 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); 731 int_usb &= ~MUSB_INTR_SUSPEND; 732 goto b_host; 733 } else 734 DBG(1, "CONNECT as b_peripheral???\n"); 735 break; 736 case OTG_STATE_B_WAIT_ACON: 737 DBG(1, "HNP: CONNECT, now b_host\n"); 738b_host: 739 musb->xceiv->state = OTG_STATE_B_HOST; 740 hcd->self.is_b_host = 1; 741 musb->ignore_disconnect = 0; 742 del_timer(&musb->otg_timer); 743 break; 744 default: 745 if ((devctl & MUSB_DEVCTL_VBUS) 746 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 747 musb->xceiv->state = OTG_STATE_A_HOST; 748 hcd->self.is_b_host = 0; 749 } 750 break; 751 } 752 753 /* poke the root hub */ 754 MUSB_HST_MODE(musb); 755 if (hcd->status_urb) 756 usb_hcd_poll_rh_status(hcd); 757 else 758 usb_hcd_resume_root_hub(hcd); 759 760 DBG(1, "CONNECT (%s) devctl %02x\n", 761 otg_state_string(musb), devctl); 762 } 763#endif /* CONFIG_USB_MUSB_HDRC_HCD */ 764 765 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 766 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n", 767 otg_state_string(musb), 768 MUSB_MODE(musb), devctl); 769 handled = IRQ_HANDLED; 770 771 switch (musb->xceiv->state) { 772#ifdef CONFIG_USB_MUSB_HDRC_HCD 773 case OTG_STATE_A_HOST: 774 case OTG_STATE_A_SUSPEND: 775 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 776 musb_root_disconnect(musb); 777 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 778 musb_platform_try_idle(musb, jiffies 779 + msecs_to_jiffies(musb->a_wait_bcon)); 780 break; 781#endif /* HOST */ 782#ifdef CONFIG_USB_MUSB_OTG 783 case OTG_STATE_B_HOST: 784 /* REVISIT this behaves for "real disconnect" 785 * cases; make sure the other transitions from 786 * from B_HOST act right too. The B_HOST code 787 * in hnp_stop() is currently not used... 788 */ 789 musb_root_disconnect(musb); 790 musb_to_hcd(musb)->self.is_b_host = 0; 791 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 792 MUSB_DEV_MODE(musb); 793 musb_g_disconnect(musb); 794 break; 795 case OTG_STATE_A_PERIPHERAL: 796 musb_hnp_stop(musb); 797 musb_root_disconnect(musb); 798 /* FALLTHROUGH */ 799 case OTG_STATE_B_WAIT_ACON: 800 /* FALLTHROUGH */ 801#endif /* OTG */ 802#ifdef CONFIG_USB_GADGET_MUSB_HDRC 803 case OTG_STATE_B_PERIPHERAL: 804 case OTG_STATE_B_IDLE: 805 musb_g_disconnect(musb); 806 break; 807#endif /* GADGET */ 808 default: 809 WARNING("unhandled DISCONNECT transition (%s)\n", 810 otg_state_string(musb)); 811 break; 812 } 813 } 814 815 /* mentor saves a bit: bus reset and babble share the same irq. 816 * only host sees babble; only peripheral sees bus reset. 817 */ 818 if (int_usb & MUSB_INTR_RESET) { 819 handled = IRQ_HANDLED; 820 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 821 /* 822 * Looks like non-HS BABBLE can be ignored, but 823 * HS BABBLE is an error condition. For HS the solution 824 * is to avoid babble in the first place and fix what 825 * caused BABBLE. When HS BABBLE happens we can only 826 * stop the session. 827 */ 828 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 829 DBG(1, "BABBLE devctl: %02x\n", devctl); 830 else { 831 ERR("Stopping host session -- babble\n"); 832 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 833 } 834 } else if (is_peripheral_capable()) { 835 DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); 836 switch (musb->xceiv->state) { 837#ifdef CONFIG_USB_OTG 838 case OTG_STATE_A_SUSPEND: 839 /* We need to ignore disconnect on suspend 840 * otherwise tusb 2.0 won't reconnect after a 841 * power cycle, which breaks otg compliance. 842 */ 843 musb->ignore_disconnect = 1; 844 musb_g_reset(musb); 845 /* FALLTHROUGH */ 846 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 847 /* never use invalid T(a_wait_bcon) */ 848 DBG(1, "HNP: in %s, %d msec timeout\n", 849 otg_state_string(musb), 850 TA_WAIT_BCON(musb)); 851 mod_timer(&musb->otg_timer, jiffies 852 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 853 break; 854 case OTG_STATE_A_PERIPHERAL: 855 musb->ignore_disconnect = 0; 856 del_timer(&musb->otg_timer); 857 musb_g_reset(musb); 858 break; 859 case OTG_STATE_B_WAIT_ACON: 860 DBG(1, "HNP: RESET (%s), to b_peripheral\n", 861 otg_state_string(musb)); 862 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 863 musb_g_reset(musb); 864 break; 865#endif 866 case OTG_STATE_B_IDLE: 867 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 868 /* FALLTHROUGH */ 869 case OTG_STATE_B_PERIPHERAL: 870 musb_g_reset(musb); 871 break; 872 default: 873 DBG(1, "Unhandled BUS RESET as %s\n", 874 otg_state_string(musb)); 875 } 876 } 877 } 878 879#if 0 880/* REVISIT ... this would be for multiplexing periodic endpoints, or 881 * supporting transfer phasing to prevent exceeding ISO bandwidth 882 * limits of a given frame or microframe. 883 * 884 * It's not needed for peripheral side, which dedicates endpoints; 885 * though it _might_ use SOF irqs for other purposes. 886 * 887 * And it's not currently needed for host side, which also dedicates 888 * endpoints, relies on TX/RX interval registers, and isn't claimed 889 * to support ISO transfers yet. 890 */ 891 if (int_usb & MUSB_INTR_SOF) { 892 void __iomem *mbase = musb->mregs; 893 struct musb_hw_ep *ep; 894 u8 epnum; 895 u16 frame; 896 897 DBG(6, "START_OF_FRAME\n"); 898 handled = IRQ_HANDLED; 899 900 /* start any periodic Tx transfers waiting for current frame */ 901 frame = musb_readw(mbase, MUSB_FRAME); 902 ep = musb->endpoints; 903 for (epnum = 1; (epnum < musb->nr_endpoints) 904 && (musb->epmask >= (1 << epnum)); 905 epnum++, ep++) { 906 /* 907 * FIXME handle framecounter wraps (12 bits) 908 * eliminate duplicated StartUrb logic 909 */ 910 if (ep->dwWaitFrame >= frame) { 911 ep->dwWaitFrame = 0; 912 pr_debug("SOF --> periodic TX%s on %d\n", 913 ep->tx_channel ? " DMA" : "", 914 epnum); 915 if (!ep->tx_channel) 916 musb_h_tx_start(musb, epnum); 917 else 918 cppi_hostdma_start(musb, epnum); 919 } 920 } /* end of for loop */ 921 } 922#endif 923 924 schedule_work(&musb->irq_work); 925 926 return handled; 927} 928 929/*-------------------------------------------------------------------------*/ 930 931/* 932* Program the HDRC to start (enable interrupts, dma, etc.). 933*/ 934void musb_start(struct musb *musb) 935{ 936 void __iomem *regs = musb->mregs; 937 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 938 939 DBG(2, "<== devctl %02x\n", devctl); 940 941 /* Set INT enable registers, enable interrupts */ 942 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 943 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 944 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 945 946 musb_writeb(regs, MUSB_TESTMODE, 0); 947 948 /* put into basic highspeed mode and start session */ 949 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 950 | MUSB_POWER_SOFTCONN 951 | MUSB_POWER_HSENAB 952 /* ENSUSPEND wedges tusb */ 953 /* | MUSB_POWER_ENSUSPEND */ 954 ); 955 956 musb->is_active = 0; 957 devctl = musb_readb(regs, MUSB_DEVCTL); 958 devctl &= ~MUSB_DEVCTL_SESSION; 959 960 if (is_otg_enabled(musb)) { 961 /* session started after: 962 * (a) ID-grounded irq, host mode; 963 * (b) vbus present/connect IRQ, peripheral mode; 964 * (c) peripheral initiates, using SRP 965 */ 966 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 967 musb->is_active = 1; 968 else 969 devctl |= MUSB_DEVCTL_SESSION; 970 971 } else if (is_host_enabled(musb)) { 972 /* assume ID pin is hard-wired to ground */ 973 devctl |= MUSB_DEVCTL_SESSION; 974 975 } else /* peripheral is enabled */ { 976 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 977 musb->is_active = 1; 978 } 979 musb_platform_enable(musb); 980 musb_writeb(regs, MUSB_DEVCTL, devctl); 981} 982 983 984static void musb_generic_disable(struct musb *musb) 985{ 986 void __iomem *mbase = musb->mregs; 987 u16 temp; 988 989 /* disable interrupts */ 990 musb_writeb(mbase, MUSB_INTRUSBE, 0); 991 musb_writew(mbase, MUSB_INTRTXE, 0); 992 musb_writew(mbase, MUSB_INTRRXE, 0); 993 994 /* off */ 995 musb_writeb(mbase, MUSB_DEVCTL, 0); 996 997 /* flush pending interrupts */ 998 temp = musb_readb(mbase, MUSB_INTRUSB); 999 temp = musb_readw(mbase, MUSB_INTRTX); 1000 temp = musb_readw(mbase, MUSB_INTRRX); 1001 1002} 1003 1004/* 1005 * Make the HDRC stop (disable interrupts, etc.); 1006 * reversible by musb_start 1007 * called on gadget driver unregister 1008 * with controller locked, irqs blocked 1009 * acts as a NOP unless some role activated the hardware 1010 */ 1011void musb_stop(struct musb *musb) 1012{ 1013 /* stop IRQs, timers, ... */ 1014 musb_platform_disable(musb); 1015 musb_generic_disable(musb); 1016 DBG(3, "HDRC disabled\n"); 1017 1018 /* FIXME 1019 * - mark host and/or peripheral drivers unusable/inactive 1020 * - disable DMA (and enable it in HdrcStart) 1021 * - make sure we can musb_start() after musb_stop(); with 1022 * OTG mode, gadget driver module rmmod/modprobe cycles that 1023 * - ... 1024 */ 1025 musb_platform_try_idle(musb, 0); 1026} 1027 1028static void musb_shutdown(struct platform_device *pdev) 1029{ 1030 struct musb *musb = dev_to_musb(&pdev->dev); 1031 unsigned long flags; 1032 1033 spin_lock_irqsave(&musb->lock, flags); 1034 musb_platform_disable(musb); 1035 musb_generic_disable(musb); 1036 spin_unlock_irqrestore(&musb->lock, flags); 1037 1038 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 1039 usb_remove_hcd(musb_to_hcd(musb)); 1040 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1041 musb_platform_exit(musb); 1042 1043 /* FIXME power down */ 1044} 1045 1046 1047/*-------------------------------------------------------------------------*/ 1048 1049/* 1050 * The silicon either has hard-wired endpoint configurations, or else 1051 * "dynamic fifo" sizing. The driver has support for both, though at this 1052 * writing only the dynamic sizing is very well tested. Since we switched 1053 * away from compile-time hardware parameters, we can no longer rely on 1054 * dead code elimination to leave only the relevant one in the object file. 1055 * 1056 * We don't currently use dynamic fifo setup capability to do anything 1057 * more than selecting one of a bunch of predefined configurations. 1058 */ 1059#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ 1060 || defined(CONFIG_USB_MUSB_AM35X) 1061static ushort __initdata fifo_mode = 4; 1062#elif defined(CONFIG_USB_MUSB_UX500) 1063static ushort __initdata fifo_mode = 5; 1064#else 1065static ushort __initdata fifo_mode = 2; 1066#endif 1067 1068/* "modprobe ... fifo_mode=1" etc */ 1069module_param(fifo_mode, ushort, 0); 1070MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1071 1072/* 1073 * tables defining fifo_mode values. define more if you like. 1074 * for host side, make sure both halves of ep1 are set up. 1075 */ 1076 1077/* mode 0 - fits in 2KB */ 1078static struct musb_fifo_cfg __initdata mode_0_cfg[] = { 1079{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1080{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1081{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1082{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1083{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1084}; 1085 1086/* mode 1 - fits in 4KB */ 1087static struct musb_fifo_cfg __initdata mode_1_cfg[] = { 1088{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1089{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1090{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1091{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1092{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1093}; 1094 1095/* mode 2 - fits in 4KB */ 1096static struct musb_fifo_cfg __initdata mode_2_cfg[] = { 1097{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1098{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1099{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1100{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1101{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1102{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1103}; 1104 1105/* mode 3 - fits in 4KB */ 1106static struct musb_fifo_cfg __initdata mode_3_cfg[] = { 1107{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1108{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1109{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1110{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1111{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1112{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1113}; 1114 1115/* mode 4 - fits in 16KB */ 1116static struct musb_fifo_cfg __initdata mode_4_cfg[] = { 1117{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1118{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1119{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1120{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1121{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1122{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1123{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1124{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1125{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1126{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1127{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1128{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1129{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1130{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1131{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1132{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1133{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1134{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1135{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1136{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1137{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1138{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1139{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1140{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1141{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1142{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1143{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1144}; 1145 1146/* mode 5 - fits in 8KB */ 1147static struct musb_fifo_cfg __initdata mode_5_cfg[] = { 1148{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1149{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1150{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1151{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1152{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1153{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1154{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1155{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1156{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1157{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1158{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1159{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1160{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1161{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1162{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1163{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1164{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1165{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1166{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1167{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1168{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1169{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1170{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1171{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1172{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1173{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1174{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1175}; 1176 1177/* 1178 * configure a fifo; for non-shared endpoints, this may be called 1179 * once for a tx fifo and once for an rx fifo. 1180 * 1181 * returns negative errno or offset for next fifo. 1182 */ 1183static int __init 1184fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1185 const struct musb_fifo_cfg *cfg, u16 offset) 1186{ 1187 void __iomem *mbase = musb->mregs; 1188 int size = 0; 1189 u16 maxpacket = cfg->maxpacket; 1190 u16 c_off = offset >> 3; 1191 u8 c_size; 1192 1193 /* expect hw_ep has already been zero-initialized */ 1194 1195 size = ffs(max(maxpacket, (u16) 8)) - 1; 1196 maxpacket = 1 << size; 1197 1198 c_size = size - 3; 1199 if (cfg->mode == BUF_DOUBLE) { 1200 if ((offset + (maxpacket << 1)) > 1201 (1 << (musb->config->ram_bits + 2))) 1202 return -EMSGSIZE; 1203 c_size |= MUSB_FIFOSZ_DPB; 1204 } else { 1205 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1206 return -EMSGSIZE; 1207 } 1208 1209 /* configure the FIFO */ 1210 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1211 1212#ifdef CONFIG_USB_MUSB_HDRC_HCD 1213 /* EP0 reserved endpoint for control, bidirectional; 1214 * EP1 reserved for bulk, two unidirection halves. 1215 */ 1216 if (hw_ep->epnum == 1) 1217 musb->bulk_ep = hw_ep; 1218 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1219#endif 1220 switch (cfg->style) { 1221 case FIFO_TX: 1222 musb_write_txfifosz(mbase, c_size); 1223 musb_write_txfifoadd(mbase, c_off); 1224 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1225 hw_ep->max_packet_sz_tx = maxpacket; 1226 break; 1227 case FIFO_RX: 1228 musb_write_rxfifosz(mbase, c_size); 1229 musb_write_rxfifoadd(mbase, c_off); 1230 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1231 hw_ep->max_packet_sz_rx = maxpacket; 1232 break; 1233 case FIFO_RXTX: 1234 musb_write_txfifosz(mbase, c_size); 1235 musb_write_txfifoadd(mbase, c_off); 1236 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1237 hw_ep->max_packet_sz_rx = maxpacket; 1238 1239 musb_write_rxfifosz(mbase, c_size); 1240 musb_write_rxfifoadd(mbase, c_off); 1241 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1242 hw_ep->max_packet_sz_tx = maxpacket; 1243 1244 hw_ep->is_shared_fifo = true; 1245 break; 1246 } 1247 1248 /* NOTE rx and tx endpoint irqs aren't managed separately, 1249 * which happens to be ok 1250 */ 1251 musb->epmask |= (1 << hw_ep->epnum); 1252 1253 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1254} 1255 1256static struct musb_fifo_cfg __initdata ep0_cfg = { 1257 .style = FIFO_RXTX, .maxpacket = 64, 1258}; 1259 1260static int __init ep_config_from_table(struct musb *musb) 1261{ 1262 const struct musb_fifo_cfg *cfg; 1263 unsigned i, n; 1264 int offset; 1265 struct musb_hw_ep *hw_ep = musb->endpoints; 1266 1267 if (musb->config->fifo_cfg) { 1268 cfg = musb->config->fifo_cfg; 1269 n = musb->config->fifo_cfg_size; 1270 goto done; 1271 } 1272 1273 switch (fifo_mode) { 1274 default: 1275 fifo_mode = 0; 1276 /* FALLTHROUGH */ 1277 case 0: 1278 cfg = mode_0_cfg; 1279 n = ARRAY_SIZE(mode_0_cfg); 1280 break; 1281 case 1: 1282 cfg = mode_1_cfg; 1283 n = ARRAY_SIZE(mode_1_cfg); 1284 break; 1285 case 2: 1286 cfg = mode_2_cfg; 1287 n = ARRAY_SIZE(mode_2_cfg); 1288 break; 1289 case 3: 1290 cfg = mode_3_cfg; 1291 n = ARRAY_SIZE(mode_3_cfg); 1292 break; 1293 case 4: 1294 cfg = mode_4_cfg; 1295 n = ARRAY_SIZE(mode_4_cfg); 1296 break; 1297 case 5: 1298 cfg = mode_5_cfg; 1299 n = ARRAY_SIZE(mode_5_cfg); 1300 break; 1301 } 1302 1303 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1304 musb_driver_name, fifo_mode); 1305 1306 1307done: 1308 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1309 /* assert(offset > 0) */ 1310 1311 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1312 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1313 */ 1314 1315 for (i = 0; i < n; i++) { 1316 u8 epn = cfg->hw_ep_num; 1317 1318 if (epn >= musb->config->num_eps) { 1319 pr_debug("%s: invalid ep %d\n", 1320 musb_driver_name, epn); 1321 return -EINVAL; 1322 } 1323 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1324 if (offset < 0) { 1325 pr_debug("%s: mem overrun, ep %d\n", 1326 musb_driver_name, epn); 1327 return -EINVAL; 1328 } 1329 epn++; 1330 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1331 } 1332 1333 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1334 musb_driver_name, 1335 n + 1, musb->config->num_eps * 2 - 1, 1336 offset, (1 << (musb->config->ram_bits + 2))); 1337 1338#ifdef CONFIG_USB_MUSB_HDRC_HCD 1339 if (!musb->bulk_ep) { 1340 pr_debug("%s: missing bulk\n", musb_driver_name); 1341 return -EINVAL; 1342 } 1343#endif 1344 1345 return 0; 1346} 1347 1348 1349/* 1350 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1351 * @param musb the controller 1352 */ 1353static int __init ep_config_from_hw(struct musb *musb) 1354{ 1355 u8 epnum = 0; 1356 struct musb_hw_ep *hw_ep; 1357 void *mbase = musb->mregs; 1358 int ret = 0; 1359 1360 DBG(2, "<== static silicon ep config\n"); 1361 1362 /* FIXME pick up ep0 maxpacket size */ 1363 1364 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1365 musb_ep_select(mbase, epnum); 1366 hw_ep = musb->endpoints + epnum; 1367 1368 ret = musb_read_fifosize(musb, hw_ep, epnum); 1369 if (ret < 0) 1370 break; 1371 1372 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1373 1374#ifdef CONFIG_USB_MUSB_HDRC_HCD 1375 /* pick an RX/TX endpoint for bulk */ 1376 if (hw_ep->max_packet_sz_tx < 512 1377 || hw_ep->max_packet_sz_rx < 512) 1378 continue; 1379 1380 /* REVISIT: this algorithm is lazy, we should at least 1381 * try to pick a double buffered endpoint. 1382 */ 1383 if (musb->bulk_ep) 1384 continue; 1385 musb->bulk_ep = hw_ep; 1386#endif 1387 } 1388 1389#ifdef CONFIG_USB_MUSB_HDRC_HCD 1390 if (!musb->bulk_ep) { 1391 pr_debug("%s: missing bulk\n", musb_driver_name); 1392 return -EINVAL; 1393 } 1394#endif 1395 1396 return 0; 1397} 1398 1399enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1400 1401/* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1402 * configure endpoints, or take their config from silicon 1403 */ 1404static int __init musb_core_init(u16 musb_type, struct musb *musb) 1405{ 1406 u8 reg; 1407 char *type; 1408 char aInfo[90], aRevision[32], aDate[12]; 1409 void __iomem *mbase = musb->mregs; 1410 int status = 0; 1411 int i; 1412 1413 /* log core options (read using indexed model) */ 1414 reg = musb_read_configdata(mbase); 1415 1416 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1417 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1418 strcat(aInfo, ", dyn FIFOs"); 1419 musb->dyn_fifo = true; 1420 } 1421 if (reg & MUSB_CONFIGDATA_MPRXE) { 1422 strcat(aInfo, ", bulk combine"); 1423 musb->bulk_combine = true; 1424 } 1425 if (reg & MUSB_CONFIGDATA_MPTXE) { 1426 strcat(aInfo, ", bulk split"); 1427 musb->bulk_split = true; 1428 } 1429 if (reg & MUSB_CONFIGDATA_HBRXE) { 1430 strcat(aInfo, ", HB-ISO Rx"); 1431 musb->hb_iso_rx = true; 1432 } 1433 if (reg & MUSB_CONFIGDATA_HBTXE) { 1434 strcat(aInfo, ", HB-ISO Tx"); 1435 musb->hb_iso_tx = true; 1436 } 1437 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1438 strcat(aInfo, ", SoftConn"); 1439 1440 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1441 musb_driver_name, reg, aInfo); 1442 1443 aDate[0] = 0; 1444 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1445 musb->is_multipoint = 1; 1446 type = "M"; 1447 } else { 1448 musb->is_multipoint = 0; 1449 type = ""; 1450#ifdef CONFIG_USB_MUSB_HDRC_HCD 1451#ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1452 printk(KERN_ERR 1453 "%s: kernel must blacklist external hubs\n", 1454 musb_driver_name); 1455#endif 1456#endif 1457 } 1458 1459 /* log release info */ 1460 musb->hwvers = musb_read_hwvers(mbase); 1461 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1462 MUSB_HWVERS_MINOR(musb->hwvers), 1463 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1464 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1465 musb_driver_name, type, aRevision, aDate); 1466 1467 /* configure ep0 */ 1468 musb_configure_ep0(musb); 1469 1470 /* discover endpoint configuration */ 1471 musb->nr_endpoints = 1; 1472 musb->epmask = 1; 1473 1474 if (musb->dyn_fifo) 1475 status = ep_config_from_table(musb); 1476 else 1477 status = ep_config_from_hw(musb); 1478 1479 if (status < 0) 1480 return status; 1481 1482 /* finish init, and print endpoint config */ 1483 for (i = 0; i < musb->nr_endpoints; i++) { 1484 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1485 1486 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1487#ifdef CONFIG_USB_MUSB_TUSB6010 1488 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1489 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1490 hw_ep->fifo_sync_va = 1491 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1492 1493 if (i == 0) 1494 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1495 else 1496 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1497#endif 1498 1499 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1500#ifdef CONFIG_USB_MUSB_HDRC_HCD 1501 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1502 hw_ep->rx_reinit = 1; 1503 hw_ep->tx_reinit = 1; 1504#endif 1505 1506 if (hw_ep->max_packet_sz_tx) { 1507 DBG(1, 1508 "%s: hw_ep %d%s, %smax %d\n", 1509 musb_driver_name, i, 1510 hw_ep->is_shared_fifo ? "shared" : "tx", 1511 hw_ep->tx_double_buffered 1512 ? "doublebuffer, " : "", 1513 hw_ep->max_packet_sz_tx); 1514 } 1515 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1516 DBG(1, 1517 "%s: hw_ep %d%s, %smax %d\n", 1518 musb_driver_name, i, 1519 "rx", 1520 hw_ep->rx_double_buffered 1521 ? "doublebuffer, " : "", 1522 hw_ep->max_packet_sz_rx); 1523 } 1524 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1525 DBG(1, "hw_ep %d not configured\n", i); 1526 } 1527 1528 return 0; 1529} 1530 1531/*-------------------------------------------------------------------------*/ 1532 1533#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \ 1534 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \ 1535 defined(CONFIG_ARCH_U5500) 1536 1537static irqreturn_t generic_interrupt(int irq, void *__hci) 1538{ 1539 unsigned long flags; 1540 irqreturn_t retval = IRQ_NONE; 1541 struct musb *musb = __hci; 1542 1543 spin_lock_irqsave(&musb->lock, flags); 1544 1545 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1546 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1547 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1548 1549 if (musb->int_usb || musb->int_tx || musb->int_rx) 1550 retval = musb_interrupt(musb); 1551 1552 spin_unlock_irqrestore(&musb->lock, flags); 1553 1554 return retval; 1555} 1556 1557#else 1558#define generic_interrupt NULL 1559#endif 1560 1561/* 1562 * handle all the irqs defined by the HDRC core. for now we expect: other 1563 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1564 * will be assigned, and the irq will already have been acked. 1565 * 1566 * called in irq context with spinlock held, irqs blocked 1567 */ 1568irqreturn_t musb_interrupt(struct musb *musb) 1569{ 1570 irqreturn_t retval = IRQ_NONE; 1571 u8 devctl, power; 1572 int ep_num; 1573 u32 reg; 1574 1575 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1576 power = musb_readb(musb->mregs, MUSB_POWER); 1577 1578 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n", 1579 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1580 musb->int_usb, musb->int_tx, musb->int_rx); 1581 1582#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1583 if (is_otg_enabled(musb) || is_peripheral_enabled(musb)) 1584 if (!musb->gadget_driver) { 1585 DBG(5, "No gadget driver loaded\n"); 1586 return IRQ_HANDLED; 1587 } 1588#endif 1589 1590 /* the core can interrupt us for multiple reasons; docs have 1591 * a generic interrupt flowchart to follow 1592 */ 1593 if (musb->int_usb) 1594 retval |= musb_stage0_irq(musb, musb->int_usb, 1595 devctl, power); 1596 1597 /* "stage 1" is handling endpoint irqs */ 1598 1599 /* handle endpoint 0 first */ 1600 if (musb->int_tx & 1) { 1601 if (devctl & MUSB_DEVCTL_HM) 1602 retval |= musb_h_ep0_irq(musb); 1603 else 1604 retval |= musb_g_ep0_irq(musb); 1605 } 1606 1607 /* RX on endpoints 1-15 */ 1608 reg = musb->int_rx >> 1; 1609 ep_num = 1; 1610 while (reg) { 1611 if (reg & 1) { 1612 /* musb_ep_select(musb->mregs, ep_num); */ 1613 /* REVISIT just retval = ep->rx_irq(...) */ 1614 retval = IRQ_HANDLED; 1615 if (devctl & MUSB_DEVCTL_HM) { 1616 if (is_host_capable()) 1617 musb_host_rx(musb, ep_num); 1618 } else { 1619 if (is_peripheral_capable()) 1620 musb_g_rx(musb, ep_num); 1621 } 1622 } 1623 1624 reg >>= 1; 1625 ep_num++; 1626 } 1627 1628 /* TX on endpoints 1-15 */ 1629 reg = musb->int_tx >> 1; 1630 ep_num = 1; 1631 while (reg) { 1632 if (reg & 1) { 1633 /* musb_ep_select(musb->mregs, ep_num); */ 1634 /* REVISIT just retval |= ep->tx_irq(...) */ 1635 retval = IRQ_HANDLED; 1636 if (devctl & MUSB_DEVCTL_HM) { 1637 if (is_host_capable()) 1638 musb_host_tx(musb, ep_num); 1639 } else { 1640 if (is_peripheral_capable()) 1641 musb_g_tx(musb, ep_num); 1642 } 1643 } 1644 reg >>= 1; 1645 ep_num++; 1646 } 1647 1648 return retval; 1649} 1650 1651 1652#ifndef CONFIG_MUSB_PIO_ONLY 1653static int __initdata use_dma = 1; 1654 1655/* "modprobe ... use_dma=0" etc */ 1656module_param(use_dma, bool, 0); 1657MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1658 1659void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1660{ 1661 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1662 1663 /* called with controller lock already held */ 1664 1665 if (!epnum) { 1666#ifndef CONFIG_USB_TUSB_OMAP_DMA 1667 if (!is_cppi_enabled()) { 1668 /* endpoint 0 */ 1669 if (devctl & MUSB_DEVCTL_HM) 1670 musb_h_ep0_irq(musb); 1671 else 1672 musb_g_ep0_irq(musb); 1673 } 1674#endif 1675 } else { 1676 /* endpoints 1..15 */ 1677 if (transmit) { 1678 if (devctl & MUSB_DEVCTL_HM) { 1679 if (is_host_capable()) 1680 musb_host_tx(musb, epnum); 1681 } else { 1682 if (is_peripheral_capable()) 1683 musb_g_tx(musb, epnum); 1684 } 1685 } else { 1686 /* receive */ 1687 if (devctl & MUSB_DEVCTL_HM) { 1688 if (is_host_capable()) 1689 musb_host_rx(musb, epnum); 1690 } else { 1691 if (is_peripheral_capable()) 1692 musb_g_rx(musb, epnum); 1693 } 1694 } 1695 } 1696} 1697 1698#else 1699#define use_dma 0 1700#endif 1701 1702/*-------------------------------------------------------------------------*/ 1703 1704#ifdef CONFIG_SYSFS 1705 1706static ssize_t 1707musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1708{ 1709 struct musb *musb = dev_to_musb(dev); 1710 unsigned long flags; 1711 int ret = -EINVAL; 1712 1713 spin_lock_irqsave(&musb->lock, flags); 1714 ret = sprintf(buf, "%s\n", otg_state_string(musb)); 1715 spin_unlock_irqrestore(&musb->lock, flags); 1716 1717 return ret; 1718} 1719 1720static ssize_t 1721musb_mode_store(struct device *dev, struct device_attribute *attr, 1722 const char *buf, size_t n) 1723{ 1724 struct musb *musb = dev_to_musb(dev); 1725 unsigned long flags; 1726 int status; 1727 1728 spin_lock_irqsave(&musb->lock, flags); 1729 if (sysfs_streq(buf, "host")) 1730 status = musb_platform_set_mode(musb, MUSB_HOST); 1731 else if (sysfs_streq(buf, "peripheral")) 1732 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1733 else if (sysfs_streq(buf, "otg")) 1734 status = musb_platform_set_mode(musb, MUSB_OTG); 1735 else 1736 status = -EINVAL; 1737 spin_unlock_irqrestore(&musb->lock, flags); 1738 1739 return (status == 0) ? n : status; 1740} 1741static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1742 1743static ssize_t 1744musb_vbus_store(struct device *dev, struct device_attribute *attr, 1745 const char *buf, size_t n) 1746{ 1747 struct musb *musb = dev_to_musb(dev); 1748 unsigned long flags; 1749 unsigned long val; 1750 1751 if (sscanf(buf, "%lu", &val) < 1) { 1752 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1753 return -EINVAL; 1754 } 1755 1756 spin_lock_irqsave(&musb->lock, flags); 1757 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1758 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1759 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1760 musb->is_active = 0; 1761 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1762 spin_unlock_irqrestore(&musb->lock, flags); 1763 1764 return n; 1765} 1766 1767static ssize_t 1768musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1769{ 1770 struct musb *musb = dev_to_musb(dev); 1771 unsigned long flags; 1772 unsigned long val; 1773 int vbus; 1774 1775 spin_lock_irqsave(&musb->lock, flags); 1776 val = musb->a_wait_bcon; 1777 /* FIXME get_vbus_status() is normally #defined as false... 1778 * and is effectively TUSB-specific. 1779 */ 1780 vbus = musb_platform_get_vbus_status(musb); 1781 spin_unlock_irqrestore(&musb->lock, flags); 1782 1783 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1784 vbus ? "on" : "off", val); 1785} 1786static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1787 1788#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1789 1790/* Gadget drivers can't know that a host is connected so they might want 1791 * to start SRP, but users can. This allows userspace to trigger SRP. 1792 */ 1793static ssize_t 1794musb_srp_store(struct device *dev, struct device_attribute *attr, 1795 const char *buf, size_t n) 1796{ 1797 struct musb *musb = dev_to_musb(dev); 1798 unsigned short srp; 1799 1800 if (sscanf(buf, "%hu", &srp) != 1 1801 || (srp != 1)) { 1802 dev_err(dev, "SRP: Value must be 1\n"); 1803 return -EINVAL; 1804 } 1805 1806 if (srp == 1) 1807 musb_g_wakeup(musb); 1808 1809 return n; 1810} 1811static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1812 1813#endif /* CONFIG_USB_GADGET_MUSB_HDRC */ 1814 1815static struct attribute *musb_attributes[] = { 1816 &dev_attr_mode.attr, 1817 &dev_attr_vbus.attr, 1818#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1819 &dev_attr_srp.attr, 1820#endif 1821 NULL 1822}; 1823 1824static const struct attribute_group musb_attr_group = { 1825 .attrs = musb_attributes, 1826}; 1827 1828#endif /* sysfs */ 1829 1830/* Only used to provide driver mode change events */ 1831static void musb_irq_work(struct work_struct *data) 1832{ 1833 struct musb *musb = container_of(data, struct musb, irq_work); 1834 static int old_state; 1835 1836 if (musb->xceiv->state != old_state) { 1837 old_state = musb->xceiv->state; 1838 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1839 } 1840} 1841 1842/* -------------------------------------------------------------------------- 1843 * Init support 1844 */ 1845 1846static struct musb *__init 1847allocate_instance(struct device *dev, 1848 struct musb_hdrc_config *config, void __iomem *mbase) 1849{ 1850 struct musb *musb; 1851 struct musb_hw_ep *ep; 1852 int epnum; 1853#ifdef CONFIG_USB_MUSB_HDRC_HCD 1854 struct usb_hcd *hcd; 1855 1856 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1857 if (!hcd) 1858 return NULL; 1859 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1860 1861 musb = hcd_to_musb(hcd); 1862 INIT_LIST_HEAD(&musb->control); 1863 INIT_LIST_HEAD(&musb->in_bulk); 1864 INIT_LIST_HEAD(&musb->out_bulk); 1865 1866 hcd->uses_new_polling = 1; 1867 1868 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1869 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1870#else 1871 musb = kzalloc(sizeof *musb, GFP_KERNEL); 1872 if (!musb) 1873 return NULL; 1874 1875#endif 1876 dev_set_drvdata(dev, musb); 1877 musb->mregs = mbase; 1878 musb->ctrl_base = mbase; 1879 musb->nIrq = -ENODEV; 1880 musb->config = config; 1881 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1882 for (epnum = 0, ep = musb->endpoints; 1883 epnum < musb->config->num_eps; 1884 epnum++, ep++) { 1885 ep->musb = musb; 1886 ep->epnum = epnum; 1887 } 1888 1889 musb->controller = dev; 1890 1891 return musb; 1892} 1893 1894static void musb_free(struct musb *musb) 1895{ 1896 /* this has multiple entry modes. it handles fault cleanup after 1897 * probe(), where things may be partially set up, as well as rmmod 1898 * cleanup after everything's been de-activated. 1899 */ 1900 1901#ifdef CONFIG_SYSFS 1902 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1903#endif 1904 1905#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1906 musb_gadget_cleanup(musb); 1907#endif 1908 1909 if (musb->nIrq >= 0) { 1910 if (musb->irq_wake) 1911 disable_irq_wake(musb->nIrq); 1912 free_irq(musb->nIrq, musb); 1913 } 1914 if (is_dma_capable() && musb->dma_controller) { 1915 struct dma_controller *c = musb->dma_controller; 1916 1917 (void) c->stop(c); 1918 dma_controller_destroy(c); 1919 } 1920 1921#ifdef CONFIG_USB_MUSB_HDRC_HCD 1922 usb_put_hcd(musb_to_hcd(musb)); 1923#else 1924 kfree(musb); 1925#endif 1926} 1927 1928/* 1929 * Perform generic per-controller initialization. 1930 * 1931 * @pDevice: the controller (already clocked, etc) 1932 * @nIrq: irq 1933 * @mregs: virtual address of controller registers, 1934 * not yet corrected for platform-specific offsets 1935 */ 1936static int __init 1937musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1938{ 1939 int status; 1940 struct musb *musb; 1941 struct musb_hdrc_platform_data *plat = dev->platform_data; 1942 1943 /* The driver might handle more features than the board; OK. 1944 * Fail when the board needs a feature that's not enabled. 1945 */ 1946 if (!plat) { 1947 dev_dbg(dev, "no platform_data?\n"); 1948 status = -ENODEV; 1949 goto fail0; 1950 } 1951 1952 switch (plat->mode) { 1953 case MUSB_HOST: 1954#ifdef CONFIG_USB_MUSB_HDRC_HCD 1955 break; 1956#else 1957 goto bad_config; 1958#endif 1959 case MUSB_PERIPHERAL: 1960#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1961 break; 1962#else 1963 goto bad_config; 1964#endif 1965 case MUSB_OTG: 1966#ifdef CONFIG_USB_MUSB_OTG 1967 break; 1968#else 1969bad_config: 1970#endif 1971 default: 1972 dev_err(dev, "incompatible Kconfig role setting\n"); 1973 status = -EINVAL; 1974 goto fail0; 1975 } 1976 1977 /* allocate */ 1978 musb = allocate_instance(dev, plat->config, ctrl); 1979 if (!musb) { 1980 status = -ENOMEM; 1981 goto fail0; 1982 } 1983 1984 spin_lock_init(&musb->lock); 1985 musb->board_mode = plat->mode; 1986 musb->board_set_power = plat->set_power; 1987 musb->min_power = plat->min_power; 1988 musb->ops = plat->platform_ops; 1989 1990 /* The musb_platform_init() call: 1991 * - adjusts musb->mregs and musb->isr if needed, 1992 * - may initialize an integrated tranceiver 1993 * - initializes musb->xceiv, usually by otg_get_transceiver() 1994 * - stops powering VBUS 1995 * 1996 * There are various transciever configurations. Blackfin, 1997 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1998 * external/discrete ones in various flavors (twl4030 family, 1999 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 2000 */ 2001 musb->isr = generic_interrupt; 2002 status = musb_platform_init(musb); 2003 if (status < 0) 2004 goto fail1; 2005 2006 if (!musb->isr) { 2007 status = -ENODEV; 2008 goto fail3; 2009 } 2010 2011 if (!musb->xceiv->io_ops) { 2012 musb->xceiv->io_priv = musb->mregs; 2013 musb->xceiv->io_ops = &musb_ulpi_access; 2014 } 2015 2016#ifndef CONFIG_MUSB_PIO_ONLY 2017 if (use_dma && dev->dma_mask) { 2018 struct dma_controller *c; 2019 2020 c = dma_controller_create(musb, musb->mregs); 2021 musb->dma_controller = c; 2022 if (c) 2023 (void) c->start(c); 2024 } 2025#endif 2026 /* ideally this would be abstracted in platform setup */ 2027 if (!is_dma_capable() || !musb->dma_controller) 2028 dev->dma_mask = NULL; 2029 2030 /* be sure interrupts are disabled before connecting ISR */ 2031 musb_platform_disable(musb); 2032 musb_generic_disable(musb); 2033 2034 /* setup musb parts of the core (especially endpoints) */ 2035 status = musb_core_init(plat->config->multipoint 2036 ? MUSB_CONTROLLER_MHDRC 2037 : MUSB_CONTROLLER_HDRC, musb); 2038 if (status < 0) 2039 goto fail3; 2040 2041#ifdef CONFIG_USB_MUSB_OTG 2042 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 2043#endif 2044 2045 /* Init IRQ workqueue before request_irq */ 2046 INIT_WORK(&musb->irq_work, musb_irq_work); 2047 2048 /* attach to the IRQ */ 2049 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 2050 dev_err(dev, "request_irq %d failed!\n", nIrq); 2051 status = -ENODEV; 2052 goto fail3; 2053 } 2054 musb->nIrq = nIrq; 2055/* FIXME this handles wakeup irqs wrong */ 2056 if (enable_irq_wake(nIrq) == 0) { 2057 musb->irq_wake = 1; 2058 device_init_wakeup(dev, 1); 2059 } else { 2060 musb->irq_wake = 0; 2061 } 2062 2063 /* host side needs more setup */ 2064 if (is_host_enabled(musb)) { 2065 struct usb_hcd *hcd = musb_to_hcd(musb); 2066 2067 otg_set_host(musb->xceiv, &hcd->self); 2068 2069 if (is_otg_enabled(musb)) 2070 hcd->self.otg_port = 1; 2071 musb->xceiv->host = &hcd->self; 2072 hcd->power_budget = 2 * (plat->power ? : 250); 2073 2074 /* program PHY to use external vBus if required */ 2075 if (plat->extvbus) { 2076 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2077 busctl |= MUSB_ULPI_USE_EXTVBUS; 2078 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2079 } 2080 } 2081 2082 /* For the host-only role, we can activate right away. 2083 * (We expect the ID pin to be forcibly grounded!!) 2084 * Otherwise, wait till the gadget driver hooks up. 2085 */ 2086 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2087 struct usb_hcd *hcd = musb_to_hcd(musb); 2088 2089 MUSB_HST_MODE(musb); 2090 musb->xceiv->default_a = 1; 2091 musb->xceiv->state = OTG_STATE_A_IDLE; 2092 2093 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 2094 2095 hcd->self.uses_pio_for_control = 1; 2096 DBG(1, "%s mode, status %d, devctl %02x %c\n", 2097 "HOST", status, 2098 musb_readb(musb->mregs, MUSB_DEVCTL), 2099 (musb_readb(musb->mregs, MUSB_DEVCTL) 2100 & MUSB_DEVCTL_BDEVICE 2101 ? 'B' : 'A')); 2102 2103 } else /* peripheral is enabled */ { 2104 MUSB_DEV_MODE(musb); 2105 musb->xceiv->default_a = 0; 2106 musb->xceiv->state = OTG_STATE_B_IDLE; 2107 2108 status = musb_gadget_setup(musb); 2109 2110 DBG(1, "%s mode, status %d, dev%02x\n", 2111 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2112 status, 2113 musb_readb(musb->mregs, MUSB_DEVCTL)); 2114 2115 } 2116 if (status < 0) 2117 goto fail3; 2118 2119 status = musb_init_debugfs(musb); 2120 if (status < 0) 2121 goto fail4; 2122 2123#ifdef CONFIG_SYSFS 2124 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2125 if (status) 2126 goto fail5; 2127#endif 2128 2129 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", 2130 ({char *s; 2131 switch (musb->board_mode) { 2132 case MUSB_HOST: s = "Host"; break; 2133 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2134 default: s = "OTG"; break; 2135 }; s; }), 2136 ctrl, 2137 (is_dma_capable() && musb->dma_controller) 2138 ? "DMA" : "PIO", 2139 musb->nIrq); 2140 2141 return 0; 2142 2143fail5: 2144 musb_exit_debugfs(musb); 2145 2146fail4: 2147 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 2148 usb_remove_hcd(musb_to_hcd(musb)); 2149 else 2150 musb_gadget_cleanup(musb); 2151 2152fail3: 2153 if (musb->irq_wake) 2154 device_init_wakeup(dev, 0); 2155 musb_platform_exit(musb); 2156 2157fail1: 2158 dev_err(musb->controller, 2159 "musb_init_controller failed with status %d\n", status); 2160 2161 musb_free(musb); 2162 2163fail0: 2164 2165 return status; 2166 2167} 2168 2169/*-------------------------------------------------------------------------*/ 2170 2171/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2172 * bridge to a platform device; this driver then suffices. 2173 */ 2174 2175#ifndef CONFIG_MUSB_PIO_ONLY 2176static u64 *orig_dma_mask; 2177#endif 2178 2179static int __init musb_probe(struct platform_device *pdev) 2180{ 2181 struct device *dev = &pdev->dev; 2182 int irq = platform_get_irq_byname(pdev, "mc"); 2183 int status; 2184 struct resource *iomem; 2185 void __iomem *base; 2186 2187 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2188 if (!iomem || irq <= 0) 2189 return -ENODEV; 2190 2191 base = ioremap(iomem->start, resource_size(iomem)); 2192 if (!base) { 2193 dev_err(dev, "ioremap failed\n"); 2194 return -ENOMEM; 2195 } 2196 2197#ifndef CONFIG_MUSB_PIO_ONLY 2198 /* clobbered by use_dma=n */ 2199 orig_dma_mask = dev->dma_mask; 2200#endif 2201 status = musb_init_controller(dev, irq, base); 2202 if (status < 0) 2203 iounmap(base); 2204 2205 return status; 2206} 2207 2208static int __exit musb_remove(struct platform_device *pdev) 2209{ 2210 struct musb *musb = dev_to_musb(&pdev->dev); 2211 void __iomem *ctrl_base = musb->ctrl_base; 2212 2213 /* this gets called on rmmod. 2214 * - Host mode: host may still be active 2215 * - Peripheral mode: peripheral is deactivated (or never-activated) 2216 * - OTG mode: both roles are deactivated (or never-activated) 2217 */ 2218 musb_exit_debugfs(musb); 2219 musb_shutdown(pdev); 2220 2221 musb_free(musb); 2222 iounmap(ctrl_base); 2223 device_init_wakeup(&pdev->dev, 0); 2224#ifndef CONFIG_MUSB_PIO_ONLY 2225 pdev->dev.dma_mask = orig_dma_mask; 2226#endif 2227 return 0; 2228} 2229 2230#ifdef CONFIG_PM 2231 2232static void musb_save_context(struct musb *musb) 2233{ 2234 int i; 2235 void __iomem *musb_base = musb->mregs; 2236 void __iomem *epio; 2237 2238 if (is_host_enabled(musb)) { 2239 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2240 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2241 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2242 } 2243 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2244 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2245 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2246 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2247 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2248 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2249 2250 for (i = 0; i < musb->config->num_eps; ++i) { 2251 epio = musb->endpoints[i].regs; 2252 musb->context.index_regs[i].txmaxp = 2253 musb_readw(epio, MUSB_TXMAXP); 2254 musb->context.index_regs[i].txcsr = 2255 musb_readw(epio, MUSB_TXCSR); 2256 musb->context.index_regs[i].rxmaxp = 2257 musb_readw(epio, MUSB_RXMAXP); 2258 musb->context.index_regs[i].rxcsr = 2259 musb_readw(epio, MUSB_RXCSR); 2260 2261 if (musb->dyn_fifo) { 2262 musb->context.index_regs[i].txfifoadd = 2263 musb_read_txfifoadd(musb_base); 2264 musb->context.index_regs[i].rxfifoadd = 2265 musb_read_rxfifoadd(musb_base); 2266 musb->context.index_regs[i].txfifosz = 2267 musb_read_txfifosz(musb_base); 2268 musb->context.index_regs[i].rxfifosz = 2269 musb_read_rxfifosz(musb_base); 2270 } 2271 if (is_host_enabled(musb)) { 2272 musb->context.index_regs[i].txtype = 2273 musb_readb(epio, MUSB_TXTYPE); 2274 musb->context.index_regs[i].txinterval = 2275 musb_readb(epio, MUSB_TXINTERVAL); 2276 musb->context.index_regs[i].rxtype = 2277 musb_readb(epio, MUSB_RXTYPE); 2278 musb->context.index_regs[i].rxinterval = 2279 musb_readb(epio, MUSB_RXINTERVAL); 2280 2281 musb->context.index_regs[i].txfunaddr = 2282 musb_read_txfunaddr(musb_base, i); 2283 musb->context.index_regs[i].txhubaddr = 2284 musb_read_txhubaddr(musb_base, i); 2285 musb->context.index_regs[i].txhubport = 2286 musb_read_txhubport(musb_base, i); 2287 2288 musb->context.index_regs[i].rxfunaddr = 2289 musb_read_rxfunaddr(musb_base, i); 2290 musb->context.index_regs[i].rxhubaddr = 2291 musb_read_rxhubaddr(musb_base, i); 2292 musb->context.index_regs[i].rxhubport = 2293 musb_read_rxhubport(musb_base, i); 2294 } 2295 } 2296} 2297 2298static void musb_restore_context(struct musb *musb) 2299{ 2300 int i; 2301 void __iomem *musb_base = musb->mregs; 2302 void __iomem *ep_target_regs; 2303 void __iomem *epio; 2304 2305 if (is_host_enabled(musb)) { 2306 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2307 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2308 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2309 } 2310 musb_writeb(musb_base, MUSB_POWER, musb->context.power); 2311 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); 2312 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); 2313 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2314 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2315 2316 for (i = 0; i < musb->config->num_eps; ++i) { 2317 epio = musb->endpoints[i].regs; 2318 musb_writew(epio, MUSB_TXMAXP, 2319 musb->context.index_regs[i].txmaxp); 2320 musb_writew(epio, MUSB_TXCSR, 2321 musb->context.index_regs[i].txcsr); 2322 musb_writew(epio, MUSB_RXMAXP, 2323 musb->context.index_regs[i].rxmaxp); 2324 musb_writew(epio, MUSB_RXCSR, 2325 musb->context.index_regs[i].rxcsr); 2326 2327 if (musb->dyn_fifo) { 2328 musb_write_txfifosz(musb_base, 2329 musb->context.index_regs[i].txfifosz); 2330 musb_write_rxfifosz(musb_base, 2331 musb->context.index_regs[i].rxfifosz); 2332 musb_write_txfifoadd(musb_base, 2333 musb->context.index_regs[i].txfifoadd); 2334 musb_write_rxfifoadd(musb_base, 2335 musb->context.index_regs[i].rxfifoadd); 2336 } 2337 2338 if (is_host_enabled(musb)) { 2339 musb_writeb(epio, MUSB_TXTYPE, 2340 musb->context.index_regs[i].txtype); 2341 musb_writeb(epio, MUSB_TXINTERVAL, 2342 musb->context.index_regs[i].txinterval); 2343 musb_writeb(epio, MUSB_RXTYPE, 2344 musb->context.index_regs[i].rxtype); 2345 musb_writeb(epio, MUSB_RXINTERVAL, 2346 2347 musb->context.index_regs[i].rxinterval); 2348 musb_write_txfunaddr(musb_base, i, 2349 musb->context.index_regs[i].txfunaddr); 2350 musb_write_txhubaddr(musb_base, i, 2351 musb->context.index_regs[i].txhubaddr); 2352 musb_write_txhubport(musb_base, i, 2353 musb->context.index_regs[i].txhubport); 2354 2355 ep_target_regs = 2356 musb_read_target_reg_base(i, musb_base); 2357 2358 musb_write_rxfunaddr(ep_target_regs, 2359 musb->context.index_regs[i].rxfunaddr); 2360 musb_write_rxhubaddr(ep_target_regs, 2361 musb->context.index_regs[i].rxhubaddr); 2362 musb_write_rxhubport(ep_target_regs, 2363 musb->context.index_regs[i].rxhubport); 2364 } 2365 } 2366} 2367 2368static int musb_suspend(struct device *dev) 2369{ 2370 struct platform_device *pdev = to_platform_device(dev); 2371 unsigned long flags; 2372 struct musb *musb = dev_to_musb(&pdev->dev); 2373 2374 spin_lock_irqsave(&musb->lock, flags); 2375 2376 if (is_peripheral_active(musb)) { 2377 /* FIXME force disconnect unless we know USB will wake 2378 * the system up quickly enough to respond ... 2379 */ 2380 } else if (is_host_active(musb)) { 2381 /* we know all the children are suspended; sometimes 2382 * they will even be wakeup-enabled. 2383 */ 2384 } 2385 2386 musb_save_context(musb); 2387 2388 spin_unlock_irqrestore(&musb->lock, flags); 2389 return 0; 2390} 2391 2392static int musb_resume_noirq(struct device *dev) 2393{ 2394 struct platform_device *pdev = to_platform_device(dev); 2395 struct musb *musb = dev_to_musb(&pdev->dev); 2396 2397 musb_restore_context(musb); 2398 2399 /* for static cmos like DaVinci, register values were preserved 2400 * unless for some reason the whole soc powered down or the USB 2401 * module got reset through the PSC (vs just being disabled). 2402 */ 2403 return 0; 2404} 2405 2406static const struct dev_pm_ops musb_dev_pm_ops = { 2407 .suspend = musb_suspend, 2408 .resume_noirq = musb_resume_noirq, 2409}; 2410 2411#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2412#else 2413#define MUSB_DEV_PM_OPS NULL 2414#endif 2415 2416static struct platform_driver musb_driver = { 2417 .driver = { 2418 .name = (char *)musb_driver_name, 2419 .bus = &platform_bus_type, 2420 .owner = THIS_MODULE, 2421 .pm = MUSB_DEV_PM_OPS, 2422 }, 2423 .remove = __exit_p(musb_remove), 2424 .shutdown = musb_shutdown, 2425}; 2426 2427/*-------------------------------------------------------------------------*/ 2428 2429static int __init musb_init(void) 2430{ 2431#ifdef CONFIG_USB_MUSB_HDRC_HCD 2432 if (usb_disabled()) 2433 return 0; 2434#endif 2435 2436 pr_info("%s: version " MUSB_VERSION ", " 2437#ifdef CONFIG_MUSB_PIO_ONLY 2438 "pio" 2439#elif defined(CONFIG_USB_TI_CPPI_DMA) 2440 "cppi-dma" 2441#elif defined(CONFIG_USB_INVENTRA_DMA) 2442 "musb-dma" 2443#elif defined(CONFIG_USB_TUSB_OMAP_DMA) 2444 "tusb-omap-dma" 2445#else 2446 "?dma?" 2447#endif 2448 ", " 2449#ifdef CONFIG_USB_MUSB_OTG 2450 "otg (peripheral+host)" 2451#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 2452 "peripheral" 2453#elif defined(CONFIG_USB_MUSB_HDRC_HCD) 2454 "host" 2455#endif 2456 ", debug=%d\n", 2457 musb_driver_name, musb_debug); 2458 return platform_driver_probe(&musb_driver, musb_probe); 2459} 2460 2461/* make us init after usbcore and i2c (transceivers, regulators, etc) 2462 * and before usb gadget and host-side drivers start to register 2463 */ 2464fs_initcall(musb_init); 2465 2466static void __exit musb_cleanup(void) 2467{ 2468 platform_driver_unregister(&musb_driver); 2469} 2470module_exit(musb_cleanup); 2471