musb_core.c revision da5108e1a350c84b185b5f11aa58fea93a204fe0
1/* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35/* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82/* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92#include <linux/module.h> 93#include <linux/kernel.h> 94#include <linux/sched.h> 95#include <linux/slab.h> 96#include <linux/init.h> 97#include <linux/list.h> 98#include <linux/kobject.h> 99#include <linux/platform_device.h> 100#include <linux/io.h> 101 102#ifdef CONFIG_ARM 103#include <mach/hardware.h> 104#include <mach/memory.h> 105#include <asm/mach-types.h> 106#endif 107 108#include "musb_core.h" 109 110 111#ifdef CONFIG_ARCH_DAVINCI 112#include "davinci.h" 113#endif 114 115#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 116 117 118unsigned musb_debug; 119module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR); 120MODULE_PARM_DESC(debug, "Debug message level. Default = 0"); 121 122#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 123#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 124 125#define MUSB_VERSION "6.0" 126 127#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 128 129#define MUSB_DRIVER_NAME "musb_hdrc" 130const char musb_driver_name[] = MUSB_DRIVER_NAME; 131 132MODULE_DESCRIPTION(DRIVER_INFO); 133MODULE_AUTHOR(DRIVER_AUTHOR); 134MODULE_LICENSE("GPL"); 135MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 136 137 138/*-------------------------------------------------------------------------*/ 139 140static inline struct musb *dev_to_musb(struct device *dev) 141{ 142#ifdef CONFIG_USB_MUSB_HDRC_HCD 143 /* usbcore insists dev->driver_data is a "struct hcd *" */ 144 return hcd_to_musb(dev_get_drvdata(dev)); 145#else 146 return dev_get_drvdata(dev); 147#endif 148} 149 150/*-------------------------------------------------------------------------*/ 151 152#if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN) 153 154/* 155 * Load an endpoint's FIFO 156 */ 157void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 158{ 159 void __iomem *fifo = hw_ep->fifo; 160 161 prefetch((u8 *)src); 162 163 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 164 'T', hw_ep->epnum, fifo, len, src); 165 166 /* we can't assume unaligned reads work */ 167 if (likely((0x01 & (unsigned long) src) == 0)) { 168 u16 index = 0; 169 170 /* best case is 32bit-aligned source address */ 171 if ((0x02 & (unsigned long) src) == 0) { 172 if (len >= 4) { 173 writesl(fifo, src + index, len >> 2); 174 index += len & ~0x03; 175 } 176 if (len & 0x02) { 177 musb_writew(fifo, 0, *(u16 *)&src[index]); 178 index += 2; 179 } 180 } else { 181 if (len >= 2) { 182 writesw(fifo, src + index, len >> 1); 183 index += len & ~0x01; 184 } 185 } 186 if (len & 0x01) 187 musb_writeb(fifo, 0, src[index]); 188 } else { 189 /* byte aligned */ 190 writesb(fifo, src, len); 191 } 192} 193 194/* 195 * Unload an endpoint's FIFO 196 */ 197void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 198{ 199 void __iomem *fifo = hw_ep->fifo; 200 201 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 202 'R', hw_ep->epnum, fifo, len, dst); 203 204 /* we can't assume unaligned writes work */ 205 if (likely((0x01 & (unsigned long) dst) == 0)) { 206 u16 index = 0; 207 208 /* best case is 32bit-aligned destination address */ 209 if ((0x02 & (unsigned long) dst) == 0) { 210 if (len >= 4) { 211 readsl(fifo, dst, len >> 2); 212 index = len & ~0x03; 213 } 214 if (len & 0x02) { 215 *(u16 *)&dst[index] = musb_readw(fifo, 0); 216 index += 2; 217 } 218 } else { 219 if (len >= 2) { 220 readsw(fifo, dst, len >> 1); 221 index = len & ~0x01; 222 } 223 } 224 if (len & 0x01) 225 dst[index] = musb_readb(fifo, 0); 226 } else { 227 /* byte aligned */ 228 readsb(fifo, dst, len); 229 } 230} 231 232#endif /* normal PIO */ 233 234 235/*-------------------------------------------------------------------------*/ 236 237/* for high speed test mode; see USB 2.0 spec 7.1.20 */ 238static const u8 musb_test_packet[53] = { 239 /* implicit SYNC then DATA0 to start */ 240 241 /* JKJKJKJK x9 */ 242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 243 /* JJKKJJKK x8 */ 244 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 245 /* JJJJKKKK x8 */ 246 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 247 /* JJJJJJJKKKKKKK x8 */ 248 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 249 /* JJJJJJJK x8 */ 250 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 251 /* JKKKKKKK x10, JK */ 252 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 253 254 /* implicit CRC16 then EOP to end */ 255}; 256 257void musb_load_testpacket(struct musb *musb) 258{ 259 void __iomem *regs = musb->endpoints[0].regs; 260 261 musb_ep_select(musb->mregs, 0); 262 musb_write_fifo(musb->control_ep, 263 sizeof(musb_test_packet), musb_test_packet); 264 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 265} 266 267/*-------------------------------------------------------------------------*/ 268 269const char *otg_state_string(struct musb *musb) 270{ 271 switch (musb->xceiv->state) { 272 case OTG_STATE_A_IDLE: return "a_idle"; 273 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; 274 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; 275 case OTG_STATE_A_HOST: return "a_host"; 276 case OTG_STATE_A_SUSPEND: return "a_suspend"; 277 case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; 278 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; 279 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; 280 case OTG_STATE_B_IDLE: return "b_idle"; 281 case OTG_STATE_B_SRP_INIT: return "b_srp_init"; 282 case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; 283 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; 284 case OTG_STATE_B_HOST: return "b_host"; 285 default: return "UNDEFINED"; 286 } 287} 288 289#ifdef CONFIG_USB_MUSB_OTG 290 291/* 292 * Handles OTG hnp timeouts, such as b_ase0_brst 293 */ 294void musb_otg_timer_func(unsigned long data) 295{ 296 struct musb *musb = (struct musb *)data; 297 unsigned long flags; 298 299 spin_lock_irqsave(&musb->lock, flags); 300 switch (musb->xceiv->state) { 301 case OTG_STATE_B_WAIT_ACON: 302 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 303 musb_g_disconnect(musb); 304 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 305 musb->is_active = 0; 306 break; 307 case OTG_STATE_A_SUSPEND: 308 case OTG_STATE_A_WAIT_BCON: 309 DBG(1, "HNP: %s timeout\n", otg_state_string(musb)); 310 musb_set_vbus(musb, 0); 311 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 312 break; 313 default: 314 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb)); 315 } 316 musb->ignore_disconnect = 0; 317 spin_unlock_irqrestore(&musb->lock, flags); 318} 319 320/* 321 * Stops the HNP transition. Caller must take care of locking. 322 */ 323void musb_hnp_stop(struct musb *musb) 324{ 325 struct usb_hcd *hcd = musb_to_hcd(musb); 326 void __iomem *mbase = musb->mregs; 327 u8 reg; 328 329 DBG(1, "HNP: stop from %s\n", otg_state_string(musb)); 330 331 switch (musb->xceiv->state) { 332 case OTG_STATE_A_PERIPHERAL: 333 musb_g_disconnect(musb); 334 DBG(1, "HNP: back to %s\n", otg_state_string(musb)); 335 break; 336 case OTG_STATE_B_HOST: 337 DBG(1, "HNP: Disabling HR\n"); 338 hcd->self.is_b_host = 0; 339 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 340 MUSB_DEV_MODE(musb); 341 reg = musb_readb(mbase, MUSB_POWER); 342 reg |= MUSB_POWER_SUSPENDM; 343 musb_writeb(mbase, MUSB_POWER, reg); 344 /* REVISIT: Start SESSION_REQUEST here? */ 345 break; 346 default: 347 DBG(1, "HNP: Stopping in unknown state %s\n", 348 otg_state_string(musb)); 349 } 350 351 /* 352 * When returning to A state after HNP, avoid hub_port_rebounce(), 353 * which cause occasional OPT A "Did not receive reset after connect" 354 * errors. 355 */ 356 musb->port1_status &= 357 ~(1 << USB_PORT_FEAT_C_CONNECTION); 358} 359 360#endif 361 362/* 363 * Interrupt Service Routine to record USB "global" interrupts. 364 * Since these do not happen often and signify things of 365 * paramount importance, it seems OK to check them individually; 366 * the order of the tests is specified in the manual 367 * 368 * @param musb instance pointer 369 * @param int_usb register contents 370 * @param devctl 371 * @param power 372 */ 373 374#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \ 375 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \ 376 | MUSB_INTR_RESET) 377 378static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 379 u8 devctl, u8 power) 380{ 381 irqreturn_t handled = IRQ_NONE; 382 void __iomem *mbase = musb->mregs; 383 384 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 385 int_usb); 386 387 /* in host mode, the peripheral may issue remote wakeup. 388 * in peripheral mode, the host may resume the link. 389 * spurious RESUME irqs happen too, paired with SUSPEND. 390 */ 391 if (int_usb & MUSB_INTR_RESUME) { 392 handled = IRQ_HANDLED; 393 DBG(3, "RESUME (%s)\n", otg_state_string(musb)); 394 395 if (devctl & MUSB_DEVCTL_HM) { 396#ifdef CONFIG_USB_MUSB_HDRC_HCD 397 switch (musb->xceiv->state) { 398 case OTG_STATE_A_SUSPEND: 399 /* remote wakeup? later, GetPortStatus 400 * will stop RESUME signaling 401 */ 402 403 if (power & MUSB_POWER_SUSPENDM) { 404 /* spurious */ 405 musb->int_usb &= ~MUSB_INTR_SUSPEND; 406 DBG(2, "Spurious SUSPENDM\n"); 407 break; 408 } 409 410 power &= ~MUSB_POWER_SUSPENDM; 411 musb_writeb(mbase, MUSB_POWER, 412 power | MUSB_POWER_RESUME); 413 414 musb->port1_status |= 415 (USB_PORT_STAT_C_SUSPEND << 16) 416 | MUSB_PORT_STAT_RESUME; 417 musb->rh_timer = jiffies 418 + msecs_to_jiffies(20); 419 420 musb->xceiv->state = OTG_STATE_A_HOST; 421 musb->is_active = 1; 422 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 423 break; 424 case OTG_STATE_B_WAIT_ACON: 425 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 426 musb->is_active = 1; 427 MUSB_DEV_MODE(musb); 428 break; 429 default: 430 WARNING("bogus %s RESUME (%s)\n", 431 "host", 432 otg_state_string(musb)); 433 } 434#endif 435 } else { 436 switch (musb->xceiv->state) { 437#ifdef CONFIG_USB_MUSB_HDRC_HCD 438 case OTG_STATE_A_SUSPEND: 439 /* possibly DISCONNECT is upcoming */ 440 musb->xceiv->state = OTG_STATE_A_HOST; 441 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 442 break; 443#endif 444#ifdef CONFIG_USB_GADGET_MUSB_HDRC 445 case OTG_STATE_B_WAIT_ACON: 446 case OTG_STATE_B_PERIPHERAL: 447 /* disconnect while suspended? we may 448 * not get a disconnect irq... 449 */ 450 if ((devctl & MUSB_DEVCTL_VBUS) 451 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 452 ) { 453 musb->int_usb |= MUSB_INTR_DISCONNECT; 454 musb->int_usb &= ~MUSB_INTR_SUSPEND; 455 break; 456 } 457 musb_g_resume(musb); 458 break; 459 case OTG_STATE_B_IDLE: 460 musb->int_usb &= ~MUSB_INTR_SUSPEND; 461 break; 462#endif 463 default: 464 WARNING("bogus %s RESUME (%s)\n", 465 "peripheral", 466 otg_state_string(musb)); 467 } 468 } 469 } 470 471#ifdef CONFIG_USB_MUSB_HDRC_HCD 472 /* see manual for the order of the tests */ 473 if (int_usb & MUSB_INTR_SESSREQ) { 474 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); 475 476 /* IRQ arrives from ID pin sense or (later, if VBUS power 477 * is removed) SRP. responses are time critical: 478 * - turn on VBUS (with silicon-specific mechanism) 479 * - go through A_WAIT_VRISE 480 * - ... to A_WAIT_BCON. 481 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 482 */ 483 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 484 musb->ep0_stage = MUSB_EP0_START; 485 musb->xceiv->state = OTG_STATE_A_IDLE; 486 MUSB_HST_MODE(musb); 487 musb_set_vbus(musb, 1); 488 489 handled = IRQ_HANDLED; 490 } 491 492 if (int_usb & MUSB_INTR_VBUSERROR) { 493 int ignore = 0; 494 495 /* During connection as an A-Device, we may see a short 496 * current spikes causing voltage drop, because of cable 497 * and peripheral capacitance combined with vbus draw. 498 * (So: less common with truly self-powered devices, where 499 * vbus doesn't act like a power supply.) 500 * 501 * Such spikes are short; usually less than ~500 usec, max 502 * of ~2 msec. That is, they're not sustained overcurrent 503 * errors, though they're reported using VBUSERROR irqs. 504 * 505 * Workarounds: (a) hardware: use self powered devices. 506 * (b) software: ignore non-repeated VBUS errors. 507 * 508 * REVISIT: do delays from lots of DEBUG_KERNEL checks 509 * make trouble here, keeping VBUS < 4.4V ? 510 */ 511 switch (musb->xceiv->state) { 512 case OTG_STATE_A_HOST: 513 /* recovery is dicey once we've gotten past the 514 * initial stages of enumeration, but if VBUS 515 * stayed ok at the other end of the link, and 516 * another reset is due (at least for high speed, 517 * to redo the chirp etc), it might work OK... 518 */ 519 case OTG_STATE_A_WAIT_BCON: 520 case OTG_STATE_A_WAIT_VRISE: 521 if (musb->vbuserr_retry) { 522 musb->vbuserr_retry--; 523 ignore = 1; 524 devctl |= MUSB_DEVCTL_SESSION; 525 musb_writeb(mbase, MUSB_DEVCTL, devctl); 526 } else { 527 musb->port1_status |= 528 (1 << USB_PORT_FEAT_OVER_CURRENT) 529 | (1 << USB_PORT_FEAT_C_OVER_CURRENT); 530 } 531 break; 532 default: 533 break; 534 } 535 536 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 537 otg_state_string(musb), 538 devctl, 539 ({ char *s; 540 switch (devctl & MUSB_DEVCTL_VBUS) { 541 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 542 s = "<SessEnd"; break; 543 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 544 s = "<AValid"; break; 545 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 546 s = "<VBusValid"; break; 547 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 548 default: 549 s = "VALID"; break; 550 }; s; }), 551 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 552 musb->port1_status); 553 554 /* go through A_WAIT_VFALL then start a new session */ 555 if (!ignore) 556 musb_set_vbus(musb, 0); 557 handled = IRQ_HANDLED; 558 } 559 560 561 if (int_usb & MUSB_INTR_SUSPEND) { 562 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", 563 otg_state_string(musb), devctl, power); 564 handled = IRQ_HANDLED; 565 566 switch (musb->xceiv->state) { 567#ifdef CONFIG_USB_MUSB_OTG 568 case OTG_STATE_A_PERIPHERAL: 569 /* We also come here if the cable is removed, since 570 * this silicon doesn't report ID-no-longer-grounded. 571 * 572 * We depend on T(a_wait_bcon) to shut us down, and 573 * hope users don't do anything dicey during this 574 * undesired detour through A_WAIT_BCON. 575 */ 576 musb_hnp_stop(musb); 577 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 578 musb_root_disconnect(musb); 579 musb_platform_try_idle(musb, jiffies 580 + msecs_to_jiffies(musb->a_wait_bcon 581 ? : OTG_TIME_A_WAIT_BCON)); 582 583 break; 584#endif 585 case OTG_STATE_B_IDLE: 586 if (!musb->is_active) 587 break; 588 case OTG_STATE_B_PERIPHERAL: 589 musb_g_suspend(musb); 590 musb->is_active = is_otg_enabled(musb) 591 && musb->xceiv->gadget->b_hnp_enable; 592 if (musb->is_active) { 593#ifdef CONFIG_USB_MUSB_OTG 594 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 595 DBG(1, "HNP: Setting timer for b_ase0_brst\n"); 596 mod_timer(&musb->otg_timer, jiffies 597 + msecs_to_jiffies( 598 OTG_TIME_B_ASE0_BRST)); 599#endif 600 } 601 break; 602 case OTG_STATE_A_WAIT_BCON: 603 if (musb->a_wait_bcon != 0) 604 musb_platform_try_idle(musb, jiffies 605 + msecs_to_jiffies(musb->a_wait_bcon)); 606 break; 607 case OTG_STATE_A_HOST: 608 musb->xceiv->state = OTG_STATE_A_SUSPEND; 609 musb->is_active = is_otg_enabled(musb) 610 && musb->xceiv->host->b_hnp_enable; 611 break; 612 case OTG_STATE_B_HOST: 613 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 614 DBG(1, "REVISIT: SUSPEND as B_HOST\n"); 615 break; 616 default: 617 /* "should not happen" */ 618 musb->is_active = 0; 619 break; 620 } 621 } 622 623 if (int_usb & MUSB_INTR_CONNECT) { 624 struct usb_hcd *hcd = musb_to_hcd(musb); 625 626 handled = IRQ_HANDLED; 627 musb->is_active = 1; 628 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); 629 630 musb->ep0_stage = MUSB_EP0_START; 631 632#ifdef CONFIG_USB_MUSB_OTG 633 /* flush endpoints when transitioning from Device Mode */ 634 if (is_peripheral_active(musb)) { 635 /* REVISIT HNP; just force disconnect */ 636 } 637 musb_writew(mbase, MUSB_INTRTXE, musb->epmask); 638 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe); 639 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7); 640#endif 641 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 642 |USB_PORT_STAT_HIGH_SPEED 643 |USB_PORT_STAT_ENABLE 644 ); 645 musb->port1_status |= USB_PORT_STAT_CONNECTION 646 |(USB_PORT_STAT_C_CONNECTION << 16); 647 648 /* high vs full speed is just a guess until after reset */ 649 if (devctl & MUSB_DEVCTL_LSDEV) 650 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 651 652 /* indicate new connection to OTG machine */ 653 switch (musb->xceiv->state) { 654 case OTG_STATE_B_PERIPHERAL: 655 if (int_usb & MUSB_INTR_SUSPEND) { 656 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); 657 int_usb &= ~MUSB_INTR_SUSPEND; 658 goto b_host; 659 } else 660 DBG(1, "CONNECT as b_peripheral???\n"); 661 break; 662 case OTG_STATE_B_WAIT_ACON: 663 DBG(1, "HNP: CONNECT, now b_host\n"); 664b_host: 665 musb->xceiv->state = OTG_STATE_B_HOST; 666 hcd->self.is_b_host = 1; 667 musb->ignore_disconnect = 0; 668 del_timer(&musb->otg_timer); 669 break; 670 default: 671 if ((devctl & MUSB_DEVCTL_VBUS) 672 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 673 musb->xceiv->state = OTG_STATE_A_HOST; 674 hcd->self.is_b_host = 0; 675 } 676 break; 677 } 678 679 /* poke the root hub */ 680 MUSB_HST_MODE(musb); 681 if (hcd->status_urb) 682 usb_hcd_poll_rh_status(hcd); 683 else 684 usb_hcd_resume_root_hub(hcd); 685 686 DBG(1, "CONNECT (%s) devctl %02x\n", 687 otg_state_string(musb), devctl); 688 } 689#endif /* CONFIG_USB_MUSB_HDRC_HCD */ 690 691 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 692 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n", 693 otg_state_string(musb), 694 MUSB_MODE(musb), devctl); 695 handled = IRQ_HANDLED; 696 697 switch (musb->xceiv->state) { 698#ifdef CONFIG_USB_MUSB_HDRC_HCD 699 case OTG_STATE_A_HOST: 700 case OTG_STATE_A_SUSPEND: 701 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 702 musb_root_disconnect(musb); 703 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 704 musb_platform_try_idle(musb, jiffies 705 + msecs_to_jiffies(musb->a_wait_bcon)); 706 break; 707#endif /* HOST */ 708#ifdef CONFIG_USB_MUSB_OTG 709 case OTG_STATE_B_HOST: 710 /* REVISIT this behaves for "real disconnect" 711 * cases; make sure the other transitions from 712 * from B_HOST act right too. The B_HOST code 713 * in hnp_stop() is currently not used... 714 */ 715 musb_root_disconnect(musb); 716 musb_to_hcd(musb)->self.is_b_host = 0; 717 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 718 MUSB_DEV_MODE(musb); 719 musb_g_disconnect(musb); 720 break; 721 case OTG_STATE_A_PERIPHERAL: 722 musb_hnp_stop(musb); 723 musb_root_disconnect(musb); 724 /* FALLTHROUGH */ 725 case OTG_STATE_B_WAIT_ACON: 726 /* FALLTHROUGH */ 727#endif /* OTG */ 728#ifdef CONFIG_USB_GADGET_MUSB_HDRC 729 case OTG_STATE_B_PERIPHERAL: 730 case OTG_STATE_B_IDLE: 731 musb_g_disconnect(musb); 732 break; 733#endif /* GADGET */ 734 default: 735 WARNING("unhandled DISCONNECT transition (%s)\n", 736 otg_state_string(musb)); 737 break; 738 } 739 } 740 741 /* mentor saves a bit: bus reset and babble share the same irq. 742 * only host sees babble; only peripheral sees bus reset. 743 */ 744 if (int_usb & MUSB_INTR_RESET) { 745 handled = IRQ_HANDLED; 746 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 747 /* 748 * Looks like non-HS BABBLE can be ignored, but 749 * HS BABBLE is an error condition. For HS the solution 750 * is to avoid babble in the first place and fix what 751 * caused BABBLE. When HS BABBLE happens we can only 752 * stop the session. 753 */ 754 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 755 DBG(1, "BABBLE devctl: %02x\n", devctl); 756 else { 757 ERR("Stopping host session -- babble\n"); 758 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 759 } 760 } else if (is_peripheral_capable()) { 761 DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); 762 switch (musb->xceiv->state) { 763#ifdef CONFIG_USB_OTG 764 case OTG_STATE_A_SUSPEND: 765 /* We need to ignore disconnect on suspend 766 * otherwise tusb 2.0 won't reconnect after a 767 * power cycle, which breaks otg compliance. 768 */ 769 musb->ignore_disconnect = 1; 770 musb_g_reset(musb); 771 /* FALLTHROUGH */ 772 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 773 /* never use invalid T(a_wait_bcon) */ 774 DBG(1, "HNP: in %s, %d msec timeout\n", 775 otg_state_string(musb), 776 TA_WAIT_BCON(musb)); 777 mod_timer(&musb->otg_timer, jiffies 778 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 779 break; 780 case OTG_STATE_A_PERIPHERAL: 781 musb->ignore_disconnect = 0; 782 del_timer(&musb->otg_timer); 783 musb_g_reset(musb); 784 break; 785 case OTG_STATE_B_WAIT_ACON: 786 DBG(1, "HNP: RESET (%s), to b_peripheral\n", 787 otg_state_string(musb)); 788 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 789 musb_g_reset(musb); 790 break; 791#endif 792 case OTG_STATE_B_IDLE: 793 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 794 /* FALLTHROUGH */ 795 case OTG_STATE_B_PERIPHERAL: 796 musb_g_reset(musb); 797 break; 798 default: 799 DBG(1, "Unhandled BUS RESET as %s\n", 800 otg_state_string(musb)); 801 } 802 } 803 } 804 805#if 0 806/* REVISIT ... this would be for multiplexing periodic endpoints, or 807 * supporting transfer phasing to prevent exceeding ISO bandwidth 808 * limits of a given frame or microframe. 809 * 810 * It's not needed for peripheral side, which dedicates endpoints; 811 * though it _might_ use SOF irqs for other purposes. 812 * 813 * And it's not currently needed for host side, which also dedicates 814 * endpoints, relies on TX/RX interval registers, and isn't claimed 815 * to support ISO transfers yet. 816 */ 817 if (int_usb & MUSB_INTR_SOF) { 818 void __iomem *mbase = musb->mregs; 819 struct musb_hw_ep *ep; 820 u8 epnum; 821 u16 frame; 822 823 DBG(6, "START_OF_FRAME\n"); 824 handled = IRQ_HANDLED; 825 826 /* start any periodic Tx transfers waiting for current frame */ 827 frame = musb_readw(mbase, MUSB_FRAME); 828 ep = musb->endpoints; 829 for (epnum = 1; (epnum < musb->nr_endpoints) 830 && (musb->epmask >= (1 << epnum)); 831 epnum++, ep++) { 832 /* 833 * FIXME handle framecounter wraps (12 bits) 834 * eliminate duplicated StartUrb logic 835 */ 836 if (ep->dwWaitFrame >= frame) { 837 ep->dwWaitFrame = 0; 838 pr_debug("SOF --> periodic TX%s on %d\n", 839 ep->tx_channel ? " DMA" : "", 840 epnum); 841 if (!ep->tx_channel) 842 musb_h_tx_start(musb, epnum); 843 else 844 cppi_hostdma_start(musb, epnum); 845 } 846 } /* end of for loop */ 847 } 848#endif 849 850 schedule_work(&musb->irq_work); 851 852 return handled; 853} 854 855/*-------------------------------------------------------------------------*/ 856 857/* 858* Program the HDRC to start (enable interrupts, dma, etc.). 859*/ 860void musb_start(struct musb *musb) 861{ 862 void __iomem *regs = musb->mregs; 863 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 864 865 DBG(2, "<== devctl %02x\n", devctl); 866 867 /* Set INT enable registers, enable interrupts */ 868 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 869 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 870 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 871 872 musb_writeb(regs, MUSB_TESTMODE, 0); 873 874 /* put into basic highspeed mode and start session */ 875 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 876 | MUSB_POWER_SOFTCONN 877 | MUSB_POWER_HSENAB 878 /* ENSUSPEND wedges tusb */ 879 /* | MUSB_POWER_ENSUSPEND */ 880 ); 881 882 musb->is_active = 0; 883 devctl = musb_readb(regs, MUSB_DEVCTL); 884 devctl &= ~MUSB_DEVCTL_SESSION; 885 886 if (is_otg_enabled(musb)) { 887 /* session started after: 888 * (a) ID-grounded irq, host mode; 889 * (b) vbus present/connect IRQ, peripheral mode; 890 * (c) peripheral initiates, using SRP 891 */ 892 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 893 musb->is_active = 1; 894 else 895 devctl |= MUSB_DEVCTL_SESSION; 896 897 } else if (is_host_enabled(musb)) { 898 /* assume ID pin is hard-wired to ground */ 899 devctl |= MUSB_DEVCTL_SESSION; 900 901 } else /* peripheral is enabled */ { 902 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 903 musb->is_active = 1; 904 } 905 musb_platform_enable(musb); 906 musb_writeb(regs, MUSB_DEVCTL, devctl); 907} 908 909 910static void musb_generic_disable(struct musb *musb) 911{ 912 void __iomem *mbase = musb->mregs; 913 u16 temp; 914 915 /* disable interrupts */ 916 musb_writeb(mbase, MUSB_INTRUSBE, 0); 917 musb_writew(mbase, MUSB_INTRTXE, 0); 918 musb_writew(mbase, MUSB_INTRRXE, 0); 919 920 /* off */ 921 musb_writeb(mbase, MUSB_DEVCTL, 0); 922 923 /* flush pending interrupts */ 924 temp = musb_readb(mbase, MUSB_INTRUSB); 925 temp = musb_readw(mbase, MUSB_INTRTX); 926 temp = musb_readw(mbase, MUSB_INTRRX); 927 928} 929 930/* 931 * Make the HDRC stop (disable interrupts, etc.); 932 * reversible by musb_start 933 * called on gadget driver unregister 934 * with controller locked, irqs blocked 935 * acts as a NOP unless some role activated the hardware 936 */ 937void musb_stop(struct musb *musb) 938{ 939 /* stop IRQs, timers, ... */ 940 musb_platform_disable(musb); 941 musb_generic_disable(musb); 942 DBG(3, "HDRC disabled\n"); 943 944 /* FIXME 945 * - mark host and/or peripheral drivers unusable/inactive 946 * - disable DMA (and enable it in HdrcStart) 947 * - make sure we can musb_start() after musb_stop(); with 948 * OTG mode, gadget driver module rmmod/modprobe cycles that 949 * - ... 950 */ 951 musb_platform_try_idle(musb, 0); 952} 953 954static void musb_shutdown(struct platform_device *pdev) 955{ 956 struct musb *musb = dev_to_musb(&pdev->dev); 957 unsigned long flags; 958 959 spin_lock_irqsave(&musb->lock, flags); 960 musb_platform_disable(musb); 961 musb_generic_disable(musb); 962 if (musb->clock) { 963 clk_put(musb->clock); 964 musb->clock = NULL; 965 } 966 spin_unlock_irqrestore(&musb->lock, flags); 967 968 /* FIXME power down */ 969} 970 971 972/*-------------------------------------------------------------------------*/ 973 974/* 975 * The silicon either has hard-wired endpoint configurations, or else 976 * "dynamic fifo" sizing. The driver has support for both, though at this 977 * writing only the dynamic sizing is very well tested. Since we switched 978 * away from compile-time hardware parameters, we can no longer rely on 979 * dead code elimination to leave only the relevant one in the object file. 980 * 981 * We don't currently use dynamic fifo setup capability to do anything 982 * more than selecting one of a bunch of predefined configurations. 983 */ 984#if defined(CONFIG_USB_TUSB6010) || \ 985 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) 986static ushort __initdata fifo_mode = 4; 987#else 988static ushort __initdata fifo_mode = 2; 989#endif 990 991/* "modprobe ... fifo_mode=1" etc */ 992module_param(fifo_mode, ushort, 0); 993MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 994 995 996enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed)); 997enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed)); 998 999struct fifo_cfg { 1000 u8 hw_ep_num; 1001 enum fifo_style style; 1002 enum buf_mode mode; 1003 u16 maxpacket; 1004}; 1005 1006/* 1007 * tables defining fifo_mode values. define more if you like. 1008 * for host side, make sure both halves of ep1 are set up. 1009 */ 1010 1011/* mode 0 - fits in 2KB */ 1012static struct fifo_cfg __initdata mode_0_cfg[] = { 1013{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1014{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1015{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1016{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1017{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1018}; 1019 1020/* mode 1 - fits in 4KB */ 1021static struct fifo_cfg __initdata mode_1_cfg[] = { 1022{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1023{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1024{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1025{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1026{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1027}; 1028 1029/* mode 2 - fits in 4KB */ 1030static struct fifo_cfg __initdata mode_2_cfg[] = { 1031{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1032{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1033{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1034{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1035{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1036{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1037}; 1038 1039/* mode 3 - fits in 4KB */ 1040static struct fifo_cfg __initdata mode_3_cfg[] = { 1041{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1042{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1043{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1044{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1045{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1046{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1047}; 1048 1049/* mode 4 - fits in 16KB */ 1050static struct fifo_cfg __initdata mode_4_cfg[] = { 1051{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1052{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1053{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1054{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1055{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1056{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1057{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1058{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1059{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1060{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1061{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1062{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1063{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1064{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1065{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1066{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1067{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1068{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1069{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1070{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1071{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1072{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1073{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1074{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1075{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1076{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1077{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1078}; 1079 1080/* mode 5 - fits in 8KB */ 1081static struct fifo_cfg __initdata mode_5_cfg[] = { 1082{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1083{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1084{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1085{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1086{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1087{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1088{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1089{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1090{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1091{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1092{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1093{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1094{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1095{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1096{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1097{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1098{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1099{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1100{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1101{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1102{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1103{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1104{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1105{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1106{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1107{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1108{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1109}; 1110 1111/* 1112 * configure a fifo; for non-shared endpoints, this may be called 1113 * once for a tx fifo and once for an rx fifo. 1114 * 1115 * returns negative errno or offset for next fifo. 1116 */ 1117static int __init 1118fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1119 const struct fifo_cfg *cfg, u16 offset) 1120{ 1121 void __iomem *mbase = musb->mregs; 1122 int size = 0; 1123 u16 maxpacket = cfg->maxpacket; 1124 u16 c_off = offset >> 3; 1125 u8 c_size; 1126 1127 /* expect hw_ep has already been zero-initialized */ 1128 1129 size = ffs(max(maxpacket, (u16) 8)) - 1; 1130 maxpacket = 1 << size; 1131 1132 c_size = size - 3; 1133 if (cfg->mode == BUF_DOUBLE) { 1134 if ((offset + (maxpacket << 1)) > 1135 (1 << (musb->config->ram_bits + 2))) 1136 return -EMSGSIZE; 1137 c_size |= MUSB_FIFOSZ_DPB; 1138 } else { 1139 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1140 return -EMSGSIZE; 1141 } 1142 1143 /* configure the FIFO */ 1144 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1145 1146#ifdef CONFIG_USB_MUSB_HDRC_HCD 1147 /* EP0 reserved endpoint for control, bidirectional; 1148 * EP1 reserved for bulk, two unidirection halves. 1149 */ 1150 if (hw_ep->epnum == 1) 1151 musb->bulk_ep = hw_ep; 1152 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1153#endif 1154 switch (cfg->style) { 1155 case FIFO_TX: 1156 musb_write_txfifosz(mbase, c_size); 1157 musb_write_txfifoadd(mbase, c_off); 1158 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1159 hw_ep->max_packet_sz_tx = maxpacket; 1160 break; 1161 case FIFO_RX: 1162 musb_write_rxfifosz(mbase, c_size); 1163 musb_write_rxfifoadd(mbase, c_off); 1164 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1165 hw_ep->max_packet_sz_rx = maxpacket; 1166 break; 1167 case FIFO_RXTX: 1168 musb_write_txfifosz(mbase, c_size); 1169 musb_write_txfifoadd(mbase, c_off); 1170 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1171 hw_ep->max_packet_sz_rx = maxpacket; 1172 1173 musb_write_rxfifosz(mbase, c_size); 1174 musb_write_rxfifoadd(mbase, c_off); 1175 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1176 hw_ep->max_packet_sz_tx = maxpacket; 1177 1178 hw_ep->is_shared_fifo = true; 1179 break; 1180 } 1181 1182 /* NOTE rx and tx endpoint irqs aren't managed separately, 1183 * which happens to be ok 1184 */ 1185 musb->epmask |= (1 << hw_ep->epnum); 1186 1187 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1188} 1189 1190static struct fifo_cfg __initdata ep0_cfg = { 1191 .style = FIFO_RXTX, .maxpacket = 64, 1192}; 1193 1194static int __init ep_config_from_table(struct musb *musb) 1195{ 1196 const struct fifo_cfg *cfg; 1197 unsigned i, n; 1198 int offset; 1199 struct musb_hw_ep *hw_ep = musb->endpoints; 1200 1201 switch (fifo_mode) { 1202 default: 1203 fifo_mode = 0; 1204 /* FALLTHROUGH */ 1205 case 0: 1206 cfg = mode_0_cfg; 1207 n = ARRAY_SIZE(mode_0_cfg); 1208 break; 1209 case 1: 1210 cfg = mode_1_cfg; 1211 n = ARRAY_SIZE(mode_1_cfg); 1212 break; 1213 case 2: 1214 cfg = mode_2_cfg; 1215 n = ARRAY_SIZE(mode_2_cfg); 1216 break; 1217 case 3: 1218 cfg = mode_3_cfg; 1219 n = ARRAY_SIZE(mode_3_cfg); 1220 break; 1221 case 4: 1222 cfg = mode_4_cfg; 1223 n = ARRAY_SIZE(mode_4_cfg); 1224 break; 1225 case 5: 1226 cfg = mode_5_cfg; 1227 n = ARRAY_SIZE(mode_5_cfg); 1228 break; 1229 } 1230 1231 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1232 musb_driver_name, fifo_mode); 1233 1234 1235 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1236 /* assert(offset > 0) */ 1237 1238 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1239 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1240 */ 1241 1242 for (i = 0; i < n; i++) { 1243 u8 epn = cfg->hw_ep_num; 1244 1245 if (epn >= musb->config->num_eps) { 1246 pr_debug("%s: invalid ep %d\n", 1247 musb_driver_name, epn); 1248 return -EINVAL; 1249 } 1250 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1251 if (offset < 0) { 1252 pr_debug("%s: mem overrun, ep %d\n", 1253 musb_driver_name, epn); 1254 return -EINVAL; 1255 } 1256 epn++; 1257 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1258 } 1259 1260 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1261 musb_driver_name, 1262 n + 1, musb->config->num_eps * 2 - 1, 1263 offset, (1 << (musb->config->ram_bits + 2))); 1264 1265#ifdef CONFIG_USB_MUSB_HDRC_HCD 1266 if (!musb->bulk_ep) { 1267 pr_debug("%s: missing bulk\n", musb_driver_name); 1268 return -EINVAL; 1269 } 1270#endif 1271 1272 return 0; 1273} 1274 1275 1276/* 1277 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1278 * @param musb the controller 1279 */ 1280static int __init ep_config_from_hw(struct musb *musb) 1281{ 1282 u8 epnum = 0; 1283 struct musb_hw_ep *hw_ep; 1284 void *mbase = musb->mregs; 1285 int ret = 0; 1286 1287 DBG(2, "<== static silicon ep config\n"); 1288 1289 /* FIXME pick up ep0 maxpacket size */ 1290 1291 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1292 musb_ep_select(mbase, epnum); 1293 hw_ep = musb->endpoints + epnum; 1294 1295 ret = musb_read_fifosize(musb, hw_ep, epnum); 1296 if (ret < 0) 1297 break; 1298 1299 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1300 1301#ifdef CONFIG_USB_MUSB_HDRC_HCD 1302 /* pick an RX/TX endpoint for bulk */ 1303 if (hw_ep->max_packet_sz_tx < 512 1304 || hw_ep->max_packet_sz_rx < 512) 1305 continue; 1306 1307 /* REVISIT: this algorithm is lazy, we should at least 1308 * try to pick a double buffered endpoint. 1309 */ 1310 if (musb->bulk_ep) 1311 continue; 1312 musb->bulk_ep = hw_ep; 1313#endif 1314 } 1315 1316#ifdef CONFIG_USB_MUSB_HDRC_HCD 1317 if (!musb->bulk_ep) { 1318 pr_debug("%s: missing bulk\n", musb_driver_name); 1319 return -EINVAL; 1320 } 1321#endif 1322 1323 return 0; 1324} 1325 1326enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1327 1328/* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1329 * configure endpoints, or take their config from silicon 1330 */ 1331static int __init musb_core_init(u16 musb_type, struct musb *musb) 1332{ 1333 u8 reg; 1334 char *type; 1335 char aInfo[90], aRevision[32], aDate[12]; 1336 void __iomem *mbase = musb->mregs; 1337 int status = 0; 1338 int i; 1339 1340 /* log core options (read using indexed model) */ 1341 reg = musb_read_configdata(mbase); 1342 1343 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1344 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1345 strcat(aInfo, ", dyn FIFOs"); 1346 musb->dyn_fifo = true; 1347 } 1348 if (reg & MUSB_CONFIGDATA_MPRXE) { 1349 strcat(aInfo, ", bulk combine"); 1350 musb->bulk_combine = true; 1351 } 1352 if (reg & MUSB_CONFIGDATA_MPTXE) { 1353 strcat(aInfo, ", bulk split"); 1354 musb->bulk_split = true; 1355 } 1356 if (reg & MUSB_CONFIGDATA_HBRXE) { 1357 strcat(aInfo, ", HB-ISO Rx"); 1358 musb->hb_iso_rx = true; 1359 } 1360 if (reg & MUSB_CONFIGDATA_HBTXE) { 1361 strcat(aInfo, ", HB-ISO Tx"); 1362 musb->hb_iso_tx = true; 1363 } 1364 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1365 strcat(aInfo, ", SoftConn"); 1366 1367 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1368 musb_driver_name, reg, aInfo); 1369 1370 aDate[0] = 0; 1371 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1372 musb->is_multipoint = 1; 1373 type = "M"; 1374 } else { 1375 musb->is_multipoint = 0; 1376 type = ""; 1377#ifdef CONFIG_USB_MUSB_HDRC_HCD 1378#ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1379 printk(KERN_ERR 1380 "%s: kernel must blacklist external hubs\n", 1381 musb_driver_name); 1382#endif 1383#endif 1384 } 1385 1386 /* log release info */ 1387 musb->hwvers = musb_read_hwvers(mbase); 1388 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1389 MUSB_HWVERS_MINOR(musb->hwvers), 1390 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1391 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1392 musb_driver_name, type, aRevision, aDate); 1393 1394 /* configure ep0 */ 1395 musb_configure_ep0(musb); 1396 1397 /* discover endpoint configuration */ 1398 musb->nr_endpoints = 1; 1399 musb->epmask = 1; 1400 1401 if (musb->dyn_fifo) 1402 status = ep_config_from_table(musb); 1403 else 1404 status = ep_config_from_hw(musb); 1405 1406 if (status < 0) 1407 return status; 1408 1409 /* finish init, and print endpoint config */ 1410 for (i = 0; i < musb->nr_endpoints; i++) { 1411 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1412 1413 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1414#ifdef CONFIG_USB_TUSB6010 1415 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1416 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1417 hw_ep->fifo_sync_va = 1418 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1419 1420 if (i == 0) 1421 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1422 else 1423 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1424#endif 1425 1426 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1427#ifdef CONFIG_USB_MUSB_HDRC_HCD 1428 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1429 hw_ep->rx_reinit = 1; 1430 hw_ep->tx_reinit = 1; 1431#endif 1432 1433 if (hw_ep->max_packet_sz_tx) { 1434 DBG(1, 1435 "%s: hw_ep %d%s, %smax %d\n", 1436 musb_driver_name, i, 1437 hw_ep->is_shared_fifo ? "shared" : "tx", 1438 hw_ep->tx_double_buffered 1439 ? "doublebuffer, " : "", 1440 hw_ep->max_packet_sz_tx); 1441 } 1442 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1443 DBG(1, 1444 "%s: hw_ep %d%s, %smax %d\n", 1445 musb_driver_name, i, 1446 "rx", 1447 hw_ep->rx_double_buffered 1448 ? "doublebuffer, " : "", 1449 hw_ep->max_packet_sz_rx); 1450 } 1451 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1452 DBG(1, "hw_ep %d not configured\n", i); 1453 } 1454 1455 return 0; 1456} 1457 1458/*-------------------------------------------------------------------------*/ 1459 1460#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) 1461 1462static irqreturn_t generic_interrupt(int irq, void *__hci) 1463{ 1464 unsigned long flags; 1465 irqreturn_t retval = IRQ_NONE; 1466 struct musb *musb = __hci; 1467 1468 spin_lock_irqsave(&musb->lock, flags); 1469 1470 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1471 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1472 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1473 1474 if (musb->int_usb || musb->int_tx || musb->int_rx) 1475 retval = musb_interrupt(musb); 1476 1477 spin_unlock_irqrestore(&musb->lock, flags); 1478 1479 return retval; 1480} 1481 1482#else 1483#define generic_interrupt NULL 1484#endif 1485 1486/* 1487 * handle all the irqs defined by the HDRC core. for now we expect: other 1488 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1489 * will be assigned, and the irq will already have been acked. 1490 * 1491 * called in irq context with spinlock held, irqs blocked 1492 */ 1493irqreturn_t musb_interrupt(struct musb *musb) 1494{ 1495 irqreturn_t retval = IRQ_NONE; 1496 u8 devctl, power; 1497 int ep_num; 1498 u32 reg; 1499 1500 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1501 power = musb_readb(musb->mregs, MUSB_POWER); 1502 1503 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n", 1504 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1505 musb->int_usb, musb->int_tx, musb->int_rx); 1506 1507#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1508 if (is_otg_enabled(musb) || is_peripheral_enabled(musb)) 1509 if (!musb->gadget_driver) { 1510 DBG(5, "No gadget driver loaded\n"); 1511 return IRQ_HANDLED; 1512 } 1513#endif 1514 1515 /* the core can interrupt us for multiple reasons; docs have 1516 * a generic interrupt flowchart to follow 1517 */ 1518 if (musb->int_usb & STAGE0_MASK) 1519 retval |= musb_stage0_irq(musb, musb->int_usb, 1520 devctl, power); 1521 1522 /* "stage 1" is handling endpoint irqs */ 1523 1524 /* handle endpoint 0 first */ 1525 if (musb->int_tx & 1) { 1526 if (devctl & MUSB_DEVCTL_HM) 1527 retval |= musb_h_ep0_irq(musb); 1528 else 1529 retval |= musb_g_ep0_irq(musb); 1530 } 1531 1532 /* RX on endpoints 1-15 */ 1533 reg = musb->int_rx >> 1; 1534 ep_num = 1; 1535 while (reg) { 1536 if (reg & 1) { 1537 /* musb_ep_select(musb->mregs, ep_num); */ 1538 /* REVISIT just retval = ep->rx_irq(...) */ 1539 retval = IRQ_HANDLED; 1540 if (devctl & MUSB_DEVCTL_HM) { 1541 if (is_host_capable()) 1542 musb_host_rx(musb, ep_num); 1543 } else { 1544 if (is_peripheral_capable()) 1545 musb_g_rx(musb, ep_num); 1546 } 1547 } 1548 1549 reg >>= 1; 1550 ep_num++; 1551 } 1552 1553 /* TX on endpoints 1-15 */ 1554 reg = musb->int_tx >> 1; 1555 ep_num = 1; 1556 while (reg) { 1557 if (reg & 1) { 1558 /* musb_ep_select(musb->mregs, ep_num); */ 1559 /* REVISIT just retval |= ep->tx_irq(...) */ 1560 retval = IRQ_HANDLED; 1561 if (devctl & MUSB_DEVCTL_HM) { 1562 if (is_host_capable()) 1563 musb_host_tx(musb, ep_num); 1564 } else { 1565 if (is_peripheral_capable()) 1566 musb_g_tx(musb, ep_num); 1567 } 1568 } 1569 reg >>= 1; 1570 ep_num++; 1571 } 1572 1573 return retval; 1574} 1575 1576 1577#ifndef CONFIG_MUSB_PIO_ONLY 1578static int __initdata use_dma = 1; 1579 1580/* "modprobe ... use_dma=0" etc */ 1581module_param(use_dma, bool, 0); 1582MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1583 1584void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1585{ 1586 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1587 1588 /* called with controller lock already held */ 1589 1590 if (!epnum) { 1591#ifndef CONFIG_USB_TUSB_OMAP_DMA 1592 if (!is_cppi_enabled()) { 1593 /* endpoint 0 */ 1594 if (devctl & MUSB_DEVCTL_HM) 1595 musb_h_ep0_irq(musb); 1596 else 1597 musb_g_ep0_irq(musb); 1598 } 1599#endif 1600 } else { 1601 /* endpoints 1..15 */ 1602 if (transmit) { 1603 if (devctl & MUSB_DEVCTL_HM) { 1604 if (is_host_capable()) 1605 musb_host_tx(musb, epnum); 1606 } else { 1607 if (is_peripheral_capable()) 1608 musb_g_tx(musb, epnum); 1609 } 1610 } else { 1611 /* receive */ 1612 if (devctl & MUSB_DEVCTL_HM) { 1613 if (is_host_capable()) 1614 musb_host_rx(musb, epnum); 1615 } else { 1616 if (is_peripheral_capable()) 1617 musb_g_rx(musb, epnum); 1618 } 1619 } 1620 } 1621} 1622 1623#else 1624#define use_dma 0 1625#endif 1626 1627/*-------------------------------------------------------------------------*/ 1628 1629#ifdef CONFIG_SYSFS 1630 1631static ssize_t 1632musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1633{ 1634 struct musb *musb = dev_to_musb(dev); 1635 unsigned long flags; 1636 int ret = -EINVAL; 1637 1638 spin_lock_irqsave(&musb->lock, flags); 1639 ret = sprintf(buf, "%s\n", otg_state_string(musb)); 1640 spin_unlock_irqrestore(&musb->lock, flags); 1641 1642 return ret; 1643} 1644 1645static ssize_t 1646musb_mode_store(struct device *dev, struct device_attribute *attr, 1647 const char *buf, size_t n) 1648{ 1649 struct musb *musb = dev_to_musb(dev); 1650 unsigned long flags; 1651 int status; 1652 1653 spin_lock_irqsave(&musb->lock, flags); 1654 if (sysfs_streq(buf, "host")) 1655 status = musb_platform_set_mode(musb, MUSB_HOST); 1656 else if (sysfs_streq(buf, "peripheral")) 1657 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1658 else if (sysfs_streq(buf, "otg")) 1659 status = musb_platform_set_mode(musb, MUSB_OTG); 1660 else 1661 status = -EINVAL; 1662 spin_unlock_irqrestore(&musb->lock, flags); 1663 1664 return (status == 0) ? n : status; 1665} 1666static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1667 1668static ssize_t 1669musb_vbus_store(struct device *dev, struct device_attribute *attr, 1670 const char *buf, size_t n) 1671{ 1672 struct musb *musb = dev_to_musb(dev); 1673 unsigned long flags; 1674 unsigned long val; 1675 1676 if (sscanf(buf, "%lu", &val) < 1) { 1677 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1678 return -EINVAL; 1679 } 1680 1681 spin_lock_irqsave(&musb->lock, flags); 1682 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1683 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1684 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1685 musb->is_active = 0; 1686 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1687 spin_unlock_irqrestore(&musb->lock, flags); 1688 1689 return n; 1690} 1691 1692static ssize_t 1693musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1694{ 1695 struct musb *musb = dev_to_musb(dev); 1696 unsigned long flags; 1697 unsigned long val; 1698 int vbus; 1699 1700 spin_lock_irqsave(&musb->lock, flags); 1701 val = musb->a_wait_bcon; 1702 /* FIXME get_vbus_status() is normally #defined as false... 1703 * and is effectively TUSB-specific. 1704 */ 1705 vbus = musb_platform_get_vbus_status(musb); 1706 spin_unlock_irqrestore(&musb->lock, flags); 1707 1708 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1709 vbus ? "on" : "off", val); 1710} 1711static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1712 1713#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1714 1715/* Gadget drivers can't know that a host is connected so they might want 1716 * to start SRP, but users can. This allows userspace to trigger SRP. 1717 */ 1718static ssize_t 1719musb_srp_store(struct device *dev, struct device_attribute *attr, 1720 const char *buf, size_t n) 1721{ 1722 struct musb *musb = dev_to_musb(dev); 1723 unsigned short srp; 1724 1725 if (sscanf(buf, "%hu", &srp) != 1 1726 || (srp != 1)) { 1727 dev_err(dev, "SRP: Value must be 1\n"); 1728 return -EINVAL; 1729 } 1730 1731 if (srp == 1) 1732 musb_g_wakeup(musb); 1733 1734 return n; 1735} 1736static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1737 1738#endif /* CONFIG_USB_GADGET_MUSB_HDRC */ 1739 1740static struct attribute *musb_attributes[] = { 1741 &dev_attr_mode.attr, 1742 &dev_attr_vbus.attr, 1743#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1744 &dev_attr_srp.attr, 1745#endif 1746 NULL 1747}; 1748 1749static const struct attribute_group musb_attr_group = { 1750 .attrs = musb_attributes, 1751}; 1752 1753#endif /* sysfs */ 1754 1755/* Only used to provide driver mode change events */ 1756static void musb_irq_work(struct work_struct *data) 1757{ 1758 struct musb *musb = container_of(data, struct musb, irq_work); 1759 static int old_state; 1760 1761 if (musb->xceiv->state != old_state) { 1762 old_state = musb->xceiv->state; 1763 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1764 } 1765} 1766 1767/* -------------------------------------------------------------------------- 1768 * Init support 1769 */ 1770 1771static struct musb *__init 1772allocate_instance(struct device *dev, 1773 struct musb_hdrc_config *config, void __iomem *mbase) 1774{ 1775 struct musb *musb; 1776 struct musb_hw_ep *ep; 1777 int epnum; 1778#ifdef CONFIG_USB_MUSB_HDRC_HCD 1779 struct usb_hcd *hcd; 1780 1781 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1782 if (!hcd) 1783 return NULL; 1784 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1785 1786 musb = hcd_to_musb(hcd); 1787 INIT_LIST_HEAD(&musb->control); 1788 INIT_LIST_HEAD(&musb->in_bulk); 1789 INIT_LIST_HEAD(&musb->out_bulk); 1790 1791 hcd->uses_new_polling = 1; 1792 1793 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1794 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1795#else 1796 musb = kzalloc(sizeof *musb, GFP_KERNEL); 1797 if (!musb) 1798 return NULL; 1799 dev_set_drvdata(dev, musb); 1800 1801#endif 1802 1803 musb->mregs = mbase; 1804 musb->ctrl_base = mbase; 1805 musb->nIrq = -ENODEV; 1806 musb->config = config; 1807 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1808 for (epnum = 0, ep = musb->endpoints; 1809 epnum < musb->config->num_eps; 1810 epnum++, ep++) { 1811 ep->musb = musb; 1812 ep->epnum = epnum; 1813 } 1814 1815 musb->controller = dev; 1816 return musb; 1817} 1818 1819static void musb_free(struct musb *musb) 1820{ 1821 /* this has multiple entry modes. it handles fault cleanup after 1822 * probe(), where things may be partially set up, as well as rmmod 1823 * cleanup after everything's been de-activated. 1824 */ 1825 1826#ifdef CONFIG_SYSFS 1827 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1828#endif 1829 1830#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1831 musb_gadget_cleanup(musb); 1832#endif 1833 1834 if (musb->nIrq >= 0) { 1835 if (musb->irq_wake) 1836 disable_irq_wake(musb->nIrq); 1837 free_irq(musb->nIrq, musb); 1838 } 1839 if (is_dma_capable() && musb->dma_controller) { 1840 struct dma_controller *c = musb->dma_controller; 1841 1842 (void) c->stop(c); 1843 dma_controller_destroy(c); 1844 } 1845 1846#ifdef CONFIG_USB_MUSB_OTG 1847 put_device(musb->xceiv->dev); 1848#endif 1849 1850 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1851 musb_platform_exit(musb); 1852 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1853 1854 if (musb->clock) { 1855 clk_disable(musb->clock); 1856 clk_put(musb->clock); 1857 } 1858 1859#ifdef CONFIG_USB_MUSB_HDRC_HCD 1860 usb_put_hcd(musb_to_hcd(musb)); 1861#else 1862 kfree(musb); 1863#endif 1864} 1865 1866/* 1867 * Perform generic per-controller initialization. 1868 * 1869 * @pDevice: the controller (already clocked, etc) 1870 * @nIrq: irq 1871 * @mregs: virtual address of controller registers, 1872 * not yet corrected for platform-specific offsets 1873 */ 1874static int __init 1875musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1876{ 1877 int status; 1878 struct musb *musb; 1879 struct musb_hdrc_platform_data *plat = dev->platform_data; 1880 1881 /* The driver might handle more features than the board; OK. 1882 * Fail when the board needs a feature that's not enabled. 1883 */ 1884 if (!plat) { 1885 dev_dbg(dev, "no platform_data?\n"); 1886 return -ENODEV; 1887 } 1888 switch (plat->mode) { 1889 case MUSB_HOST: 1890#ifdef CONFIG_USB_MUSB_HDRC_HCD 1891 break; 1892#else 1893 goto bad_config; 1894#endif 1895 case MUSB_PERIPHERAL: 1896#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1897 break; 1898#else 1899 goto bad_config; 1900#endif 1901 case MUSB_OTG: 1902#ifdef CONFIG_USB_MUSB_OTG 1903 break; 1904#else 1905bad_config: 1906#endif 1907 default: 1908 dev_err(dev, "incompatible Kconfig role setting\n"); 1909 return -EINVAL; 1910 } 1911 1912 /* allocate */ 1913 musb = allocate_instance(dev, plat->config, ctrl); 1914 if (!musb) 1915 return -ENOMEM; 1916 1917 spin_lock_init(&musb->lock); 1918 musb->board_mode = plat->mode; 1919 musb->board_set_power = plat->set_power; 1920 musb->set_clock = plat->set_clock; 1921 musb->min_power = plat->min_power; 1922 1923 /* Clock usage is chip-specific ... functional clock (DaVinci, 1924 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core 1925 * code does is make sure a clock handle is available; platform 1926 * code manages it during start/stop and suspend/resume. 1927 */ 1928 if (plat->clock) { 1929 musb->clock = clk_get(dev, plat->clock); 1930 if (IS_ERR(musb->clock)) { 1931 status = PTR_ERR(musb->clock); 1932 musb->clock = NULL; 1933 goto fail; 1934 } 1935 } 1936 1937 /* The musb_platform_init() call: 1938 * - adjusts musb->mregs and musb->isr if needed, 1939 * - may initialize an integrated tranceiver 1940 * - initializes musb->xceiv, usually by otg_get_transceiver() 1941 * - activates clocks. 1942 * - stops powering VBUS 1943 * - assigns musb->board_set_vbus if host mode is enabled 1944 * 1945 * There are various transciever configurations. Blackfin, 1946 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1947 * external/discrete ones in various flavors (twl4030 family, 1948 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1949 */ 1950 musb->isr = generic_interrupt; 1951 status = musb_platform_init(musb); 1952 1953 if (status < 0) 1954 goto fail; 1955 if (!musb->isr) { 1956 status = -ENODEV; 1957 goto fail2; 1958 } 1959 1960#ifndef CONFIG_MUSB_PIO_ONLY 1961 if (use_dma && dev->dma_mask) { 1962 struct dma_controller *c; 1963 1964 c = dma_controller_create(musb, musb->mregs); 1965 musb->dma_controller = c; 1966 if (c) 1967 (void) c->start(c); 1968 } 1969#endif 1970 /* ideally this would be abstracted in platform setup */ 1971 if (!is_dma_capable() || !musb->dma_controller) 1972 dev->dma_mask = NULL; 1973 1974 /* be sure interrupts are disabled before connecting ISR */ 1975 musb_platform_disable(musb); 1976 musb_generic_disable(musb); 1977 1978 /* setup musb parts of the core (especially endpoints) */ 1979 status = musb_core_init(plat->config->multipoint 1980 ? MUSB_CONTROLLER_MHDRC 1981 : MUSB_CONTROLLER_HDRC, musb); 1982 if (status < 0) 1983 goto fail2; 1984 1985#ifdef CONFIG_USB_MUSB_OTG 1986 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 1987#endif 1988 1989 /* Init IRQ workqueue before request_irq */ 1990 INIT_WORK(&musb->irq_work, musb_irq_work); 1991 1992 /* attach to the IRQ */ 1993 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 1994 dev_err(dev, "request_irq %d failed!\n", nIrq); 1995 status = -ENODEV; 1996 goto fail2; 1997 } 1998 musb->nIrq = nIrq; 1999/* FIXME this handles wakeup irqs wrong */ 2000 if (enable_irq_wake(nIrq) == 0) { 2001 musb->irq_wake = 1; 2002 device_init_wakeup(dev, 1); 2003 } else { 2004 musb->irq_wake = 0; 2005 } 2006 2007 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n", 2008 musb_driver_name, 2009 ({char *s; 2010 switch (musb->board_mode) { 2011 case MUSB_HOST: s = "Host"; break; 2012 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2013 default: s = "OTG"; break; 2014 }; s; }), 2015 ctrl, 2016 (is_dma_capable() && musb->dma_controller) 2017 ? "DMA" : "PIO", 2018 musb->nIrq); 2019 2020 /* host side needs more setup */ 2021 if (is_host_enabled(musb)) { 2022 struct usb_hcd *hcd = musb_to_hcd(musb); 2023 u8 busctl; 2024 2025 otg_set_host(musb->xceiv, &hcd->self); 2026 2027 if (is_otg_enabled(musb)) 2028 hcd->self.otg_port = 1; 2029 musb->xceiv->host = &hcd->self; 2030 hcd->power_budget = 2 * (plat->power ? : 250); 2031 2032 /* program PHY to use external vBus if required */ 2033 if (plat->extvbus) { 2034 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL); 2035 busctl |= MUSB_ULPI_USE_EXTVBUS; 2036 musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl); 2037 } 2038 } 2039 2040 /* For the host-only role, we can activate right away. 2041 * (We expect the ID pin to be forcibly grounded!!) 2042 * Otherwise, wait till the gadget driver hooks up. 2043 */ 2044 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2045 MUSB_HST_MODE(musb); 2046 musb->xceiv->default_a = 1; 2047 musb->xceiv->state = OTG_STATE_A_IDLE; 2048 2049 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 2050 if (status) 2051 goto fail; 2052 2053 DBG(1, "%s mode, status %d, devctl %02x %c\n", 2054 "HOST", status, 2055 musb_readb(musb->mregs, MUSB_DEVCTL), 2056 (musb_readb(musb->mregs, MUSB_DEVCTL) 2057 & MUSB_DEVCTL_BDEVICE 2058 ? 'B' : 'A')); 2059 2060 } else /* peripheral is enabled */ { 2061 MUSB_DEV_MODE(musb); 2062 musb->xceiv->default_a = 0; 2063 musb->xceiv->state = OTG_STATE_B_IDLE; 2064 2065 status = musb_gadget_setup(musb); 2066 if (status) 2067 goto fail; 2068 2069 DBG(1, "%s mode, status %d, dev%02x\n", 2070 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2071 status, 2072 musb_readb(musb->mregs, MUSB_DEVCTL)); 2073 2074 } 2075 2076#ifdef CONFIG_SYSFS 2077 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2078#endif 2079 if (status) 2080 goto fail2; 2081 2082 return 0; 2083 2084fail2: 2085 musb_platform_exit(musb); 2086fail: 2087 dev_err(musb->controller, 2088 "musb_init_controller failed with status %d\n", status); 2089 2090 if (musb->clock) 2091 clk_put(musb->clock); 2092 device_init_wakeup(dev, 0); 2093 musb_free(musb); 2094 2095 return status; 2096 2097} 2098 2099/*-------------------------------------------------------------------------*/ 2100 2101/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2102 * bridge to a platform device; this driver then suffices. 2103 */ 2104 2105#ifndef CONFIG_MUSB_PIO_ONLY 2106static u64 *orig_dma_mask; 2107#endif 2108 2109static int __init musb_probe(struct platform_device *pdev) 2110{ 2111 struct device *dev = &pdev->dev; 2112 int irq = platform_get_irq(pdev, 0); 2113 int status; 2114 struct resource *iomem; 2115 void __iomem *base; 2116 2117 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2118 if (!iomem || irq == 0) 2119 return -ENODEV; 2120 2121 base = ioremap(iomem->start, resource_size(iomem)); 2122 if (!base) { 2123 dev_err(dev, "ioremap failed\n"); 2124 return -ENOMEM; 2125 } 2126 2127#ifndef CONFIG_MUSB_PIO_ONLY 2128 /* clobbered by use_dma=n */ 2129 orig_dma_mask = dev->dma_mask; 2130#endif 2131 2132 status = musb_init_controller(dev, irq, base); 2133 if (status < 0) 2134 iounmap(base); 2135 2136 return status; 2137} 2138 2139static int __exit musb_remove(struct platform_device *pdev) 2140{ 2141 struct musb *musb = dev_to_musb(&pdev->dev); 2142 void __iomem *ctrl_base = musb->ctrl_base; 2143 2144 /* this gets called on rmmod. 2145 * - Host mode: host may still be active 2146 * - Peripheral mode: peripheral is deactivated (or never-activated) 2147 * - OTG mode: both roles are deactivated (or never-activated) 2148 */ 2149 musb_shutdown(pdev); 2150#ifdef CONFIG_USB_MUSB_HDRC_HCD 2151 if (musb->board_mode == MUSB_HOST) 2152 usb_remove_hcd(musb_to_hcd(musb)); 2153#endif 2154 musb_free(musb); 2155 iounmap(ctrl_base); 2156 device_init_wakeup(&pdev->dev, 0); 2157#ifndef CONFIG_MUSB_PIO_ONLY 2158 pdev->dev.dma_mask = orig_dma_mask; 2159#endif 2160 return 0; 2161} 2162 2163#ifdef CONFIG_PM 2164 2165static struct musb_context_registers musb_context; 2166 2167void musb_save_context(struct musb *musb) 2168{ 2169 int i; 2170 void __iomem *musb_base = musb->mregs; 2171 2172 if (is_host_enabled(musb)) { 2173 musb_context.frame = musb_readw(musb_base, MUSB_FRAME); 2174 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2175 } 2176 musb_context.power = musb_readb(musb_base, MUSB_POWER); 2177 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2178 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2179 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2180 musb_context.index = musb_readb(musb_base, MUSB_INDEX); 2181 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2182 2183 for (i = 0; i < MUSB_C_NUM_EPS; ++i) { 2184 musb_writeb(musb_base, MUSB_INDEX, i); 2185 musb_context.index_regs[i].txmaxp = 2186 musb_readw(musb_base, 0x10 + MUSB_TXMAXP); 2187 musb_context.index_regs[i].txcsr = 2188 musb_readw(musb_base, 0x10 + MUSB_TXCSR); 2189 musb_context.index_regs[i].rxmaxp = 2190 musb_readw(musb_base, 0x10 + MUSB_RXMAXP); 2191 musb_context.index_regs[i].rxcsr = 2192 musb_readw(musb_base, 0x10 + MUSB_RXCSR); 2193 2194 if (musb->dyn_fifo) { 2195 musb_context.index_regs[i].txfifoadd = 2196 musb_read_txfifoadd(musb_base); 2197 musb_context.index_regs[i].rxfifoadd = 2198 musb_read_rxfifoadd(musb_base); 2199 musb_context.index_regs[i].txfifosz = 2200 musb_read_txfifosz(musb_base); 2201 musb_context.index_regs[i].rxfifosz = 2202 musb_read_rxfifosz(musb_base); 2203 } 2204 if (is_host_enabled(musb)) { 2205 musb_context.index_regs[i].txtype = 2206 musb_readb(musb_base, 0x10 + MUSB_TXTYPE); 2207 musb_context.index_regs[i].txinterval = 2208 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL); 2209 musb_context.index_regs[i].rxtype = 2210 musb_readb(musb_base, 0x10 + MUSB_RXTYPE); 2211 musb_context.index_regs[i].rxinterval = 2212 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL); 2213 2214 musb_context.index_regs[i].txfunaddr = 2215 musb_read_txfunaddr(musb_base, i); 2216 musb_context.index_regs[i].txhubaddr = 2217 musb_read_txhubaddr(musb_base, i); 2218 musb_context.index_regs[i].txhubport = 2219 musb_read_txhubport(musb_base, i); 2220 2221 musb_context.index_regs[i].rxfunaddr = 2222 musb_read_rxfunaddr(musb_base, i); 2223 musb_context.index_regs[i].rxhubaddr = 2224 musb_read_rxhubaddr(musb_base, i); 2225 musb_context.index_regs[i].rxhubport = 2226 musb_read_rxhubport(musb_base, i); 2227 } 2228 } 2229 2230 musb_writeb(musb_base, MUSB_INDEX, musb_context.index); 2231 2232 musb_platform_save_context(musb, &musb_context); 2233} 2234 2235void musb_restore_context(struct musb *musb) 2236{ 2237 int i; 2238 void __iomem *musb_base = musb->mregs; 2239 void __iomem *ep_target_regs; 2240 2241 musb_platform_restore_context(musb, &musb_context); 2242 2243 if (is_host_enabled(musb)) { 2244 musb_writew(musb_base, MUSB_FRAME, musb_context.frame); 2245 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode); 2246 } 2247 musb_writeb(musb_base, MUSB_POWER, musb_context.power); 2248 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe); 2249 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe); 2250 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe); 2251 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl); 2252 2253 for (i = 0; i < MUSB_C_NUM_EPS; ++i) { 2254 musb_writeb(musb_base, MUSB_INDEX, i); 2255 musb_writew(musb_base, 0x10 + MUSB_TXMAXP, 2256 musb_context.index_regs[i].txmaxp); 2257 musb_writew(musb_base, 0x10 + MUSB_TXCSR, 2258 musb_context.index_regs[i].txcsr); 2259 musb_writew(musb_base, 0x10 + MUSB_RXMAXP, 2260 musb_context.index_regs[i].rxmaxp); 2261 musb_writew(musb_base, 0x10 + MUSB_RXCSR, 2262 musb_context.index_regs[i].rxcsr); 2263 2264 if (musb->dyn_fifo) { 2265 musb_write_txfifosz(musb_base, 2266 musb_context.index_regs[i].txfifosz); 2267 musb_write_rxfifosz(musb_base, 2268 musb_context.index_regs[i].rxfifosz); 2269 musb_write_txfifoadd(musb_base, 2270 musb_context.index_regs[i].txfifoadd); 2271 musb_write_rxfifoadd(musb_base, 2272 musb_context.index_regs[i].rxfifoadd); 2273 } 2274 2275 if (is_host_enabled(musb)) { 2276 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE, 2277 musb_context.index_regs[i].txtype); 2278 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL, 2279 musb_context.index_regs[i].txinterval); 2280 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE, 2281 musb_context.index_regs[i].rxtype); 2282 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL, 2283 2284 musb_context.index_regs[i].rxinterval); 2285 musb_write_txfunaddr(musb_base, i, 2286 musb_context.index_regs[i].txfunaddr); 2287 musb_write_txhubaddr(musb_base, i, 2288 musb_context.index_regs[i].txhubaddr); 2289 musb_write_txhubport(musb_base, i, 2290 musb_context.index_regs[i].txhubport); 2291 2292 ep_target_regs = 2293 musb_read_target_reg_base(i, musb_base); 2294 2295 musb_write_rxfunaddr(ep_target_regs, 2296 musb_context.index_regs[i].rxfunaddr); 2297 musb_write_rxhubaddr(ep_target_regs, 2298 musb_context.index_regs[i].rxhubaddr); 2299 musb_write_rxhubport(ep_target_regs, 2300 musb_context.index_regs[i].rxhubport); 2301 } 2302 } 2303 2304 musb_writeb(musb_base, MUSB_INDEX, musb_context.index); 2305} 2306 2307static int musb_suspend(struct device *dev) 2308{ 2309 struct platform_device *pdev = to_platform_device(dev); 2310 unsigned long flags; 2311 struct musb *musb = dev_to_musb(&pdev->dev); 2312 2313 if (!musb->clock) 2314 return 0; 2315 2316 spin_lock_irqsave(&musb->lock, flags); 2317 2318 if (is_peripheral_active(musb)) { 2319 /* FIXME force disconnect unless we know USB will wake 2320 * the system up quickly enough to respond ... 2321 */ 2322 } else if (is_host_active(musb)) { 2323 /* we know all the children are suspended; sometimes 2324 * they will even be wakeup-enabled. 2325 */ 2326 } 2327 2328 musb_save_context(musb); 2329 2330 if (musb->set_clock) 2331 musb->set_clock(musb->clock, 0); 2332 else 2333 clk_disable(musb->clock); 2334 spin_unlock_irqrestore(&musb->lock, flags); 2335 return 0; 2336} 2337 2338static int musb_resume_noirq(struct device *dev) 2339{ 2340 struct platform_device *pdev = to_platform_device(dev); 2341 struct musb *musb = dev_to_musb(&pdev->dev); 2342 2343 if (!musb->clock) 2344 return 0; 2345 2346 if (musb->set_clock) 2347 musb->set_clock(musb->clock, 1); 2348 else 2349 clk_enable(musb->clock); 2350 2351 musb_restore_context(musb); 2352 2353 /* for static cmos like DaVinci, register values were preserved 2354 * unless for some reason the whole soc powered down or the USB 2355 * module got reset through the PSC (vs just being disabled). 2356 */ 2357 return 0; 2358} 2359 2360static const struct dev_pm_ops musb_dev_pm_ops = { 2361 .suspend = musb_suspend, 2362 .resume_noirq = musb_resume_noirq, 2363}; 2364 2365#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2366#else 2367#define MUSB_DEV_PM_OPS NULL 2368#endif 2369 2370static struct platform_driver musb_driver = { 2371 .driver = { 2372 .name = (char *)musb_driver_name, 2373 .bus = &platform_bus_type, 2374 .owner = THIS_MODULE, 2375 .pm = MUSB_DEV_PM_OPS, 2376 }, 2377 .remove = __exit_p(musb_remove), 2378 .shutdown = musb_shutdown, 2379}; 2380 2381/*-------------------------------------------------------------------------*/ 2382 2383static int __init musb_init(void) 2384{ 2385#ifdef CONFIG_USB_MUSB_HDRC_HCD 2386 if (usb_disabled()) 2387 return 0; 2388#endif 2389 2390 pr_info("%s: version " MUSB_VERSION ", " 2391#ifdef CONFIG_MUSB_PIO_ONLY 2392 "pio" 2393#elif defined(CONFIG_USB_TI_CPPI_DMA) 2394 "cppi-dma" 2395#elif defined(CONFIG_USB_INVENTRA_DMA) 2396 "musb-dma" 2397#elif defined(CONFIG_USB_TUSB_OMAP_DMA) 2398 "tusb-omap-dma" 2399#else 2400 "?dma?" 2401#endif 2402 ", " 2403#ifdef CONFIG_USB_MUSB_OTG 2404 "otg (peripheral+host)" 2405#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 2406 "peripheral" 2407#elif defined(CONFIG_USB_MUSB_HDRC_HCD) 2408 "host" 2409#endif 2410 ", debug=%d\n", 2411 musb_driver_name, musb_debug); 2412 return platform_driver_probe(&musb_driver, musb_probe); 2413} 2414 2415/* make us init after usbcore and i2c (transceivers, regulators, etc) 2416 * and before usb gadget and host-side drivers start to register 2417 */ 2418fs_initcall(musb_init); 2419 2420static void __exit musb_cleanup(void) 2421{ 2422 platform_driver_unregister(&musb_driver); 2423} 2424module_exit(musb_cleanup); 2425