musb_core.c revision de2e1b0c988c901989713869a8bea3b3d02bb9ce
1/* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35/* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82/* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92#include <linux/module.h> 93#include <linux/kernel.h> 94#include <linux/sched.h> 95#include <linux/slab.h> 96#include <linux/init.h> 97#include <linux/list.h> 98#include <linux/kobject.h> 99#include <linux/platform_device.h> 100#include <linux/io.h> 101 102#ifdef CONFIG_ARM 103#include <mach/hardware.h> 104#include <mach/memory.h> 105#include <asm/mach-types.h> 106#endif 107 108#include "musb_core.h" 109 110 111#ifdef CONFIG_ARCH_DAVINCI 112#include "davinci.h" 113#endif 114 115#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 116 117 118unsigned musb_debug; 119module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR); 120MODULE_PARM_DESC(debug, "Debug message level. Default = 0"); 121 122#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 123#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 124 125#define MUSB_VERSION "6.0" 126 127#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 128 129#define MUSB_DRIVER_NAME "musb_hdrc" 130const char musb_driver_name[] = MUSB_DRIVER_NAME; 131 132MODULE_DESCRIPTION(DRIVER_INFO); 133MODULE_AUTHOR(DRIVER_AUTHOR); 134MODULE_LICENSE("GPL"); 135MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 136 137 138/*-------------------------------------------------------------------------*/ 139 140static inline struct musb *dev_to_musb(struct device *dev) 141{ 142#ifdef CONFIG_USB_MUSB_HDRC_HCD 143 /* usbcore insists dev->driver_data is a "struct hcd *" */ 144 return hcd_to_musb(dev_get_drvdata(dev)); 145#else 146 return dev_get_drvdata(dev); 147#endif 148} 149 150/*-------------------------------------------------------------------------*/ 151 152#if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN) 153 154/* 155 * Load an endpoint's FIFO 156 */ 157void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 158{ 159 void __iomem *fifo = hw_ep->fifo; 160 161 prefetch((u8 *)src); 162 163 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 164 'T', hw_ep->epnum, fifo, len, src); 165 166 /* we can't assume unaligned reads work */ 167 if (likely((0x01 & (unsigned long) src) == 0)) { 168 u16 index = 0; 169 170 /* best case is 32bit-aligned source address */ 171 if ((0x02 & (unsigned long) src) == 0) { 172 if (len >= 4) { 173 writesl(fifo, src + index, len >> 2); 174 index += len & ~0x03; 175 } 176 if (len & 0x02) { 177 musb_writew(fifo, 0, *(u16 *)&src[index]); 178 index += 2; 179 } 180 } else { 181 if (len >= 2) { 182 writesw(fifo, src + index, len >> 1); 183 index += len & ~0x01; 184 } 185 } 186 if (len & 0x01) 187 musb_writeb(fifo, 0, src[index]); 188 } else { 189 /* byte aligned */ 190 writesb(fifo, src, len); 191 } 192} 193 194/* 195 * Unload an endpoint's FIFO 196 */ 197void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 198{ 199 void __iomem *fifo = hw_ep->fifo; 200 201 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 202 'R', hw_ep->epnum, fifo, len, dst); 203 204 /* we can't assume unaligned writes work */ 205 if (likely((0x01 & (unsigned long) dst) == 0)) { 206 u16 index = 0; 207 208 /* best case is 32bit-aligned destination address */ 209 if ((0x02 & (unsigned long) dst) == 0) { 210 if (len >= 4) { 211 readsl(fifo, dst, len >> 2); 212 index = len & ~0x03; 213 } 214 if (len & 0x02) { 215 *(u16 *)&dst[index] = musb_readw(fifo, 0); 216 index += 2; 217 } 218 } else { 219 if (len >= 2) { 220 readsw(fifo, dst, len >> 1); 221 index = len & ~0x01; 222 } 223 } 224 if (len & 0x01) 225 dst[index] = musb_readb(fifo, 0); 226 } else { 227 /* byte aligned */ 228 readsb(fifo, dst, len); 229 } 230} 231 232#endif /* normal PIO */ 233 234 235/*-------------------------------------------------------------------------*/ 236 237/* for high speed test mode; see USB 2.0 spec 7.1.20 */ 238static const u8 musb_test_packet[53] = { 239 /* implicit SYNC then DATA0 to start */ 240 241 /* JKJKJKJK x9 */ 242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 243 /* JJKKJJKK x8 */ 244 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 245 /* JJJJKKKK x8 */ 246 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 247 /* JJJJJJJKKKKKKK x8 */ 248 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 249 /* JJJJJJJK x8 */ 250 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 251 /* JKKKKKKK x10, JK */ 252 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 253 254 /* implicit CRC16 then EOP to end */ 255}; 256 257void musb_load_testpacket(struct musb *musb) 258{ 259 void __iomem *regs = musb->endpoints[0].regs; 260 261 musb_ep_select(musb->mregs, 0); 262 musb_write_fifo(musb->control_ep, 263 sizeof(musb_test_packet), musb_test_packet); 264 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 265} 266 267/*-------------------------------------------------------------------------*/ 268 269const char *otg_state_string(struct musb *musb) 270{ 271 switch (musb->xceiv->state) { 272 case OTG_STATE_A_IDLE: return "a_idle"; 273 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; 274 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; 275 case OTG_STATE_A_HOST: return "a_host"; 276 case OTG_STATE_A_SUSPEND: return "a_suspend"; 277 case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; 278 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; 279 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; 280 case OTG_STATE_B_IDLE: return "b_idle"; 281 case OTG_STATE_B_SRP_INIT: return "b_srp_init"; 282 case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; 283 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; 284 case OTG_STATE_B_HOST: return "b_host"; 285 default: return "UNDEFINED"; 286 } 287} 288 289#ifdef CONFIG_USB_MUSB_OTG 290 291/* 292 * Handles OTG hnp timeouts, such as b_ase0_brst 293 */ 294void musb_otg_timer_func(unsigned long data) 295{ 296 struct musb *musb = (struct musb *)data; 297 unsigned long flags; 298 299 spin_lock_irqsave(&musb->lock, flags); 300 switch (musb->xceiv->state) { 301 case OTG_STATE_B_WAIT_ACON: 302 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 303 musb_g_disconnect(musb); 304 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 305 musb->is_active = 0; 306 break; 307 case OTG_STATE_A_SUSPEND: 308 case OTG_STATE_A_WAIT_BCON: 309 DBG(1, "HNP: %s timeout\n", otg_state_string(musb)); 310 musb_set_vbus(musb, 0); 311 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 312 break; 313 default: 314 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb)); 315 } 316 musb->ignore_disconnect = 0; 317 spin_unlock_irqrestore(&musb->lock, flags); 318} 319 320/* 321 * Stops the HNP transition. Caller must take care of locking. 322 */ 323void musb_hnp_stop(struct musb *musb) 324{ 325 struct usb_hcd *hcd = musb_to_hcd(musb); 326 void __iomem *mbase = musb->mregs; 327 u8 reg; 328 329 DBG(1, "HNP: stop from %s\n", otg_state_string(musb)); 330 331 switch (musb->xceiv->state) { 332 case OTG_STATE_A_PERIPHERAL: 333 musb_g_disconnect(musb); 334 DBG(1, "HNP: back to %s\n", otg_state_string(musb)); 335 break; 336 case OTG_STATE_B_HOST: 337 DBG(1, "HNP: Disabling HR\n"); 338 hcd->self.is_b_host = 0; 339 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 340 MUSB_DEV_MODE(musb); 341 reg = musb_readb(mbase, MUSB_POWER); 342 reg |= MUSB_POWER_SUSPENDM; 343 musb_writeb(mbase, MUSB_POWER, reg); 344 /* REVISIT: Start SESSION_REQUEST here? */ 345 break; 346 default: 347 DBG(1, "HNP: Stopping in unknown state %s\n", 348 otg_state_string(musb)); 349 } 350 351 /* 352 * When returning to A state after HNP, avoid hub_port_rebounce(), 353 * which cause occasional OPT A "Did not receive reset after connect" 354 * errors. 355 */ 356 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 357} 358 359#endif 360 361/* 362 * Interrupt Service Routine to record USB "global" interrupts. 363 * Since these do not happen often and signify things of 364 * paramount importance, it seems OK to check them individually; 365 * the order of the tests is specified in the manual 366 * 367 * @param musb instance pointer 368 * @param int_usb register contents 369 * @param devctl 370 * @param power 371 */ 372 373#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \ 374 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \ 375 | MUSB_INTR_RESET) 376 377static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 378 u8 devctl, u8 power) 379{ 380 irqreturn_t handled = IRQ_NONE; 381 382 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 383 int_usb); 384 385 /* in host mode, the peripheral may issue remote wakeup. 386 * in peripheral mode, the host may resume the link. 387 * spurious RESUME irqs happen too, paired with SUSPEND. 388 */ 389 if (int_usb & MUSB_INTR_RESUME) { 390 handled = IRQ_HANDLED; 391 DBG(3, "RESUME (%s)\n", otg_state_string(musb)); 392 393 if (devctl & MUSB_DEVCTL_HM) { 394#ifdef CONFIG_USB_MUSB_HDRC_HCD 395 void __iomem *mbase = musb->mregs; 396 397 switch (musb->xceiv->state) { 398 case OTG_STATE_A_SUSPEND: 399 /* remote wakeup? later, GetPortStatus 400 * will stop RESUME signaling 401 */ 402 403 if (power & MUSB_POWER_SUSPENDM) { 404 /* spurious */ 405 musb->int_usb &= ~MUSB_INTR_SUSPEND; 406 DBG(2, "Spurious SUSPENDM\n"); 407 break; 408 } 409 410 power &= ~MUSB_POWER_SUSPENDM; 411 musb_writeb(mbase, MUSB_POWER, 412 power | MUSB_POWER_RESUME); 413 414 musb->port1_status |= 415 (USB_PORT_STAT_C_SUSPEND << 16) 416 | MUSB_PORT_STAT_RESUME; 417 musb->rh_timer = jiffies 418 + msecs_to_jiffies(20); 419 420 musb->xceiv->state = OTG_STATE_A_HOST; 421 musb->is_active = 1; 422 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 423 break; 424 case OTG_STATE_B_WAIT_ACON: 425 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 426 musb->is_active = 1; 427 MUSB_DEV_MODE(musb); 428 break; 429 default: 430 WARNING("bogus %s RESUME (%s)\n", 431 "host", 432 otg_state_string(musb)); 433 } 434#endif 435 } else { 436 switch (musb->xceiv->state) { 437#ifdef CONFIG_USB_MUSB_HDRC_HCD 438 case OTG_STATE_A_SUSPEND: 439 /* possibly DISCONNECT is upcoming */ 440 musb->xceiv->state = OTG_STATE_A_HOST; 441 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 442 break; 443#endif 444#ifdef CONFIG_USB_GADGET_MUSB_HDRC 445 case OTG_STATE_B_WAIT_ACON: 446 case OTG_STATE_B_PERIPHERAL: 447 /* disconnect while suspended? we may 448 * not get a disconnect irq... 449 */ 450 if ((devctl & MUSB_DEVCTL_VBUS) 451 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 452 ) { 453 musb->int_usb |= MUSB_INTR_DISCONNECT; 454 musb->int_usb &= ~MUSB_INTR_SUSPEND; 455 break; 456 } 457 musb_g_resume(musb); 458 break; 459 case OTG_STATE_B_IDLE: 460 musb->int_usb &= ~MUSB_INTR_SUSPEND; 461 break; 462#endif 463 default: 464 WARNING("bogus %s RESUME (%s)\n", 465 "peripheral", 466 otg_state_string(musb)); 467 } 468 } 469 } 470 471#ifdef CONFIG_USB_MUSB_HDRC_HCD 472 /* see manual for the order of the tests */ 473 if (int_usb & MUSB_INTR_SESSREQ) { 474 void __iomem *mbase = musb->mregs; 475 476 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); 477 478 /* IRQ arrives from ID pin sense or (later, if VBUS power 479 * is removed) SRP. responses are time critical: 480 * - turn on VBUS (with silicon-specific mechanism) 481 * - go through A_WAIT_VRISE 482 * - ... to A_WAIT_BCON. 483 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 484 */ 485 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 486 musb->ep0_stage = MUSB_EP0_START; 487 musb->xceiv->state = OTG_STATE_A_IDLE; 488 MUSB_HST_MODE(musb); 489 musb_set_vbus(musb, 1); 490 491 handled = IRQ_HANDLED; 492 } 493 494 if (int_usb & MUSB_INTR_VBUSERROR) { 495 int ignore = 0; 496 497 /* During connection as an A-Device, we may see a short 498 * current spikes causing voltage drop, because of cable 499 * and peripheral capacitance combined with vbus draw. 500 * (So: less common with truly self-powered devices, where 501 * vbus doesn't act like a power supply.) 502 * 503 * Such spikes are short; usually less than ~500 usec, max 504 * of ~2 msec. That is, they're not sustained overcurrent 505 * errors, though they're reported using VBUSERROR irqs. 506 * 507 * Workarounds: (a) hardware: use self powered devices. 508 * (b) software: ignore non-repeated VBUS errors. 509 * 510 * REVISIT: do delays from lots of DEBUG_KERNEL checks 511 * make trouble here, keeping VBUS < 4.4V ? 512 */ 513 switch (musb->xceiv->state) { 514 case OTG_STATE_A_HOST: 515 /* recovery is dicey once we've gotten past the 516 * initial stages of enumeration, but if VBUS 517 * stayed ok at the other end of the link, and 518 * another reset is due (at least for high speed, 519 * to redo the chirp etc), it might work OK... 520 */ 521 case OTG_STATE_A_WAIT_BCON: 522 case OTG_STATE_A_WAIT_VRISE: 523 if (musb->vbuserr_retry) { 524 void __iomem *mbase = musb->mregs; 525 526 musb->vbuserr_retry--; 527 ignore = 1; 528 devctl |= MUSB_DEVCTL_SESSION; 529 musb_writeb(mbase, MUSB_DEVCTL, devctl); 530 } else { 531 musb->port1_status |= 532 USB_PORT_STAT_OVERCURRENT 533 | (USB_PORT_STAT_C_OVERCURRENT << 16); 534 } 535 break; 536 default: 537 break; 538 } 539 540 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 541 otg_state_string(musb), 542 devctl, 543 ({ char *s; 544 switch (devctl & MUSB_DEVCTL_VBUS) { 545 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 546 s = "<SessEnd"; break; 547 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 548 s = "<AValid"; break; 549 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 550 s = "<VBusValid"; break; 551 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 552 default: 553 s = "VALID"; break; 554 }; s; }), 555 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 556 musb->port1_status); 557 558 /* go through A_WAIT_VFALL then start a new session */ 559 if (!ignore) 560 musb_set_vbus(musb, 0); 561 handled = IRQ_HANDLED; 562 } 563 564 565 if (int_usb & MUSB_INTR_SUSPEND) { 566 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", 567 otg_state_string(musb), devctl, power); 568 handled = IRQ_HANDLED; 569 570 switch (musb->xceiv->state) { 571#ifdef CONFIG_USB_MUSB_OTG 572 case OTG_STATE_A_PERIPHERAL: 573 /* We also come here if the cable is removed, since 574 * this silicon doesn't report ID-no-longer-grounded. 575 * 576 * We depend on T(a_wait_bcon) to shut us down, and 577 * hope users don't do anything dicey during this 578 * undesired detour through A_WAIT_BCON. 579 */ 580 musb_hnp_stop(musb); 581 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 582 musb_root_disconnect(musb); 583 musb_platform_try_idle(musb, jiffies 584 + msecs_to_jiffies(musb->a_wait_bcon 585 ? : OTG_TIME_A_WAIT_BCON)); 586 587 break; 588#endif 589 case OTG_STATE_B_IDLE: 590 if (!musb->is_active) 591 break; 592 case OTG_STATE_B_PERIPHERAL: 593 musb_g_suspend(musb); 594 musb->is_active = is_otg_enabled(musb) 595 && musb->xceiv->gadget->b_hnp_enable; 596 if (musb->is_active) { 597#ifdef CONFIG_USB_MUSB_OTG 598 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 599 DBG(1, "HNP: Setting timer for b_ase0_brst\n"); 600 mod_timer(&musb->otg_timer, jiffies 601 + msecs_to_jiffies( 602 OTG_TIME_B_ASE0_BRST)); 603#endif 604 } 605 break; 606 case OTG_STATE_A_WAIT_BCON: 607 if (musb->a_wait_bcon != 0) 608 musb_platform_try_idle(musb, jiffies 609 + msecs_to_jiffies(musb->a_wait_bcon)); 610 break; 611 case OTG_STATE_A_HOST: 612 musb->xceiv->state = OTG_STATE_A_SUSPEND; 613 musb->is_active = is_otg_enabled(musb) 614 && musb->xceiv->host->b_hnp_enable; 615 break; 616 case OTG_STATE_B_HOST: 617 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 618 DBG(1, "REVISIT: SUSPEND as B_HOST\n"); 619 break; 620 default: 621 /* "should not happen" */ 622 musb->is_active = 0; 623 break; 624 } 625 } 626 627 if (int_usb & MUSB_INTR_CONNECT) { 628 struct usb_hcd *hcd = musb_to_hcd(musb); 629 void __iomem *mbase = musb->mregs; 630 631 handled = IRQ_HANDLED; 632 musb->is_active = 1; 633 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); 634 635 musb->ep0_stage = MUSB_EP0_START; 636 637#ifdef CONFIG_USB_MUSB_OTG 638 /* flush endpoints when transitioning from Device Mode */ 639 if (is_peripheral_active(musb)) { 640 /* REVISIT HNP; just force disconnect */ 641 } 642 musb_writew(mbase, MUSB_INTRTXE, musb->epmask); 643 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe); 644 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7); 645#endif 646 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 647 |USB_PORT_STAT_HIGH_SPEED 648 |USB_PORT_STAT_ENABLE 649 ); 650 musb->port1_status |= USB_PORT_STAT_CONNECTION 651 |(USB_PORT_STAT_C_CONNECTION << 16); 652 653 /* high vs full speed is just a guess until after reset */ 654 if (devctl & MUSB_DEVCTL_LSDEV) 655 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 656 657 /* indicate new connection to OTG machine */ 658 switch (musb->xceiv->state) { 659 case OTG_STATE_B_PERIPHERAL: 660 if (int_usb & MUSB_INTR_SUSPEND) { 661 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); 662 int_usb &= ~MUSB_INTR_SUSPEND; 663 goto b_host; 664 } else 665 DBG(1, "CONNECT as b_peripheral???\n"); 666 break; 667 case OTG_STATE_B_WAIT_ACON: 668 DBG(1, "HNP: CONNECT, now b_host\n"); 669b_host: 670 musb->xceiv->state = OTG_STATE_B_HOST; 671 hcd->self.is_b_host = 1; 672 musb->ignore_disconnect = 0; 673 del_timer(&musb->otg_timer); 674 break; 675 default: 676 if ((devctl & MUSB_DEVCTL_VBUS) 677 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 678 musb->xceiv->state = OTG_STATE_A_HOST; 679 hcd->self.is_b_host = 0; 680 } 681 break; 682 } 683 684 /* poke the root hub */ 685 MUSB_HST_MODE(musb); 686 if (hcd->status_urb) 687 usb_hcd_poll_rh_status(hcd); 688 else 689 usb_hcd_resume_root_hub(hcd); 690 691 DBG(1, "CONNECT (%s) devctl %02x\n", 692 otg_state_string(musb), devctl); 693 } 694#endif /* CONFIG_USB_MUSB_HDRC_HCD */ 695 696 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 697 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n", 698 otg_state_string(musb), 699 MUSB_MODE(musb), devctl); 700 handled = IRQ_HANDLED; 701 702 switch (musb->xceiv->state) { 703#ifdef CONFIG_USB_MUSB_HDRC_HCD 704 case OTG_STATE_A_HOST: 705 case OTG_STATE_A_SUSPEND: 706 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 707 musb_root_disconnect(musb); 708 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 709 musb_platform_try_idle(musb, jiffies 710 + msecs_to_jiffies(musb->a_wait_bcon)); 711 break; 712#endif /* HOST */ 713#ifdef CONFIG_USB_MUSB_OTG 714 case OTG_STATE_B_HOST: 715 /* REVISIT this behaves for "real disconnect" 716 * cases; make sure the other transitions from 717 * from B_HOST act right too. The B_HOST code 718 * in hnp_stop() is currently not used... 719 */ 720 musb_root_disconnect(musb); 721 musb_to_hcd(musb)->self.is_b_host = 0; 722 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 723 MUSB_DEV_MODE(musb); 724 musb_g_disconnect(musb); 725 break; 726 case OTG_STATE_A_PERIPHERAL: 727 musb_hnp_stop(musb); 728 musb_root_disconnect(musb); 729 /* FALLTHROUGH */ 730 case OTG_STATE_B_WAIT_ACON: 731 /* FALLTHROUGH */ 732#endif /* OTG */ 733#ifdef CONFIG_USB_GADGET_MUSB_HDRC 734 case OTG_STATE_B_PERIPHERAL: 735 case OTG_STATE_B_IDLE: 736 musb_g_disconnect(musb); 737 break; 738#endif /* GADGET */ 739 default: 740 WARNING("unhandled DISCONNECT transition (%s)\n", 741 otg_state_string(musb)); 742 break; 743 } 744 } 745 746 /* mentor saves a bit: bus reset and babble share the same irq. 747 * only host sees babble; only peripheral sees bus reset. 748 */ 749 if (int_usb & MUSB_INTR_RESET) { 750 handled = IRQ_HANDLED; 751 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 752 /* 753 * Looks like non-HS BABBLE can be ignored, but 754 * HS BABBLE is an error condition. For HS the solution 755 * is to avoid babble in the first place and fix what 756 * caused BABBLE. When HS BABBLE happens we can only 757 * stop the session. 758 */ 759 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 760 DBG(1, "BABBLE devctl: %02x\n", devctl); 761 else { 762 ERR("Stopping host session -- babble\n"); 763 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 764 } 765 } else if (is_peripheral_capable()) { 766 DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); 767 switch (musb->xceiv->state) { 768#ifdef CONFIG_USB_OTG 769 case OTG_STATE_A_SUSPEND: 770 /* We need to ignore disconnect on suspend 771 * otherwise tusb 2.0 won't reconnect after a 772 * power cycle, which breaks otg compliance. 773 */ 774 musb->ignore_disconnect = 1; 775 musb_g_reset(musb); 776 /* FALLTHROUGH */ 777 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 778 /* never use invalid T(a_wait_bcon) */ 779 DBG(1, "HNP: in %s, %d msec timeout\n", 780 otg_state_string(musb), 781 TA_WAIT_BCON(musb)); 782 mod_timer(&musb->otg_timer, jiffies 783 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 784 break; 785 case OTG_STATE_A_PERIPHERAL: 786 musb->ignore_disconnect = 0; 787 del_timer(&musb->otg_timer); 788 musb_g_reset(musb); 789 break; 790 case OTG_STATE_B_WAIT_ACON: 791 DBG(1, "HNP: RESET (%s), to b_peripheral\n", 792 otg_state_string(musb)); 793 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 794 musb_g_reset(musb); 795 break; 796#endif 797 case OTG_STATE_B_IDLE: 798 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 799 /* FALLTHROUGH */ 800 case OTG_STATE_B_PERIPHERAL: 801 musb_g_reset(musb); 802 break; 803 default: 804 DBG(1, "Unhandled BUS RESET as %s\n", 805 otg_state_string(musb)); 806 } 807 } 808 } 809 810#if 0 811/* REVISIT ... this would be for multiplexing periodic endpoints, or 812 * supporting transfer phasing to prevent exceeding ISO bandwidth 813 * limits of a given frame or microframe. 814 * 815 * It's not needed for peripheral side, which dedicates endpoints; 816 * though it _might_ use SOF irqs for other purposes. 817 * 818 * And it's not currently needed for host side, which also dedicates 819 * endpoints, relies on TX/RX interval registers, and isn't claimed 820 * to support ISO transfers yet. 821 */ 822 if (int_usb & MUSB_INTR_SOF) { 823 void __iomem *mbase = musb->mregs; 824 struct musb_hw_ep *ep; 825 u8 epnum; 826 u16 frame; 827 828 DBG(6, "START_OF_FRAME\n"); 829 handled = IRQ_HANDLED; 830 831 /* start any periodic Tx transfers waiting for current frame */ 832 frame = musb_readw(mbase, MUSB_FRAME); 833 ep = musb->endpoints; 834 for (epnum = 1; (epnum < musb->nr_endpoints) 835 && (musb->epmask >= (1 << epnum)); 836 epnum++, ep++) { 837 /* 838 * FIXME handle framecounter wraps (12 bits) 839 * eliminate duplicated StartUrb logic 840 */ 841 if (ep->dwWaitFrame >= frame) { 842 ep->dwWaitFrame = 0; 843 pr_debug("SOF --> periodic TX%s on %d\n", 844 ep->tx_channel ? " DMA" : "", 845 epnum); 846 if (!ep->tx_channel) 847 musb_h_tx_start(musb, epnum); 848 else 849 cppi_hostdma_start(musb, epnum); 850 } 851 } /* end of for loop */ 852 } 853#endif 854 855 schedule_work(&musb->irq_work); 856 857 return handled; 858} 859 860/*-------------------------------------------------------------------------*/ 861 862/* 863* Program the HDRC to start (enable interrupts, dma, etc.). 864*/ 865void musb_start(struct musb *musb) 866{ 867 void __iomem *regs = musb->mregs; 868 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 869 870 DBG(2, "<== devctl %02x\n", devctl); 871 872 /* Set INT enable registers, enable interrupts */ 873 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 874 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 875 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 876 877 musb_writeb(regs, MUSB_TESTMODE, 0); 878 879 /* put into basic highspeed mode and start session */ 880 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 881 | MUSB_POWER_SOFTCONN 882 | MUSB_POWER_HSENAB 883 /* ENSUSPEND wedges tusb */ 884 /* | MUSB_POWER_ENSUSPEND */ 885 ); 886 887 musb->is_active = 0; 888 devctl = musb_readb(regs, MUSB_DEVCTL); 889 devctl &= ~MUSB_DEVCTL_SESSION; 890 891 if (is_otg_enabled(musb)) { 892 /* session started after: 893 * (a) ID-grounded irq, host mode; 894 * (b) vbus present/connect IRQ, peripheral mode; 895 * (c) peripheral initiates, using SRP 896 */ 897 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 898 musb->is_active = 1; 899 else 900 devctl |= MUSB_DEVCTL_SESSION; 901 902 } else if (is_host_enabled(musb)) { 903 /* assume ID pin is hard-wired to ground */ 904 devctl |= MUSB_DEVCTL_SESSION; 905 906 } else /* peripheral is enabled */ { 907 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 908 musb->is_active = 1; 909 } 910 musb_platform_enable(musb); 911 musb_writeb(regs, MUSB_DEVCTL, devctl); 912} 913 914 915static void musb_generic_disable(struct musb *musb) 916{ 917 void __iomem *mbase = musb->mregs; 918 u16 temp; 919 920 /* disable interrupts */ 921 musb_writeb(mbase, MUSB_INTRUSBE, 0); 922 musb_writew(mbase, MUSB_INTRTXE, 0); 923 musb_writew(mbase, MUSB_INTRRXE, 0); 924 925 /* off */ 926 musb_writeb(mbase, MUSB_DEVCTL, 0); 927 928 /* flush pending interrupts */ 929 temp = musb_readb(mbase, MUSB_INTRUSB); 930 temp = musb_readw(mbase, MUSB_INTRTX); 931 temp = musb_readw(mbase, MUSB_INTRRX); 932 933} 934 935/* 936 * Make the HDRC stop (disable interrupts, etc.); 937 * reversible by musb_start 938 * called on gadget driver unregister 939 * with controller locked, irqs blocked 940 * acts as a NOP unless some role activated the hardware 941 */ 942void musb_stop(struct musb *musb) 943{ 944 /* stop IRQs, timers, ... */ 945 musb_platform_disable(musb); 946 musb_generic_disable(musb); 947 DBG(3, "HDRC disabled\n"); 948 949 /* FIXME 950 * - mark host and/or peripheral drivers unusable/inactive 951 * - disable DMA (and enable it in HdrcStart) 952 * - make sure we can musb_start() after musb_stop(); with 953 * OTG mode, gadget driver module rmmod/modprobe cycles that 954 * - ... 955 */ 956 musb_platform_try_idle(musb, 0); 957} 958 959static void musb_shutdown(struct platform_device *pdev) 960{ 961 struct musb *musb = dev_to_musb(&pdev->dev); 962 unsigned long flags; 963 964 spin_lock_irqsave(&musb->lock, flags); 965 musb_platform_disable(musb); 966 musb_generic_disable(musb); 967 if (musb->clock) 968 clk_put(musb->clock); 969 spin_unlock_irqrestore(&musb->lock, flags); 970 971 /* FIXME power down */ 972} 973 974 975/*-------------------------------------------------------------------------*/ 976 977/* 978 * The silicon either has hard-wired endpoint configurations, or else 979 * "dynamic fifo" sizing. The driver has support for both, though at this 980 * writing only the dynamic sizing is very well tested. Since we switched 981 * away from compile-time hardware parameters, we can no longer rely on 982 * dead code elimination to leave only the relevant one in the object file. 983 * 984 * We don't currently use dynamic fifo setup capability to do anything 985 * more than selecting one of a bunch of predefined configurations. 986 */ 987#if defined(CONFIG_USB_TUSB6010) || \ 988 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) 989static ushort __initdata fifo_mode = 4; 990#else 991static ushort __initdata fifo_mode = 2; 992#endif 993 994/* "modprobe ... fifo_mode=1" etc */ 995module_param(fifo_mode, ushort, 0); 996MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 997 998/* 999 * tables defining fifo_mode values. define more if you like. 1000 * for host side, make sure both halves of ep1 are set up. 1001 */ 1002 1003/* mode 0 - fits in 2KB */ 1004static struct musb_fifo_cfg __initdata mode_0_cfg[] = { 1005{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1006{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1007{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1008{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1009{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1010}; 1011 1012/* mode 1 - fits in 4KB */ 1013static struct musb_fifo_cfg __initdata mode_1_cfg[] = { 1014{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1015{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1016{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1017{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1018{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1019}; 1020 1021/* mode 2 - fits in 4KB */ 1022static struct musb_fifo_cfg __initdata mode_2_cfg[] = { 1023{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1024{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1025{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1026{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1027{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1028{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1029}; 1030 1031/* mode 3 - fits in 4KB */ 1032static struct musb_fifo_cfg __initdata mode_3_cfg[] = { 1033{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1034{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1035{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1036{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1037{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1038{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1039}; 1040 1041/* mode 4 - fits in 16KB */ 1042static struct musb_fifo_cfg __initdata mode_4_cfg[] = { 1043{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1044{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1045{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1046{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1047{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1048{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1049{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1050{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1051{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1052{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1053{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1054{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1055{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1056{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1057{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1058{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1059{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1060{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1061{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1062{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1063{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1064{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1065{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1066{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1067{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1068{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1069{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1070}; 1071 1072/* mode 5 - fits in 8KB */ 1073static struct musb_fifo_cfg __initdata mode_5_cfg[] = { 1074{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1075{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1076{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1077{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1078{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1079{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1080{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1081{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1082{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1083{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1084{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1085{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1086{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1087{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1088{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1089{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1090{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1091{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1092{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1093{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1094{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1095{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1096{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1097{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1098{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1099{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1100{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1101}; 1102 1103/* 1104 * configure a fifo; for non-shared endpoints, this may be called 1105 * once for a tx fifo and once for an rx fifo. 1106 * 1107 * returns negative errno or offset for next fifo. 1108 */ 1109static int __init 1110fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1111 const struct musb_fifo_cfg *cfg, u16 offset) 1112{ 1113 void __iomem *mbase = musb->mregs; 1114 int size = 0; 1115 u16 maxpacket = cfg->maxpacket; 1116 u16 c_off = offset >> 3; 1117 u8 c_size; 1118 1119 /* expect hw_ep has already been zero-initialized */ 1120 1121 size = ffs(max(maxpacket, (u16) 8)) - 1; 1122 maxpacket = 1 << size; 1123 1124 c_size = size - 3; 1125 if (cfg->mode == BUF_DOUBLE) { 1126 if ((offset + (maxpacket << 1)) > 1127 (1 << (musb->config->ram_bits + 2))) 1128 return -EMSGSIZE; 1129 c_size |= MUSB_FIFOSZ_DPB; 1130 } else { 1131 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1132 return -EMSGSIZE; 1133 } 1134 1135 /* configure the FIFO */ 1136 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1137 1138#ifdef CONFIG_USB_MUSB_HDRC_HCD 1139 /* EP0 reserved endpoint for control, bidirectional; 1140 * EP1 reserved for bulk, two unidirection halves. 1141 */ 1142 if (hw_ep->epnum == 1) 1143 musb->bulk_ep = hw_ep; 1144 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1145#endif 1146 switch (cfg->style) { 1147 case FIFO_TX: 1148 musb_write_txfifosz(mbase, c_size); 1149 musb_write_txfifoadd(mbase, c_off); 1150 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1151 hw_ep->max_packet_sz_tx = maxpacket; 1152 break; 1153 case FIFO_RX: 1154 musb_write_rxfifosz(mbase, c_size); 1155 musb_write_rxfifoadd(mbase, c_off); 1156 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1157 hw_ep->max_packet_sz_rx = maxpacket; 1158 break; 1159 case FIFO_RXTX: 1160 musb_write_txfifosz(mbase, c_size); 1161 musb_write_txfifoadd(mbase, c_off); 1162 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1163 hw_ep->max_packet_sz_rx = maxpacket; 1164 1165 musb_write_rxfifosz(mbase, c_size); 1166 musb_write_rxfifoadd(mbase, c_off); 1167 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1168 hw_ep->max_packet_sz_tx = maxpacket; 1169 1170 hw_ep->is_shared_fifo = true; 1171 break; 1172 } 1173 1174 /* NOTE rx and tx endpoint irqs aren't managed separately, 1175 * which happens to be ok 1176 */ 1177 musb->epmask |= (1 << hw_ep->epnum); 1178 1179 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1180} 1181 1182static struct musb_fifo_cfg __initdata ep0_cfg = { 1183 .style = FIFO_RXTX, .maxpacket = 64, 1184}; 1185 1186static int __init ep_config_from_table(struct musb *musb) 1187{ 1188 const struct musb_fifo_cfg *cfg; 1189 unsigned i, n; 1190 int offset; 1191 struct musb_hw_ep *hw_ep = musb->endpoints; 1192 1193 if (musb->config->fifo_cfg) { 1194 cfg = musb->config->fifo_cfg; 1195 n = musb->config->fifo_cfg_size; 1196 goto done; 1197 } 1198 1199 switch (fifo_mode) { 1200 default: 1201 fifo_mode = 0; 1202 /* FALLTHROUGH */ 1203 case 0: 1204 cfg = mode_0_cfg; 1205 n = ARRAY_SIZE(mode_0_cfg); 1206 break; 1207 case 1: 1208 cfg = mode_1_cfg; 1209 n = ARRAY_SIZE(mode_1_cfg); 1210 break; 1211 case 2: 1212 cfg = mode_2_cfg; 1213 n = ARRAY_SIZE(mode_2_cfg); 1214 break; 1215 case 3: 1216 cfg = mode_3_cfg; 1217 n = ARRAY_SIZE(mode_3_cfg); 1218 break; 1219 case 4: 1220 cfg = mode_4_cfg; 1221 n = ARRAY_SIZE(mode_4_cfg); 1222 break; 1223 case 5: 1224 cfg = mode_5_cfg; 1225 n = ARRAY_SIZE(mode_5_cfg); 1226 break; 1227 } 1228 1229 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1230 musb_driver_name, fifo_mode); 1231 1232 1233done: 1234 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1235 /* assert(offset > 0) */ 1236 1237 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1238 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1239 */ 1240 1241 for (i = 0; i < n; i++) { 1242 u8 epn = cfg->hw_ep_num; 1243 1244 if (epn >= musb->config->num_eps) { 1245 pr_debug("%s: invalid ep %d\n", 1246 musb_driver_name, epn); 1247 return -EINVAL; 1248 } 1249 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1250 if (offset < 0) { 1251 pr_debug("%s: mem overrun, ep %d\n", 1252 musb_driver_name, epn); 1253 return -EINVAL; 1254 } 1255 epn++; 1256 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1257 } 1258 1259 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1260 musb_driver_name, 1261 n + 1, musb->config->num_eps * 2 - 1, 1262 offset, (1 << (musb->config->ram_bits + 2))); 1263 1264#ifdef CONFIG_USB_MUSB_HDRC_HCD 1265 if (!musb->bulk_ep) { 1266 pr_debug("%s: missing bulk\n", musb_driver_name); 1267 return -EINVAL; 1268 } 1269#endif 1270 1271 return 0; 1272} 1273 1274 1275/* 1276 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1277 * @param musb the controller 1278 */ 1279static int __init ep_config_from_hw(struct musb *musb) 1280{ 1281 u8 epnum = 0; 1282 struct musb_hw_ep *hw_ep; 1283 void *mbase = musb->mregs; 1284 int ret = 0; 1285 1286 DBG(2, "<== static silicon ep config\n"); 1287 1288 /* FIXME pick up ep0 maxpacket size */ 1289 1290 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1291 musb_ep_select(mbase, epnum); 1292 hw_ep = musb->endpoints + epnum; 1293 1294 ret = musb_read_fifosize(musb, hw_ep, epnum); 1295 if (ret < 0) 1296 break; 1297 1298 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1299 1300#ifdef CONFIG_USB_MUSB_HDRC_HCD 1301 /* pick an RX/TX endpoint for bulk */ 1302 if (hw_ep->max_packet_sz_tx < 512 1303 || hw_ep->max_packet_sz_rx < 512) 1304 continue; 1305 1306 /* REVISIT: this algorithm is lazy, we should at least 1307 * try to pick a double buffered endpoint. 1308 */ 1309 if (musb->bulk_ep) 1310 continue; 1311 musb->bulk_ep = hw_ep; 1312#endif 1313 } 1314 1315#ifdef CONFIG_USB_MUSB_HDRC_HCD 1316 if (!musb->bulk_ep) { 1317 pr_debug("%s: missing bulk\n", musb_driver_name); 1318 return -EINVAL; 1319 } 1320#endif 1321 1322 return 0; 1323} 1324 1325enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1326 1327/* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1328 * configure endpoints, or take their config from silicon 1329 */ 1330static int __init musb_core_init(u16 musb_type, struct musb *musb) 1331{ 1332 u8 reg; 1333 char *type; 1334 char aInfo[90], aRevision[32], aDate[12]; 1335 void __iomem *mbase = musb->mregs; 1336 int status = 0; 1337 int i; 1338 1339 /* log core options (read using indexed model) */ 1340 reg = musb_read_configdata(mbase); 1341 1342 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1343 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1344 strcat(aInfo, ", dyn FIFOs"); 1345 musb->dyn_fifo = true; 1346 } 1347 if (reg & MUSB_CONFIGDATA_MPRXE) { 1348 strcat(aInfo, ", bulk combine"); 1349 musb->bulk_combine = true; 1350 } 1351 if (reg & MUSB_CONFIGDATA_MPTXE) { 1352 strcat(aInfo, ", bulk split"); 1353 musb->bulk_split = true; 1354 } 1355 if (reg & MUSB_CONFIGDATA_HBRXE) { 1356 strcat(aInfo, ", HB-ISO Rx"); 1357 musb->hb_iso_rx = true; 1358 } 1359 if (reg & MUSB_CONFIGDATA_HBTXE) { 1360 strcat(aInfo, ", HB-ISO Tx"); 1361 musb->hb_iso_tx = true; 1362 } 1363 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1364 strcat(aInfo, ", SoftConn"); 1365 1366 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1367 musb_driver_name, reg, aInfo); 1368 1369 aDate[0] = 0; 1370 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1371 musb->is_multipoint = 1; 1372 type = "M"; 1373 } else { 1374 musb->is_multipoint = 0; 1375 type = ""; 1376#ifdef CONFIG_USB_MUSB_HDRC_HCD 1377#ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1378 printk(KERN_ERR 1379 "%s: kernel must blacklist external hubs\n", 1380 musb_driver_name); 1381#endif 1382#endif 1383 } 1384 1385 /* log release info */ 1386 musb->hwvers = musb_read_hwvers(mbase); 1387 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1388 MUSB_HWVERS_MINOR(musb->hwvers), 1389 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1390 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1391 musb_driver_name, type, aRevision, aDate); 1392 1393 /* configure ep0 */ 1394 musb_configure_ep0(musb); 1395 1396 /* discover endpoint configuration */ 1397 musb->nr_endpoints = 1; 1398 musb->epmask = 1; 1399 1400 if (musb->dyn_fifo) 1401 status = ep_config_from_table(musb); 1402 else 1403 status = ep_config_from_hw(musb); 1404 1405 if (status < 0) 1406 return status; 1407 1408 /* finish init, and print endpoint config */ 1409 for (i = 0; i < musb->nr_endpoints; i++) { 1410 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1411 1412 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1413#ifdef CONFIG_USB_TUSB6010 1414 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1415 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1416 hw_ep->fifo_sync_va = 1417 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1418 1419 if (i == 0) 1420 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1421 else 1422 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1423#endif 1424 1425 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1426#ifdef CONFIG_USB_MUSB_HDRC_HCD 1427 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1428 hw_ep->rx_reinit = 1; 1429 hw_ep->tx_reinit = 1; 1430#endif 1431 1432 if (hw_ep->max_packet_sz_tx) { 1433 DBG(1, 1434 "%s: hw_ep %d%s, %smax %d\n", 1435 musb_driver_name, i, 1436 hw_ep->is_shared_fifo ? "shared" : "tx", 1437 hw_ep->tx_double_buffered 1438 ? "doublebuffer, " : "", 1439 hw_ep->max_packet_sz_tx); 1440 } 1441 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1442 DBG(1, 1443 "%s: hw_ep %d%s, %smax %d\n", 1444 musb_driver_name, i, 1445 "rx", 1446 hw_ep->rx_double_buffered 1447 ? "doublebuffer, " : "", 1448 hw_ep->max_packet_sz_rx); 1449 } 1450 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1451 DBG(1, "hw_ep %d not configured\n", i); 1452 } 1453 1454 return 0; 1455} 1456 1457/*-------------------------------------------------------------------------*/ 1458 1459#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) 1460 1461static irqreturn_t generic_interrupt(int irq, void *__hci) 1462{ 1463 unsigned long flags; 1464 irqreturn_t retval = IRQ_NONE; 1465 struct musb *musb = __hci; 1466 1467 spin_lock_irqsave(&musb->lock, flags); 1468 1469 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1470 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1471 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1472 1473 if (musb->int_usb || musb->int_tx || musb->int_rx) 1474 retval = musb_interrupt(musb); 1475 1476 spin_unlock_irqrestore(&musb->lock, flags); 1477 1478 return retval; 1479} 1480 1481#else 1482#define generic_interrupt NULL 1483#endif 1484 1485/* 1486 * handle all the irqs defined by the HDRC core. for now we expect: other 1487 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1488 * will be assigned, and the irq will already have been acked. 1489 * 1490 * called in irq context with spinlock held, irqs blocked 1491 */ 1492irqreturn_t musb_interrupt(struct musb *musb) 1493{ 1494 irqreturn_t retval = IRQ_NONE; 1495 u8 devctl, power; 1496 int ep_num; 1497 u32 reg; 1498 1499 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1500 power = musb_readb(musb->mregs, MUSB_POWER); 1501 1502 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n", 1503 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1504 musb->int_usb, musb->int_tx, musb->int_rx); 1505 1506#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1507 if (is_otg_enabled(musb) || is_peripheral_enabled(musb)) 1508 if (!musb->gadget_driver) { 1509 DBG(5, "No gadget driver loaded\n"); 1510 return IRQ_HANDLED; 1511 } 1512#endif 1513 1514 /* the core can interrupt us for multiple reasons; docs have 1515 * a generic interrupt flowchart to follow 1516 */ 1517 if (musb->int_usb & STAGE0_MASK) 1518 retval |= musb_stage0_irq(musb, musb->int_usb, 1519 devctl, power); 1520 1521 /* "stage 1" is handling endpoint irqs */ 1522 1523 /* handle endpoint 0 first */ 1524 if (musb->int_tx & 1) { 1525 if (devctl & MUSB_DEVCTL_HM) 1526 retval |= musb_h_ep0_irq(musb); 1527 else 1528 retval |= musb_g_ep0_irq(musb); 1529 } 1530 1531 /* RX on endpoints 1-15 */ 1532 reg = musb->int_rx >> 1; 1533 ep_num = 1; 1534 while (reg) { 1535 if (reg & 1) { 1536 /* musb_ep_select(musb->mregs, ep_num); */ 1537 /* REVISIT just retval = ep->rx_irq(...) */ 1538 retval = IRQ_HANDLED; 1539 if (devctl & MUSB_DEVCTL_HM) { 1540 if (is_host_capable()) 1541 musb_host_rx(musb, ep_num); 1542 } else { 1543 if (is_peripheral_capable()) 1544 musb_g_rx(musb, ep_num); 1545 } 1546 } 1547 1548 reg >>= 1; 1549 ep_num++; 1550 } 1551 1552 /* TX on endpoints 1-15 */ 1553 reg = musb->int_tx >> 1; 1554 ep_num = 1; 1555 while (reg) { 1556 if (reg & 1) { 1557 /* musb_ep_select(musb->mregs, ep_num); */ 1558 /* REVISIT just retval |= ep->tx_irq(...) */ 1559 retval = IRQ_HANDLED; 1560 if (devctl & MUSB_DEVCTL_HM) { 1561 if (is_host_capable()) 1562 musb_host_tx(musb, ep_num); 1563 } else { 1564 if (is_peripheral_capable()) 1565 musb_g_tx(musb, ep_num); 1566 } 1567 } 1568 reg >>= 1; 1569 ep_num++; 1570 } 1571 1572 return retval; 1573} 1574 1575 1576#ifndef CONFIG_MUSB_PIO_ONLY 1577static int __initdata use_dma = 1; 1578 1579/* "modprobe ... use_dma=0" etc */ 1580module_param(use_dma, bool, 0); 1581MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1582 1583void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1584{ 1585 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1586 1587 /* called with controller lock already held */ 1588 1589 if (!epnum) { 1590#ifndef CONFIG_USB_TUSB_OMAP_DMA 1591 if (!is_cppi_enabled()) { 1592 /* endpoint 0 */ 1593 if (devctl & MUSB_DEVCTL_HM) 1594 musb_h_ep0_irq(musb); 1595 else 1596 musb_g_ep0_irq(musb); 1597 } 1598#endif 1599 } else { 1600 /* endpoints 1..15 */ 1601 if (transmit) { 1602 if (devctl & MUSB_DEVCTL_HM) { 1603 if (is_host_capable()) 1604 musb_host_tx(musb, epnum); 1605 } else { 1606 if (is_peripheral_capable()) 1607 musb_g_tx(musb, epnum); 1608 } 1609 } else { 1610 /* receive */ 1611 if (devctl & MUSB_DEVCTL_HM) { 1612 if (is_host_capable()) 1613 musb_host_rx(musb, epnum); 1614 } else { 1615 if (is_peripheral_capable()) 1616 musb_g_rx(musb, epnum); 1617 } 1618 } 1619 } 1620} 1621 1622#else 1623#define use_dma 0 1624#endif 1625 1626/*-------------------------------------------------------------------------*/ 1627 1628#ifdef CONFIG_SYSFS 1629 1630static ssize_t 1631musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1632{ 1633 struct musb *musb = dev_to_musb(dev); 1634 unsigned long flags; 1635 int ret = -EINVAL; 1636 1637 spin_lock_irqsave(&musb->lock, flags); 1638 ret = sprintf(buf, "%s\n", otg_state_string(musb)); 1639 spin_unlock_irqrestore(&musb->lock, flags); 1640 1641 return ret; 1642} 1643 1644static ssize_t 1645musb_mode_store(struct device *dev, struct device_attribute *attr, 1646 const char *buf, size_t n) 1647{ 1648 struct musb *musb = dev_to_musb(dev); 1649 unsigned long flags; 1650 int status; 1651 1652 spin_lock_irqsave(&musb->lock, flags); 1653 if (sysfs_streq(buf, "host")) 1654 status = musb_platform_set_mode(musb, MUSB_HOST); 1655 else if (sysfs_streq(buf, "peripheral")) 1656 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1657 else if (sysfs_streq(buf, "otg")) 1658 status = musb_platform_set_mode(musb, MUSB_OTG); 1659 else 1660 status = -EINVAL; 1661 spin_unlock_irqrestore(&musb->lock, flags); 1662 1663 return (status == 0) ? n : status; 1664} 1665static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1666 1667static ssize_t 1668musb_vbus_store(struct device *dev, struct device_attribute *attr, 1669 const char *buf, size_t n) 1670{ 1671 struct musb *musb = dev_to_musb(dev); 1672 unsigned long flags; 1673 unsigned long val; 1674 1675 if (sscanf(buf, "%lu", &val) < 1) { 1676 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1677 return -EINVAL; 1678 } 1679 1680 spin_lock_irqsave(&musb->lock, flags); 1681 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1682 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1683 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1684 musb->is_active = 0; 1685 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1686 spin_unlock_irqrestore(&musb->lock, flags); 1687 1688 return n; 1689} 1690 1691static ssize_t 1692musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1693{ 1694 struct musb *musb = dev_to_musb(dev); 1695 unsigned long flags; 1696 unsigned long val; 1697 int vbus; 1698 1699 spin_lock_irqsave(&musb->lock, flags); 1700 val = musb->a_wait_bcon; 1701 /* FIXME get_vbus_status() is normally #defined as false... 1702 * and is effectively TUSB-specific. 1703 */ 1704 vbus = musb_platform_get_vbus_status(musb); 1705 spin_unlock_irqrestore(&musb->lock, flags); 1706 1707 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1708 vbus ? "on" : "off", val); 1709} 1710static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1711 1712#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1713 1714/* Gadget drivers can't know that a host is connected so they might want 1715 * to start SRP, but users can. This allows userspace to trigger SRP. 1716 */ 1717static ssize_t 1718musb_srp_store(struct device *dev, struct device_attribute *attr, 1719 const char *buf, size_t n) 1720{ 1721 struct musb *musb = dev_to_musb(dev); 1722 unsigned short srp; 1723 1724 if (sscanf(buf, "%hu", &srp) != 1 1725 || (srp != 1)) { 1726 dev_err(dev, "SRP: Value must be 1\n"); 1727 return -EINVAL; 1728 } 1729 1730 if (srp == 1) 1731 musb_g_wakeup(musb); 1732 1733 return n; 1734} 1735static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1736 1737#endif /* CONFIG_USB_GADGET_MUSB_HDRC */ 1738 1739static struct attribute *musb_attributes[] = { 1740 &dev_attr_mode.attr, 1741 &dev_attr_vbus.attr, 1742#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1743 &dev_attr_srp.attr, 1744#endif 1745 NULL 1746}; 1747 1748static const struct attribute_group musb_attr_group = { 1749 .attrs = musb_attributes, 1750}; 1751 1752#endif /* sysfs */ 1753 1754/* Only used to provide driver mode change events */ 1755static void musb_irq_work(struct work_struct *data) 1756{ 1757 struct musb *musb = container_of(data, struct musb, irq_work); 1758 static int old_state; 1759 1760 if (musb->xceiv->state != old_state) { 1761 old_state = musb->xceiv->state; 1762 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1763 } 1764} 1765 1766/* -------------------------------------------------------------------------- 1767 * Init support 1768 */ 1769 1770static struct musb *__init 1771allocate_instance(struct device *dev, 1772 struct musb_hdrc_config *config, void __iomem *mbase) 1773{ 1774 struct musb *musb; 1775 struct musb_hw_ep *ep; 1776 int epnum; 1777#ifdef CONFIG_USB_MUSB_HDRC_HCD 1778 struct usb_hcd *hcd; 1779 1780 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1781 if (!hcd) 1782 return NULL; 1783 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1784 1785 musb = hcd_to_musb(hcd); 1786 INIT_LIST_HEAD(&musb->control); 1787 INIT_LIST_HEAD(&musb->in_bulk); 1788 INIT_LIST_HEAD(&musb->out_bulk); 1789 1790 hcd->uses_new_polling = 1; 1791 1792 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1793 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1794#else 1795 musb = kzalloc(sizeof *musb, GFP_KERNEL); 1796 if (!musb) 1797 return NULL; 1798 dev_set_drvdata(dev, musb); 1799 1800#endif 1801 1802 musb->mregs = mbase; 1803 musb->ctrl_base = mbase; 1804 musb->nIrq = -ENODEV; 1805 musb->config = config; 1806 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1807 for (epnum = 0, ep = musb->endpoints; 1808 epnum < musb->config->num_eps; 1809 epnum++, ep++) { 1810 ep->musb = musb; 1811 ep->epnum = epnum; 1812 } 1813 1814 musb->controller = dev; 1815 return musb; 1816} 1817 1818static void musb_free(struct musb *musb) 1819{ 1820 /* this has multiple entry modes. it handles fault cleanup after 1821 * probe(), where things may be partially set up, as well as rmmod 1822 * cleanup after everything's been de-activated. 1823 */ 1824 1825#ifdef CONFIG_SYSFS 1826 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1827#endif 1828 1829#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1830 musb_gadget_cleanup(musb); 1831#endif 1832 1833 if (musb->nIrq >= 0) { 1834 if (musb->irq_wake) 1835 disable_irq_wake(musb->nIrq); 1836 free_irq(musb->nIrq, musb); 1837 } 1838 if (is_dma_capable() && musb->dma_controller) { 1839 struct dma_controller *c = musb->dma_controller; 1840 1841 (void) c->stop(c); 1842 dma_controller_destroy(c); 1843 } 1844 1845#ifdef CONFIG_USB_MUSB_OTG 1846 put_device(musb->xceiv->dev); 1847#endif 1848 1849#ifdef CONFIG_USB_MUSB_HDRC_HCD 1850 usb_put_hcd(musb_to_hcd(musb)); 1851#else 1852 kfree(musb); 1853#endif 1854} 1855 1856/* 1857 * Perform generic per-controller initialization. 1858 * 1859 * @pDevice: the controller (already clocked, etc) 1860 * @nIrq: irq 1861 * @mregs: virtual address of controller registers, 1862 * not yet corrected for platform-specific offsets 1863 */ 1864static int __init 1865musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1866{ 1867 int status; 1868 struct musb *musb; 1869 struct musb_hdrc_platform_data *plat = dev->platform_data; 1870 1871 /* The driver might handle more features than the board; OK. 1872 * Fail when the board needs a feature that's not enabled. 1873 */ 1874 if (!plat) { 1875 dev_dbg(dev, "no platform_data?\n"); 1876 status = -ENODEV; 1877 goto fail0; 1878 } 1879 1880 switch (plat->mode) { 1881 case MUSB_HOST: 1882#ifdef CONFIG_USB_MUSB_HDRC_HCD 1883 break; 1884#else 1885 goto bad_config; 1886#endif 1887 case MUSB_PERIPHERAL: 1888#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1889 break; 1890#else 1891 goto bad_config; 1892#endif 1893 case MUSB_OTG: 1894#ifdef CONFIG_USB_MUSB_OTG 1895 break; 1896#else 1897bad_config: 1898#endif 1899 default: 1900 dev_err(dev, "incompatible Kconfig role setting\n"); 1901 status = -EINVAL; 1902 goto fail0; 1903 } 1904 1905 /* allocate */ 1906 musb = allocate_instance(dev, plat->config, ctrl); 1907 if (!musb) { 1908 status = -ENOMEM; 1909 goto fail0; 1910 } 1911 1912 spin_lock_init(&musb->lock); 1913 musb->board_mode = plat->mode; 1914 musb->board_set_power = plat->set_power; 1915 musb->set_clock = plat->set_clock; 1916 musb->min_power = plat->min_power; 1917 1918 /* Clock usage is chip-specific ... functional clock (DaVinci, 1919 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core 1920 * code does is make sure a clock handle is available; platform 1921 * code manages it during start/stop and suspend/resume. 1922 */ 1923 if (plat->clock) { 1924 musb->clock = clk_get(dev, plat->clock); 1925 if (IS_ERR(musb->clock)) { 1926 status = PTR_ERR(musb->clock); 1927 musb->clock = NULL; 1928 goto fail1; 1929 } 1930 } 1931 1932 /* The musb_platform_init() call: 1933 * - adjusts musb->mregs and musb->isr if needed, 1934 * - may initialize an integrated tranceiver 1935 * - initializes musb->xceiv, usually by otg_get_transceiver() 1936 * - activates clocks. 1937 * - stops powering VBUS 1938 * - assigns musb->board_set_vbus if host mode is enabled 1939 * 1940 * There are various transciever configurations. Blackfin, 1941 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1942 * external/discrete ones in various flavors (twl4030 family, 1943 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1944 */ 1945 musb->isr = generic_interrupt; 1946 status = musb_platform_init(musb, plat->board_data); 1947 if (status < 0) 1948 goto fail2; 1949 1950 if (!musb->isr) { 1951 status = -ENODEV; 1952 goto fail3; 1953 } 1954 1955#ifndef CONFIG_MUSB_PIO_ONLY 1956 if (use_dma && dev->dma_mask) { 1957 struct dma_controller *c; 1958 1959 c = dma_controller_create(musb, musb->mregs); 1960 musb->dma_controller = c; 1961 if (c) 1962 (void) c->start(c); 1963 } 1964#endif 1965 /* ideally this would be abstracted in platform setup */ 1966 if (!is_dma_capable() || !musb->dma_controller) 1967 dev->dma_mask = NULL; 1968 1969 /* be sure interrupts are disabled before connecting ISR */ 1970 musb_platform_disable(musb); 1971 musb_generic_disable(musb); 1972 1973 /* setup musb parts of the core (especially endpoints) */ 1974 status = musb_core_init(plat->config->multipoint 1975 ? MUSB_CONTROLLER_MHDRC 1976 : MUSB_CONTROLLER_HDRC, musb); 1977 if (status < 0) 1978 goto fail3; 1979 1980#ifdef CONFIG_USB_MUSB_OTG 1981 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 1982#endif 1983 1984 /* Init IRQ workqueue before request_irq */ 1985 INIT_WORK(&musb->irq_work, musb_irq_work); 1986 1987 /* attach to the IRQ */ 1988 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 1989 dev_err(dev, "request_irq %d failed!\n", nIrq); 1990 status = -ENODEV; 1991 goto fail3; 1992 } 1993 musb->nIrq = nIrq; 1994/* FIXME this handles wakeup irqs wrong */ 1995 if (enable_irq_wake(nIrq) == 0) { 1996 musb->irq_wake = 1; 1997 device_init_wakeup(dev, 1); 1998 } else { 1999 musb->irq_wake = 0; 2000 } 2001 2002 /* host side needs more setup */ 2003 if (is_host_enabled(musb)) { 2004 struct usb_hcd *hcd = musb_to_hcd(musb); 2005 2006 otg_set_host(musb->xceiv, &hcd->self); 2007 2008 if (is_otg_enabled(musb)) 2009 hcd->self.otg_port = 1; 2010 musb->xceiv->host = &hcd->self; 2011 hcd->power_budget = 2 * (plat->power ? : 250); 2012 2013 /* program PHY to use external vBus if required */ 2014 if (plat->extvbus) { 2015 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2016 busctl |= MUSB_ULPI_USE_EXTVBUS; 2017 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2018 } 2019 } 2020 2021 /* For the host-only role, we can activate right away. 2022 * (We expect the ID pin to be forcibly grounded!!) 2023 * Otherwise, wait till the gadget driver hooks up. 2024 */ 2025 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2026 MUSB_HST_MODE(musb); 2027 musb->xceiv->default_a = 1; 2028 musb->xceiv->state = OTG_STATE_A_IDLE; 2029 2030 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 2031 2032 DBG(1, "%s mode, status %d, devctl %02x %c\n", 2033 "HOST", status, 2034 musb_readb(musb->mregs, MUSB_DEVCTL), 2035 (musb_readb(musb->mregs, MUSB_DEVCTL) 2036 & MUSB_DEVCTL_BDEVICE 2037 ? 'B' : 'A')); 2038 2039 } else /* peripheral is enabled */ { 2040 MUSB_DEV_MODE(musb); 2041 musb->xceiv->default_a = 0; 2042 musb->xceiv->state = OTG_STATE_B_IDLE; 2043 2044 status = musb_gadget_setup(musb); 2045 2046 DBG(1, "%s mode, status %d, dev%02x\n", 2047 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2048 status, 2049 musb_readb(musb->mregs, MUSB_DEVCTL)); 2050 2051 } 2052 if (status < 0) 2053 goto fail3; 2054 2055#ifdef CONFIG_SYSFS 2056 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2057 if (status) 2058 goto fail4; 2059#endif 2060 2061 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", 2062 ({char *s; 2063 switch (musb->board_mode) { 2064 case MUSB_HOST: s = "Host"; break; 2065 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2066 default: s = "OTG"; break; 2067 }; s; }), 2068 ctrl, 2069 (is_dma_capable() && musb->dma_controller) 2070 ? "DMA" : "PIO", 2071 musb->nIrq); 2072 2073 return 0; 2074 2075fail4: 2076 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 2077 usb_remove_hcd(musb_to_hcd(musb)); 2078 else 2079 musb_gadget_cleanup(musb); 2080 2081fail3: 2082 if (musb->irq_wake) 2083 device_init_wakeup(dev, 0); 2084 musb_platform_exit(musb); 2085 2086fail2: 2087 if (musb->clock) 2088 clk_put(musb->clock); 2089 2090fail1: 2091 dev_err(musb->controller, 2092 "musb_init_controller failed with status %d\n", status); 2093 2094 musb_free(musb); 2095 2096fail0: 2097 2098 return status; 2099 2100} 2101 2102/*-------------------------------------------------------------------------*/ 2103 2104/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2105 * bridge to a platform device; this driver then suffices. 2106 */ 2107 2108#ifndef CONFIG_MUSB_PIO_ONLY 2109static u64 *orig_dma_mask; 2110#endif 2111 2112static int __init musb_probe(struct platform_device *pdev) 2113{ 2114 struct device *dev = &pdev->dev; 2115 int irq = platform_get_irq(pdev, 0); 2116 int status; 2117 struct resource *iomem; 2118 void __iomem *base; 2119 2120 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2121 if (!iomem || irq == 0) 2122 return -ENODEV; 2123 2124 base = ioremap(iomem->start, resource_size(iomem)); 2125 if (!base) { 2126 dev_err(dev, "ioremap failed\n"); 2127 return -ENOMEM; 2128 } 2129 2130#ifndef CONFIG_MUSB_PIO_ONLY 2131 /* clobbered by use_dma=n */ 2132 orig_dma_mask = dev->dma_mask; 2133#endif 2134 status = musb_init_controller(dev, irq, base); 2135 if (status < 0) 2136 iounmap(base); 2137 2138 return status; 2139} 2140 2141static int __exit musb_remove(struct platform_device *pdev) 2142{ 2143 struct musb *musb = dev_to_musb(&pdev->dev); 2144 void __iomem *ctrl_base = musb->ctrl_base; 2145 2146 /* this gets called on rmmod. 2147 * - Host mode: host may still be active 2148 * - Peripheral mode: peripheral is deactivated (or never-activated) 2149 * - OTG mode: both roles are deactivated (or never-activated) 2150 */ 2151 musb_shutdown(pdev); 2152#ifdef CONFIG_USB_MUSB_HDRC_HCD 2153 if (musb->board_mode == MUSB_HOST) 2154 usb_remove_hcd(musb_to_hcd(musb)); 2155#endif 2156 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2157 musb_platform_exit(musb); 2158 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2159 2160 musb_free(musb); 2161 iounmap(ctrl_base); 2162 device_init_wakeup(&pdev->dev, 0); 2163#ifndef CONFIG_MUSB_PIO_ONLY 2164 pdev->dev.dma_mask = orig_dma_mask; 2165#endif 2166 return 0; 2167} 2168 2169#ifdef CONFIG_PM 2170 2171static struct musb_context_registers musb_context; 2172 2173void musb_save_context(struct musb *musb) 2174{ 2175 int i; 2176 void __iomem *musb_base = musb->mregs; 2177 2178 if (is_host_enabled(musb)) { 2179 musb_context.frame = musb_readw(musb_base, MUSB_FRAME); 2180 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2181 musb_context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2182 } 2183 musb_context.power = musb_readb(musb_base, MUSB_POWER); 2184 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2185 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2186 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2187 musb_context.index = musb_readb(musb_base, MUSB_INDEX); 2188 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2189 2190 for (i = 0; i < MUSB_C_NUM_EPS; ++i) { 2191 musb_writeb(musb_base, MUSB_INDEX, i); 2192 musb_context.index_regs[i].txmaxp = 2193 musb_readw(musb_base, 0x10 + MUSB_TXMAXP); 2194 musb_context.index_regs[i].txcsr = 2195 musb_readw(musb_base, 0x10 + MUSB_TXCSR); 2196 musb_context.index_regs[i].rxmaxp = 2197 musb_readw(musb_base, 0x10 + MUSB_RXMAXP); 2198 musb_context.index_regs[i].rxcsr = 2199 musb_readw(musb_base, 0x10 + MUSB_RXCSR); 2200 2201 if (musb->dyn_fifo) { 2202 musb_context.index_regs[i].txfifoadd = 2203 musb_read_txfifoadd(musb_base); 2204 musb_context.index_regs[i].rxfifoadd = 2205 musb_read_rxfifoadd(musb_base); 2206 musb_context.index_regs[i].txfifosz = 2207 musb_read_txfifosz(musb_base); 2208 musb_context.index_regs[i].rxfifosz = 2209 musb_read_rxfifosz(musb_base); 2210 } 2211 if (is_host_enabled(musb)) { 2212 musb_context.index_regs[i].txtype = 2213 musb_readb(musb_base, 0x10 + MUSB_TXTYPE); 2214 musb_context.index_regs[i].txinterval = 2215 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL); 2216 musb_context.index_regs[i].rxtype = 2217 musb_readb(musb_base, 0x10 + MUSB_RXTYPE); 2218 musb_context.index_regs[i].rxinterval = 2219 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL); 2220 2221 musb_context.index_regs[i].txfunaddr = 2222 musb_read_txfunaddr(musb_base, i); 2223 musb_context.index_regs[i].txhubaddr = 2224 musb_read_txhubaddr(musb_base, i); 2225 musb_context.index_regs[i].txhubport = 2226 musb_read_txhubport(musb_base, i); 2227 2228 musb_context.index_regs[i].rxfunaddr = 2229 musb_read_rxfunaddr(musb_base, i); 2230 musb_context.index_regs[i].rxhubaddr = 2231 musb_read_rxhubaddr(musb_base, i); 2232 musb_context.index_regs[i].rxhubport = 2233 musb_read_rxhubport(musb_base, i); 2234 } 2235 } 2236 2237 musb_writeb(musb_base, MUSB_INDEX, musb_context.index); 2238 2239 musb_platform_save_context(musb, &musb_context); 2240} 2241 2242void musb_restore_context(struct musb *musb) 2243{ 2244 int i; 2245 void __iomem *musb_base = musb->mregs; 2246 void __iomem *ep_target_regs; 2247 2248 musb_platform_restore_context(musb, &musb_context); 2249 2250 if (is_host_enabled(musb)) { 2251 musb_writew(musb_base, MUSB_FRAME, musb_context.frame); 2252 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode); 2253 musb_write_ulpi_buscontrol(musb->mregs, musb_context.busctl); 2254 } 2255 musb_writeb(musb_base, MUSB_POWER, musb_context.power); 2256 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe); 2257 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe); 2258 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe); 2259 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl); 2260 2261 for (i = 0; i < MUSB_C_NUM_EPS; ++i) { 2262 musb_writeb(musb_base, MUSB_INDEX, i); 2263 musb_writew(musb_base, 0x10 + MUSB_TXMAXP, 2264 musb_context.index_regs[i].txmaxp); 2265 musb_writew(musb_base, 0x10 + MUSB_TXCSR, 2266 musb_context.index_regs[i].txcsr); 2267 musb_writew(musb_base, 0x10 + MUSB_RXMAXP, 2268 musb_context.index_regs[i].rxmaxp); 2269 musb_writew(musb_base, 0x10 + MUSB_RXCSR, 2270 musb_context.index_regs[i].rxcsr); 2271 2272 if (musb->dyn_fifo) { 2273 musb_write_txfifosz(musb_base, 2274 musb_context.index_regs[i].txfifosz); 2275 musb_write_rxfifosz(musb_base, 2276 musb_context.index_regs[i].rxfifosz); 2277 musb_write_txfifoadd(musb_base, 2278 musb_context.index_regs[i].txfifoadd); 2279 musb_write_rxfifoadd(musb_base, 2280 musb_context.index_regs[i].rxfifoadd); 2281 } 2282 2283 if (is_host_enabled(musb)) { 2284 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE, 2285 musb_context.index_regs[i].txtype); 2286 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL, 2287 musb_context.index_regs[i].txinterval); 2288 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE, 2289 musb_context.index_regs[i].rxtype); 2290 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL, 2291 2292 musb_context.index_regs[i].rxinterval); 2293 musb_write_txfunaddr(musb_base, i, 2294 musb_context.index_regs[i].txfunaddr); 2295 musb_write_txhubaddr(musb_base, i, 2296 musb_context.index_regs[i].txhubaddr); 2297 musb_write_txhubport(musb_base, i, 2298 musb_context.index_regs[i].txhubport); 2299 2300 ep_target_regs = 2301 musb_read_target_reg_base(i, musb_base); 2302 2303 musb_write_rxfunaddr(ep_target_regs, 2304 musb_context.index_regs[i].rxfunaddr); 2305 musb_write_rxhubaddr(ep_target_regs, 2306 musb_context.index_regs[i].rxhubaddr); 2307 musb_write_rxhubport(ep_target_regs, 2308 musb_context.index_regs[i].rxhubport); 2309 } 2310 } 2311 2312 musb_writeb(musb_base, MUSB_INDEX, musb_context.index); 2313} 2314 2315static int musb_suspend(struct device *dev) 2316{ 2317 struct platform_device *pdev = to_platform_device(dev); 2318 unsigned long flags; 2319 struct musb *musb = dev_to_musb(&pdev->dev); 2320 2321 if (!musb->clock) 2322 return 0; 2323 2324 spin_lock_irqsave(&musb->lock, flags); 2325 2326 if (is_peripheral_active(musb)) { 2327 /* FIXME force disconnect unless we know USB will wake 2328 * the system up quickly enough to respond ... 2329 */ 2330 } else if (is_host_active(musb)) { 2331 /* we know all the children are suspended; sometimes 2332 * they will even be wakeup-enabled. 2333 */ 2334 } 2335 2336 musb_save_context(musb); 2337 2338 if (musb->set_clock) 2339 musb->set_clock(musb->clock, 0); 2340 else 2341 clk_disable(musb->clock); 2342 spin_unlock_irqrestore(&musb->lock, flags); 2343 return 0; 2344} 2345 2346static int musb_resume_noirq(struct device *dev) 2347{ 2348 struct platform_device *pdev = to_platform_device(dev); 2349 struct musb *musb = dev_to_musb(&pdev->dev); 2350 2351 if (!musb->clock) 2352 return 0; 2353 2354 if (musb->set_clock) 2355 musb->set_clock(musb->clock, 1); 2356 else 2357 clk_enable(musb->clock); 2358 2359 musb_restore_context(musb); 2360 2361 /* for static cmos like DaVinci, register values were preserved 2362 * unless for some reason the whole soc powered down or the USB 2363 * module got reset through the PSC (vs just being disabled). 2364 */ 2365 return 0; 2366} 2367 2368static const struct dev_pm_ops musb_dev_pm_ops = { 2369 .suspend = musb_suspend, 2370 .resume_noirq = musb_resume_noirq, 2371}; 2372 2373#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2374#else 2375#define MUSB_DEV_PM_OPS NULL 2376#endif 2377 2378static struct platform_driver musb_driver = { 2379 .driver = { 2380 .name = (char *)musb_driver_name, 2381 .bus = &platform_bus_type, 2382 .owner = THIS_MODULE, 2383 .pm = MUSB_DEV_PM_OPS, 2384 }, 2385 .remove = __exit_p(musb_remove), 2386 .shutdown = musb_shutdown, 2387}; 2388 2389/*-------------------------------------------------------------------------*/ 2390 2391static int __init musb_init(void) 2392{ 2393#ifdef CONFIG_USB_MUSB_HDRC_HCD 2394 if (usb_disabled()) 2395 return 0; 2396#endif 2397 2398 pr_info("%s: version " MUSB_VERSION ", " 2399#ifdef CONFIG_MUSB_PIO_ONLY 2400 "pio" 2401#elif defined(CONFIG_USB_TI_CPPI_DMA) 2402 "cppi-dma" 2403#elif defined(CONFIG_USB_INVENTRA_DMA) 2404 "musb-dma" 2405#elif defined(CONFIG_USB_TUSB_OMAP_DMA) 2406 "tusb-omap-dma" 2407#else 2408 "?dma?" 2409#endif 2410 ", " 2411#ifdef CONFIG_USB_MUSB_OTG 2412 "otg (peripheral+host)" 2413#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 2414 "peripheral" 2415#elif defined(CONFIG_USB_MUSB_HDRC_HCD) 2416 "host" 2417#endif 2418 ", debug=%d\n", 2419 musb_driver_name, musb_debug); 2420 return platform_driver_probe(&musb_driver, musb_probe); 2421} 2422 2423/* make us init after usbcore and i2c (transceivers, regulators, etc) 2424 * and before usb gadget and host-side drivers start to register 2425 */ 2426fs_initcall(musb_init); 2427 2428static void __exit musb_cleanup(void) 2429{ 2430 platform_driver_unregister(&musb_driver); 2431} 2432module_exit(musb_cleanup); 2433