musb_core.c revision f7ec94370f417fedad4db1054228ef958d48b926
1/* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35/* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82/* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92#include <linux/module.h> 93#include <linux/kernel.h> 94#include <linux/sched.h> 95#include <linux/slab.h> 96#include <linux/init.h> 97#include <linux/list.h> 98#include <linux/kobject.h> 99#include <linux/platform_device.h> 100#include <linux/io.h> 101 102#ifdef CONFIG_ARM 103#include <mach/hardware.h> 104#include <mach/memory.h> 105#include <asm/mach-types.h> 106#endif 107 108#include "musb_core.h" 109 110 111#ifdef CONFIG_ARCH_DAVINCI 112#include "davinci.h" 113#endif 114 115#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 116 117 118unsigned musb_debug; 119module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR); 120MODULE_PARM_DESC(debug, "Debug message level. Default = 0"); 121 122#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 123#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 124 125#define MUSB_VERSION "6.0" 126 127#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 128 129#define MUSB_DRIVER_NAME "musb-hdrc" 130const char musb_driver_name[] = MUSB_DRIVER_NAME; 131 132MODULE_DESCRIPTION(DRIVER_INFO); 133MODULE_AUTHOR(DRIVER_AUTHOR); 134MODULE_LICENSE("GPL"); 135MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 136 137 138/*-------------------------------------------------------------------------*/ 139 140static inline struct musb *dev_to_musb(struct device *dev) 141{ 142#ifdef CONFIG_USB_MUSB_HDRC_HCD 143 /* usbcore insists dev->driver_data is a "struct hcd *" */ 144 return hcd_to_musb(dev_get_drvdata(dev)); 145#else 146 return dev_get_drvdata(dev); 147#endif 148} 149 150/*-------------------------------------------------------------------------*/ 151 152#ifndef CONFIG_BLACKFIN 153static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset) 154{ 155 void __iomem *addr = otg->io_priv; 156 int i = 0; 157 u8 r; 158 u8 power; 159 160 /* Make sure the transceiver is not in low power mode */ 161 power = musb_readb(addr, MUSB_POWER); 162 power &= ~MUSB_POWER_SUSPENDM; 163 musb_writeb(addr, MUSB_POWER, power); 164 165 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the 166 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. 167 */ 168 169 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, 171 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); 172 173 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 174 & MUSB_ULPI_REG_CMPLT)) { 175 i++; 176 if (i == 10000) { 177 DBG(3, "ULPI read timed out\n"); 178 return -ETIMEDOUT; 179 } 180 181 } 182 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 183 r &= ~MUSB_ULPI_REG_CMPLT; 184 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 185 186 return musb_readb(addr, MUSB_ULPI_REG_DATA); 187} 188 189static int musb_ulpi_write(struct otg_transceiver *otg, 190 u32 offset, u32 data) 191{ 192 void __iomem *addr = otg->io_priv; 193 int i = 0; 194 u8 r = 0; 195 u8 power; 196 197 /* Make sure the transceiver is not in low power mode */ 198 power = musb_readb(addr, MUSB_POWER); 199 power &= ~MUSB_POWER_SUSPENDM; 200 musb_writeb(addr, MUSB_POWER, power); 201 202 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); 203 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); 204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); 205 206 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) 207 & MUSB_ULPI_REG_CMPLT)) { 208 i++; 209 if (i == 10000) { 210 DBG(3, "ULPI write timed out\n"); 211 return -ETIMEDOUT; 212 } 213 } 214 215 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); 216 r &= ~MUSB_ULPI_REG_CMPLT; 217 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); 218 219 return 0; 220} 221#else 222#define musb_ulpi_read NULL 223#define musb_ulpi_write NULL 224#endif 225 226static struct otg_io_access_ops musb_ulpi_access = { 227 .read = musb_ulpi_read, 228 .write = musb_ulpi_write, 229}; 230 231/*-------------------------------------------------------------------------*/ 232 233#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) 234 235/* 236 * Load an endpoint's FIFO 237 */ 238void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 239{ 240 void __iomem *fifo = hw_ep->fifo; 241 242 prefetch((u8 *)src); 243 244 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 245 'T', hw_ep->epnum, fifo, len, src); 246 247 /* we can't assume unaligned reads work */ 248 if (likely((0x01 & (unsigned long) src) == 0)) { 249 u16 index = 0; 250 251 /* best case is 32bit-aligned source address */ 252 if ((0x02 & (unsigned long) src) == 0) { 253 if (len >= 4) { 254 writesl(fifo, src + index, len >> 2); 255 index += len & ~0x03; 256 } 257 if (len & 0x02) { 258 musb_writew(fifo, 0, *(u16 *)&src[index]); 259 index += 2; 260 } 261 } else { 262 if (len >= 2) { 263 writesw(fifo, src + index, len >> 1); 264 index += len & ~0x01; 265 } 266 } 267 if (len & 0x01) 268 musb_writeb(fifo, 0, src[index]); 269 } else { 270 /* byte aligned */ 271 writesb(fifo, src, len); 272 } 273} 274 275#if !defined(CONFIG_USB_MUSB_AM35X) 276/* 277 * Unload an endpoint's FIFO 278 */ 279void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 280{ 281 void __iomem *fifo = hw_ep->fifo; 282 283 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 284 'R', hw_ep->epnum, fifo, len, dst); 285 286 /* we can't assume unaligned writes work */ 287 if (likely((0x01 & (unsigned long) dst) == 0)) { 288 u16 index = 0; 289 290 /* best case is 32bit-aligned destination address */ 291 if ((0x02 & (unsigned long) dst) == 0) { 292 if (len >= 4) { 293 readsl(fifo, dst, len >> 2); 294 index = len & ~0x03; 295 } 296 if (len & 0x02) { 297 *(u16 *)&dst[index] = musb_readw(fifo, 0); 298 index += 2; 299 } 300 } else { 301 if (len >= 2) { 302 readsw(fifo, dst, len >> 1); 303 index = len & ~0x01; 304 } 305 } 306 if (len & 0x01) 307 dst[index] = musb_readb(fifo, 0); 308 } else { 309 /* byte aligned */ 310 readsb(fifo, dst, len); 311 } 312} 313#endif 314 315#endif /* normal PIO */ 316 317 318/*-------------------------------------------------------------------------*/ 319 320/* for high speed test mode; see USB 2.0 spec 7.1.20 */ 321static const u8 musb_test_packet[53] = { 322 /* implicit SYNC then DATA0 to start */ 323 324 /* JKJKJKJK x9 */ 325 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 326 /* JJKKJJKK x8 */ 327 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 328 /* JJJJKKKK x8 */ 329 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 330 /* JJJJJJJKKKKKKK x8 */ 331 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 332 /* JJJJJJJK x8 */ 333 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 334 /* JKKKKKKK x10, JK */ 335 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 336 337 /* implicit CRC16 then EOP to end */ 338}; 339 340void musb_load_testpacket(struct musb *musb) 341{ 342 void __iomem *regs = musb->endpoints[0].regs; 343 344 musb_ep_select(musb->mregs, 0); 345 musb_write_fifo(musb->control_ep, 346 sizeof(musb_test_packet), musb_test_packet); 347 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 348} 349 350/*-------------------------------------------------------------------------*/ 351 352const char *otg_state_string(struct musb *musb) 353{ 354 switch (musb->xceiv->state) { 355 case OTG_STATE_A_IDLE: return "a_idle"; 356 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; 357 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; 358 case OTG_STATE_A_HOST: return "a_host"; 359 case OTG_STATE_A_SUSPEND: return "a_suspend"; 360 case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; 361 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; 362 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; 363 case OTG_STATE_B_IDLE: return "b_idle"; 364 case OTG_STATE_B_SRP_INIT: return "b_srp_init"; 365 case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; 366 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; 367 case OTG_STATE_B_HOST: return "b_host"; 368 default: return "UNDEFINED"; 369 } 370} 371 372#ifdef CONFIG_USB_MUSB_OTG 373 374/* 375 * Handles OTG hnp timeouts, such as b_ase0_brst 376 */ 377void musb_otg_timer_func(unsigned long data) 378{ 379 struct musb *musb = (struct musb *)data; 380 unsigned long flags; 381 382 spin_lock_irqsave(&musb->lock, flags); 383 switch (musb->xceiv->state) { 384 case OTG_STATE_B_WAIT_ACON: 385 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 386 musb_g_disconnect(musb); 387 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 388 musb->is_active = 0; 389 break; 390 case OTG_STATE_A_SUSPEND: 391 case OTG_STATE_A_WAIT_BCON: 392 DBG(1, "HNP: %s timeout\n", otg_state_string(musb)); 393 musb_platform_set_vbus(musb, 0); 394 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 395 break; 396 default: 397 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb)); 398 } 399 musb->ignore_disconnect = 0; 400 spin_unlock_irqrestore(&musb->lock, flags); 401} 402 403/* 404 * Stops the HNP transition. Caller must take care of locking. 405 */ 406void musb_hnp_stop(struct musb *musb) 407{ 408 struct usb_hcd *hcd = musb_to_hcd(musb); 409 void __iomem *mbase = musb->mregs; 410 u8 reg; 411 412 DBG(1, "HNP: stop from %s\n", otg_state_string(musb)); 413 414 switch (musb->xceiv->state) { 415 case OTG_STATE_A_PERIPHERAL: 416 musb_g_disconnect(musb); 417 DBG(1, "HNP: back to %s\n", otg_state_string(musb)); 418 break; 419 case OTG_STATE_B_HOST: 420 DBG(1, "HNP: Disabling HR\n"); 421 hcd->self.is_b_host = 0; 422 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 423 MUSB_DEV_MODE(musb); 424 reg = musb_readb(mbase, MUSB_POWER); 425 reg |= MUSB_POWER_SUSPENDM; 426 musb_writeb(mbase, MUSB_POWER, reg); 427 /* REVISIT: Start SESSION_REQUEST here? */ 428 break; 429 default: 430 DBG(1, "HNP: Stopping in unknown state %s\n", 431 otg_state_string(musb)); 432 } 433 434 /* 435 * When returning to A state after HNP, avoid hub_port_rebounce(), 436 * which cause occasional OPT A "Did not receive reset after connect" 437 * errors. 438 */ 439 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); 440} 441 442#endif 443 444/* 445 * Interrupt Service Routine to record USB "global" interrupts. 446 * Since these do not happen often and signify things of 447 * paramount importance, it seems OK to check them individually; 448 * the order of the tests is specified in the manual 449 * 450 * @param musb instance pointer 451 * @param int_usb register contents 452 * @param devctl 453 * @param power 454 */ 455 456static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 457 u8 devctl, u8 power) 458{ 459 irqreturn_t handled = IRQ_NONE; 460 461 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 462 int_usb); 463 464 /* in host mode, the peripheral may issue remote wakeup. 465 * in peripheral mode, the host may resume the link. 466 * spurious RESUME irqs happen too, paired with SUSPEND. 467 */ 468 if (int_usb & MUSB_INTR_RESUME) { 469 handled = IRQ_HANDLED; 470 DBG(3, "RESUME (%s)\n", otg_state_string(musb)); 471 472 if (devctl & MUSB_DEVCTL_HM) { 473#ifdef CONFIG_USB_MUSB_HDRC_HCD 474 void __iomem *mbase = musb->mregs; 475 476 switch (musb->xceiv->state) { 477 case OTG_STATE_A_SUSPEND: 478 /* remote wakeup? later, GetPortStatus 479 * will stop RESUME signaling 480 */ 481 482 if (power & MUSB_POWER_SUSPENDM) { 483 /* spurious */ 484 musb->int_usb &= ~MUSB_INTR_SUSPEND; 485 DBG(2, "Spurious SUSPENDM\n"); 486 break; 487 } 488 489 power &= ~MUSB_POWER_SUSPENDM; 490 musb_writeb(mbase, MUSB_POWER, 491 power | MUSB_POWER_RESUME); 492 493 musb->port1_status |= 494 (USB_PORT_STAT_C_SUSPEND << 16) 495 | MUSB_PORT_STAT_RESUME; 496 musb->rh_timer = jiffies 497 + msecs_to_jiffies(20); 498 499 musb->xceiv->state = OTG_STATE_A_HOST; 500 musb->is_active = 1; 501 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 502 break; 503 case OTG_STATE_B_WAIT_ACON: 504 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 505 musb->is_active = 1; 506 MUSB_DEV_MODE(musb); 507 break; 508 default: 509 WARNING("bogus %s RESUME (%s)\n", 510 "host", 511 otg_state_string(musb)); 512 } 513#endif 514 } else { 515 switch (musb->xceiv->state) { 516#ifdef CONFIG_USB_MUSB_HDRC_HCD 517 case OTG_STATE_A_SUSPEND: 518 /* possibly DISCONNECT is upcoming */ 519 musb->xceiv->state = OTG_STATE_A_HOST; 520 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 521 break; 522#endif 523#ifdef CONFIG_USB_GADGET_MUSB_HDRC 524 case OTG_STATE_B_WAIT_ACON: 525 case OTG_STATE_B_PERIPHERAL: 526 /* disconnect while suspended? we may 527 * not get a disconnect irq... 528 */ 529 if ((devctl & MUSB_DEVCTL_VBUS) 530 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 531 ) { 532 musb->int_usb |= MUSB_INTR_DISCONNECT; 533 musb->int_usb &= ~MUSB_INTR_SUSPEND; 534 break; 535 } 536 musb_g_resume(musb); 537 break; 538 case OTG_STATE_B_IDLE: 539 musb->int_usb &= ~MUSB_INTR_SUSPEND; 540 break; 541#endif 542 default: 543 WARNING("bogus %s RESUME (%s)\n", 544 "peripheral", 545 otg_state_string(musb)); 546 } 547 } 548 } 549 550#ifdef CONFIG_USB_MUSB_HDRC_HCD 551 /* see manual for the order of the tests */ 552 if (int_usb & MUSB_INTR_SESSREQ) { 553 void __iomem *mbase = musb->mregs; 554 555 if (devctl & MUSB_DEVCTL_BDEVICE) { 556 DBG(3, "SessReq while on B state\n"); 557 return IRQ_HANDLED; 558 } 559 560 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); 561 562 /* IRQ arrives from ID pin sense or (later, if VBUS power 563 * is removed) SRP. responses are time critical: 564 * - turn on VBUS (with silicon-specific mechanism) 565 * - go through A_WAIT_VRISE 566 * - ... to A_WAIT_BCON. 567 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 568 */ 569 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 570 musb->ep0_stage = MUSB_EP0_START; 571 musb->xceiv->state = OTG_STATE_A_IDLE; 572 MUSB_HST_MODE(musb); 573 musb_platform_set_vbus(musb, 1); 574 575 handled = IRQ_HANDLED; 576 } 577 578 if (int_usb & MUSB_INTR_VBUSERROR) { 579 int ignore = 0; 580 581 /* During connection as an A-Device, we may see a short 582 * current spikes causing voltage drop, because of cable 583 * and peripheral capacitance combined with vbus draw. 584 * (So: less common with truly self-powered devices, where 585 * vbus doesn't act like a power supply.) 586 * 587 * Such spikes are short; usually less than ~500 usec, max 588 * of ~2 msec. That is, they're not sustained overcurrent 589 * errors, though they're reported using VBUSERROR irqs. 590 * 591 * Workarounds: (a) hardware: use self powered devices. 592 * (b) software: ignore non-repeated VBUS errors. 593 * 594 * REVISIT: do delays from lots of DEBUG_KERNEL checks 595 * make trouble here, keeping VBUS < 4.4V ? 596 */ 597 switch (musb->xceiv->state) { 598 case OTG_STATE_A_HOST: 599 /* recovery is dicey once we've gotten past the 600 * initial stages of enumeration, but if VBUS 601 * stayed ok at the other end of the link, and 602 * another reset is due (at least for high speed, 603 * to redo the chirp etc), it might work OK... 604 */ 605 case OTG_STATE_A_WAIT_BCON: 606 case OTG_STATE_A_WAIT_VRISE: 607 if (musb->vbuserr_retry) { 608 void __iomem *mbase = musb->mregs; 609 610 musb->vbuserr_retry--; 611 ignore = 1; 612 devctl |= MUSB_DEVCTL_SESSION; 613 musb_writeb(mbase, MUSB_DEVCTL, devctl); 614 } else { 615 musb->port1_status |= 616 USB_PORT_STAT_OVERCURRENT 617 | (USB_PORT_STAT_C_OVERCURRENT << 16); 618 } 619 break; 620 default: 621 break; 622 } 623 624 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 625 otg_state_string(musb), 626 devctl, 627 ({ char *s; 628 switch (devctl & MUSB_DEVCTL_VBUS) { 629 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 630 s = "<SessEnd"; break; 631 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 632 s = "<AValid"; break; 633 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 634 s = "<VBusValid"; break; 635 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 636 default: 637 s = "VALID"; break; 638 }; s; }), 639 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 640 musb->port1_status); 641 642 /* go through A_WAIT_VFALL then start a new session */ 643 if (!ignore) 644 musb_platform_set_vbus(musb, 0); 645 handled = IRQ_HANDLED; 646 } 647 648#endif 649 if (int_usb & MUSB_INTR_SUSPEND) { 650 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", 651 otg_state_string(musb), devctl, power); 652 handled = IRQ_HANDLED; 653 654 switch (musb->xceiv->state) { 655#ifdef CONFIG_USB_MUSB_OTG 656 case OTG_STATE_A_PERIPHERAL: 657 /* We also come here if the cable is removed, since 658 * this silicon doesn't report ID-no-longer-grounded. 659 * 660 * We depend on T(a_wait_bcon) to shut us down, and 661 * hope users don't do anything dicey during this 662 * undesired detour through A_WAIT_BCON. 663 */ 664 musb_hnp_stop(musb); 665 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 666 musb_root_disconnect(musb); 667 musb_platform_try_idle(musb, jiffies 668 + msecs_to_jiffies(musb->a_wait_bcon 669 ? : OTG_TIME_A_WAIT_BCON)); 670 671 break; 672#endif 673 case OTG_STATE_B_IDLE: 674 if (!musb->is_active) 675 break; 676 case OTG_STATE_B_PERIPHERAL: 677 musb_g_suspend(musb); 678 musb->is_active = is_otg_enabled(musb) 679 && musb->xceiv->gadget->b_hnp_enable; 680 if (musb->is_active) { 681#ifdef CONFIG_USB_MUSB_OTG 682 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 683 DBG(1, "HNP: Setting timer for b_ase0_brst\n"); 684 mod_timer(&musb->otg_timer, jiffies 685 + msecs_to_jiffies( 686 OTG_TIME_B_ASE0_BRST)); 687#endif 688 } 689 break; 690 case OTG_STATE_A_WAIT_BCON: 691 if (musb->a_wait_bcon != 0) 692 musb_platform_try_idle(musb, jiffies 693 + msecs_to_jiffies(musb->a_wait_bcon)); 694 break; 695 case OTG_STATE_A_HOST: 696 musb->xceiv->state = OTG_STATE_A_SUSPEND; 697 musb->is_active = is_otg_enabled(musb) 698 && musb->xceiv->host->b_hnp_enable; 699 break; 700 case OTG_STATE_B_HOST: 701 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 702 DBG(1, "REVISIT: SUSPEND as B_HOST\n"); 703 break; 704 default: 705 /* "should not happen" */ 706 musb->is_active = 0; 707 break; 708 } 709 } 710 711#ifdef CONFIG_USB_MUSB_HDRC_HCD 712 if (int_usb & MUSB_INTR_CONNECT) { 713 struct usb_hcd *hcd = musb_to_hcd(musb); 714 715 handled = IRQ_HANDLED; 716 musb->is_active = 1; 717 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); 718 719 musb->ep0_stage = MUSB_EP0_START; 720 721#ifdef CONFIG_USB_MUSB_OTG 722 /* flush endpoints when transitioning from Device Mode */ 723 if (is_peripheral_active(musb)) { 724 /* REVISIT HNP; just force disconnect */ 725 } 726 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); 727 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); 728 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); 729#endif 730 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 731 |USB_PORT_STAT_HIGH_SPEED 732 |USB_PORT_STAT_ENABLE 733 ); 734 musb->port1_status |= USB_PORT_STAT_CONNECTION 735 |(USB_PORT_STAT_C_CONNECTION << 16); 736 737 /* high vs full speed is just a guess until after reset */ 738 if (devctl & MUSB_DEVCTL_LSDEV) 739 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 740 741 /* indicate new connection to OTG machine */ 742 switch (musb->xceiv->state) { 743 case OTG_STATE_B_PERIPHERAL: 744 if (int_usb & MUSB_INTR_SUSPEND) { 745 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); 746 int_usb &= ~MUSB_INTR_SUSPEND; 747 goto b_host; 748 } else 749 DBG(1, "CONNECT as b_peripheral???\n"); 750 break; 751 case OTG_STATE_B_WAIT_ACON: 752 DBG(1, "HNP: CONNECT, now b_host\n"); 753b_host: 754 musb->xceiv->state = OTG_STATE_B_HOST; 755 hcd->self.is_b_host = 1; 756 musb->ignore_disconnect = 0; 757 del_timer(&musb->otg_timer); 758 break; 759 default: 760 if ((devctl & MUSB_DEVCTL_VBUS) 761 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 762 musb->xceiv->state = OTG_STATE_A_HOST; 763 hcd->self.is_b_host = 0; 764 } 765 break; 766 } 767 768 /* poke the root hub */ 769 MUSB_HST_MODE(musb); 770 if (hcd->status_urb) 771 usb_hcd_poll_rh_status(hcd); 772 else 773 usb_hcd_resume_root_hub(hcd); 774 775 DBG(1, "CONNECT (%s) devctl %02x\n", 776 otg_state_string(musb), devctl); 777 } 778#endif /* CONFIG_USB_MUSB_HDRC_HCD */ 779 780 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 781 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n", 782 otg_state_string(musb), 783 MUSB_MODE(musb), devctl); 784 handled = IRQ_HANDLED; 785 786 switch (musb->xceiv->state) { 787#ifdef CONFIG_USB_MUSB_HDRC_HCD 788 case OTG_STATE_A_HOST: 789 case OTG_STATE_A_SUSPEND: 790 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 791 musb_root_disconnect(musb); 792 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 793 musb_platform_try_idle(musb, jiffies 794 + msecs_to_jiffies(musb->a_wait_bcon)); 795 break; 796#endif /* HOST */ 797#ifdef CONFIG_USB_MUSB_OTG 798 case OTG_STATE_B_HOST: 799 /* REVISIT this behaves for "real disconnect" 800 * cases; make sure the other transitions from 801 * from B_HOST act right too. The B_HOST code 802 * in hnp_stop() is currently not used... 803 */ 804 musb_root_disconnect(musb); 805 musb_to_hcd(musb)->self.is_b_host = 0; 806 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 807 MUSB_DEV_MODE(musb); 808 musb_g_disconnect(musb); 809 break; 810 case OTG_STATE_A_PERIPHERAL: 811 musb_hnp_stop(musb); 812 musb_root_disconnect(musb); 813 /* FALLTHROUGH */ 814 case OTG_STATE_B_WAIT_ACON: 815 /* FALLTHROUGH */ 816#endif /* OTG */ 817#ifdef CONFIG_USB_GADGET_MUSB_HDRC 818 case OTG_STATE_B_PERIPHERAL: 819 case OTG_STATE_B_IDLE: 820 musb_g_disconnect(musb); 821 break; 822#endif /* GADGET */ 823 default: 824 WARNING("unhandled DISCONNECT transition (%s)\n", 825 otg_state_string(musb)); 826 break; 827 } 828 } 829 830 /* mentor saves a bit: bus reset and babble share the same irq. 831 * only host sees babble; only peripheral sees bus reset. 832 */ 833 if (int_usb & MUSB_INTR_RESET) { 834 handled = IRQ_HANDLED; 835 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 836 /* 837 * Looks like non-HS BABBLE can be ignored, but 838 * HS BABBLE is an error condition. For HS the solution 839 * is to avoid babble in the first place and fix what 840 * caused BABBLE. When HS BABBLE happens we can only 841 * stop the session. 842 */ 843 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 844 DBG(1, "BABBLE devctl: %02x\n", devctl); 845 else { 846 ERR("Stopping host session -- babble\n"); 847 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 848 } 849 } else if (is_peripheral_capable()) { 850 DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); 851 switch (musb->xceiv->state) { 852#ifdef CONFIG_USB_OTG 853 case OTG_STATE_A_SUSPEND: 854 /* We need to ignore disconnect on suspend 855 * otherwise tusb 2.0 won't reconnect after a 856 * power cycle, which breaks otg compliance. 857 */ 858 musb->ignore_disconnect = 1; 859 musb_g_reset(musb); 860 /* FALLTHROUGH */ 861 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 862 /* never use invalid T(a_wait_bcon) */ 863 DBG(1, "HNP: in %s, %d msec timeout\n", 864 otg_state_string(musb), 865 TA_WAIT_BCON(musb)); 866 mod_timer(&musb->otg_timer, jiffies 867 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 868 break; 869 case OTG_STATE_A_PERIPHERAL: 870 musb->ignore_disconnect = 0; 871 del_timer(&musb->otg_timer); 872 musb_g_reset(musb); 873 break; 874 case OTG_STATE_B_WAIT_ACON: 875 DBG(1, "HNP: RESET (%s), to b_peripheral\n", 876 otg_state_string(musb)); 877 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 878 musb_g_reset(musb); 879 break; 880#endif 881 case OTG_STATE_B_IDLE: 882 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 883 /* FALLTHROUGH */ 884 case OTG_STATE_B_PERIPHERAL: 885 musb_g_reset(musb); 886 break; 887 default: 888 DBG(1, "Unhandled BUS RESET as %s\n", 889 otg_state_string(musb)); 890 } 891 } 892 } 893 894#if 0 895/* REVISIT ... this would be for multiplexing periodic endpoints, or 896 * supporting transfer phasing to prevent exceeding ISO bandwidth 897 * limits of a given frame or microframe. 898 * 899 * It's not needed for peripheral side, which dedicates endpoints; 900 * though it _might_ use SOF irqs for other purposes. 901 * 902 * And it's not currently needed for host side, which also dedicates 903 * endpoints, relies on TX/RX interval registers, and isn't claimed 904 * to support ISO transfers yet. 905 */ 906 if (int_usb & MUSB_INTR_SOF) { 907 void __iomem *mbase = musb->mregs; 908 struct musb_hw_ep *ep; 909 u8 epnum; 910 u16 frame; 911 912 DBG(6, "START_OF_FRAME\n"); 913 handled = IRQ_HANDLED; 914 915 /* start any periodic Tx transfers waiting for current frame */ 916 frame = musb_readw(mbase, MUSB_FRAME); 917 ep = musb->endpoints; 918 for (epnum = 1; (epnum < musb->nr_endpoints) 919 && (musb->epmask >= (1 << epnum)); 920 epnum++, ep++) { 921 /* 922 * FIXME handle framecounter wraps (12 bits) 923 * eliminate duplicated StartUrb logic 924 */ 925 if (ep->dwWaitFrame >= frame) { 926 ep->dwWaitFrame = 0; 927 pr_debug("SOF --> periodic TX%s on %d\n", 928 ep->tx_channel ? " DMA" : "", 929 epnum); 930 if (!ep->tx_channel) 931 musb_h_tx_start(musb, epnum); 932 else 933 cppi_hostdma_start(musb, epnum); 934 } 935 } /* end of for loop */ 936 } 937#endif 938 939 schedule_work(&musb->irq_work); 940 941 return handled; 942} 943 944/*-------------------------------------------------------------------------*/ 945 946/* 947* Program the HDRC to start (enable interrupts, dma, etc.). 948*/ 949void musb_start(struct musb *musb) 950{ 951 void __iomem *regs = musb->mregs; 952 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 953 954 DBG(2, "<== devctl %02x\n", devctl); 955 956 /* Set INT enable registers, enable interrupts */ 957 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 958 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 959 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 960 961 musb_writeb(regs, MUSB_TESTMODE, 0); 962 963 /* put into basic highspeed mode and start session */ 964 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 965 | MUSB_POWER_SOFTCONN 966 | MUSB_POWER_HSENAB 967 /* ENSUSPEND wedges tusb */ 968 /* | MUSB_POWER_ENSUSPEND */ 969 ); 970 971 musb->is_active = 0; 972 devctl = musb_readb(regs, MUSB_DEVCTL); 973 devctl &= ~MUSB_DEVCTL_SESSION; 974 975 if (is_otg_enabled(musb)) { 976 /* session started after: 977 * (a) ID-grounded irq, host mode; 978 * (b) vbus present/connect IRQ, peripheral mode; 979 * (c) peripheral initiates, using SRP 980 */ 981 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 982 musb->is_active = 1; 983 else 984 devctl |= MUSB_DEVCTL_SESSION; 985 986 } else if (is_host_enabled(musb)) { 987 /* assume ID pin is hard-wired to ground */ 988 devctl |= MUSB_DEVCTL_SESSION; 989 990 } else /* peripheral is enabled */ { 991 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 992 musb->is_active = 1; 993 } 994 musb_platform_enable(musb); 995 musb_writeb(regs, MUSB_DEVCTL, devctl); 996} 997 998 999static void musb_generic_disable(struct musb *musb) 1000{ 1001 void __iomem *mbase = musb->mregs; 1002 u16 temp; 1003 1004 /* disable interrupts */ 1005 musb_writeb(mbase, MUSB_INTRUSBE, 0); 1006 musb_writew(mbase, MUSB_INTRTXE, 0); 1007 musb_writew(mbase, MUSB_INTRRXE, 0); 1008 1009 /* off */ 1010 musb_writeb(mbase, MUSB_DEVCTL, 0); 1011 1012 /* flush pending interrupts */ 1013 temp = musb_readb(mbase, MUSB_INTRUSB); 1014 temp = musb_readw(mbase, MUSB_INTRTX); 1015 temp = musb_readw(mbase, MUSB_INTRRX); 1016 1017} 1018 1019/* 1020 * Make the HDRC stop (disable interrupts, etc.); 1021 * reversible by musb_start 1022 * called on gadget driver unregister 1023 * with controller locked, irqs blocked 1024 * acts as a NOP unless some role activated the hardware 1025 */ 1026void musb_stop(struct musb *musb) 1027{ 1028 /* stop IRQs, timers, ... */ 1029 musb_platform_disable(musb); 1030 musb_generic_disable(musb); 1031 DBG(3, "HDRC disabled\n"); 1032 1033 /* FIXME 1034 * - mark host and/or peripheral drivers unusable/inactive 1035 * - disable DMA (and enable it in HdrcStart) 1036 * - make sure we can musb_start() after musb_stop(); with 1037 * OTG mode, gadget driver module rmmod/modprobe cycles that 1038 * - ... 1039 */ 1040 musb_platform_try_idle(musb, 0); 1041} 1042 1043static void musb_shutdown(struct platform_device *pdev) 1044{ 1045 struct musb *musb = dev_to_musb(&pdev->dev); 1046 unsigned long flags; 1047 1048 spin_lock_irqsave(&musb->lock, flags); 1049 musb_platform_disable(musb); 1050 musb_generic_disable(musb); 1051 if (musb->clock) 1052 clk_put(musb->clock); 1053 spin_unlock_irqrestore(&musb->lock, flags); 1054 1055 /* FIXME power down */ 1056} 1057 1058 1059/*-------------------------------------------------------------------------*/ 1060 1061/* 1062 * The silicon either has hard-wired endpoint configurations, or else 1063 * "dynamic fifo" sizing. The driver has support for both, though at this 1064 * writing only the dynamic sizing is very well tested. Since we switched 1065 * away from compile-time hardware parameters, we can no longer rely on 1066 * dead code elimination to leave only the relevant one in the object file. 1067 * 1068 * We don't currently use dynamic fifo setup capability to do anything 1069 * more than selecting one of a bunch of predefined configurations. 1070 */ 1071#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ 1072 || defined(CONFIG_USB_MUSB_AM35X) 1073static ushort __initdata fifo_mode = 4; 1074#else 1075static ushort __initdata fifo_mode = 2; 1076#endif 1077 1078/* "modprobe ... fifo_mode=1" etc */ 1079module_param(fifo_mode, ushort, 0); 1080MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 1081 1082/* 1083 * tables defining fifo_mode values. define more if you like. 1084 * for host side, make sure both halves of ep1 are set up. 1085 */ 1086 1087/* mode 0 - fits in 2KB */ 1088static struct musb_fifo_cfg __initdata mode_0_cfg[] = { 1089{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1090{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1091{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1092{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1093{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1094}; 1095 1096/* mode 1 - fits in 4KB */ 1097static struct musb_fifo_cfg __initdata mode_1_cfg[] = { 1098{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1099{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1100{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1101{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1102{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1103}; 1104 1105/* mode 2 - fits in 4KB */ 1106static struct musb_fifo_cfg __initdata mode_2_cfg[] = { 1107{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1108{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1109{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1110{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1111{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1112{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1113}; 1114 1115/* mode 3 - fits in 4KB */ 1116static struct musb_fifo_cfg __initdata mode_3_cfg[] = { 1117{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1118{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1119{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1120{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1121{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1122{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1123}; 1124 1125/* mode 4 - fits in 16KB */ 1126static struct musb_fifo_cfg __initdata mode_4_cfg[] = { 1127{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1128{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1129{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1130{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1131{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1132{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1133{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1134{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1135{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1136{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1137{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1138{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1139{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1140{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1141{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1142{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1143{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1144{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1145{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, 1146{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, 1147{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, 1148{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, 1149{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, 1150{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, 1151{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, 1152{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1153{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1154}; 1155 1156/* mode 5 - fits in 8KB */ 1157static struct musb_fifo_cfg __initdata mode_5_cfg[] = { 1158{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1159{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1160{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1161{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1162{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1163{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1164{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1165{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1166{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1167{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1168{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, 1169{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, 1170{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, 1171{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, 1172{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, 1173{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, 1174{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, 1175{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, 1176{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, 1177{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, 1178{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, 1179{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, 1180{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, 1181{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, 1182{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, 1183{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1184{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1185}; 1186 1187/* 1188 * configure a fifo; for non-shared endpoints, this may be called 1189 * once for a tx fifo and once for an rx fifo. 1190 * 1191 * returns negative errno or offset for next fifo. 1192 */ 1193static int __init 1194fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1195 const struct musb_fifo_cfg *cfg, u16 offset) 1196{ 1197 void __iomem *mbase = musb->mregs; 1198 int size = 0; 1199 u16 maxpacket = cfg->maxpacket; 1200 u16 c_off = offset >> 3; 1201 u8 c_size; 1202 1203 /* expect hw_ep has already been zero-initialized */ 1204 1205 size = ffs(max(maxpacket, (u16) 8)) - 1; 1206 maxpacket = 1 << size; 1207 1208 c_size = size - 3; 1209 if (cfg->mode == BUF_DOUBLE) { 1210 if ((offset + (maxpacket << 1)) > 1211 (1 << (musb->config->ram_bits + 2))) 1212 return -EMSGSIZE; 1213 c_size |= MUSB_FIFOSZ_DPB; 1214 } else { 1215 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1216 return -EMSGSIZE; 1217 } 1218 1219 /* configure the FIFO */ 1220 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1221 1222#ifdef CONFIG_USB_MUSB_HDRC_HCD 1223 /* EP0 reserved endpoint for control, bidirectional; 1224 * EP1 reserved for bulk, two unidirection halves. 1225 */ 1226 if (hw_ep->epnum == 1) 1227 musb->bulk_ep = hw_ep; 1228 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1229#endif 1230 switch (cfg->style) { 1231 case FIFO_TX: 1232 musb_write_txfifosz(mbase, c_size); 1233 musb_write_txfifoadd(mbase, c_off); 1234 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1235 hw_ep->max_packet_sz_tx = maxpacket; 1236 break; 1237 case FIFO_RX: 1238 musb_write_rxfifosz(mbase, c_size); 1239 musb_write_rxfifoadd(mbase, c_off); 1240 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1241 hw_ep->max_packet_sz_rx = maxpacket; 1242 break; 1243 case FIFO_RXTX: 1244 musb_write_txfifosz(mbase, c_size); 1245 musb_write_txfifoadd(mbase, c_off); 1246 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1247 hw_ep->max_packet_sz_rx = maxpacket; 1248 1249 musb_write_rxfifosz(mbase, c_size); 1250 musb_write_rxfifoadd(mbase, c_off); 1251 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1252 hw_ep->max_packet_sz_tx = maxpacket; 1253 1254 hw_ep->is_shared_fifo = true; 1255 break; 1256 } 1257 1258 /* NOTE rx and tx endpoint irqs aren't managed separately, 1259 * which happens to be ok 1260 */ 1261 musb->epmask |= (1 << hw_ep->epnum); 1262 1263 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1264} 1265 1266static struct musb_fifo_cfg __initdata ep0_cfg = { 1267 .style = FIFO_RXTX, .maxpacket = 64, 1268}; 1269 1270static int __init ep_config_from_table(struct musb *musb) 1271{ 1272 const struct musb_fifo_cfg *cfg; 1273 unsigned i, n; 1274 int offset; 1275 struct musb_hw_ep *hw_ep = musb->endpoints; 1276 1277 if (musb->config->fifo_cfg) { 1278 cfg = musb->config->fifo_cfg; 1279 n = musb->config->fifo_cfg_size; 1280 goto done; 1281 } 1282 1283 switch (fifo_mode) { 1284 default: 1285 fifo_mode = 0; 1286 /* FALLTHROUGH */ 1287 case 0: 1288 cfg = mode_0_cfg; 1289 n = ARRAY_SIZE(mode_0_cfg); 1290 break; 1291 case 1: 1292 cfg = mode_1_cfg; 1293 n = ARRAY_SIZE(mode_1_cfg); 1294 break; 1295 case 2: 1296 cfg = mode_2_cfg; 1297 n = ARRAY_SIZE(mode_2_cfg); 1298 break; 1299 case 3: 1300 cfg = mode_3_cfg; 1301 n = ARRAY_SIZE(mode_3_cfg); 1302 break; 1303 case 4: 1304 cfg = mode_4_cfg; 1305 n = ARRAY_SIZE(mode_4_cfg); 1306 break; 1307 case 5: 1308 cfg = mode_5_cfg; 1309 n = ARRAY_SIZE(mode_5_cfg); 1310 break; 1311 } 1312 1313 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1314 musb_driver_name, fifo_mode); 1315 1316 1317done: 1318 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1319 /* assert(offset > 0) */ 1320 1321 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1322 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1323 */ 1324 1325 for (i = 0; i < n; i++) { 1326 u8 epn = cfg->hw_ep_num; 1327 1328 if (epn >= musb->config->num_eps) { 1329 pr_debug("%s: invalid ep %d\n", 1330 musb_driver_name, epn); 1331 return -EINVAL; 1332 } 1333 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1334 if (offset < 0) { 1335 pr_debug("%s: mem overrun, ep %d\n", 1336 musb_driver_name, epn); 1337 return -EINVAL; 1338 } 1339 epn++; 1340 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1341 } 1342 1343 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1344 musb_driver_name, 1345 n + 1, musb->config->num_eps * 2 - 1, 1346 offset, (1 << (musb->config->ram_bits + 2))); 1347 1348#ifdef CONFIG_USB_MUSB_HDRC_HCD 1349 if (!musb->bulk_ep) { 1350 pr_debug("%s: missing bulk\n", musb_driver_name); 1351 return -EINVAL; 1352 } 1353#endif 1354 1355 return 0; 1356} 1357 1358 1359/* 1360 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1361 * @param musb the controller 1362 */ 1363static int __init ep_config_from_hw(struct musb *musb) 1364{ 1365 u8 epnum = 0; 1366 struct musb_hw_ep *hw_ep; 1367 void *mbase = musb->mregs; 1368 int ret = 0; 1369 1370 DBG(2, "<== static silicon ep config\n"); 1371 1372 /* FIXME pick up ep0 maxpacket size */ 1373 1374 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1375 musb_ep_select(mbase, epnum); 1376 hw_ep = musb->endpoints + epnum; 1377 1378 ret = musb_read_fifosize(musb, hw_ep, epnum); 1379 if (ret < 0) 1380 break; 1381 1382 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1383 1384#ifdef CONFIG_USB_MUSB_HDRC_HCD 1385 /* pick an RX/TX endpoint for bulk */ 1386 if (hw_ep->max_packet_sz_tx < 512 1387 || hw_ep->max_packet_sz_rx < 512) 1388 continue; 1389 1390 /* REVISIT: this algorithm is lazy, we should at least 1391 * try to pick a double buffered endpoint. 1392 */ 1393 if (musb->bulk_ep) 1394 continue; 1395 musb->bulk_ep = hw_ep; 1396#endif 1397 } 1398 1399#ifdef CONFIG_USB_MUSB_HDRC_HCD 1400 if (!musb->bulk_ep) { 1401 pr_debug("%s: missing bulk\n", musb_driver_name); 1402 return -EINVAL; 1403 } 1404#endif 1405 1406 return 0; 1407} 1408 1409enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1410 1411/* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1412 * configure endpoints, or take their config from silicon 1413 */ 1414static int __init musb_core_init(u16 musb_type, struct musb *musb) 1415{ 1416 u8 reg; 1417 char *type; 1418 char aInfo[90], aRevision[32], aDate[12]; 1419 void __iomem *mbase = musb->mregs; 1420 int status = 0; 1421 int i; 1422 1423 /* log core options (read using indexed model) */ 1424 reg = musb_read_configdata(mbase); 1425 1426 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1427 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1428 strcat(aInfo, ", dyn FIFOs"); 1429 musb->dyn_fifo = true; 1430 } 1431 if (reg & MUSB_CONFIGDATA_MPRXE) { 1432 strcat(aInfo, ", bulk combine"); 1433 musb->bulk_combine = true; 1434 } 1435 if (reg & MUSB_CONFIGDATA_MPTXE) { 1436 strcat(aInfo, ", bulk split"); 1437 musb->bulk_split = true; 1438 } 1439 if (reg & MUSB_CONFIGDATA_HBRXE) { 1440 strcat(aInfo, ", HB-ISO Rx"); 1441 musb->hb_iso_rx = true; 1442 } 1443 if (reg & MUSB_CONFIGDATA_HBTXE) { 1444 strcat(aInfo, ", HB-ISO Tx"); 1445 musb->hb_iso_tx = true; 1446 } 1447 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1448 strcat(aInfo, ", SoftConn"); 1449 1450 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1451 musb_driver_name, reg, aInfo); 1452 1453 aDate[0] = 0; 1454 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1455 musb->is_multipoint = 1; 1456 type = "M"; 1457 } else { 1458 musb->is_multipoint = 0; 1459 type = ""; 1460#ifdef CONFIG_USB_MUSB_HDRC_HCD 1461#ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1462 printk(KERN_ERR 1463 "%s: kernel must blacklist external hubs\n", 1464 musb_driver_name); 1465#endif 1466#endif 1467 } 1468 1469 /* log release info */ 1470 musb->hwvers = musb_read_hwvers(mbase); 1471 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), 1472 MUSB_HWVERS_MINOR(musb->hwvers), 1473 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); 1474 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1475 musb_driver_name, type, aRevision, aDate); 1476 1477 /* configure ep0 */ 1478 musb_configure_ep0(musb); 1479 1480 /* discover endpoint configuration */ 1481 musb->nr_endpoints = 1; 1482 musb->epmask = 1; 1483 1484 if (musb->dyn_fifo) 1485 status = ep_config_from_table(musb); 1486 else 1487 status = ep_config_from_hw(musb); 1488 1489 if (status < 0) 1490 return status; 1491 1492 /* finish init, and print endpoint config */ 1493 for (i = 0; i < musb->nr_endpoints; i++) { 1494 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1495 1496 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1497#ifdef CONFIG_USB_MUSB_TUSB6010 1498 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1499 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1500 hw_ep->fifo_sync_va = 1501 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1502 1503 if (i == 0) 1504 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1505 else 1506 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1507#endif 1508 1509 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1510#ifdef CONFIG_USB_MUSB_HDRC_HCD 1511 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1512 hw_ep->rx_reinit = 1; 1513 hw_ep->tx_reinit = 1; 1514#endif 1515 1516 if (hw_ep->max_packet_sz_tx) { 1517 DBG(1, 1518 "%s: hw_ep %d%s, %smax %d\n", 1519 musb_driver_name, i, 1520 hw_ep->is_shared_fifo ? "shared" : "tx", 1521 hw_ep->tx_double_buffered 1522 ? "doublebuffer, " : "", 1523 hw_ep->max_packet_sz_tx); 1524 } 1525 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1526 DBG(1, 1527 "%s: hw_ep %d%s, %smax %d\n", 1528 musb_driver_name, i, 1529 "rx", 1530 hw_ep->rx_double_buffered 1531 ? "doublebuffer, " : "", 1532 hw_ep->max_packet_sz_rx); 1533 } 1534 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1535 DBG(1, "hw_ep %d not configured\n", i); 1536 } 1537 1538 return 0; 1539} 1540 1541/*-------------------------------------------------------------------------*/ 1542 1543#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \ 1544 defined(CONFIG_ARCH_OMAP4) 1545 1546static irqreturn_t generic_interrupt(int irq, void *__hci) 1547{ 1548 unsigned long flags; 1549 irqreturn_t retval = IRQ_NONE; 1550 struct musb *musb = __hci; 1551 1552 spin_lock_irqsave(&musb->lock, flags); 1553 1554 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1555 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1556 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1557 1558 if (musb->int_usb || musb->int_tx || musb->int_rx) 1559 retval = musb_interrupt(musb); 1560 1561 spin_unlock_irqrestore(&musb->lock, flags); 1562 1563 return retval; 1564} 1565 1566#else 1567#define generic_interrupt NULL 1568#endif 1569 1570/* 1571 * handle all the irqs defined by the HDRC core. for now we expect: other 1572 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1573 * will be assigned, and the irq will already have been acked. 1574 * 1575 * called in irq context with spinlock held, irqs blocked 1576 */ 1577irqreturn_t musb_interrupt(struct musb *musb) 1578{ 1579 irqreturn_t retval = IRQ_NONE; 1580 u8 devctl, power; 1581 int ep_num; 1582 u32 reg; 1583 1584 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1585 power = musb_readb(musb->mregs, MUSB_POWER); 1586 1587 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n", 1588 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1589 musb->int_usb, musb->int_tx, musb->int_rx); 1590 1591#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1592 if (is_otg_enabled(musb) || is_peripheral_enabled(musb)) 1593 if (!musb->gadget_driver) { 1594 DBG(5, "No gadget driver loaded\n"); 1595 return IRQ_HANDLED; 1596 } 1597#endif 1598 1599 /* the core can interrupt us for multiple reasons; docs have 1600 * a generic interrupt flowchart to follow 1601 */ 1602 if (musb->int_usb) 1603 retval |= musb_stage0_irq(musb, musb->int_usb, 1604 devctl, power); 1605 1606 /* "stage 1" is handling endpoint irqs */ 1607 1608 /* handle endpoint 0 first */ 1609 if (musb->int_tx & 1) { 1610 if (devctl & MUSB_DEVCTL_HM) 1611 retval |= musb_h_ep0_irq(musb); 1612 else 1613 retval |= musb_g_ep0_irq(musb); 1614 } 1615 1616 /* RX on endpoints 1-15 */ 1617 reg = musb->int_rx >> 1; 1618 ep_num = 1; 1619 while (reg) { 1620 if (reg & 1) { 1621 /* musb_ep_select(musb->mregs, ep_num); */ 1622 /* REVISIT just retval = ep->rx_irq(...) */ 1623 retval = IRQ_HANDLED; 1624 if (devctl & MUSB_DEVCTL_HM) { 1625 if (is_host_capable()) 1626 musb_host_rx(musb, ep_num); 1627 } else { 1628 if (is_peripheral_capable()) 1629 musb_g_rx(musb, ep_num); 1630 } 1631 } 1632 1633 reg >>= 1; 1634 ep_num++; 1635 } 1636 1637 /* TX on endpoints 1-15 */ 1638 reg = musb->int_tx >> 1; 1639 ep_num = 1; 1640 while (reg) { 1641 if (reg & 1) { 1642 /* musb_ep_select(musb->mregs, ep_num); */ 1643 /* REVISIT just retval |= ep->tx_irq(...) */ 1644 retval = IRQ_HANDLED; 1645 if (devctl & MUSB_DEVCTL_HM) { 1646 if (is_host_capable()) 1647 musb_host_tx(musb, ep_num); 1648 } else { 1649 if (is_peripheral_capable()) 1650 musb_g_tx(musb, ep_num); 1651 } 1652 } 1653 reg >>= 1; 1654 ep_num++; 1655 } 1656 1657 return retval; 1658} 1659 1660 1661#ifndef CONFIG_MUSB_PIO_ONLY 1662static int __initdata use_dma = 1; 1663 1664/* "modprobe ... use_dma=0" etc */ 1665module_param(use_dma, bool, 0); 1666MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1667 1668void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1669{ 1670 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1671 1672 /* called with controller lock already held */ 1673 1674 if (!epnum) { 1675#ifndef CONFIG_USB_TUSB_OMAP_DMA 1676 if (!is_cppi_enabled()) { 1677 /* endpoint 0 */ 1678 if (devctl & MUSB_DEVCTL_HM) 1679 musb_h_ep0_irq(musb); 1680 else 1681 musb_g_ep0_irq(musb); 1682 } 1683#endif 1684 } else { 1685 /* endpoints 1..15 */ 1686 if (transmit) { 1687 if (devctl & MUSB_DEVCTL_HM) { 1688 if (is_host_capable()) 1689 musb_host_tx(musb, epnum); 1690 } else { 1691 if (is_peripheral_capable()) 1692 musb_g_tx(musb, epnum); 1693 } 1694 } else { 1695 /* receive */ 1696 if (devctl & MUSB_DEVCTL_HM) { 1697 if (is_host_capable()) 1698 musb_host_rx(musb, epnum); 1699 } else { 1700 if (is_peripheral_capable()) 1701 musb_g_rx(musb, epnum); 1702 } 1703 } 1704 } 1705} 1706 1707#else 1708#define use_dma 0 1709#endif 1710 1711/*-------------------------------------------------------------------------*/ 1712 1713#ifdef CONFIG_SYSFS 1714 1715static ssize_t 1716musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1717{ 1718 struct musb *musb = dev_to_musb(dev); 1719 unsigned long flags; 1720 int ret = -EINVAL; 1721 1722 spin_lock_irqsave(&musb->lock, flags); 1723 ret = sprintf(buf, "%s\n", otg_state_string(musb)); 1724 spin_unlock_irqrestore(&musb->lock, flags); 1725 1726 return ret; 1727} 1728 1729static ssize_t 1730musb_mode_store(struct device *dev, struct device_attribute *attr, 1731 const char *buf, size_t n) 1732{ 1733 struct musb *musb = dev_to_musb(dev); 1734 unsigned long flags; 1735 int status; 1736 1737 spin_lock_irqsave(&musb->lock, flags); 1738 if (sysfs_streq(buf, "host")) 1739 status = musb_platform_set_mode(musb, MUSB_HOST); 1740 else if (sysfs_streq(buf, "peripheral")) 1741 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1742 else if (sysfs_streq(buf, "otg")) 1743 status = musb_platform_set_mode(musb, MUSB_OTG); 1744 else 1745 status = -EINVAL; 1746 spin_unlock_irqrestore(&musb->lock, flags); 1747 1748 return (status == 0) ? n : status; 1749} 1750static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1751 1752static ssize_t 1753musb_vbus_store(struct device *dev, struct device_attribute *attr, 1754 const char *buf, size_t n) 1755{ 1756 struct musb *musb = dev_to_musb(dev); 1757 unsigned long flags; 1758 unsigned long val; 1759 1760 if (sscanf(buf, "%lu", &val) < 1) { 1761 dev_err(dev, "Invalid VBUS timeout ms value\n"); 1762 return -EINVAL; 1763 } 1764 1765 spin_lock_irqsave(&musb->lock, flags); 1766 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1767 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1768 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1769 musb->is_active = 0; 1770 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1771 spin_unlock_irqrestore(&musb->lock, flags); 1772 1773 return n; 1774} 1775 1776static ssize_t 1777musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1778{ 1779 struct musb *musb = dev_to_musb(dev); 1780 unsigned long flags; 1781 unsigned long val; 1782 int vbus; 1783 1784 spin_lock_irqsave(&musb->lock, flags); 1785 val = musb->a_wait_bcon; 1786 /* FIXME get_vbus_status() is normally #defined as false... 1787 * and is effectively TUSB-specific. 1788 */ 1789 vbus = musb_platform_get_vbus_status(musb); 1790 spin_unlock_irqrestore(&musb->lock, flags); 1791 1792 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1793 vbus ? "on" : "off", val); 1794} 1795static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1796 1797#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1798 1799/* Gadget drivers can't know that a host is connected so they might want 1800 * to start SRP, but users can. This allows userspace to trigger SRP. 1801 */ 1802static ssize_t 1803musb_srp_store(struct device *dev, struct device_attribute *attr, 1804 const char *buf, size_t n) 1805{ 1806 struct musb *musb = dev_to_musb(dev); 1807 unsigned short srp; 1808 1809 if (sscanf(buf, "%hu", &srp) != 1 1810 || (srp != 1)) { 1811 dev_err(dev, "SRP: Value must be 1\n"); 1812 return -EINVAL; 1813 } 1814 1815 if (srp == 1) 1816 musb_g_wakeup(musb); 1817 1818 return n; 1819} 1820static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1821 1822#endif /* CONFIG_USB_GADGET_MUSB_HDRC */ 1823 1824static struct attribute *musb_attributes[] = { 1825 &dev_attr_mode.attr, 1826 &dev_attr_vbus.attr, 1827#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1828 &dev_attr_srp.attr, 1829#endif 1830 NULL 1831}; 1832 1833static const struct attribute_group musb_attr_group = { 1834 .attrs = musb_attributes, 1835}; 1836 1837#endif /* sysfs */ 1838 1839/* Only used to provide driver mode change events */ 1840static void musb_irq_work(struct work_struct *data) 1841{ 1842 struct musb *musb = container_of(data, struct musb, irq_work); 1843 static int old_state; 1844 1845 if (musb->xceiv->state != old_state) { 1846 old_state = musb->xceiv->state; 1847 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1848 } 1849} 1850 1851/* -------------------------------------------------------------------------- 1852 * Init support 1853 */ 1854 1855static struct musb *__init 1856allocate_instance(struct device *dev, 1857 struct musb_hdrc_config *config, void __iomem *mbase) 1858{ 1859 struct musb *musb; 1860 struct musb_hw_ep *ep; 1861 int epnum; 1862#ifdef CONFIG_USB_MUSB_HDRC_HCD 1863 struct usb_hcd *hcd; 1864 1865 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1866 if (!hcd) 1867 return NULL; 1868 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1869 1870 musb = hcd_to_musb(hcd); 1871 INIT_LIST_HEAD(&musb->control); 1872 INIT_LIST_HEAD(&musb->in_bulk); 1873 INIT_LIST_HEAD(&musb->out_bulk); 1874 1875 hcd->uses_new_polling = 1; 1876 1877 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1878 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1879#else 1880 musb = kzalloc(sizeof *musb, GFP_KERNEL); 1881 if (!musb) 1882 return NULL; 1883 dev_set_drvdata(dev, musb); 1884 1885#endif 1886 1887 musb->mregs = mbase; 1888 musb->ctrl_base = mbase; 1889 musb->nIrq = -ENODEV; 1890 musb->config = config; 1891 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1892 for (epnum = 0, ep = musb->endpoints; 1893 epnum < musb->config->num_eps; 1894 epnum++, ep++) { 1895 ep->musb = musb; 1896 ep->epnum = epnum; 1897 } 1898 1899 musb->controller = dev; 1900 1901 return musb; 1902} 1903 1904static void musb_free(struct musb *musb) 1905{ 1906 /* this has multiple entry modes. it handles fault cleanup after 1907 * probe(), where things may be partially set up, as well as rmmod 1908 * cleanup after everything's been de-activated. 1909 */ 1910 1911#ifdef CONFIG_SYSFS 1912 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); 1913#endif 1914 1915#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1916 musb_gadget_cleanup(musb); 1917#endif 1918 1919 if (musb->nIrq >= 0) { 1920 if (musb->irq_wake) 1921 disable_irq_wake(musb->nIrq); 1922 free_irq(musb->nIrq, musb); 1923 } 1924 if (is_dma_capable() && musb->dma_controller) { 1925 struct dma_controller *c = musb->dma_controller; 1926 1927 (void) c->stop(c); 1928 dma_controller_destroy(c); 1929 } 1930 1931#ifdef CONFIG_USB_MUSB_HDRC_HCD 1932 usb_put_hcd(musb_to_hcd(musb)); 1933#else 1934 kfree(musb); 1935#endif 1936} 1937 1938/* 1939 * Perform generic per-controller initialization. 1940 * 1941 * @pDevice: the controller (already clocked, etc) 1942 * @nIrq: irq 1943 * @mregs: virtual address of controller registers, 1944 * not yet corrected for platform-specific offsets 1945 */ 1946static int __init 1947musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1948{ 1949 int status; 1950 struct musb *musb; 1951 struct musb_hdrc_platform_data *plat = dev->platform_data; 1952 1953 /* The driver might handle more features than the board; OK. 1954 * Fail when the board needs a feature that's not enabled. 1955 */ 1956 if (!plat) { 1957 dev_dbg(dev, "no platform_data?\n"); 1958 status = -ENODEV; 1959 goto fail0; 1960 } 1961 1962 switch (plat->mode) { 1963 case MUSB_HOST: 1964#ifdef CONFIG_USB_MUSB_HDRC_HCD 1965 break; 1966#else 1967 goto bad_config; 1968#endif 1969 case MUSB_PERIPHERAL: 1970#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1971 break; 1972#else 1973 goto bad_config; 1974#endif 1975 case MUSB_OTG: 1976#ifdef CONFIG_USB_MUSB_OTG 1977 break; 1978#else 1979bad_config: 1980#endif 1981 default: 1982 dev_err(dev, "incompatible Kconfig role setting\n"); 1983 status = -EINVAL; 1984 goto fail0; 1985 } 1986 1987 /* allocate */ 1988 musb = allocate_instance(dev, plat->config, ctrl); 1989 if (!musb) { 1990 status = -ENOMEM; 1991 goto fail0; 1992 } 1993 1994 spin_lock_init(&musb->lock); 1995 musb->board_mode = plat->mode; 1996 musb->board_set_power = plat->set_power; 1997 musb->set_clock = plat->set_clock; 1998 musb->min_power = plat->min_power; 1999 musb->ops = plat->platform_ops; 2000 2001 /* Clock usage is chip-specific ... functional clock (DaVinci, 2002 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core 2003 * code does is make sure a clock handle is available; platform 2004 * code manages it during start/stop and suspend/resume. 2005 */ 2006 if (plat->clock) { 2007 musb->clock = clk_get(dev, plat->clock); 2008 if (IS_ERR(musb->clock)) { 2009 status = PTR_ERR(musb->clock); 2010 musb->clock = NULL; 2011 goto fail1; 2012 } 2013 } 2014 2015 /* The musb_platform_init() call: 2016 * - adjusts musb->mregs and musb->isr if needed, 2017 * - may initialize an integrated tranceiver 2018 * - initializes musb->xceiv, usually by otg_get_transceiver() 2019 * - activates clocks. 2020 * - stops powering VBUS 2021 * - assigns musb->board_set_vbus if host mode is enabled 2022 * 2023 * There are various transciever configurations. Blackfin, 2024 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 2025 * external/discrete ones in various flavors (twl4030 family, 2026 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 2027 */ 2028 musb->isr = generic_interrupt; 2029 status = musb_platform_init(musb); 2030 if (status < 0) 2031 goto fail2; 2032 2033 if (!musb->isr) { 2034 status = -ENODEV; 2035 goto fail3; 2036 } 2037 2038 if (!musb->xceiv->io_ops) { 2039 musb->xceiv->io_priv = musb->mregs; 2040 musb->xceiv->io_ops = &musb_ulpi_access; 2041 } 2042 2043#ifndef CONFIG_MUSB_PIO_ONLY 2044 if (use_dma && dev->dma_mask) { 2045 struct dma_controller *c; 2046 2047 c = dma_controller_create(musb, musb->mregs); 2048 musb->dma_controller = c; 2049 if (c) 2050 (void) c->start(c); 2051 } 2052#endif 2053 /* ideally this would be abstracted in platform setup */ 2054 if (!is_dma_capable() || !musb->dma_controller) 2055 dev->dma_mask = NULL; 2056 2057 /* be sure interrupts are disabled before connecting ISR */ 2058 musb_platform_disable(musb); 2059 musb_generic_disable(musb); 2060 2061 /* setup musb parts of the core (especially endpoints) */ 2062 status = musb_core_init(plat->config->multipoint 2063 ? MUSB_CONTROLLER_MHDRC 2064 : MUSB_CONTROLLER_HDRC, musb); 2065 if (status < 0) 2066 goto fail3; 2067 2068#ifdef CONFIG_USB_MUSB_OTG 2069 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 2070#endif 2071 2072 /* Init IRQ workqueue before request_irq */ 2073 INIT_WORK(&musb->irq_work, musb_irq_work); 2074 2075 /* attach to the IRQ */ 2076 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 2077 dev_err(dev, "request_irq %d failed!\n", nIrq); 2078 status = -ENODEV; 2079 goto fail3; 2080 } 2081 musb->nIrq = nIrq; 2082/* FIXME this handles wakeup irqs wrong */ 2083 if (enable_irq_wake(nIrq) == 0) { 2084 musb->irq_wake = 1; 2085 device_init_wakeup(dev, 1); 2086 } else { 2087 musb->irq_wake = 0; 2088 } 2089 2090 /* host side needs more setup */ 2091 if (is_host_enabled(musb)) { 2092 struct usb_hcd *hcd = musb_to_hcd(musb); 2093 2094 otg_set_host(musb->xceiv, &hcd->self); 2095 2096 if (is_otg_enabled(musb)) 2097 hcd->self.otg_port = 1; 2098 musb->xceiv->host = &hcd->self; 2099 hcd->power_budget = 2 * (plat->power ? : 250); 2100 2101 /* program PHY to use external vBus if required */ 2102 if (plat->extvbus) { 2103 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); 2104 busctl |= MUSB_ULPI_USE_EXTVBUS; 2105 musb_write_ulpi_buscontrol(musb->mregs, busctl); 2106 } 2107 } 2108 2109 /* For the host-only role, we can activate right away. 2110 * (We expect the ID pin to be forcibly grounded!!) 2111 * Otherwise, wait till the gadget driver hooks up. 2112 */ 2113 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2114 MUSB_HST_MODE(musb); 2115 musb->xceiv->default_a = 1; 2116 musb->xceiv->state = OTG_STATE_A_IDLE; 2117 2118 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 2119 2120 DBG(1, "%s mode, status %d, devctl %02x %c\n", 2121 "HOST", status, 2122 musb_readb(musb->mregs, MUSB_DEVCTL), 2123 (musb_readb(musb->mregs, MUSB_DEVCTL) 2124 & MUSB_DEVCTL_BDEVICE 2125 ? 'B' : 'A')); 2126 2127 } else /* peripheral is enabled */ { 2128 MUSB_DEV_MODE(musb); 2129 musb->xceiv->default_a = 0; 2130 musb->xceiv->state = OTG_STATE_B_IDLE; 2131 2132 status = musb_gadget_setup(musb); 2133 2134 DBG(1, "%s mode, status %d, dev%02x\n", 2135 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2136 status, 2137 musb_readb(musb->mregs, MUSB_DEVCTL)); 2138 2139 } 2140 if (status < 0) 2141 goto fail3; 2142 2143 status = musb_init_debugfs(musb); 2144 if (status < 0) 2145 goto fail4; 2146 2147#ifdef CONFIG_SYSFS 2148 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); 2149 if (status) 2150 goto fail5; 2151#endif 2152 2153 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", 2154 ({char *s; 2155 switch (musb->board_mode) { 2156 case MUSB_HOST: s = "Host"; break; 2157 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2158 default: s = "OTG"; break; 2159 }; s; }), 2160 ctrl, 2161 (is_dma_capable() && musb->dma_controller) 2162 ? "DMA" : "PIO", 2163 musb->nIrq); 2164 2165 return 0; 2166 2167fail5: 2168 musb_exit_debugfs(musb); 2169 2170fail4: 2171 if (!is_otg_enabled(musb) && is_host_enabled(musb)) 2172 usb_remove_hcd(musb_to_hcd(musb)); 2173 else 2174 musb_gadget_cleanup(musb); 2175 2176fail3: 2177 if (musb->irq_wake) 2178 device_init_wakeup(dev, 0); 2179 musb_platform_exit(musb); 2180 2181fail2: 2182 if (musb->clock) 2183 clk_put(musb->clock); 2184 2185fail1: 2186 dev_err(musb->controller, 2187 "musb_init_controller failed with status %d\n", status); 2188 2189 musb_free(musb); 2190 2191fail0: 2192 2193 return status; 2194 2195} 2196 2197/*-------------------------------------------------------------------------*/ 2198 2199/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2200 * bridge to a platform device; this driver then suffices. 2201 */ 2202 2203#ifndef CONFIG_MUSB_PIO_ONLY 2204static u64 *orig_dma_mask; 2205#endif 2206 2207static int __init musb_probe(struct platform_device *pdev) 2208{ 2209 struct device *dev = &pdev->dev; 2210 int irq = platform_get_irq_byname(pdev, "mc"); 2211 int status; 2212 struct resource *iomem; 2213 void __iomem *base; 2214 2215 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2216 if (!iomem || irq == 0) 2217 return -ENODEV; 2218 2219 base = ioremap(iomem->start, resource_size(iomem)); 2220 if (!base) { 2221 dev_err(dev, "ioremap failed\n"); 2222 return -ENOMEM; 2223 } 2224 2225#ifndef CONFIG_MUSB_PIO_ONLY 2226 /* clobbered by use_dma=n */ 2227 orig_dma_mask = dev->dma_mask; 2228#endif 2229 status = musb_init_controller(dev, irq, base); 2230 if (status < 0) 2231 iounmap(base); 2232 2233 return status; 2234} 2235 2236static int __exit musb_remove(struct platform_device *pdev) 2237{ 2238 struct musb *musb = dev_to_musb(&pdev->dev); 2239 void __iomem *ctrl_base = musb->ctrl_base; 2240 2241 /* this gets called on rmmod. 2242 * - Host mode: host may still be active 2243 * - Peripheral mode: peripheral is deactivated (or never-activated) 2244 * - OTG mode: both roles are deactivated (or never-activated) 2245 */ 2246 musb_exit_debugfs(musb); 2247 musb_shutdown(pdev); 2248#ifdef CONFIG_USB_MUSB_HDRC_HCD 2249 if (musb->board_mode == MUSB_HOST) 2250 usb_remove_hcd(musb_to_hcd(musb)); 2251#endif 2252 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2253 musb_platform_exit(musb); 2254 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 2255 2256 musb_free(musb); 2257 iounmap(ctrl_base); 2258 device_init_wakeup(&pdev->dev, 0); 2259#ifndef CONFIG_MUSB_PIO_ONLY 2260 pdev->dev.dma_mask = orig_dma_mask; 2261#endif 2262 return 0; 2263} 2264 2265#ifdef CONFIG_PM 2266 2267void musb_save_context(struct musb *musb) 2268{ 2269 int i; 2270 void __iomem *musb_base = musb->mregs; 2271 void __iomem *epio; 2272 2273 if (is_host_enabled(musb)) { 2274 musb->context.frame = musb_readw(musb_base, MUSB_FRAME); 2275 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); 2276 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); 2277 } 2278 musb->context.power = musb_readb(musb_base, MUSB_POWER); 2279 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); 2280 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); 2281 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); 2282 musb->context.index = musb_readb(musb_base, MUSB_INDEX); 2283 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); 2284 2285 for (i = 0; i < musb->config->num_eps; ++i) { 2286 epio = musb->endpoints[i].regs; 2287 musb->context.index_regs[i].txmaxp = 2288 musb_readw(epio, MUSB_TXMAXP); 2289 musb->context.index_regs[i].txcsr = 2290 musb_readw(epio, MUSB_TXCSR); 2291 musb->context.index_regs[i].rxmaxp = 2292 musb_readw(epio, MUSB_RXMAXP); 2293 musb->context.index_regs[i].rxcsr = 2294 musb_readw(epio, MUSB_RXCSR); 2295 2296 if (musb->dyn_fifo) { 2297 musb->context.index_regs[i].txfifoadd = 2298 musb_read_txfifoadd(musb_base); 2299 musb->context.index_regs[i].rxfifoadd = 2300 musb_read_rxfifoadd(musb_base); 2301 musb->context.index_regs[i].txfifosz = 2302 musb_read_txfifosz(musb_base); 2303 musb->context.index_regs[i].rxfifosz = 2304 musb_read_rxfifosz(musb_base); 2305 } 2306 if (is_host_enabled(musb)) { 2307 musb->context.index_regs[i].txtype = 2308 musb_readb(epio, MUSB_TXTYPE); 2309 musb->context.index_regs[i].txinterval = 2310 musb_readb(epio, MUSB_TXINTERVAL); 2311 musb->context.index_regs[i].rxtype = 2312 musb_readb(epio, MUSB_RXTYPE); 2313 musb->context.index_regs[i].rxinterval = 2314 musb_readb(epio, MUSB_RXINTERVAL); 2315 2316 musb->context.index_regs[i].txfunaddr = 2317 musb_read_txfunaddr(musb_base, i); 2318 musb->context.index_regs[i].txhubaddr = 2319 musb_read_txhubaddr(musb_base, i); 2320 musb->context.index_regs[i].txhubport = 2321 musb_read_txhubport(musb_base, i); 2322 2323 musb->context.index_regs[i].rxfunaddr = 2324 musb_read_rxfunaddr(musb_base, i); 2325 musb->context.index_regs[i].rxhubaddr = 2326 musb_read_rxhubaddr(musb_base, i); 2327 musb->context.index_regs[i].rxhubport = 2328 musb_read_rxhubport(musb_base, i); 2329 } 2330 } 2331 2332 musb_platform_save_context(musb, &musb->context); 2333} 2334 2335void musb_restore_context(struct musb *musb) 2336{ 2337 int i; 2338 void __iomem *musb_base = musb->mregs; 2339 void __iomem *ep_target_regs; 2340 void __iomem *epio; 2341 2342 musb_platform_restore_context(musb, &musb->context); 2343 2344 if (is_host_enabled(musb)) { 2345 musb_writew(musb_base, MUSB_FRAME, musb->context.frame); 2346 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); 2347 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); 2348 } 2349 musb_writeb(musb_base, MUSB_POWER, musb->context.power); 2350 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); 2351 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); 2352 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); 2353 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); 2354 2355 for (i = 0; i < musb->config->num_eps; ++i) { 2356 epio = musb->endpoints[i].regs; 2357 musb_writew(epio, MUSB_TXMAXP, 2358 musb->context.index_regs[i].txmaxp); 2359 musb_writew(epio, MUSB_TXCSR, 2360 musb->context.index_regs[i].txcsr); 2361 musb_writew(epio, MUSB_RXMAXP, 2362 musb->context.index_regs[i].rxmaxp); 2363 musb_writew(epio, MUSB_RXCSR, 2364 musb->context.index_regs[i].rxcsr); 2365 2366 if (musb->dyn_fifo) { 2367 musb_write_txfifosz(musb_base, 2368 musb->context.index_regs[i].txfifosz); 2369 musb_write_rxfifosz(musb_base, 2370 musb->context.index_regs[i].rxfifosz); 2371 musb_write_txfifoadd(musb_base, 2372 musb->context.index_regs[i].txfifoadd); 2373 musb_write_rxfifoadd(musb_base, 2374 musb->context.index_regs[i].rxfifoadd); 2375 } 2376 2377 if (is_host_enabled(musb)) { 2378 musb_writeb(epio, MUSB_TXTYPE, 2379 musb->context.index_regs[i].txtype); 2380 musb_writeb(epio, MUSB_TXINTERVAL, 2381 musb->context.index_regs[i].txinterval); 2382 musb_writeb(epio, MUSB_RXTYPE, 2383 musb->context.index_regs[i].rxtype); 2384 musb_writeb(epio, MUSB_RXINTERVAL, 2385 2386 musb->context.index_regs[i].rxinterval); 2387 musb_write_txfunaddr(musb_base, i, 2388 musb->context.index_regs[i].txfunaddr); 2389 musb_write_txhubaddr(musb_base, i, 2390 musb->context.index_regs[i].txhubaddr); 2391 musb_write_txhubport(musb_base, i, 2392 musb->context.index_regs[i].txhubport); 2393 2394 ep_target_regs = 2395 musb_read_target_reg_base(i, musb_base); 2396 2397 musb_write_rxfunaddr(ep_target_regs, 2398 musb->context.index_regs[i].rxfunaddr); 2399 musb_write_rxhubaddr(ep_target_regs, 2400 musb->context.index_regs[i].rxhubaddr); 2401 musb_write_rxhubport(ep_target_regs, 2402 musb->context.index_regs[i].rxhubport); 2403 } 2404 } 2405} 2406 2407static int musb_suspend(struct device *dev) 2408{ 2409 struct platform_device *pdev = to_platform_device(dev); 2410 unsigned long flags; 2411 struct musb *musb = dev_to_musb(&pdev->dev); 2412 2413 if (!musb->clock) 2414 return 0; 2415 2416 spin_lock_irqsave(&musb->lock, flags); 2417 2418 if (is_peripheral_active(musb)) { 2419 /* FIXME force disconnect unless we know USB will wake 2420 * the system up quickly enough to respond ... 2421 */ 2422 } else if (is_host_active(musb)) { 2423 /* we know all the children are suspended; sometimes 2424 * they will even be wakeup-enabled. 2425 */ 2426 } 2427 2428 musb_save_context(musb); 2429 2430 if (musb->set_clock) 2431 musb->set_clock(musb->clock, 0); 2432 else 2433 clk_disable(musb->clock); 2434 spin_unlock_irqrestore(&musb->lock, flags); 2435 return 0; 2436} 2437 2438static int musb_resume_noirq(struct device *dev) 2439{ 2440 struct platform_device *pdev = to_platform_device(dev); 2441 struct musb *musb = dev_to_musb(&pdev->dev); 2442 2443 if (!musb->clock) 2444 return 0; 2445 2446 if (musb->set_clock) 2447 musb->set_clock(musb->clock, 1); 2448 else 2449 clk_enable(musb->clock); 2450 2451 musb_restore_context(musb); 2452 2453 /* for static cmos like DaVinci, register values were preserved 2454 * unless for some reason the whole soc powered down or the USB 2455 * module got reset through the PSC (vs just being disabled). 2456 */ 2457 return 0; 2458} 2459 2460static const struct dev_pm_ops musb_dev_pm_ops = { 2461 .suspend = musb_suspend, 2462 .resume_noirq = musb_resume_noirq, 2463}; 2464 2465#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) 2466#else 2467#define MUSB_DEV_PM_OPS NULL 2468#endif 2469 2470static struct platform_driver musb_driver = { 2471 .driver = { 2472 .name = (char *)musb_driver_name, 2473 .bus = &platform_bus_type, 2474 .owner = THIS_MODULE, 2475 .pm = MUSB_DEV_PM_OPS, 2476 }, 2477 .remove = __exit_p(musb_remove), 2478 .shutdown = musb_shutdown, 2479}; 2480 2481/*-------------------------------------------------------------------------*/ 2482 2483static int __init musb_init(void) 2484{ 2485#ifdef CONFIG_USB_MUSB_HDRC_HCD 2486 if (usb_disabled()) 2487 return 0; 2488#endif 2489 2490 pr_info("%s: version " MUSB_VERSION ", " 2491#ifdef CONFIG_MUSB_PIO_ONLY 2492 "pio" 2493#elif defined(CONFIG_USB_TI_CPPI_DMA) 2494 "cppi-dma" 2495#elif defined(CONFIG_USB_INVENTRA_DMA) 2496 "musb-dma" 2497#elif defined(CONFIG_USB_TUSB_OMAP_DMA) 2498 "tusb-omap-dma" 2499#else 2500 "?dma?" 2501#endif 2502 ", " 2503#ifdef CONFIG_USB_MUSB_OTG 2504 "otg (peripheral+host)" 2505#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 2506 "peripheral" 2507#elif defined(CONFIG_USB_MUSB_HDRC_HCD) 2508 "host" 2509#endif 2510 ", debug=%d\n", 2511 musb_driver_name, musb_debug); 2512 return platform_driver_probe(&musb_driver, musb_probe); 2513} 2514 2515/* make us init after usbcore and i2c (transceivers, regulators, etc) 2516 * and before usb gadget and host-side drivers start to register 2517 */ 2518fs_initcall(musb_init); 2519 2520static void __exit musb_cleanup(void) 2521{ 2522 platform_driver_unregister(&musb_driver); 2523} 2524module_exit(musb_cleanup); 2525