musb_core.c revision f7f9d63eac12b345d6243d1d608b7944a05be921
1/* 2 * MUSB OTG driver core code 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35/* 36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux. 37 * 38 * This consists of a Host Controller Driver (HCD) and a peripheral 39 * controller driver implementing the "Gadget" API; OTG support is 40 * in the works. These are normal Linux-USB controller drivers which 41 * use IRQs and have no dedicated thread. 42 * 43 * This version of the driver has only been used with products from 44 * Texas Instruments. Those products integrate the Inventra logic 45 * with other DMA, IRQ, and bus modules, as well as other logic that 46 * needs to be reflected in this driver. 47 * 48 * 49 * NOTE: the original Mentor code here was pretty much a collection 50 * of mechanisms that don't seem to have been fully integrated/working 51 * for *any* Linux kernel version. This version aims at Linux 2.6.now, 52 * Key open issues include: 53 * 54 * - Lack of host-side transaction scheduling, for all transfer types. 55 * The hardware doesn't do it; instead, software must. 56 * 57 * This is not an issue for OTG devices that don't support external 58 * hubs, but for more "normal" USB hosts it's a user issue that the 59 * "multipoint" support doesn't scale in the expected ways. That 60 * includes DaVinci EVM in a common non-OTG mode. 61 * 62 * * Control and bulk use dedicated endpoints, and there's as 63 * yet no mechanism to either (a) reclaim the hardware when 64 * peripherals are NAKing, which gets complicated with bulk 65 * endpoints, or (b) use more than a single bulk endpoint in 66 * each direction. 67 * 68 * RESULT: one device may be perceived as blocking another one. 69 * 70 * * Interrupt and isochronous will dynamically allocate endpoint 71 * hardware, but (a) there's no record keeping for bandwidth; 72 * (b) in the common case that few endpoints are available, there 73 * is no mechanism to reuse endpoints to talk to multiple devices. 74 * 75 * RESULT: At one extreme, bandwidth can be overcommitted in 76 * some hardware configurations, no faults will be reported. 77 * At the other extreme, the bandwidth capabilities which do 78 * exist tend to be severely undercommitted. You can't yet hook 79 * up both a keyboard and a mouse to an external USB hub. 80 */ 81 82/* 83 * This gets many kinds of configuration information: 84 * - Kconfig for everything user-configurable 85 * - platform_device for addressing, irq, and platform_data 86 * - platform_data is mostly for board-specific informarion 87 * (plus recentrly, SOC or family details) 88 * 89 * Most of the conditional compilation will (someday) vanish. 90 */ 91 92#include <linux/module.h> 93#include <linux/kernel.h> 94#include <linux/sched.h> 95#include <linux/slab.h> 96#include <linux/init.h> 97#include <linux/list.h> 98#include <linux/kobject.h> 99#include <linux/platform_device.h> 100#include <linux/io.h> 101 102#ifdef CONFIG_ARM 103#include <mach/hardware.h> 104#include <mach/memory.h> 105#include <asm/mach-types.h> 106#endif 107 108#include "musb_core.h" 109 110 111#ifdef CONFIG_ARCH_DAVINCI 112#include "davinci.h" 113#endif 114 115#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) 116 117 118unsigned musb_debug; 119module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR); 120MODULE_PARM_DESC(debug, "Debug message level. Default = 0"); 121 122#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" 123#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" 124 125#define MUSB_VERSION "6.0" 126 127#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION 128 129#define MUSB_DRIVER_NAME "musb_hdrc" 130const char musb_driver_name[] = MUSB_DRIVER_NAME; 131 132MODULE_DESCRIPTION(DRIVER_INFO); 133MODULE_AUTHOR(DRIVER_AUTHOR); 134MODULE_LICENSE("GPL"); 135MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); 136 137 138/*-------------------------------------------------------------------------*/ 139 140static inline struct musb *dev_to_musb(struct device *dev) 141{ 142#ifdef CONFIG_USB_MUSB_HDRC_HCD 143 /* usbcore insists dev->driver_data is a "struct hcd *" */ 144 return hcd_to_musb(dev_get_drvdata(dev)); 145#else 146 return dev_get_drvdata(dev); 147#endif 148} 149 150/*-------------------------------------------------------------------------*/ 151 152#if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN) 153 154/* 155 * Load an endpoint's FIFO 156 */ 157void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) 158{ 159 void __iomem *fifo = hw_ep->fifo; 160 161 prefetch((u8 *)src); 162 163 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 164 'T', hw_ep->epnum, fifo, len, src); 165 166 /* we can't assume unaligned reads work */ 167 if (likely((0x01 & (unsigned long) src) == 0)) { 168 u16 index = 0; 169 170 /* best case is 32bit-aligned source address */ 171 if ((0x02 & (unsigned long) src) == 0) { 172 if (len >= 4) { 173 writesl(fifo, src + index, len >> 2); 174 index += len & ~0x03; 175 } 176 if (len & 0x02) { 177 musb_writew(fifo, 0, *(u16 *)&src[index]); 178 index += 2; 179 } 180 } else { 181 if (len >= 2) { 182 writesw(fifo, src + index, len >> 1); 183 index += len & ~0x01; 184 } 185 } 186 if (len & 0x01) 187 musb_writeb(fifo, 0, src[index]); 188 } else { 189 /* byte aligned */ 190 writesb(fifo, src, len); 191 } 192} 193 194/* 195 * Unload an endpoint's FIFO 196 */ 197void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 198{ 199 void __iomem *fifo = hw_ep->fifo; 200 201 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 202 'R', hw_ep->epnum, fifo, len, dst); 203 204 /* we can't assume unaligned writes work */ 205 if (likely((0x01 & (unsigned long) dst) == 0)) { 206 u16 index = 0; 207 208 /* best case is 32bit-aligned destination address */ 209 if ((0x02 & (unsigned long) dst) == 0) { 210 if (len >= 4) { 211 readsl(fifo, dst, len >> 2); 212 index = len & ~0x03; 213 } 214 if (len & 0x02) { 215 *(u16 *)&dst[index] = musb_readw(fifo, 0); 216 index += 2; 217 } 218 } else { 219 if (len >= 2) { 220 readsw(fifo, dst, len >> 1); 221 index = len & ~0x01; 222 } 223 } 224 if (len & 0x01) 225 dst[index] = musb_readb(fifo, 0); 226 } else { 227 /* byte aligned */ 228 readsb(fifo, dst, len); 229 } 230} 231 232#endif /* normal PIO */ 233 234 235/*-------------------------------------------------------------------------*/ 236 237/* for high speed test mode; see USB 2.0 spec 7.1.20 */ 238static const u8 musb_test_packet[53] = { 239 /* implicit SYNC then DATA0 to start */ 240 241 /* JKJKJKJK x9 */ 242 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 243 /* JJKKJJKK x8 */ 244 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 245 /* JJJJKKKK x8 */ 246 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 247 /* JJJJJJJKKKKKKK x8 */ 248 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 249 /* JJJJJJJK x8 */ 250 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 251 /* JKKKKKKK x10, JK */ 252 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e 253 254 /* implicit CRC16 then EOP to end */ 255}; 256 257void musb_load_testpacket(struct musb *musb) 258{ 259 void __iomem *regs = musb->endpoints[0].regs; 260 261 musb_ep_select(musb->mregs, 0); 262 musb_write_fifo(musb->control_ep, 263 sizeof(musb_test_packet), musb_test_packet); 264 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); 265} 266 267/*-------------------------------------------------------------------------*/ 268 269const char *otg_state_string(struct musb *musb) 270{ 271 switch (musb->xceiv->state) { 272 case OTG_STATE_A_IDLE: return "a_idle"; 273 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; 274 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; 275 case OTG_STATE_A_HOST: return "a_host"; 276 case OTG_STATE_A_SUSPEND: return "a_suspend"; 277 case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; 278 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; 279 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; 280 case OTG_STATE_B_IDLE: return "b_idle"; 281 case OTG_STATE_B_SRP_INIT: return "b_srp_init"; 282 case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; 283 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; 284 case OTG_STATE_B_HOST: return "b_host"; 285 default: return "UNDEFINED"; 286 } 287} 288 289#ifdef CONFIG_USB_MUSB_OTG 290 291/* 292 * Handles OTG hnp timeouts, such as b_ase0_brst 293 */ 294void musb_otg_timer_func(unsigned long data) 295{ 296 struct musb *musb = (struct musb *)data; 297 unsigned long flags; 298 299 spin_lock_irqsave(&musb->lock, flags); 300 switch (musb->xceiv->state) { 301 case OTG_STATE_B_WAIT_ACON: 302 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); 303 musb_g_disconnect(musb); 304 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 305 musb->is_active = 0; 306 break; 307 case OTG_STATE_A_WAIT_BCON: 308 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n"); 309 musb_hnp_stop(musb); 310 break; 311 default: 312 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb)); 313 } 314 musb->ignore_disconnect = 0; 315 spin_unlock_irqrestore(&musb->lock, flags); 316} 317 318/* 319 * Stops the HNP transition. Caller must take care of locking. 320 */ 321void musb_hnp_stop(struct musb *musb) 322{ 323 struct usb_hcd *hcd = musb_to_hcd(musb); 324 void __iomem *mbase = musb->mregs; 325 u8 reg; 326 327 switch (musb->xceiv->state) { 328 case OTG_STATE_A_PERIPHERAL: 329 case OTG_STATE_A_WAIT_VFALL: 330 case OTG_STATE_A_WAIT_BCON: 331 DBG(1, "HNP: Switching back to A-host\n"); 332 musb_g_disconnect(musb); 333 musb->xceiv->state = OTG_STATE_A_IDLE; 334 MUSB_HST_MODE(musb); 335 musb->is_active = 0; 336 break; 337 case OTG_STATE_B_HOST: 338 DBG(1, "HNP: Disabling HR\n"); 339 hcd->self.is_b_host = 0; 340 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 341 MUSB_DEV_MODE(musb); 342 reg = musb_readb(mbase, MUSB_POWER); 343 reg |= MUSB_POWER_SUSPENDM; 344 musb_writeb(mbase, MUSB_POWER, reg); 345 /* REVISIT: Start SESSION_REQUEST here? */ 346 break; 347 default: 348 DBG(1, "HNP: Stopping in unknown state %s\n", 349 otg_state_string(musb)); 350 } 351 352 /* 353 * When returning to A state after HNP, avoid hub_port_rebounce(), 354 * which cause occasional OPT A "Did not receive reset after connect" 355 * errors. 356 */ 357 musb->port1_status &= 358 ~(1 << USB_PORT_FEAT_C_CONNECTION); 359} 360 361#endif 362 363/* 364 * Interrupt Service Routine to record USB "global" interrupts. 365 * Since these do not happen often and signify things of 366 * paramount importance, it seems OK to check them individually; 367 * the order of the tests is specified in the manual 368 * 369 * @param musb instance pointer 370 * @param int_usb register contents 371 * @param devctl 372 * @param power 373 */ 374 375#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \ 376 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \ 377 | MUSB_INTR_RESET) 378 379static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, 380 u8 devctl, u8 power) 381{ 382 irqreturn_t handled = IRQ_NONE; 383 void __iomem *mbase = musb->mregs; 384 385 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, 386 int_usb); 387 388 /* in host mode, the peripheral may issue remote wakeup. 389 * in peripheral mode, the host may resume the link. 390 * spurious RESUME irqs happen too, paired with SUSPEND. 391 */ 392 if (int_usb & MUSB_INTR_RESUME) { 393 handled = IRQ_HANDLED; 394 DBG(3, "RESUME (%s)\n", otg_state_string(musb)); 395 396 if (devctl & MUSB_DEVCTL_HM) { 397#ifdef CONFIG_USB_MUSB_HDRC_HCD 398 switch (musb->xceiv->state) { 399 case OTG_STATE_A_SUSPEND: 400 /* remote wakeup? later, GetPortStatus 401 * will stop RESUME signaling 402 */ 403 404 if (power & MUSB_POWER_SUSPENDM) { 405 /* spurious */ 406 musb->int_usb &= ~MUSB_INTR_SUSPEND; 407 DBG(2, "Spurious SUSPENDM\n"); 408 break; 409 } 410 411 power &= ~MUSB_POWER_SUSPENDM; 412 musb_writeb(mbase, MUSB_POWER, 413 power | MUSB_POWER_RESUME); 414 415 musb->port1_status |= 416 (USB_PORT_STAT_C_SUSPEND << 16) 417 | MUSB_PORT_STAT_RESUME; 418 musb->rh_timer = jiffies 419 + msecs_to_jiffies(20); 420 421 musb->xceiv->state = OTG_STATE_A_HOST; 422 musb->is_active = 1; 423 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 424 break; 425 case OTG_STATE_B_WAIT_ACON: 426 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 427 musb->is_active = 1; 428 MUSB_DEV_MODE(musb); 429 break; 430 default: 431 WARNING("bogus %s RESUME (%s)\n", 432 "host", 433 otg_state_string(musb)); 434 } 435#endif 436 } else { 437 switch (musb->xceiv->state) { 438#ifdef CONFIG_USB_MUSB_HDRC_HCD 439 case OTG_STATE_A_SUSPEND: 440 /* possibly DISCONNECT is upcoming */ 441 musb->xceiv->state = OTG_STATE_A_HOST; 442 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 443 break; 444#endif 445#ifdef CONFIG_USB_GADGET_MUSB_HDRC 446 case OTG_STATE_B_WAIT_ACON: 447 case OTG_STATE_B_PERIPHERAL: 448 /* disconnect while suspended? we may 449 * not get a disconnect irq... 450 */ 451 if ((devctl & MUSB_DEVCTL_VBUS) 452 != (3 << MUSB_DEVCTL_VBUS_SHIFT) 453 ) { 454 musb->int_usb |= MUSB_INTR_DISCONNECT; 455 musb->int_usb &= ~MUSB_INTR_SUSPEND; 456 break; 457 } 458 musb_g_resume(musb); 459 break; 460 case OTG_STATE_B_IDLE: 461 musb->int_usb &= ~MUSB_INTR_SUSPEND; 462 break; 463#endif 464 default: 465 WARNING("bogus %s RESUME (%s)\n", 466 "peripheral", 467 otg_state_string(musb)); 468 } 469 } 470 } 471 472#ifdef CONFIG_USB_MUSB_HDRC_HCD 473 /* see manual for the order of the tests */ 474 if (int_usb & MUSB_INTR_SESSREQ) { 475 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); 476 477 /* IRQ arrives from ID pin sense or (later, if VBUS power 478 * is removed) SRP. responses are time critical: 479 * - turn on VBUS (with silicon-specific mechanism) 480 * - go through A_WAIT_VRISE 481 * - ... to A_WAIT_BCON. 482 * a_wait_vrise_tmout triggers VBUS_ERROR transitions 483 */ 484 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 485 musb->ep0_stage = MUSB_EP0_START; 486 musb->xceiv->state = OTG_STATE_A_IDLE; 487 MUSB_HST_MODE(musb); 488 musb_set_vbus(musb, 1); 489 490 handled = IRQ_HANDLED; 491 } 492 493 if (int_usb & MUSB_INTR_VBUSERROR) { 494 int ignore = 0; 495 496 /* During connection as an A-Device, we may see a short 497 * current spikes causing voltage drop, because of cable 498 * and peripheral capacitance combined with vbus draw. 499 * (So: less common with truly self-powered devices, where 500 * vbus doesn't act like a power supply.) 501 * 502 * Such spikes are short; usually less than ~500 usec, max 503 * of ~2 msec. That is, they're not sustained overcurrent 504 * errors, though they're reported using VBUSERROR irqs. 505 * 506 * Workarounds: (a) hardware: use self powered devices. 507 * (b) software: ignore non-repeated VBUS errors. 508 * 509 * REVISIT: do delays from lots of DEBUG_KERNEL checks 510 * make trouble here, keeping VBUS < 4.4V ? 511 */ 512 switch (musb->xceiv->state) { 513 case OTG_STATE_A_HOST: 514 /* recovery is dicey once we've gotten past the 515 * initial stages of enumeration, but if VBUS 516 * stayed ok at the other end of the link, and 517 * another reset is due (at least for high speed, 518 * to redo the chirp etc), it might work OK... 519 */ 520 case OTG_STATE_A_WAIT_BCON: 521 case OTG_STATE_A_WAIT_VRISE: 522 if (musb->vbuserr_retry) { 523 musb->vbuserr_retry--; 524 ignore = 1; 525 devctl |= MUSB_DEVCTL_SESSION; 526 musb_writeb(mbase, MUSB_DEVCTL, devctl); 527 } else { 528 musb->port1_status |= 529 (1 << USB_PORT_FEAT_OVER_CURRENT) 530 | (1 << USB_PORT_FEAT_C_OVER_CURRENT); 531 } 532 break; 533 default: 534 break; 535 } 536 537 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", 538 otg_state_string(musb), 539 devctl, 540 ({ char *s; 541 switch (devctl & MUSB_DEVCTL_VBUS) { 542 case 0 << MUSB_DEVCTL_VBUS_SHIFT: 543 s = "<SessEnd"; break; 544 case 1 << MUSB_DEVCTL_VBUS_SHIFT: 545 s = "<AValid"; break; 546 case 2 << MUSB_DEVCTL_VBUS_SHIFT: 547 s = "<VBusValid"; break; 548 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ 549 default: 550 s = "VALID"; break; 551 }; s; }), 552 VBUSERR_RETRY_COUNT - musb->vbuserr_retry, 553 musb->port1_status); 554 555 /* go through A_WAIT_VFALL then start a new session */ 556 if (!ignore) 557 musb_set_vbus(musb, 0); 558 handled = IRQ_HANDLED; 559 } 560 561 if (int_usb & MUSB_INTR_CONNECT) { 562 struct usb_hcd *hcd = musb_to_hcd(musb); 563 564 handled = IRQ_HANDLED; 565 musb->is_active = 1; 566 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); 567 568 musb->ep0_stage = MUSB_EP0_START; 569 570#ifdef CONFIG_USB_MUSB_OTG 571 /* flush endpoints when transitioning from Device Mode */ 572 if (is_peripheral_active(musb)) { 573 /* REVISIT HNP; just force disconnect */ 574 } 575 musb_writew(mbase, MUSB_INTRTXE, musb->epmask); 576 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe); 577 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7); 578#endif 579 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED 580 |USB_PORT_STAT_HIGH_SPEED 581 |USB_PORT_STAT_ENABLE 582 ); 583 musb->port1_status |= USB_PORT_STAT_CONNECTION 584 |(USB_PORT_STAT_C_CONNECTION << 16); 585 586 /* high vs full speed is just a guess until after reset */ 587 if (devctl & MUSB_DEVCTL_LSDEV) 588 musb->port1_status |= USB_PORT_STAT_LOW_SPEED; 589 590 if (hcd->status_urb) 591 usb_hcd_poll_rh_status(hcd); 592 else 593 usb_hcd_resume_root_hub(hcd); 594 595 MUSB_HST_MODE(musb); 596 597 /* indicate new connection to OTG machine */ 598 switch (musb->xceiv->state) { 599 case OTG_STATE_B_PERIPHERAL: 600 if (int_usb & MUSB_INTR_SUSPEND) { 601 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); 602 musb->xceiv->state = OTG_STATE_B_HOST; 603 hcd->self.is_b_host = 1; 604 int_usb &= ~MUSB_INTR_SUSPEND; 605 } else 606 DBG(1, "CONNECT as b_peripheral???\n"); 607 break; 608 case OTG_STATE_B_WAIT_ACON: 609 DBG(1, "HNP: Waiting to switch to b_host state\n"); 610 musb->xceiv->state = OTG_STATE_B_HOST; 611 hcd->self.is_b_host = 1; 612 break; 613 default: 614 if ((devctl & MUSB_DEVCTL_VBUS) 615 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { 616 musb->xceiv->state = OTG_STATE_A_HOST; 617 hcd->self.is_b_host = 0; 618 } 619 break; 620 } 621 DBG(1, "CONNECT (%s) devctl %02x\n", 622 otg_state_string(musb), devctl); 623 } 624#endif /* CONFIG_USB_MUSB_HDRC_HCD */ 625 626 /* mentor saves a bit: bus reset and babble share the same irq. 627 * only host sees babble; only peripheral sees bus reset. 628 */ 629 if (int_usb & MUSB_INTR_RESET) { 630 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { 631 /* 632 * Looks like non-HS BABBLE can be ignored, but 633 * HS BABBLE is an error condition. For HS the solution 634 * is to avoid babble in the first place and fix what 635 * caused BABBLE. When HS BABBLE happens we can only 636 * stop the session. 637 */ 638 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) 639 DBG(1, "BABBLE devctl: %02x\n", devctl); 640 else { 641 ERR("Stopping host session -- babble\n"); 642 musb_writeb(mbase, MUSB_DEVCTL, 0); 643 } 644 } else if (is_peripheral_capable()) { 645 DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); 646 switch (musb->xceiv->state) { 647#ifdef CONFIG_USB_OTG 648 case OTG_STATE_A_SUSPEND: 649 /* We need to ignore disconnect on suspend 650 * otherwise tusb 2.0 won't reconnect after a 651 * power cycle, which breaks otg compliance. 652 */ 653 musb->ignore_disconnect = 1; 654 musb_g_reset(musb); 655 /* FALLTHROUGH */ 656 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ 657 /* never use invalid T(a_wait_bcon) */ 658 DBG(1, "HNP: in %s, %d msec timeout\n", 659 otg_state_string(musb), 660 TA_WAIT_BCON(musb)); 661 mod_timer(&musb->otg_timer, jiffies 662 + msecs_to_jiffies(TA_WAIT_BCON(musb))); 663 break; 664 case OTG_STATE_A_PERIPHERAL: 665 musb_hnp_stop(musb); 666 break; 667 case OTG_STATE_B_WAIT_ACON: 668 DBG(1, "HNP: RESET (%s), to b_peripheral\n", 669 otg_state_string(musb)); 670 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 671 musb_g_reset(musb); 672 break; 673#endif 674 case OTG_STATE_B_IDLE: 675 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 676 /* FALLTHROUGH */ 677 case OTG_STATE_B_PERIPHERAL: 678 musb_g_reset(musb); 679 break; 680 default: 681 DBG(1, "Unhandled BUS RESET as %s\n", 682 otg_state_string(musb)); 683 } 684 } 685 686 handled = IRQ_HANDLED; 687 } 688 schedule_work(&musb->irq_work); 689 690 return handled; 691} 692 693/* 694 * Interrupt Service Routine to record USB "global" interrupts. 695 * Since these do not happen often and signify things of 696 * paramount importance, it seems OK to check them individually; 697 * the order of the tests is specified in the manual 698 * 699 * @param musb instance pointer 700 * @param int_usb register contents 701 * @param devctl 702 * @param power 703 */ 704static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb, 705 u8 devctl, u8 power) 706{ 707 irqreturn_t handled = IRQ_NONE; 708 709#if 0 710/* REVISIT ... this would be for multiplexing periodic endpoints, or 711 * supporting transfer phasing to prevent exceeding ISO bandwidth 712 * limits of a given frame or microframe. 713 * 714 * It's not needed for peripheral side, which dedicates endpoints; 715 * though it _might_ use SOF irqs for other purposes. 716 * 717 * And it's not currently needed for host side, which also dedicates 718 * endpoints, relies on TX/RX interval registers, and isn't claimed 719 * to support ISO transfers yet. 720 */ 721 if (int_usb & MUSB_INTR_SOF) { 722 void __iomem *mbase = musb->mregs; 723 struct musb_hw_ep *ep; 724 u8 epnum; 725 u16 frame; 726 727 DBG(6, "START_OF_FRAME\n"); 728 handled = IRQ_HANDLED; 729 730 /* start any periodic Tx transfers waiting for current frame */ 731 frame = musb_readw(mbase, MUSB_FRAME); 732 ep = musb->endpoints; 733 for (epnum = 1; (epnum < musb->nr_endpoints) 734 && (musb->epmask >= (1 << epnum)); 735 epnum++, ep++) { 736 /* 737 * FIXME handle framecounter wraps (12 bits) 738 * eliminate duplicated StartUrb logic 739 */ 740 if (ep->dwWaitFrame >= frame) { 741 ep->dwWaitFrame = 0; 742 pr_debug("SOF --> periodic TX%s on %d\n", 743 ep->tx_channel ? " DMA" : "", 744 epnum); 745 if (!ep->tx_channel) 746 musb_h_tx_start(musb, epnum); 747 else 748 cppi_hostdma_start(musb, epnum); 749 } 750 } /* end of for loop */ 751 } 752#endif 753 754 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { 755 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n", 756 otg_state_string(musb), 757 MUSB_MODE(musb), devctl); 758 handled = IRQ_HANDLED; 759 760 switch (musb->xceiv->state) { 761#ifdef CONFIG_USB_MUSB_HDRC_HCD 762 case OTG_STATE_A_HOST: 763 case OTG_STATE_A_SUSPEND: 764 usb_hcd_resume_root_hub(musb_to_hcd(musb)); 765 musb_root_disconnect(musb); 766 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) 767 musb_platform_try_idle(musb, jiffies 768 + msecs_to_jiffies(musb->a_wait_bcon)); 769 break; 770#endif /* HOST */ 771#ifdef CONFIG_USB_MUSB_OTG 772 case OTG_STATE_B_HOST: 773 musb_hnp_stop(musb); 774 break; 775 case OTG_STATE_A_PERIPHERAL: 776 musb_hnp_stop(musb); 777 musb_root_disconnect(musb); 778 /* FALLTHROUGH */ 779 case OTG_STATE_B_WAIT_ACON: 780 /* FALLTHROUGH */ 781#endif /* OTG */ 782#ifdef CONFIG_USB_GADGET_MUSB_HDRC 783 case OTG_STATE_B_PERIPHERAL: 784 case OTG_STATE_B_IDLE: 785 musb_g_disconnect(musb); 786 break; 787#endif /* GADGET */ 788 default: 789 WARNING("unhandled DISCONNECT transition (%s)\n", 790 otg_state_string(musb)); 791 break; 792 } 793 794 schedule_work(&musb->irq_work); 795 } 796 797 if (int_usb & MUSB_INTR_SUSPEND) { 798 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", 799 otg_state_string(musb), devctl, power); 800 handled = IRQ_HANDLED; 801 802 switch (musb->xceiv->state) { 803#ifdef CONFIG_USB_MUSB_OTG 804 case OTG_STATE_A_PERIPHERAL: 805 /* 806 * We cannot stop HNP here, devctl BDEVICE might be 807 * still set. 808 */ 809 break; 810#endif 811 case OTG_STATE_B_PERIPHERAL: 812 musb_g_suspend(musb); 813 musb->is_active = is_otg_enabled(musb) 814 && musb->xceiv->gadget->b_hnp_enable; 815 if (musb->is_active) { 816#ifdef CONFIG_USB_MUSB_OTG 817 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; 818 DBG(1, "HNP: Setting timer for b_ase0_brst\n"); 819 mod_timer(&musb->otg_timer, jiffies 820 + msecs_to_jiffies( 821 OTG_TIME_B_ASE0_BRST)); 822#endif 823 } 824 break; 825 case OTG_STATE_A_WAIT_BCON: 826 if (musb->a_wait_bcon != 0) 827 musb_platform_try_idle(musb, jiffies 828 + msecs_to_jiffies(musb->a_wait_bcon)); 829 break; 830 case OTG_STATE_A_HOST: 831 musb->xceiv->state = OTG_STATE_A_SUSPEND; 832 musb->is_active = is_otg_enabled(musb) 833 && musb->xceiv->host->b_hnp_enable; 834 break; 835 case OTG_STATE_B_HOST: 836 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ 837 DBG(1, "REVISIT: SUSPEND as B_HOST\n"); 838 break; 839 default: 840 /* "should not happen" */ 841 musb->is_active = 0; 842 break; 843 } 844 schedule_work(&musb->irq_work); 845 } 846 847 848 return handled; 849} 850 851/*-------------------------------------------------------------------------*/ 852 853/* 854* Program the HDRC to start (enable interrupts, dma, etc.). 855*/ 856void musb_start(struct musb *musb) 857{ 858 void __iomem *regs = musb->mregs; 859 u8 devctl = musb_readb(regs, MUSB_DEVCTL); 860 861 DBG(2, "<== devctl %02x\n", devctl); 862 863 /* Set INT enable registers, enable interrupts */ 864 musb_writew(regs, MUSB_INTRTXE, musb->epmask); 865 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); 866 musb_writeb(regs, MUSB_INTRUSBE, 0xf7); 867 868 musb_writeb(regs, MUSB_TESTMODE, 0); 869 870 /* put into basic highspeed mode and start session */ 871 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE 872 | MUSB_POWER_SOFTCONN 873 | MUSB_POWER_HSENAB 874 /* ENSUSPEND wedges tusb */ 875 /* | MUSB_POWER_ENSUSPEND */ 876 ); 877 878 musb->is_active = 0; 879 devctl = musb_readb(regs, MUSB_DEVCTL); 880 devctl &= ~MUSB_DEVCTL_SESSION; 881 882 if (is_otg_enabled(musb)) { 883 /* session started after: 884 * (a) ID-grounded irq, host mode; 885 * (b) vbus present/connect IRQ, peripheral mode; 886 * (c) peripheral initiates, using SRP 887 */ 888 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 889 musb->is_active = 1; 890 else 891 devctl |= MUSB_DEVCTL_SESSION; 892 893 } else if (is_host_enabled(musb)) { 894 /* assume ID pin is hard-wired to ground */ 895 devctl |= MUSB_DEVCTL_SESSION; 896 897 } else /* peripheral is enabled */ { 898 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 899 musb->is_active = 1; 900 } 901 musb_platform_enable(musb); 902 musb_writeb(regs, MUSB_DEVCTL, devctl); 903} 904 905 906static void musb_generic_disable(struct musb *musb) 907{ 908 void __iomem *mbase = musb->mregs; 909 u16 temp; 910 911 /* disable interrupts */ 912 musb_writeb(mbase, MUSB_INTRUSBE, 0); 913 musb_writew(mbase, MUSB_INTRTXE, 0); 914 musb_writew(mbase, MUSB_INTRRXE, 0); 915 916 /* off */ 917 musb_writeb(mbase, MUSB_DEVCTL, 0); 918 919 /* flush pending interrupts */ 920 temp = musb_readb(mbase, MUSB_INTRUSB); 921 temp = musb_readw(mbase, MUSB_INTRTX); 922 temp = musb_readw(mbase, MUSB_INTRRX); 923 924} 925 926/* 927 * Make the HDRC stop (disable interrupts, etc.); 928 * reversible by musb_start 929 * called on gadget driver unregister 930 * with controller locked, irqs blocked 931 * acts as a NOP unless some role activated the hardware 932 */ 933void musb_stop(struct musb *musb) 934{ 935 /* stop IRQs, timers, ... */ 936 musb_platform_disable(musb); 937 musb_generic_disable(musb); 938 DBG(3, "HDRC disabled\n"); 939 940 /* FIXME 941 * - mark host and/or peripheral drivers unusable/inactive 942 * - disable DMA (and enable it in HdrcStart) 943 * - make sure we can musb_start() after musb_stop(); with 944 * OTG mode, gadget driver module rmmod/modprobe cycles that 945 * - ... 946 */ 947 musb_platform_try_idle(musb, 0); 948} 949 950static void musb_shutdown(struct platform_device *pdev) 951{ 952 struct musb *musb = dev_to_musb(&pdev->dev); 953 unsigned long flags; 954 955 spin_lock_irqsave(&musb->lock, flags); 956 musb_platform_disable(musb); 957 musb_generic_disable(musb); 958 if (musb->clock) { 959 clk_put(musb->clock); 960 musb->clock = NULL; 961 } 962 spin_unlock_irqrestore(&musb->lock, flags); 963 964 /* FIXME power down */ 965} 966 967 968/*-------------------------------------------------------------------------*/ 969 970/* 971 * The silicon either has hard-wired endpoint configurations, or else 972 * "dynamic fifo" sizing. The driver has support for both, though at this 973 * writing only the dynamic sizing is very well tested. Since we switched 974 * away from compile-time hardware parameters, we can no longer rely on 975 * dead code elimination to leave only the relevant one in the object file. 976 * 977 * We don't currently use dynamic fifo setup capability to do anything 978 * more than selecting one of a bunch of predefined configurations. 979 */ 980#if defined(CONFIG_USB_TUSB6010) || \ 981 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) 982static ushort __initdata fifo_mode = 4; 983#else 984static ushort __initdata fifo_mode = 2; 985#endif 986 987/* "modprobe ... fifo_mode=1" etc */ 988module_param(fifo_mode, ushort, 0); 989MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); 990 991 992enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed)); 993enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed)); 994 995struct fifo_cfg { 996 u8 hw_ep_num; 997 enum fifo_style style; 998 enum buf_mode mode; 999 u16 maxpacket; 1000}; 1001 1002/* 1003 * tables defining fifo_mode values. define more if you like. 1004 * for host side, make sure both halves of ep1 are set up. 1005 */ 1006 1007/* mode 0 - fits in 2KB */ 1008static struct fifo_cfg __initdata mode_0_cfg[] = { 1009{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1010{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1011{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, 1012{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1013{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1014}; 1015 1016/* mode 1 - fits in 4KB */ 1017static struct fifo_cfg __initdata mode_1_cfg[] = { 1018{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1019{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1020{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1021{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1022{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1023}; 1024 1025/* mode 2 - fits in 4KB */ 1026static struct fifo_cfg __initdata mode_2_cfg[] = { 1027{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1028{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1029{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1030{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1031{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1032{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1033}; 1034 1035/* mode 3 - fits in 4KB */ 1036static struct fifo_cfg __initdata mode_3_cfg[] = { 1037{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1038{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, 1039{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1040{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1041{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, 1042{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, 1043}; 1044 1045/* mode 4 - fits in 16KB */ 1046static struct fifo_cfg __initdata mode_4_cfg[] = { 1047{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, 1048{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, 1049{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, 1050{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, 1051{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, 1052{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, 1053{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, 1054{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, 1055{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, 1056{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, 1057{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, 1058{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, 1059{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, 1060{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, 1061{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, 1062{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, 1063{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, 1064{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, 1065{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, }, 1066{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, }, 1067{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, }, 1068{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, }, 1069{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, }, 1070{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, }, 1071{ .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, }, 1072{ .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, }, 1073{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, 1074{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, 1075}; 1076 1077 1078/* 1079 * configure a fifo; for non-shared endpoints, this may be called 1080 * once for a tx fifo and once for an rx fifo. 1081 * 1082 * returns negative errno or offset for next fifo. 1083 */ 1084static int __init 1085fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, 1086 const struct fifo_cfg *cfg, u16 offset) 1087{ 1088 void __iomem *mbase = musb->mregs; 1089 int size = 0; 1090 u16 maxpacket = cfg->maxpacket; 1091 u16 c_off = offset >> 3; 1092 u8 c_size; 1093 1094 /* expect hw_ep has already been zero-initialized */ 1095 1096 size = ffs(max(maxpacket, (u16) 8)) - 1; 1097 maxpacket = 1 << size; 1098 1099 c_size = size - 3; 1100 if (cfg->mode == BUF_DOUBLE) { 1101 if ((offset + (maxpacket << 1)) > 1102 (1 << (musb->config->ram_bits + 2))) 1103 return -EMSGSIZE; 1104 c_size |= MUSB_FIFOSZ_DPB; 1105 } else { 1106 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) 1107 return -EMSGSIZE; 1108 } 1109 1110 /* configure the FIFO */ 1111 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); 1112 1113#ifdef CONFIG_USB_MUSB_HDRC_HCD 1114 /* EP0 reserved endpoint for control, bidirectional; 1115 * EP1 reserved for bulk, two unidirection halves. 1116 */ 1117 if (hw_ep->epnum == 1) 1118 musb->bulk_ep = hw_ep; 1119 /* REVISIT error check: be sure ep0 can both rx and tx ... */ 1120#endif 1121 switch (cfg->style) { 1122 case FIFO_TX: 1123 musb_write_txfifosz(mbase, c_size); 1124 musb_write_txfifoadd(mbase, c_off); 1125 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1126 hw_ep->max_packet_sz_tx = maxpacket; 1127 break; 1128 case FIFO_RX: 1129 musb_write_rxfifosz(mbase, c_size); 1130 musb_write_rxfifoadd(mbase, c_off); 1131 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1132 hw_ep->max_packet_sz_rx = maxpacket; 1133 break; 1134 case FIFO_RXTX: 1135 musb_write_txfifosz(mbase, c_size); 1136 musb_write_txfifoadd(mbase, c_off); 1137 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); 1138 hw_ep->max_packet_sz_rx = maxpacket; 1139 1140 musb_write_rxfifosz(mbase, c_size); 1141 musb_write_rxfifoadd(mbase, c_off); 1142 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; 1143 hw_ep->max_packet_sz_tx = maxpacket; 1144 1145 hw_ep->is_shared_fifo = true; 1146 break; 1147 } 1148 1149 /* NOTE rx and tx endpoint irqs aren't managed separately, 1150 * which happens to be ok 1151 */ 1152 musb->epmask |= (1 << hw_ep->epnum); 1153 1154 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); 1155} 1156 1157static struct fifo_cfg __initdata ep0_cfg = { 1158 .style = FIFO_RXTX, .maxpacket = 64, 1159}; 1160 1161static int __init ep_config_from_table(struct musb *musb) 1162{ 1163 const struct fifo_cfg *cfg; 1164 unsigned i, n; 1165 int offset; 1166 struct musb_hw_ep *hw_ep = musb->endpoints; 1167 1168 switch (fifo_mode) { 1169 default: 1170 fifo_mode = 0; 1171 /* FALLTHROUGH */ 1172 case 0: 1173 cfg = mode_0_cfg; 1174 n = ARRAY_SIZE(mode_0_cfg); 1175 break; 1176 case 1: 1177 cfg = mode_1_cfg; 1178 n = ARRAY_SIZE(mode_1_cfg); 1179 break; 1180 case 2: 1181 cfg = mode_2_cfg; 1182 n = ARRAY_SIZE(mode_2_cfg); 1183 break; 1184 case 3: 1185 cfg = mode_3_cfg; 1186 n = ARRAY_SIZE(mode_3_cfg); 1187 break; 1188 case 4: 1189 cfg = mode_4_cfg; 1190 n = ARRAY_SIZE(mode_4_cfg); 1191 break; 1192 } 1193 1194 printk(KERN_DEBUG "%s: setup fifo_mode %d\n", 1195 musb_driver_name, fifo_mode); 1196 1197 1198 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); 1199 /* assert(offset > 0) */ 1200 1201 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would 1202 * be better than static musb->config->num_eps and DYN_FIFO_SIZE... 1203 */ 1204 1205 for (i = 0; i < n; i++) { 1206 u8 epn = cfg->hw_ep_num; 1207 1208 if (epn >= musb->config->num_eps) { 1209 pr_debug("%s: invalid ep %d\n", 1210 musb_driver_name, epn); 1211 return -EINVAL; 1212 } 1213 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); 1214 if (offset < 0) { 1215 pr_debug("%s: mem overrun, ep %d\n", 1216 musb_driver_name, epn); 1217 return -EINVAL; 1218 } 1219 epn++; 1220 musb->nr_endpoints = max(epn, musb->nr_endpoints); 1221 } 1222 1223 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", 1224 musb_driver_name, 1225 n + 1, musb->config->num_eps * 2 - 1, 1226 offset, (1 << (musb->config->ram_bits + 2))); 1227 1228#ifdef CONFIG_USB_MUSB_HDRC_HCD 1229 if (!musb->bulk_ep) { 1230 pr_debug("%s: missing bulk\n", musb_driver_name); 1231 return -EINVAL; 1232 } 1233#endif 1234 1235 return 0; 1236} 1237 1238 1239/* 1240 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false 1241 * @param musb the controller 1242 */ 1243static int __init ep_config_from_hw(struct musb *musb) 1244{ 1245 u8 epnum = 0; 1246 struct musb_hw_ep *hw_ep; 1247 void *mbase = musb->mregs; 1248 int ret = 0; 1249 1250 DBG(2, "<== static silicon ep config\n"); 1251 1252 /* FIXME pick up ep0 maxpacket size */ 1253 1254 for (epnum = 1; epnum < musb->config->num_eps; epnum++) { 1255 musb_ep_select(mbase, epnum); 1256 hw_ep = musb->endpoints + epnum; 1257 1258 ret = musb_read_fifosize(musb, hw_ep, epnum); 1259 if (ret < 0) 1260 break; 1261 1262 /* FIXME set up hw_ep->{rx,tx}_double_buffered */ 1263 1264#ifdef CONFIG_USB_MUSB_HDRC_HCD 1265 /* pick an RX/TX endpoint for bulk */ 1266 if (hw_ep->max_packet_sz_tx < 512 1267 || hw_ep->max_packet_sz_rx < 512) 1268 continue; 1269 1270 /* REVISIT: this algorithm is lazy, we should at least 1271 * try to pick a double buffered endpoint. 1272 */ 1273 if (musb->bulk_ep) 1274 continue; 1275 musb->bulk_ep = hw_ep; 1276#endif 1277 } 1278 1279#ifdef CONFIG_USB_MUSB_HDRC_HCD 1280 if (!musb->bulk_ep) { 1281 pr_debug("%s: missing bulk\n", musb_driver_name); 1282 return -EINVAL; 1283 } 1284#endif 1285 1286 return 0; 1287} 1288 1289enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; 1290 1291/* Initialize MUSB (M)HDRC part of the USB hardware subsystem; 1292 * configure endpoints, or take their config from silicon 1293 */ 1294static int __init musb_core_init(u16 musb_type, struct musb *musb) 1295{ 1296#ifdef MUSB_AHB_ID 1297 u32 data; 1298#endif 1299 u8 reg; 1300 char *type; 1301 u16 hwvers, rev_major, rev_minor; 1302 char aInfo[78], aRevision[32], aDate[12]; 1303 void __iomem *mbase = musb->mregs; 1304 int status = 0; 1305 int i; 1306 1307 /* log core options (read using indexed model) */ 1308 musb_ep_select(mbase, 0); 1309 reg = musb_read_configdata(mbase); 1310 1311 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); 1312 if (reg & MUSB_CONFIGDATA_DYNFIFO) 1313 strcat(aInfo, ", dyn FIFOs"); 1314 if (reg & MUSB_CONFIGDATA_MPRXE) { 1315 strcat(aInfo, ", bulk combine"); 1316#ifdef C_MP_RX 1317 musb->bulk_combine = true; 1318#else 1319 strcat(aInfo, " (X)"); /* no driver support */ 1320#endif 1321 } 1322 if (reg & MUSB_CONFIGDATA_MPTXE) { 1323 strcat(aInfo, ", bulk split"); 1324#ifdef C_MP_TX 1325 musb->bulk_split = true; 1326#else 1327 strcat(aInfo, " (X)"); /* no driver support */ 1328#endif 1329 } 1330 if (reg & MUSB_CONFIGDATA_HBRXE) { 1331 strcat(aInfo, ", HB-ISO Rx"); 1332 strcat(aInfo, " (X)"); /* no driver support */ 1333 } 1334 if (reg & MUSB_CONFIGDATA_HBTXE) { 1335 strcat(aInfo, ", HB-ISO Tx"); 1336 strcat(aInfo, " (X)"); /* no driver support */ 1337 } 1338 if (reg & MUSB_CONFIGDATA_SOFTCONE) 1339 strcat(aInfo, ", SoftConn"); 1340 1341 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", 1342 musb_driver_name, reg, aInfo); 1343 1344#ifdef MUSB_AHB_ID 1345 data = musb_readl(mbase, 0x404); 1346 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff), 1347 (data >> 16) & 0xff, (data >> 24) & 0xff); 1348 /* FIXME ID2 and ID3 are unused */ 1349 data = musb_readl(mbase, 0x408); 1350 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data); 1351 data = musb_readl(mbase, 0x40c); 1352 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data); 1353 reg = musb_readb(mbase, 0x400); 1354 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC; 1355#else 1356 aDate[0] = 0; 1357#endif 1358 if (MUSB_CONTROLLER_MHDRC == musb_type) { 1359 musb->is_multipoint = 1; 1360 type = "M"; 1361 } else { 1362 musb->is_multipoint = 0; 1363 type = ""; 1364#ifdef CONFIG_USB_MUSB_HDRC_HCD 1365#ifndef CONFIG_USB_OTG_BLACKLIST_HUB 1366 printk(KERN_ERR 1367 "%s: kernel must blacklist external hubs\n", 1368 musb_driver_name); 1369#endif 1370#endif 1371 } 1372 1373 /* log release info */ 1374 hwvers = musb_read_hwvers(mbase); 1375 rev_major = (hwvers >> 10) & 0x1f; 1376 rev_minor = hwvers & 0x3ff; 1377 snprintf(aRevision, 32, "%d.%d%s", rev_major, 1378 rev_minor, (hwvers & 0x8000) ? "RC" : ""); 1379 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", 1380 musb_driver_name, type, aRevision, aDate); 1381 1382 /* configure ep0 */ 1383 musb_configure_ep0(musb); 1384 1385 /* discover endpoint configuration */ 1386 musb->nr_endpoints = 1; 1387 musb->epmask = 1; 1388 1389 if (reg & MUSB_CONFIGDATA_DYNFIFO) { 1390 if (musb->config->dyn_fifo) 1391 status = ep_config_from_table(musb); 1392 else { 1393 ERR("reconfigure software for Dynamic FIFOs\n"); 1394 status = -ENODEV; 1395 } 1396 } else { 1397 if (!musb->config->dyn_fifo) 1398 status = ep_config_from_hw(musb); 1399 else { 1400 ERR("reconfigure software for static FIFOs\n"); 1401 return -ENODEV; 1402 } 1403 } 1404 1405 if (status < 0) 1406 return status; 1407 1408 /* finish init, and print endpoint config */ 1409 for (i = 0; i < musb->nr_endpoints; i++) { 1410 struct musb_hw_ep *hw_ep = musb->endpoints + i; 1411 1412 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; 1413#ifdef CONFIG_USB_TUSB6010 1414 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); 1415 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); 1416 hw_ep->fifo_sync_va = 1417 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); 1418 1419 if (i == 0) 1420 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; 1421 else 1422 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); 1423#endif 1424 1425 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; 1426#ifdef CONFIG_USB_MUSB_HDRC_HCD 1427 hw_ep->target_regs = musb_read_target_reg_base(i, mbase); 1428 hw_ep->rx_reinit = 1; 1429 hw_ep->tx_reinit = 1; 1430#endif 1431 1432 if (hw_ep->max_packet_sz_tx) { 1433 printk(KERN_DEBUG 1434 "%s: hw_ep %d%s, %smax %d\n", 1435 musb_driver_name, i, 1436 hw_ep->is_shared_fifo ? "shared" : "tx", 1437 hw_ep->tx_double_buffered 1438 ? "doublebuffer, " : "", 1439 hw_ep->max_packet_sz_tx); 1440 } 1441 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { 1442 printk(KERN_DEBUG 1443 "%s: hw_ep %d%s, %smax %d\n", 1444 musb_driver_name, i, 1445 "rx", 1446 hw_ep->rx_double_buffered 1447 ? "doublebuffer, " : "", 1448 hw_ep->max_packet_sz_rx); 1449 } 1450 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) 1451 DBG(1, "hw_ep %d not configured\n", i); 1452 } 1453 1454 return 0; 1455} 1456 1457/*-------------------------------------------------------------------------*/ 1458 1459#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) 1460 1461static irqreturn_t generic_interrupt(int irq, void *__hci) 1462{ 1463 unsigned long flags; 1464 irqreturn_t retval = IRQ_NONE; 1465 struct musb *musb = __hci; 1466 1467 spin_lock_irqsave(&musb->lock, flags); 1468 1469 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); 1470 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); 1471 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); 1472 1473 if (musb->int_usb || musb->int_tx || musb->int_rx) 1474 retval = musb_interrupt(musb); 1475 1476 spin_unlock_irqrestore(&musb->lock, flags); 1477 1478 return retval; 1479} 1480 1481#else 1482#define generic_interrupt NULL 1483#endif 1484 1485/* 1486 * handle all the irqs defined by the HDRC core. for now we expect: other 1487 * irq sources (phy, dma, etc) will be handled first, musb->int_* values 1488 * will be assigned, and the irq will already have been acked. 1489 * 1490 * called in irq context with spinlock held, irqs blocked 1491 */ 1492irqreturn_t musb_interrupt(struct musb *musb) 1493{ 1494 irqreturn_t retval = IRQ_NONE; 1495 u8 devctl, power; 1496 int ep_num; 1497 u32 reg; 1498 1499 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1500 power = musb_readb(musb->mregs, MUSB_POWER); 1501 1502 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n", 1503 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", 1504 musb->int_usb, musb->int_tx, musb->int_rx); 1505 1506 /* the core can interrupt us for multiple reasons; docs have 1507 * a generic interrupt flowchart to follow 1508 */ 1509 if (musb->int_usb & STAGE0_MASK) 1510 retval |= musb_stage0_irq(musb, musb->int_usb, 1511 devctl, power); 1512 1513 /* "stage 1" is handling endpoint irqs */ 1514 1515 /* handle endpoint 0 first */ 1516 if (musb->int_tx & 1) { 1517 if (devctl & MUSB_DEVCTL_HM) 1518 retval |= musb_h_ep0_irq(musb); 1519 else 1520 retval |= musb_g_ep0_irq(musb); 1521 } 1522 1523 /* RX on endpoints 1-15 */ 1524 reg = musb->int_rx >> 1; 1525 ep_num = 1; 1526 while (reg) { 1527 if (reg & 1) { 1528 /* musb_ep_select(musb->mregs, ep_num); */ 1529 /* REVISIT just retval = ep->rx_irq(...) */ 1530 retval = IRQ_HANDLED; 1531 if (devctl & MUSB_DEVCTL_HM) { 1532 if (is_host_capable()) 1533 musb_host_rx(musb, ep_num); 1534 } else { 1535 if (is_peripheral_capable()) 1536 musb_g_rx(musb, ep_num); 1537 } 1538 } 1539 1540 reg >>= 1; 1541 ep_num++; 1542 } 1543 1544 /* TX on endpoints 1-15 */ 1545 reg = musb->int_tx >> 1; 1546 ep_num = 1; 1547 while (reg) { 1548 if (reg & 1) { 1549 /* musb_ep_select(musb->mregs, ep_num); */ 1550 /* REVISIT just retval |= ep->tx_irq(...) */ 1551 retval = IRQ_HANDLED; 1552 if (devctl & MUSB_DEVCTL_HM) { 1553 if (is_host_capable()) 1554 musb_host_tx(musb, ep_num); 1555 } else { 1556 if (is_peripheral_capable()) 1557 musb_g_tx(musb, ep_num); 1558 } 1559 } 1560 reg >>= 1; 1561 ep_num++; 1562 } 1563 1564 /* finish handling "global" interrupts after handling fifos */ 1565 if (musb->int_usb) 1566 retval |= musb_stage2_irq(musb, 1567 musb->int_usb, devctl, power); 1568 1569 return retval; 1570} 1571 1572 1573#ifndef CONFIG_MUSB_PIO_ONLY 1574static int __initdata use_dma = 1; 1575 1576/* "modprobe ... use_dma=0" etc */ 1577module_param(use_dma, bool, 0); 1578MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); 1579 1580void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) 1581{ 1582 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1583 1584 /* called with controller lock already held */ 1585 1586 if (!epnum) { 1587#ifndef CONFIG_USB_TUSB_OMAP_DMA 1588 if (!is_cppi_enabled()) { 1589 /* endpoint 0 */ 1590 if (devctl & MUSB_DEVCTL_HM) 1591 musb_h_ep0_irq(musb); 1592 else 1593 musb_g_ep0_irq(musb); 1594 } 1595#endif 1596 } else { 1597 /* endpoints 1..15 */ 1598 if (transmit) { 1599 if (devctl & MUSB_DEVCTL_HM) { 1600 if (is_host_capable()) 1601 musb_host_tx(musb, epnum); 1602 } else { 1603 if (is_peripheral_capable()) 1604 musb_g_tx(musb, epnum); 1605 } 1606 } else { 1607 /* receive */ 1608 if (devctl & MUSB_DEVCTL_HM) { 1609 if (is_host_capable()) 1610 musb_host_rx(musb, epnum); 1611 } else { 1612 if (is_peripheral_capable()) 1613 musb_g_rx(musb, epnum); 1614 } 1615 } 1616 } 1617} 1618 1619#else 1620#define use_dma 0 1621#endif 1622 1623/*-------------------------------------------------------------------------*/ 1624 1625#ifdef CONFIG_SYSFS 1626 1627static ssize_t 1628musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1629{ 1630 struct musb *musb = dev_to_musb(dev); 1631 unsigned long flags; 1632 int ret = -EINVAL; 1633 1634 spin_lock_irqsave(&musb->lock, flags); 1635 ret = sprintf(buf, "%s\n", otg_state_string(musb)); 1636 spin_unlock_irqrestore(&musb->lock, flags); 1637 1638 return ret; 1639} 1640 1641static ssize_t 1642musb_mode_store(struct device *dev, struct device_attribute *attr, 1643 const char *buf, size_t n) 1644{ 1645 struct musb *musb = dev_to_musb(dev); 1646 unsigned long flags; 1647 int status; 1648 1649 spin_lock_irqsave(&musb->lock, flags); 1650 if (sysfs_streq(buf, "host")) 1651 status = musb_platform_set_mode(musb, MUSB_HOST); 1652 else if (sysfs_streq(buf, "peripheral")) 1653 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); 1654 else if (sysfs_streq(buf, "otg")) 1655 status = musb_platform_set_mode(musb, MUSB_OTG); 1656 else 1657 status = -EINVAL; 1658 spin_unlock_irqrestore(&musb->lock, flags); 1659 1660 return (status == 0) ? n : status; 1661} 1662static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); 1663 1664static ssize_t 1665musb_vbus_store(struct device *dev, struct device_attribute *attr, 1666 const char *buf, size_t n) 1667{ 1668 struct musb *musb = dev_to_musb(dev); 1669 unsigned long flags; 1670 unsigned long val; 1671 1672 if (sscanf(buf, "%lu", &val) < 1) { 1673 printk(KERN_ERR "Invalid VBUS timeout ms value\n"); 1674 return -EINVAL; 1675 } 1676 1677 spin_lock_irqsave(&musb->lock, flags); 1678 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ 1679 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; 1680 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) 1681 musb->is_active = 0; 1682 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); 1683 spin_unlock_irqrestore(&musb->lock, flags); 1684 1685 return n; 1686} 1687 1688static ssize_t 1689musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) 1690{ 1691 struct musb *musb = dev_to_musb(dev); 1692 unsigned long flags; 1693 unsigned long val; 1694 int vbus; 1695 1696 spin_lock_irqsave(&musb->lock, flags); 1697 val = musb->a_wait_bcon; 1698 /* FIXME get_vbus_status() is normally #defined as false... 1699 * and is effectively TUSB-specific. 1700 */ 1701 vbus = musb_platform_get_vbus_status(musb); 1702 spin_unlock_irqrestore(&musb->lock, flags); 1703 1704 return sprintf(buf, "Vbus %s, timeout %lu msec\n", 1705 vbus ? "on" : "off", val); 1706} 1707static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); 1708 1709#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1710 1711/* Gadget drivers can't know that a host is connected so they might want 1712 * to start SRP, but users can. This allows userspace to trigger SRP. 1713 */ 1714static ssize_t 1715musb_srp_store(struct device *dev, struct device_attribute *attr, 1716 const char *buf, size_t n) 1717{ 1718 struct musb *musb = dev_to_musb(dev); 1719 unsigned short srp; 1720 1721 if (sscanf(buf, "%hu", &srp) != 1 1722 || (srp != 1)) { 1723 printk(KERN_ERR "SRP: Value must be 1\n"); 1724 return -EINVAL; 1725 } 1726 1727 if (srp == 1) 1728 musb_g_wakeup(musb); 1729 1730 return n; 1731} 1732static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); 1733 1734#endif /* CONFIG_USB_GADGET_MUSB_HDRC */ 1735 1736#endif /* sysfs */ 1737 1738/* Only used to provide driver mode change events */ 1739static void musb_irq_work(struct work_struct *data) 1740{ 1741 struct musb *musb = container_of(data, struct musb, irq_work); 1742 static int old_state; 1743 1744 if (musb->xceiv->state != old_state) { 1745 old_state = musb->xceiv->state; 1746 sysfs_notify(&musb->controller->kobj, NULL, "mode"); 1747 } 1748} 1749 1750/* -------------------------------------------------------------------------- 1751 * Init support 1752 */ 1753 1754static struct musb *__init 1755allocate_instance(struct device *dev, 1756 struct musb_hdrc_config *config, void __iomem *mbase) 1757{ 1758 struct musb *musb; 1759 struct musb_hw_ep *ep; 1760 int epnum; 1761#ifdef CONFIG_USB_MUSB_HDRC_HCD 1762 struct usb_hcd *hcd; 1763 1764 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 1765 if (!hcd) 1766 return NULL; 1767 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 1768 1769 musb = hcd_to_musb(hcd); 1770 INIT_LIST_HEAD(&musb->control); 1771 INIT_LIST_HEAD(&musb->in_bulk); 1772 INIT_LIST_HEAD(&musb->out_bulk); 1773 1774 hcd->uses_new_polling = 1; 1775 1776 musb->vbuserr_retry = VBUSERR_RETRY_COUNT; 1777 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; 1778#else 1779 musb = kzalloc(sizeof *musb, GFP_KERNEL); 1780 if (!musb) 1781 return NULL; 1782 dev_set_drvdata(dev, musb); 1783 1784#endif 1785 1786 musb->mregs = mbase; 1787 musb->ctrl_base = mbase; 1788 musb->nIrq = -ENODEV; 1789 musb->config = config; 1790 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); 1791 for (epnum = 0, ep = musb->endpoints; 1792 epnum < musb->config->num_eps; 1793 epnum++, ep++) { 1794 ep->musb = musb; 1795 ep->epnum = epnum; 1796 } 1797 1798 musb->controller = dev; 1799 return musb; 1800} 1801 1802static void musb_free(struct musb *musb) 1803{ 1804 /* this has multiple entry modes. it handles fault cleanup after 1805 * probe(), where things may be partially set up, as well as rmmod 1806 * cleanup after everything's been de-activated. 1807 */ 1808 1809#ifdef CONFIG_SYSFS 1810 device_remove_file(musb->controller, &dev_attr_mode); 1811 device_remove_file(musb->controller, &dev_attr_vbus); 1812#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1813 device_remove_file(musb->controller, &dev_attr_srp); 1814#endif 1815#endif 1816 1817#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1818 musb_gadget_cleanup(musb); 1819#endif 1820 1821 if (musb->nIrq >= 0) { 1822 if (musb->irq_wake) 1823 disable_irq_wake(musb->nIrq); 1824 free_irq(musb->nIrq, musb); 1825 } 1826 if (is_dma_capable() && musb->dma_controller) { 1827 struct dma_controller *c = musb->dma_controller; 1828 1829 (void) c->stop(c); 1830 dma_controller_destroy(c); 1831 } 1832 1833 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1834 musb_platform_exit(musb); 1835 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 1836 1837 if (musb->clock) { 1838 clk_disable(musb->clock); 1839 clk_put(musb->clock); 1840 } 1841 1842#ifdef CONFIG_USB_MUSB_OTG 1843 put_device(musb->xceiv->dev); 1844#endif 1845 1846#ifdef CONFIG_USB_MUSB_HDRC_HCD 1847 usb_put_hcd(musb_to_hcd(musb)); 1848#else 1849 kfree(musb); 1850#endif 1851} 1852 1853/* 1854 * Perform generic per-controller initialization. 1855 * 1856 * @pDevice: the controller (already clocked, etc) 1857 * @nIrq: irq 1858 * @mregs: virtual address of controller registers, 1859 * not yet corrected for platform-specific offsets 1860 */ 1861static int __init 1862musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) 1863{ 1864 int status; 1865 struct musb *musb; 1866 struct musb_hdrc_platform_data *plat = dev->platform_data; 1867 1868 /* The driver might handle more features than the board; OK. 1869 * Fail when the board needs a feature that's not enabled. 1870 */ 1871 if (!plat) { 1872 dev_dbg(dev, "no platform_data?\n"); 1873 return -ENODEV; 1874 } 1875 switch (plat->mode) { 1876 case MUSB_HOST: 1877#ifdef CONFIG_USB_MUSB_HDRC_HCD 1878 break; 1879#else 1880 goto bad_config; 1881#endif 1882 case MUSB_PERIPHERAL: 1883#ifdef CONFIG_USB_GADGET_MUSB_HDRC 1884 break; 1885#else 1886 goto bad_config; 1887#endif 1888 case MUSB_OTG: 1889#ifdef CONFIG_USB_MUSB_OTG 1890 break; 1891#else 1892bad_config: 1893#endif 1894 default: 1895 dev_err(dev, "incompatible Kconfig role setting\n"); 1896 return -EINVAL; 1897 } 1898 1899 /* allocate */ 1900 musb = allocate_instance(dev, plat->config, ctrl); 1901 if (!musb) 1902 return -ENOMEM; 1903 1904 spin_lock_init(&musb->lock); 1905 musb->board_mode = plat->mode; 1906 musb->board_set_power = plat->set_power; 1907 musb->set_clock = plat->set_clock; 1908 musb->min_power = plat->min_power; 1909 1910 /* Clock usage is chip-specific ... functional clock (DaVinci, 1911 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core 1912 * code does is make sure a clock handle is available; platform 1913 * code manages it during start/stop and suspend/resume. 1914 */ 1915 if (plat->clock) { 1916 musb->clock = clk_get(dev, plat->clock); 1917 if (IS_ERR(musb->clock)) { 1918 status = PTR_ERR(musb->clock); 1919 musb->clock = NULL; 1920 goto fail; 1921 } 1922 } 1923 1924 /* The musb_platform_init() call: 1925 * - adjusts musb->mregs and musb->isr if needed, 1926 * - may initialize an integrated tranceiver 1927 * - initializes musb->xceiv, usually by otg_get_transceiver() 1928 * - activates clocks. 1929 * - stops powering VBUS 1930 * - assigns musb->board_set_vbus if host mode is enabled 1931 * 1932 * There are various transciever configurations. Blackfin, 1933 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses 1934 * external/discrete ones in various flavors (twl4030 family, 1935 * isp1504, non-OTG, etc) mostly hooking up through ULPI. 1936 */ 1937 musb->isr = generic_interrupt; 1938 status = musb_platform_init(musb); 1939 1940 if (status < 0) 1941 goto fail; 1942 if (!musb->isr) { 1943 status = -ENODEV; 1944 goto fail2; 1945 } 1946 1947#ifndef CONFIG_MUSB_PIO_ONLY 1948 if (use_dma && dev->dma_mask) { 1949 struct dma_controller *c; 1950 1951 c = dma_controller_create(musb, musb->mregs); 1952 musb->dma_controller = c; 1953 if (c) 1954 (void) c->start(c); 1955 } 1956#endif 1957 /* ideally this would be abstracted in platform setup */ 1958 if (!is_dma_capable() || !musb->dma_controller) 1959 dev->dma_mask = NULL; 1960 1961 /* be sure interrupts are disabled before connecting ISR */ 1962 musb_platform_disable(musb); 1963 musb_generic_disable(musb); 1964 1965 /* setup musb parts of the core (especially endpoints) */ 1966 status = musb_core_init(plat->config->multipoint 1967 ? MUSB_CONTROLLER_MHDRC 1968 : MUSB_CONTROLLER_HDRC, musb); 1969 if (status < 0) 1970 goto fail2; 1971 1972#ifdef CONFIG_USB_OTG 1973 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); 1974#endif 1975 1976 /* Init IRQ workqueue before request_irq */ 1977 INIT_WORK(&musb->irq_work, musb_irq_work); 1978 1979 /* attach to the IRQ */ 1980 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { 1981 dev_err(dev, "request_irq %d failed!\n", nIrq); 1982 status = -ENODEV; 1983 goto fail2; 1984 } 1985 musb->nIrq = nIrq; 1986/* FIXME this handles wakeup irqs wrong */ 1987 if (enable_irq_wake(nIrq) == 0) { 1988 musb->irq_wake = 1; 1989 device_init_wakeup(dev, 1); 1990 } else { 1991 musb->irq_wake = 0; 1992 } 1993 1994 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n", 1995 musb_driver_name, 1996 ({char *s; 1997 switch (musb->board_mode) { 1998 case MUSB_HOST: s = "Host"; break; 1999 case MUSB_PERIPHERAL: s = "Peripheral"; break; 2000 default: s = "OTG"; break; 2001 }; s; }), 2002 ctrl, 2003 (is_dma_capable() && musb->dma_controller) 2004 ? "DMA" : "PIO", 2005 musb->nIrq); 2006 2007 /* host side needs more setup */ 2008 if (is_host_enabled(musb)) { 2009 struct usb_hcd *hcd = musb_to_hcd(musb); 2010 2011 otg_set_host(musb->xceiv, &hcd->self); 2012 2013 if (is_otg_enabled(musb)) 2014 hcd->self.otg_port = 1; 2015 musb->xceiv->host = &hcd->self; 2016 hcd->power_budget = 2 * (plat->power ? : 250); 2017 } 2018 2019 /* For the host-only role, we can activate right away. 2020 * (We expect the ID pin to be forcibly grounded!!) 2021 * Otherwise, wait till the gadget driver hooks up. 2022 */ 2023 if (!is_otg_enabled(musb) && is_host_enabled(musb)) { 2024 MUSB_HST_MODE(musb); 2025 musb->xceiv->default_a = 1; 2026 musb->xceiv->state = OTG_STATE_A_IDLE; 2027 2028 status = usb_add_hcd(musb_to_hcd(musb), -1, 0); 2029 if (status) 2030 goto fail; 2031 2032 DBG(1, "%s mode, status %d, devctl %02x %c\n", 2033 "HOST", status, 2034 musb_readb(musb->mregs, MUSB_DEVCTL), 2035 (musb_readb(musb->mregs, MUSB_DEVCTL) 2036 & MUSB_DEVCTL_BDEVICE 2037 ? 'B' : 'A')); 2038 2039 } else /* peripheral is enabled */ { 2040 MUSB_DEV_MODE(musb); 2041 musb->xceiv->default_a = 0; 2042 musb->xceiv->state = OTG_STATE_B_IDLE; 2043 2044 status = musb_gadget_setup(musb); 2045 if (status) 2046 goto fail; 2047 2048 DBG(1, "%s mode, status %d, dev%02x\n", 2049 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", 2050 status, 2051 musb_readb(musb->mregs, MUSB_DEVCTL)); 2052 2053 } 2054 2055#ifdef CONFIG_SYSFS 2056 status = device_create_file(dev, &dev_attr_mode); 2057 status = device_create_file(dev, &dev_attr_vbus); 2058#ifdef CONFIG_USB_GADGET_MUSB_HDRC 2059 status = device_create_file(dev, &dev_attr_srp); 2060#endif /* CONFIG_USB_GADGET_MUSB_HDRC */ 2061 status = 0; 2062#endif 2063 if (status) 2064 goto fail2; 2065 2066 return 0; 2067 2068fail2: 2069#ifdef CONFIG_SYSFS 2070 device_remove_file(musb->controller, &dev_attr_mode); 2071 device_remove_file(musb->controller, &dev_attr_vbus); 2072#ifdef CONFIG_USB_GADGET_MUSB_HDRC 2073 device_remove_file(musb->controller, &dev_attr_srp); 2074#endif 2075#endif 2076 musb_platform_exit(musb); 2077fail: 2078 dev_err(musb->controller, 2079 "musb_init_controller failed with status %d\n", status); 2080 2081 if (musb->clock) 2082 clk_put(musb->clock); 2083 device_init_wakeup(dev, 0); 2084 musb_free(musb); 2085 2086 return status; 2087 2088} 2089 2090/*-------------------------------------------------------------------------*/ 2091 2092/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just 2093 * bridge to a platform device; this driver then suffices. 2094 */ 2095 2096#ifndef CONFIG_MUSB_PIO_ONLY 2097static u64 *orig_dma_mask; 2098#endif 2099 2100static int __init musb_probe(struct platform_device *pdev) 2101{ 2102 struct device *dev = &pdev->dev; 2103 int irq = platform_get_irq(pdev, 0); 2104 struct resource *iomem; 2105 void __iomem *base; 2106 2107 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2108 if (!iomem || irq == 0) 2109 return -ENODEV; 2110 2111 base = ioremap(iomem->start, iomem->end - iomem->start + 1); 2112 if (!base) { 2113 dev_err(dev, "ioremap failed\n"); 2114 return -ENOMEM; 2115 } 2116 2117#ifndef CONFIG_MUSB_PIO_ONLY 2118 /* clobbered by use_dma=n */ 2119 orig_dma_mask = dev->dma_mask; 2120#endif 2121 return musb_init_controller(dev, irq, base); 2122} 2123 2124static int __devexit musb_remove(struct platform_device *pdev) 2125{ 2126 struct musb *musb = dev_to_musb(&pdev->dev); 2127 void __iomem *ctrl_base = musb->ctrl_base; 2128 2129 /* this gets called on rmmod. 2130 * - Host mode: host may still be active 2131 * - Peripheral mode: peripheral is deactivated (or never-activated) 2132 * - OTG mode: both roles are deactivated (or never-activated) 2133 */ 2134 musb_shutdown(pdev); 2135#ifdef CONFIG_USB_MUSB_HDRC_HCD 2136 if (musb->board_mode == MUSB_HOST) 2137 usb_remove_hcd(musb_to_hcd(musb)); 2138#endif 2139 musb_free(musb); 2140 iounmap(ctrl_base); 2141 device_init_wakeup(&pdev->dev, 0); 2142#ifndef CONFIG_MUSB_PIO_ONLY 2143 pdev->dev.dma_mask = orig_dma_mask; 2144#endif 2145 return 0; 2146} 2147 2148#ifdef CONFIG_PM 2149 2150static int musb_suspend(struct platform_device *pdev, pm_message_t message) 2151{ 2152 unsigned long flags; 2153 struct musb *musb = dev_to_musb(&pdev->dev); 2154 2155 if (!musb->clock) 2156 return 0; 2157 2158 spin_lock_irqsave(&musb->lock, flags); 2159 2160 if (is_peripheral_active(musb)) { 2161 /* FIXME force disconnect unless we know USB will wake 2162 * the system up quickly enough to respond ... 2163 */ 2164 } else if (is_host_active(musb)) { 2165 /* we know all the children are suspended; sometimes 2166 * they will even be wakeup-enabled. 2167 */ 2168 } 2169 2170 if (musb->set_clock) 2171 musb->set_clock(musb->clock, 0); 2172 else 2173 clk_disable(musb->clock); 2174 spin_unlock_irqrestore(&musb->lock, flags); 2175 return 0; 2176} 2177 2178static int musb_resume_early(struct platform_device *pdev) 2179{ 2180 struct musb *musb = dev_to_musb(&pdev->dev); 2181 2182 if (!musb->clock) 2183 return 0; 2184 2185 if (musb->set_clock) 2186 musb->set_clock(musb->clock, 1); 2187 else 2188 clk_enable(musb->clock); 2189 2190 /* for static cmos like DaVinci, register values were preserved 2191 * unless for some reason the whole soc powered down or the USB 2192 * module got reset through the PSC (vs just being disabled). 2193 */ 2194 return 0; 2195} 2196 2197#else 2198#define musb_suspend NULL 2199#define musb_resume_early NULL 2200#endif 2201 2202static struct platform_driver musb_driver = { 2203 .driver = { 2204 .name = (char *)musb_driver_name, 2205 .bus = &platform_bus_type, 2206 .owner = THIS_MODULE, 2207 }, 2208 .remove = __devexit_p(musb_remove), 2209 .shutdown = musb_shutdown, 2210 .suspend = musb_suspend, 2211 .resume_early = musb_resume_early, 2212}; 2213 2214/*-------------------------------------------------------------------------*/ 2215 2216static int __init musb_init(void) 2217{ 2218#ifdef CONFIG_USB_MUSB_HDRC_HCD 2219 if (usb_disabled()) 2220 return 0; 2221#endif 2222 2223 pr_info("%s: version " MUSB_VERSION ", " 2224#ifdef CONFIG_MUSB_PIO_ONLY 2225 "pio" 2226#elif defined(CONFIG_USB_TI_CPPI_DMA) 2227 "cppi-dma" 2228#elif defined(CONFIG_USB_INVENTRA_DMA) 2229 "musb-dma" 2230#elif defined(CONFIG_USB_TUSB_OMAP_DMA) 2231 "tusb-omap-dma" 2232#else 2233 "?dma?" 2234#endif 2235 ", " 2236#ifdef CONFIG_USB_MUSB_OTG 2237 "otg (peripheral+host)" 2238#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 2239 "peripheral" 2240#elif defined(CONFIG_USB_MUSB_HDRC_HCD) 2241 "host" 2242#endif 2243 ", debug=%d\n", 2244 musb_driver_name, musb_debug); 2245 return platform_driver_probe(&musb_driver, musb_probe); 2246} 2247 2248/* make us init after usbcore and i2c (transceivers, regulators, etc) 2249 * and before usb gadget and host-side drivers start to register 2250 */ 2251fs_initcall(musb_init); 2252 2253static void __exit musb_cleanup(void) 2254{ 2255 platform_driver_unregister(&musb_driver); 2256} 2257module_exit(musb_cleanup); 2258