1/* 2 * MUSB OTG driver host support 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36#include <linux/module.h> 37#include <linux/kernel.h> 38#include <linux/delay.h> 39#include <linux/sched.h> 40#include <linux/slab.h> 41#include <linux/errno.h> 42#include <linux/init.h> 43#include <linux/list.h> 44#include <linux/dma-mapping.h> 45 46#include "musb_core.h" 47#include "musb_host.h" 48 49 50/* MUSB HOST status 22-mar-2006 51 * 52 * - There's still lots of partial code duplication for fault paths, so 53 * they aren't handled as consistently as they need to be. 54 * 55 * - PIO mostly behaved when last tested. 56 * + including ep0, with all usbtest cases 9, 10 57 * + usbtest 14 (ep0out) doesn't seem to run at all 58 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest 59 * configurations, but otherwise double buffering passes basic tests. 60 * + for 2.6.N, for N > ~10, needs API changes for hcd framework. 61 * 62 * - DMA (CPPI) ... partially behaves, not currently recommended 63 * + about 1/15 the speed of typical EHCI implementations (PCI) 64 * + RX, all too often reqpkt seems to misbehave after tx 65 * + TX, no known issues (other than evident silicon issue) 66 * 67 * - DMA (Mentor/OMAP) ...has at least toggle update problems 68 * 69 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet 70 * starvation ... nothing yet for TX, interrupt, or bulk. 71 * 72 * - Not tested with HNP, but some SRP paths seem to behave. 73 * 74 * NOTE 24-August-2006: 75 * 76 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an 77 * extra endpoint for periodic use enabling hub + keybd + mouse. That 78 * mostly works, except that with "usbnet" it's easy to trigger cases 79 * with "ping" where RX loses. (a) ping to davinci, even "ping -f", 80 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses 81 * although ARP RX wins. (That test was done with a full speed link.) 82 */ 83 84 85/* 86 * NOTE on endpoint usage: 87 * 88 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN 89 * and OUT endpoints ... hardware is dedicated for those "async" queue(s). 90 * (Yes, bulk _could_ use more of the endpoints than that, and would even 91 * benefit from it.) 92 * 93 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. 94 * So far that scheduling is both dumb and optimistic: the endpoint will be 95 * "claimed" until its software queue is no longer refilled. No multiplexing 96 * of transfers between endpoints, or anything clever. 97 */ 98 99 100static void musb_ep_program(struct musb *musb, u8 epnum, 101 struct urb *urb, int is_out, 102 u8 *buf, u32 offset, u32 len); 103 104/* 105 * Clear TX fifo. Needed to avoid BABBLE errors. 106 */ 107static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) 108{ 109 struct musb *musb = ep->musb; 110 void __iomem *epio = ep->regs; 111 u16 csr; 112 u16 lastcsr = 0; 113 int retries = 1000; 114 115 csr = musb_readw(epio, MUSB_TXCSR); 116 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { 117 if (csr != lastcsr) 118 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr); 119 lastcsr = csr; 120 csr |= MUSB_TXCSR_FLUSHFIFO; 121 musb_writew(epio, MUSB_TXCSR, csr); 122 csr = musb_readw(epio, MUSB_TXCSR); 123 if (WARN(retries-- < 1, 124 "Could not flush host TX%d fifo: csr: %04x\n", 125 ep->epnum, csr)) 126 return; 127 mdelay(1); 128 } 129} 130 131static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) 132{ 133 void __iomem *epio = ep->regs; 134 u16 csr; 135 int retries = 5; 136 137 /* scrub any data left in the fifo */ 138 do { 139 csr = musb_readw(epio, MUSB_TXCSR); 140 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) 141 break; 142 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO); 143 csr = musb_readw(epio, MUSB_TXCSR); 144 udelay(10); 145 } while (--retries); 146 147 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", 148 ep->epnum, csr); 149 150 /* and reset for the next transfer */ 151 musb_writew(epio, MUSB_TXCSR, 0); 152} 153 154/* 155 * Start transmit. Caller is responsible for locking shared resources. 156 * musb must be locked. 157 */ 158static inline void musb_h_tx_start(struct musb_hw_ep *ep) 159{ 160 u16 txcsr; 161 162 /* NOTE: no locks here; caller should lock and select EP */ 163 if (ep->epnum) { 164 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 165 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; 166 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 167 } else { 168 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; 169 musb_writew(ep->regs, MUSB_CSR0, txcsr); 170 } 171 172} 173 174static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep) 175{ 176 u16 txcsr; 177 178 /* NOTE: no locks here; caller should lock and select EP */ 179 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 180 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; 181 if (is_cppi_enabled()) 182 txcsr |= MUSB_TXCSR_DMAMODE; 183 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 184} 185 186static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh) 187{ 188 if (is_in != 0 || ep->is_shared_fifo) 189 ep->in_qh = qh; 190 if (is_in == 0 || ep->is_shared_fifo) 191 ep->out_qh = qh; 192} 193 194static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in) 195{ 196 return is_in ? ep->in_qh : ep->out_qh; 197} 198 199/* 200 * Start the URB at the front of an endpoint's queue 201 * end must be claimed from the caller. 202 * 203 * Context: controller locked, irqs blocked 204 */ 205static void 206musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) 207{ 208 u16 frame; 209 u32 len; 210 void __iomem *mbase = musb->mregs; 211 struct urb *urb = next_urb(qh); 212 void *buf = urb->transfer_buffer; 213 u32 offset = 0; 214 struct musb_hw_ep *hw_ep = qh->hw_ep; 215 unsigned pipe = urb->pipe; 216 u8 address = usb_pipedevice(pipe); 217 int epnum = hw_ep->epnum; 218 219 /* initialize software qh state */ 220 qh->offset = 0; 221 qh->segsize = 0; 222 223 /* gather right source of data */ 224 switch (qh->type) { 225 case USB_ENDPOINT_XFER_CONTROL: 226 /* control transfers always start with SETUP */ 227 is_in = 0; 228 musb->ep0_stage = MUSB_EP0_START; 229 buf = urb->setup_packet; 230 len = 8; 231 break; 232 case USB_ENDPOINT_XFER_ISOC: 233 qh->iso_idx = 0; 234 qh->frame = 0; 235 offset = urb->iso_frame_desc[0].offset; 236 len = urb->iso_frame_desc[0].length; 237 break; 238 default: /* bulk, interrupt */ 239 /* actual_length may be nonzero on retry paths */ 240 buf = urb->transfer_buffer + urb->actual_length; 241 len = urb->transfer_buffer_length - urb->actual_length; 242 } 243 244 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", 245 qh, urb, address, qh->epnum, 246 is_in ? "in" : "out", 247 ({char *s; switch (qh->type) { 248 case USB_ENDPOINT_XFER_CONTROL: s = ""; break; 249 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break; 250 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break; 251 default: s = "-intr"; break; 252 }; s; }), 253 epnum, buf + offset, len); 254 255 /* Configure endpoint */ 256 musb_ep_set_qh(hw_ep, is_in, qh); 257 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len); 258 259 /* transmit may have more work: start it when it is time */ 260 if (is_in) 261 return; 262 263 /* determine if the time is right for a periodic transfer */ 264 switch (qh->type) { 265 case USB_ENDPOINT_XFER_ISOC: 266 case USB_ENDPOINT_XFER_INT: 267 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n"); 268 frame = musb_readw(mbase, MUSB_FRAME); 269 /* FIXME this doesn't implement that scheduling policy ... 270 * or handle framecounter wrapping 271 */ 272 if ((urb->transfer_flags & URB_ISO_ASAP) 273 || (frame >= urb->start_frame)) { 274 /* REVISIT the SOF irq handler shouldn't duplicate 275 * this code; and we don't init urb->start_frame... 276 */ 277 qh->frame = 0; 278 goto start; 279 } else { 280 qh->frame = urb->start_frame; 281 /* enable SOF interrupt so we can count down */ 282 dev_dbg(musb->controller, "SOF for %d\n", epnum); 283#if 1 /* ifndef CONFIG_ARCH_DAVINCI */ 284 musb_writeb(mbase, MUSB_INTRUSBE, 0xff); 285#endif 286 } 287 break; 288 default: 289start: 290 dev_dbg(musb->controller, "Start TX%d %s\n", epnum, 291 hw_ep->tx_channel ? "dma" : "pio"); 292 293 if (!hw_ep->tx_channel) 294 musb_h_tx_start(hw_ep); 295 else if (is_cppi_enabled() || tusb_dma_omap()) 296 musb_h_tx_dma_start(hw_ep); 297 } 298} 299 300/* Context: caller owns controller lock, IRQs are blocked */ 301static void musb_giveback(struct musb *musb, struct urb *urb, int status) 302__releases(musb->lock) 303__acquires(musb->lock) 304{ 305 dev_dbg(musb->controller, 306 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", 307 urb, urb->complete, status, 308 usb_pipedevice(urb->pipe), 309 usb_pipeendpoint(urb->pipe), 310 usb_pipein(urb->pipe) ? "in" : "out", 311 urb->actual_length, urb->transfer_buffer_length 312 ); 313 314 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb); 315 spin_unlock(&musb->lock); 316 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status); 317 spin_lock(&musb->lock); 318} 319 320/* For bulk/interrupt endpoints only */ 321static inline void musb_save_toggle(struct musb_qh *qh, int is_in, 322 struct urb *urb) 323{ 324 void __iomem *epio = qh->hw_ep->regs; 325 u16 csr; 326 327 /* 328 * FIXME: the current Mentor DMA code seems to have 329 * problems getting toggle correct. 330 */ 331 332 if (is_in) 333 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE; 334 else 335 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE; 336 337 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0); 338} 339 340/* 341 * Advance this hardware endpoint's queue, completing the specified URB and 342 * advancing to either the next URB queued to that qh, or else invalidating 343 * that qh and advancing to the next qh scheduled after the current one. 344 * 345 * Context: caller owns controller lock, IRQs are blocked 346 */ 347static void musb_advance_schedule(struct musb *musb, struct urb *urb, 348 struct musb_hw_ep *hw_ep, int is_in) 349{ 350 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in); 351 struct musb_hw_ep *ep = qh->hw_ep; 352 int ready = qh->is_ready; 353 int status; 354 355 status = (urb->status == -EINPROGRESS) ? 0 : urb->status; 356 357 /* save toggle eagerly, for paranoia */ 358 switch (qh->type) { 359 case USB_ENDPOINT_XFER_BULK: 360 case USB_ENDPOINT_XFER_INT: 361 musb_save_toggle(qh, is_in, urb); 362 break; 363 case USB_ENDPOINT_XFER_ISOC: 364 if (status == 0 && urb->error_count) 365 status = -EXDEV; 366 break; 367 } 368 369 qh->is_ready = 0; 370 musb_giveback(musb, urb, status); 371 qh->is_ready = ready; 372 373 /* reclaim resources (and bandwidth) ASAP; deschedule it, and 374 * invalidate qh as soon as list_empty(&hep->urb_list) 375 */ 376 if (list_empty(&qh->hep->urb_list)) { 377 struct list_head *head; 378 379 if (is_in) 380 ep->rx_reinit = 1; 381 else 382 ep->tx_reinit = 1; 383 384 /* Clobber old pointers to this qh */ 385 musb_ep_set_qh(ep, is_in, NULL); 386 qh->hep->hcpriv = NULL; 387 388 switch (qh->type) { 389 390 case USB_ENDPOINT_XFER_CONTROL: 391 case USB_ENDPOINT_XFER_BULK: 392 /* fifo policy for these lists, except that NAKing 393 * should rotate a qh to the end (for fairness). 394 */ 395 if (qh->mux == 1) { 396 head = qh->ring.prev; 397 list_del(&qh->ring); 398 kfree(qh); 399 qh = first_qh(head); 400 break; 401 } 402 403 case USB_ENDPOINT_XFER_ISOC: 404 case USB_ENDPOINT_XFER_INT: 405 /* this is where periodic bandwidth should be 406 * de-allocated if it's tracked and allocated; 407 * and where we'd update the schedule tree... 408 */ 409 kfree(qh); 410 qh = NULL; 411 break; 412 } 413 } 414 415 if (qh != NULL && qh->is_ready) { 416 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n", 417 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); 418 musb_start_urb(musb, is_in, qh); 419 } 420} 421 422static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) 423{ 424 /* we don't want fifo to fill itself again; 425 * ignore dma (various models), 426 * leave toggle alone (may not have been saved yet) 427 */ 428 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; 429 csr &= ~(MUSB_RXCSR_H_REQPKT 430 | MUSB_RXCSR_H_AUTOREQ 431 | MUSB_RXCSR_AUTOCLEAR); 432 433 /* write 2x to allow double buffering */ 434 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 435 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 436 437 /* flush writebuffer */ 438 return musb_readw(hw_ep->regs, MUSB_RXCSR); 439} 440 441/* 442 * PIO RX for a packet (or part of it). 443 */ 444static bool 445musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) 446{ 447 u16 rx_count; 448 u8 *buf; 449 u16 csr; 450 bool done = false; 451 u32 length; 452 int do_flush = 0; 453 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 454 void __iomem *epio = hw_ep->regs; 455 struct musb_qh *qh = hw_ep->in_qh; 456 int pipe = urb->pipe; 457 void *buffer = urb->transfer_buffer; 458 459 /* musb_ep_select(mbase, epnum); */ 460 rx_count = musb_readw(epio, MUSB_RXCOUNT); 461 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, 462 urb->transfer_buffer, qh->offset, 463 urb->transfer_buffer_length); 464 465 /* unload FIFO */ 466 if (usb_pipeisoc(pipe)) { 467 int status = 0; 468 struct usb_iso_packet_descriptor *d; 469 470 if (iso_err) { 471 status = -EILSEQ; 472 urb->error_count++; 473 } 474 475 d = urb->iso_frame_desc + qh->iso_idx; 476 buf = buffer + d->offset; 477 length = d->length; 478 if (rx_count > length) { 479 if (status == 0) { 480 status = -EOVERFLOW; 481 urb->error_count++; 482 } 483 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); 484 do_flush = 1; 485 } else 486 length = rx_count; 487 urb->actual_length += length; 488 d->actual_length = length; 489 490 d->status = status; 491 492 /* see if we are done */ 493 done = (++qh->iso_idx >= urb->number_of_packets); 494 } else { 495 /* non-isoch */ 496 buf = buffer + qh->offset; 497 length = urb->transfer_buffer_length - qh->offset; 498 if (rx_count > length) { 499 if (urb->status == -EINPROGRESS) 500 urb->status = -EOVERFLOW; 501 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); 502 do_flush = 1; 503 } else 504 length = rx_count; 505 urb->actual_length += length; 506 qh->offset += length; 507 508 /* see if we are done */ 509 done = (urb->actual_length == urb->transfer_buffer_length) 510 || (rx_count < qh->maxpacket) 511 || (urb->status != -EINPROGRESS); 512 if (done 513 && (urb->status == -EINPROGRESS) 514 && (urb->transfer_flags & URB_SHORT_NOT_OK) 515 && (urb->actual_length 516 < urb->transfer_buffer_length)) 517 urb->status = -EREMOTEIO; 518 } 519 520 musb_read_fifo(hw_ep, length, buf); 521 522 csr = musb_readw(epio, MUSB_RXCSR); 523 csr |= MUSB_RXCSR_H_WZC_BITS; 524 if (unlikely(do_flush)) 525 musb_h_flush_rxfifo(hw_ep, csr); 526 else { 527 /* REVISIT this assumes AUTOCLEAR is never set */ 528 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); 529 if (!done) 530 csr |= MUSB_RXCSR_H_REQPKT; 531 musb_writew(epio, MUSB_RXCSR, csr); 532 } 533 534 return done; 535} 536 537/* we don't always need to reinit a given side of an endpoint... 538 * when we do, use tx/rx reinit routine and then construct a new CSR 539 * to address data toggle, NYET, and DMA or PIO. 540 * 541 * it's possible that driver bugs (especially for DMA) or aborting a 542 * transfer might have left the endpoint busier than it should be. 543 * the busy/not-empty tests are basically paranoia. 544 */ 545static void 546musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) 547{ 548 u16 csr; 549 550 /* NOTE: we know the "rx" fifo reinit never triggers for ep0. 551 * That always uses tx_reinit since ep0 repurposes TX register 552 * offsets; the initial SETUP packet is also a kind of OUT. 553 */ 554 555 /* if programmed for Tx, put it in RX mode */ 556 if (ep->is_shared_fifo) { 557 csr = musb_readw(ep->regs, MUSB_TXCSR); 558 if (csr & MUSB_TXCSR_MODE) { 559 musb_h_tx_flush_fifo(ep); 560 csr = musb_readw(ep->regs, MUSB_TXCSR); 561 musb_writew(ep->regs, MUSB_TXCSR, 562 csr | MUSB_TXCSR_FRCDATATOG); 563 } 564 565 /* 566 * Clear the MODE bit (and everything else) to enable Rx. 567 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB. 568 */ 569 if (csr & MUSB_TXCSR_DMAMODE) 570 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE); 571 musb_writew(ep->regs, MUSB_TXCSR, 0); 572 573 /* scrub all previous state, clearing toggle */ 574 } else { 575 csr = musb_readw(ep->regs, MUSB_RXCSR); 576 if (csr & MUSB_RXCSR_RXPKTRDY) 577 WARNING("rx%d, packet/%d ready?\n", ep->epnum, 578 musb_readw(ep->regs, MUSB_RXCOUNT)); 579 580 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); 581 } 582 583 /* target addr and (for multipoint) hub addr/port */ 584 if (musb->is_multipoint) { 585 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg); 586 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg); 587 musb_write_rxhubport(ep->target_regs, qh->h_port_reg); 588 589 } else 590 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); 591 592 /* protocol/endpoint, interval/NAKlimit, i/o size */ 593 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); 594 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); 595 /* NOTE: bulk combining rewrites high bits of maxpacket */ 596 /* Set RXMAXP with the FIFO size of the endpoint 597 * to disable double buffer mode. 598 */ 599 if (musb->double_buffer_not_ok) 600 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx); 601 else 602 musb_writew(ep->regs, MUSB_RXMAXP, 603 qh->maxpacket | ((qh->hb_mult - 1) << 11)); 604 605 ep->rx_reinit = 0; 606} 607 608static bool musb_tx_dma_program(struct dma_controller *dma, 609 struct musb_hw_ep *hw_ep, struct musb_qh *qh, 610 struct urb *urb, u32 offset, u32 length) 611{ 612 struct dma_channel *channel = hw_ep->tx_channel; 613 void __iomem *epio = hw_ep->regs; 614 u16 pkt_size = qh->maxpacket; 615 u16 csr; 616 u8 mode; 617 618#ifdef CONFIG_USB_INVENTRA_DMA 619 if (length > channel->max_len) 620 length = channel->max_len; 621 622 csr = musb_readw(epio, MUSB_TXCSR); 623 if (length > pkt_size) { 624 mode = 1; 625 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; 626 /* autoset shouldn't be set in high bandwidth */ 627 if (qh->hb_mult == 1) 628 csr |= MUSB_TXCSR_AUTOSET; 629 } else { 630 mode = 0; 631 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); 632 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ 633 } 634 channel->desired_mode = mode; 635 musb_writew(epio, MUSB_TXCSR, csr); 636#else 637 if (!is_cppi_enabled() && !tusb_dma_omap()) 638 return false; 639 640 channel->actual_len = 0; 641 642 /* 643 * TX uses "RNDIS" mode automatically but needs help 644 * to identify the zero-length-final-packet case. 645 */ 646 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; 647#endif 648 649 qh->segsize = length; 650 651 /* 652 * Ensure the data reaches to main memory before starting 653 * DMA transfer 654 */ 655 wmb(); 656 657 if (!dma->channel_program(channel, pkt_size, mode, 658 urb->transfer_dma + offset, length)) { 659 dma->channel_release(channel); 660 hw_ep->tx_channel = NULL; 661 662 csr = musb_readw(epio, MUSB_TXCSR); 663 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 664 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); 665 return false; 666 } 667 return true; 668} 669 670/* 671 * Program an HDRC endpoint as per the given URB 672 * Context: irqs blocked, controller lock held 673 */ 674static void musb_ep_program(struct musb *musb, u8 epnum, 675 struct urb *urb, int is_out, 676 u8 *buf, u32 offset, u32 len) 677{ 678 struct dma_controller *dma_controller; 679 struct dma_channel *dma_channel; 680 u8 dma_ok; 681 void __iomem *mbase = musb->mregs; 682 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 683 void __iomem *epio = hw_ep->regs; 684 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); 685 u16 packet_sz = qh->maxpacket; 686 687 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s " 688 "h_addr%02x h_port%02x bytes %d\n", 689 is_out ? "-->" : "<--", 690 epnum, urb, urb->dev->speed, 691 qh->addr_reg, qh->epnum, is_out ? "out" : "in", 692 qh->h_addr_reg, qh->h_port_reg, 693 len); 694 695 musb_ep_select(mbase, epnum); 696 697 /* candidate for DMA? */ 698 dma_controller = musb->dma_controller; 699 if (is_dma_capable() && epnum && dma_controller) { 700 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; 701 if (!dma_channel) { 702 dma_channel = dma_controller->channel_alloc( 703 dma_controller, hw_ep, is_out); 704 if (is_out) 705 hw_ep->tx_channel = dma_channel; 706 else 707 hw_ep->rx_channel = dma_channel; 708 } 709 } else 710 dma_channel = NULL; 711 712 /* make sure we clear DMAEnab, autoSet bits from previous run */ 713 714 /* OUT/transmit/EP0 or IN/receive? */ 715 if (is_out) { 716 u16 csr; 717 u16 int_txe; 718 u16 load_count; 719 720 csr = musb_readw(epio, MUSB_TXCSR); 721 722 /* disable interrupt in case we flush */ 723 int_txe = musb_readw(mbase, MUSB_INTRTXE); 724 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); 725 726 /* general endpoint setup */ 727 if (epnum) { 728 /* flush all old state, set default */ 729 musb_h_tx_flush_fifo(hw_ep); 730 731 /* 732 * We must not clear the DMAMODE bit before or in 733 * the same cycle with the DMAENAB bit, so we clear 734 * the latter first... 735 */ 736 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT 737 | MUSB_TXCSR_AUTOSET 738 | MUSB_TXCSR_DMAENAB 739 | MUSB_TXCSR_FRCDATATOG 740 | MUSB_TXCSR_H_RXSTALL 741 | MUSB_TXCSR_H_ERROR 742 | MUSB_TXCSR_TXPKTRDY 743 ); 744 csr |= MUSB_TXCSR_MODE; 745 746 if (usb_gettoggle(urb->dev, qh->epnum, 1)) 747 csr |= MUSB_TXCSR_H_WR_DATATOGGLE 748 | MUSB_TXCSR_H_DATATOGGLE; 749 else 750 csr |= MUSB_TXCSR_CLRDATATOG; 751 752 musb_writew(epio, MUSB_TXCSR, csr); 753 /* REVISIT may need to clear FLUSHFIFO ... */ 754 csr &= ~MUSB_TXCSR_DMAMODE; 755 musb_writew(epio, MUSB_TXCSR, csr); 756 csr = musb_readw(epio, MUSB_TXCSR); 757 } else { 758 /* endpoint 0: just flush */ 759 musb_h_ep0_flush_fifo(hw_ep); 760 } 761 762 /* target addr and (for multipoint) hub addr/port */ 763 if (musb->is_multipoint) { 764 musb_write_txfunaddr(mbase, epnum, qh->addr_reg); 765 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg); 766 musb_write_txhubport(mbase, epnum, qh->h_port_reg); 767/* FIXME if !epnum, do the same for RX ... */ 768 } else 769 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); 770 771 /* protocol/endpoint/interval/NAKlimit */ 772 if (epnum) { 773 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); 774 if (musb->double_buffer_not_ok) 775 musb_writew(epio, MUSB_TXMAXP, 776 hw_ep->max_packet_sz_tx); 777 else if (can_bulk_split(musb, qh->type)) 778 musb_writew(epio, MUSB_TXMAXP, packet_sz 779 | ((hw_ep->max_packet_sz_tx / 780 packet_sz) - 1) << 11); 781 else 782 musb_writew(epio, MUSB_TXMAXP, 783 qh->maxpacket | 784 ((qh->hb_mult - 1) << 11)); 785 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); 786 } else { 787 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); 788 if (musb->is_multipoint) 789 musb_writeb(epio, MUSB_TYPE0, 790 qh->type_reg); 791 } 792 793 if (can_bulk_split(musb, qh->type)) 794 load_count = min((u32) hw_ep->max_packet_sz_tx, 795 len); 796 else 797 load_count = min((u32) packet_sz, len); 798 799 if (dma_channel && musb_tx_dma_program(dma_controller, 800 hw_ep, qh, urb, offset, len)) 801 load_count = 0; 802 803 if (load_count) { 804 /* PIO to load FIFO */ 805 qh->segsize = load_count; 806 musb_write_fifo(hw_ep, load_count, buf); 807 } 808 809 /* re-enable interrupt */ 810 musb_writew(mbase, MUSB_INTRTXE, int_txe); 811 812 /* IN/receive */ 813 } else { 814 u16 csr; 815 816 if (hw_ep->rx_reinit) { 817 musb_rx_reinit(musb, qh, hw_ep); 818 819 /* init new state: toggle and NYET, maybe DMA later */ 820 if (usb_gettoggle(urb->dev, qh->epnum, 0)) 821 csr = MUSB_RXCSR_H_WR_DATATOGGLE 822 | MUSB_RXCSR_H_DATATOGGLE; 823 else 824 csr = 0; 825 if (qh->type == USB_ENDPOINT_XFER_INT) 826 csr |= MUSB_RXCSR_DISNYET; 827 828 } else { 829 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 830 831 if (csr & (MUSB_RXCSR_RXPKTRDY 832 | MUSB_RXCSR_DMAENAB 833 | MUSB_RXCSR_H_REQPKT)) 834 ERR("broken !rx_reinit, ep%d csr %04x\n", 835 hw_ep->epnum, csr); 836 837 /* scrub any stale state, leaving toggle alone */ 838 csr &= MUSB_RXCSR_DISNYET; 839 } 840 841 /* kick things off */ 842 843 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { 844 /* Candidate for DMA */ 845 dma_channel->actual_len = 0L; 846 qh->segsize = len; 847 848 /* AUTOREQ is in a DMA register */ 849 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 850 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 851 852 /* 853 * Unless caller treats short RX transfers as 854 * errors, we dare not queue multiple transfers. 855 */ 856 dma_ok = dma_controller->channel_program(dma_channel, 857 packet_sz, !(urb->transfer_flags & 858 URB_SHORT_NOT_OK), 859 urb->transfer_dma + offset, 860 qh->segsize); 861 if (!dma_ok) { 862 dma_controller->channel_release(dma_channel); 863 hw_ep->rx_channel = dma_channel = NULL; 864 } else 865 csr |= MUSB_RXCSR_DMAENAB; 866 } 867 868 csr |= MUSB_RXCSR_H_REQPKT; 869 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr); 870 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 871 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 872 } 873} 874 875 876/* 877 * Service the default endpoint (ep0) as host. 878 * Return true until it's time to start the status stage. 879 */ 880static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) 881{ 882 bool more = false; 883 u8 *fifo_dest = NULL; 884 u16 fifo_count = 0; 885 struct musb_hw_ep *hw_ep = musb->control_ep; 886 struct musb_qh *qh = hw_ep->in_qh; 887 struct usb_ctrlrequest *request; 888 889 switch (musb->ep0_stage) { 890 case MUSB_EP0_IN: 891 fifo_dest = urb->transfer_buffer + urb->actual_length; 892 fifo_count = min_t(size_t, len, urb->transfer_buffer_length - 893 urb->actual_length); 894 if (fifo_count < len) 895 urb->status = -EOVERFLOW; 896 897 musb_read_fifo(hw_ep, fifo_count, fifo_dest); 898 899 urb->actual_length += fifo_count; 900 if (len < qh->maxpacket) { 901 /* always terminate on short read; it's 902 * rarely reported as an error. 903 */ 904 } else if (urb->actual_length < 905 urb->transfer_buffer_length) 906 more = true; 907 break; 908 case MUSB_EP0_START: 909 request = (struct usb_ctrlrequest *) urb->setup_packet; 910 911 if (!request->wLength) { 912 dev_dbg(musb->controller, "start no-DATA\n"); 913 break; 914 } else if (request->bRequestType & USB_DIR_IN) { 915 dev_dbg(musb->controller, "start IN-DATA\n"); 916 musb->ep0_stage = MUSB_EP0_IN; 917 more = true; 918 break; 919 } else { 920 dev_dbg(musb->controller, "start OUT-DATA\n"); 921 musb->ep0_stage = MUSB_EP0_OUT; 922 more = true; 923 } 924 /* FALLTHROUGH */ 925 case MUSB_EP0_OUT: 926 fifo_count = min_t(size_t, qh->maxpacket, 927 urb->transfer_buffer_length - 928 urb->actual_length); 929 if (fifo_count) { 930 fifo_dest = (u8 *) (urb->transfer_buffer 931 + urb->actual_length); 932 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n", 933 fifo_count, 934 (fifo_count == 1) ? "" : "s", 935 fifo_dest); 936 musb_write_fifo(hw_ep, fifo_count, fifo_dest); 937 938 urb->actual_length += fifo_count; 939 more = true; 940 } 941 break; 942 default: 943 ERR("bogus ep0 stage %d\n", musb->ep0_stage); 944 break; 945 } 946 947 return more; 948} 949 950/* 951 * Handle default endpoint interrupt as host. Only called in IRQ time 952 * from musb_interrupt(). 953 * 954 * called with controller irqlocked 955 */ 956irqreturn_t musb_h_ep0_irq(struct musb *musb) 957{ 958 struct urb *urb; 959 u16 csr, len; 960 int status = 0; 961 void __iomem *mbase = musb->mregs; 962 struct musb_hw_ep *hw_ep = musb->control_ep; 963 void __iomem *epio = hw_ep->regs; 964 struct musb_qh *qh = hw_ep->in_qh; 965 bool complete = false; 966 irqreturn_t retval = IRQ_NONE; 967 968 /* ep0 only has one queue, "in" */ 969 urb = next_urb(qh); 970 971 musb_ep_select(mbase, 0); 972 csr = musb_readw(epio, MUSB_CSR0); 973 len = (csr & MUSB_CSR0_RXPKTRDY) 974 ? musb_readb(epio, MUSB_COUNT0) 975 : 0; 976 977 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", 978 csr, qh, len, urb, musb->ep0_stage); 979 980 /* if we just did status stage, we are done */ 981 if (MUSB_EP0_STATUS == musb->ep0_stage) { 982 retval = IRQ_HANDLED; 983 complete = true; 984 } 985 986 /* prepare status */ 987 if (csr & MUSB_CSR0_H_RXSTALL) { 988 dev_dbg(musb->controller, "STALLING ENDPOINT\n"); 989 status = -EPIPE; 990 991 } else if (csr & MUSB_CSR0_H_ERROR) { 992 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr); 993 status = -EPROTO; 994 995 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { 996 dev_dbg(musb->controller, "control NAK timeout\n"); 997 998 /* NOTE: this code path would be a good place to PAUSE a 999 * control transfer, if another one is queued, so that 1000 * ep0 is more likely to stay busy. That's already done 1001 * for bulk RX transfers. 1002 * 1003 * if (qh->ring.next != &musb->control), then 1004 * we have a candidate... NAKing is *NOT* an error 1005 */ 1006 musb_writew(epio, MUSB_CSR0, 0); 1007 retval = IRQ_HANDLED; 1008 } 1009 1010 if (status) { 1011 dev_dbg(musb->controller, "aborting\n"); 1012 retval = IRQ_HANDLED; 1013 if (urb) 1014 urb->status = status; 1015 complete = true; 1016 1017 /* use the proper sequence to abort the transfer */ 1018 if (csr & MUSB_CSR0_H_REQPKT) { 1019 csr &= ~MUSB_CSR0_H_REQPKT; 1020 musb_writew(epio, MUSB_CSR0, csr); 1021 csr &= ~MUSB_CSR0_H_NAKTIMEOUT; 1022 musb_writew(epio, MUSB_CSR0, csr); 1023 } else { 1024 musb_h_ep0_flush_fifo(hw_ep); 1025 } 1026 1027 musb_writeb(epio, MUSB_NAKLIMIT0, 0); 1028 1029 /* clear it */ 1030 musb_writew(epio, MUSB_CSR0, 0); 1031 } 1032 1033 if (unlikely(!urb)) { 1034 /* stop endpoint since we have no place for its data, this 1035 * SHOULD NEVER HAPPEN! */ 1036 ERR("no URB for end 0\n"); 1037 1038 musb_h_ep0_flush_fifo(hw_ep); 1039 goto done; 1040 } 1041 1042 if (!complete) { 1043 /* call common logic and prepare response */ 1044 if (musb_h_ep0_continue(musb, len, urb)) { 1045 /* more packets required */ 1046 csr = (MUSB_EP0_IN == musb->ep0_stage) 1047 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; 1048 } else { 1049 /* data transfer complete; perform status phase */ 1050 if (usb_pipeout(urb->pipe) 1051 || !urb->transfer_buffer_length) 1052 csr = MUSB_CSR0_H_STATUSPKT 1053 | MUSB_CSR0_H_REQPKT; 1054 else 1055 csr = MUSB_CSR0_H_STATUSPKT 1056 | MUSB_CSR0_TXPKTRDY; 1057 1058 /* flag status stage */ 1059 musb->ep0_stage = MUSB_EP0_STATUS; 1060 1061 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr); 1062 1063 } 1064 musb_writew(epio, MUSB_CSR0, csr); 1065 retval = IRQ_HANDLED; 1066 } else 1067 musb->ep0_stage = MUSB_EP0_IDLE; 1068 1069 /* call completion handler if done */ 1070 if (complete) 1071 musb_advance_schedule(musb, urb, hw_ep, 1); 1072done: 1073 return retval; 1074} 1075 1076 1077#ifdef CONFIG_USB_INVENTRA_DMA 1078 1079/* Host side TX (OUT) using Mentor DMA works as follows: 1080 submit_urb -> 1081 - if queue was empty, Program Endpoint 1082 - ... which starts DMA to fifo in mode 1 or 0 1083 1084 DMA Isr (transfer complete) -> TxAvail() 1085 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens 1086 only in musb_cleanup_urb) 1087 - TxPktRdy has to be set in mode 0 or for 1088 short packets in mode 1. 1089*/ 1090 1091#endif 1092 1093/* Service a Tx-Available or dma completion irq for the endpoint */ 1094void musb_host_tx(struct musb *musb, u8 epnum) 1095{ 1096 int pipe; 1097 bool done = false; 1098 u16 tx_csr; 1099 size_t length = 0; 1100 size_t offset = 0; 1101 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1102 void __iomem *epio = hw_ep->regs; 1103 struct musb_qh *qh = hw_ep->out_qh; 1104 struct urb *urb = next_urb(qh); 1105 u32 status = 0; 1106 void __iomem *mbase = musb->mregs; 1107 struct dma_channel *dma; 1108 bool transfer_pending = false; 1109 1110 musb_ep_select(mbase, epnum); 1111 tx_csr = musb_readw(epio, MUSB_TXCSR); 1112 1113 /* with CPPI, DMA sometimes triggers "extra" irqs */ 1114 if (!urb) { 1115 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1116 return; 1117 } 1118 1119 pipe = urb->pipe; 1120 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; 1121 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, 1122 dma ? ", dma" : ""); 1123 1124 /* check for errors */ 1125 if (tx_csr & MUSB_TXCSR_H_RXSTALL) { 1126 /* dma was disabled, fifo flushed */ 1127 dev_dbg(musb->controller, "TX end %d stall\n", epnum); 1128 1129 /* stall; record URB status */ 1130 status = -EPIPE; 1131 1132 } else if (tx_csr & MUSB_TXCSR_H_ERROR) { 1133 /* (NON-ISO) dma was disabled, fifo flushed */ 1134 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum); 1135 1136 status = -ETIMEDOUT; 1137 1138 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { 1139 dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum); 1140 1141 /* NOTE: this code path would be a good place to PAUSE a 1142 * transfer, if there's some other (nonperiodic) tx urb 1143 * that could use this fifo. (dma complicates it...) 1144 * That's already done for bulk RX transfers. 1145 * 1146 * if (bulk && qh->ring.next != &musb->out_bulk), then 1147 * we have a candidate... NAKing is *NOT* an error 1148 */ 1149 musb_ep_select(mbase, epnum); 1150 musb_writew(epio, MUSB_TXCSR, 1151 MUSB_TXCSR_H_WZC_BITS 1152 | MUSB_TXCSR_TXPKTRDY); 1153 return; 1154 } 1155 1156 if (status) { 1157 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1158 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1159 (void) musb->dma_controller->channel_abort(dma); 1160 } 1161 1162 /* do the proper sequence to abort the transfer in the 1163 * usb core; the dma engine should already be stopped. 1164 */ 1165 musb_h_tx_flush_fifo(hw_ep); 1166 tx_csr &= ~(MUSB_TXCSR_AUTOSET 1167 | MUSB_TXCSR_DMAENAB 1168 | MUSB_TXCSR_H_ERROR 1169 | MUSB_TXCSR_H_RXSTALL 1170 | MUSB_TXCSR_H_NAKTIMEOUT 1171 ); 1172 1173 musb_ep_select(mbase, epnum); 1174 musb_writew(epio, MUSB_TXCSR, tx_csr); 1175 /* REVISIT may need to clear FLUSHFIFO ... */ 1176 musb_writew(epio, MUSB_TXCSR, tx_csr); 1177 musb_writeb(epio, MUSB_TXINTERVAL, 0); 1178 1179 done = true; 1180 } 1181 1182 /* second cppi case */ 1183 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1184 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1185 return; 1186 } 1187 1188 if (is_dma_capable() && dma && !status) { 1189 /* 1190 * DMA has completed. But if we're using DMA mode 1 (multi 1191 * packet DMA), we need a terminal TXPKTRDY interrupt before 1192 * we can consider this transfer completed, lest we trash 1193 * its last packet when writing the next URB's data. So we 1194 * switch back to mode 0 to get that interrupt; we'll come 1195 * back here once it happens. 1196 */ 1197 if (tx_csr & MUSB_TXCSR_DMAMODE) { 1198 /* 1199 * We shouldn't clear DMAMODE with DMAENAB set; so 1200 * clear them in a safe order. That should be OK 1201 * once TXPKTRDY has been set (and I've never seen 1202 * it being 0 at this moment -- DMA interrupt latency 1203 * is significant) but if it hasn't been then we have 1204 * no choice but to stop being polite and ignore the 1205 * programmer's guide... :-) 1206 * 1207 * Note that we must write TXCSR with TXPKTRDY cleared 1208 * in order not to re-trigger the packet send (this bit 1209 * can't be cleared by CPU), and there's another caveat: 1210 * TXPKTRDY may be set shortly and then cleared in the 1211 * double-buffered FIFO mode, so we do an extra TXCSR 1212 * read for debouncing... 1213 */ 1214 tx_csr &= musb_readw(epio, MUSB_TXCSR); 1215 if (tx_csr & MUSB_TXCSR_TXPKTRDY) { 1216 tx_csr &= ~(MUSB_TXCSR_DMAENAB | 1217 MUSB_TXCSR_TXPKTRDY); 1218 musb_writew(epio, MUSB_TXCSR, 1219 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1220 } 1221 tx_csr &= ~(MUSB_TXCSR_DMAMODE | 1222 MUSB_TXCSR_TXPKTRDY); 1223 musb_writew(epio, MUSB_TXCSR, 1224 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1225 1226 /* 1227 * There is no guarantee that we'll get an interrupt 1228 * after clearing DMAMODE as we might have done this 1229 * too late (after TXPKTRDY was cleared by controller). 1230 * Re-read TXCSR as we have spoiled its previous value. 1231 */ 1232 tx_csr = musb_readw(epio, MUSB_TXCSR); 1233 } 1234 1235 /* 1236 * We may get here from a DMA completion or TXPKTRDY interrupt. 1237 * In any case, we must check the FIFO status here and bail out 1238 * only if the FIFO still has data -- that should prevent the 1239 * "missed" TXPKTRDY interrupts and deal with double-buffered 1240 * FIFO mode too... 1241 */ 1242 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { 1243 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, " 1244 "CSR %04x\n", tx_csr); 1245 return; 1246 } 1247 } 1248 1249 if (!status || dma || usb_pipeisoc(pipe)) { 1250 if (dma) 1251 length = dma->actual_len; 1252 else 1253 length = qh->segsize; 1254 qh->offset += length; 1255 1256 if (usb_pipeisoc(pipe)) { 1257 struct usb_iso_packet_descriptor *d; 1258 1259 d = urb->iso_frame_desc + qh->iso_idx; 1260 d->actual_length = length; 1261 d->status = status; 1262 if (++qh->iso_idx >= urb->number_of_packets) { 1263 done = true; 1264 } else { 1265 d++; 1266 offset = d->offset; 1267 length = d->length; 1268 } 1269 } else if (dma && urb->transfer_buffer_length == qh->offset) { 1270 done = true; 1271 } else { 1272 /* see if we need to send more data, or ZLP */ 1273 if (qh->segsize < qh->maxpacket) 1274 done = true; 1275 else if (qh->offset == urb->transfer_buffer_length 1276 && !(urb->transfer_flags 1277 & URB_ZERO_PACKET)) 1278 done = true; 1279 if (!done) { 1280 offset = qh->offset; 1281 length = urb->transfer_buffer_length - offset; 1282 transfer_pending = true; 1283 } 1284 } 1285 } 1286 1287 /* urb->status != -EINPROGRESS means request has been faulted, 1288 * so we must abort this transfer after cleanup 1289 */ 1290 if (urb->status != -EINPROGRESS) { 1291 done = true; 1292 if (status == 0) 1293 status = urb->status; 1294 } 1295 1296 if (done) { 1297 /* set status */ 1298 urb->status = status; 1299 urb->actual_length = qh->offset; 1300 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); 1301 return; 1302 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) { 1303 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, 1304 offset, length)) { 1305 if (is_cppi_enabled() || tusb_dma_omap()) 1306 musb_h_tx_dma_start(hw_ep); 1307 return; 1308 } 1309 } else if (tx_csr & MUSB_TXCSR_DMAENAB) { 1310 dev_dbg(musb->controller, "not complete, but DMA enabled?\n"); 1311 return; 1312 } 1313 1314 /* 1315 * PIO: start next packet in this URB. 1316 * 1317 * REVISIT: some docs say that when hw_ep->tx_double_buffered, 1318 * (and presumably, FIFO is not half-full) we should write *two* 1319 * packets before updating TXCSR; other docs disagree... 1320 */ 1321 if (length > qh->maxpacket) 1322 length = qh->maxpacket; 1323 /* Unmap the buffer so that CPU can use it */ 1324 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb); 1325 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); 1326 qh->segsize = length; 1327 1328 musb_ep_select(mbase, epnum); 1329 musb_writew(epio, MUSB_TXCSR, 1330 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); 1331} 1332 1333 1334#ifdef CONFIG_USB_INVENTRA_DMA 1335 1336/* Host side RX (IN) using Mentor DMA works as follows: 1337 submit_urb -> 1338 - if queue was empty, ProgramEndpoint 1339 - first IN token is sent out (by setting ReqPkt) 1340 LinuxIsr -> RxReady() 1341 /\ => first packet is received 1342 | - Set in mode 0 (DmaEnab, ~ReqPkt) 1343 | -> DMA Isr (transfer complete) -> RxReady() 1344 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) 1345 | - if urb not complete, send next IN token (ReqPkt) 1346 | | else complete urb. 1347 | | 1348 --------------------------- 1349 * 1350 * Nuances of mode 1: 1351 * For short packets, no ack (+RxPktRdy) is sent automatically 1352 * (even if AutoClear is ON) 1353 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent 1354 * automatically => major problem, as collecting the next packet becomes 1355 * difficult. Hence mode 1 is not used. 1356 * 1357 * REVISIT 1358 * All we care about at this driver level is that 1359 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; 1360 * (b) termination conditions are: short RX, or buffer full; 1361 * (c) fault modes include 1362 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. 1363 * (and that endpoint's dma queue stops immediately) 1364 * - overflow (full, PLUS more bytes in the terminal packet) 1365 * 1366 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would 1367 * thus be a great candidate for using mode 1 ... for all but the 1368 * last packet of one URB's transfer. 1369 */ 1370 1371#endif 1372 1373/* Schedule next QH from musb->in_bulk and move the current qh to 1374 * the end; avoids starvation for other endpoints. 1375 */ 1376static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep) 1377{ 1378 struct dma_channel *dma; 1379 struct urb *urb; 1380 void __iomem *mbase = musb->mregs; 1381 void __iomem *epio = ep->regs; 1382 struct musb_qh *cur_qh, *next_qh; 1383 u16 rx_csr; 1384 1385 musb_ep_select(mbase, ep->epnum); 1386 dma = is_dma_capable() ? ep->rx_channel : NULL; 1387 1388 /* clear nak timeout bit */ 1389 rx_csr = musb_readw(epio, MUSB_RXCSR); 1390 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 1391 rx_csr &= ~MUSB_RXCSR_DATAERROR; 1392 musb_writew(epio, MUSB_RXCSR, rx_csr); 1393 1394 cur_qh = first_qh(&musb->in_bulk); 1395 if (cur_qh) { 1396 urb = next_urb(cur_qh); 1397 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1398 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1399 musb->dma_controller->channel_abort(dma); 1400 urb->actual_length += dma->actual_len; 1401 dma->actual_len = 0L; 1402 } 1403 musb_save_toggle(cur_qh, 1, urb); 1404 1405 /* move cur_qh to end of queue */ 1406 list_move_tail(&cur_qh->ring, &musb->in_bulk); 1407 1408 /* get the next qh from musb->in_bulk */ 1409 next_qh = first_qh(&musb->in_bulk); 1410 1411 /* set rx_reinit and schedule the next qh */ 1412 ep->rx_reinit = 1; 1413 musb_start_urb(musb, 1, next_qh); 1414 } 1415} 1416 1417/* 1418 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, 1419 * and high-bandwidth IN transfer cases. 1420 */ 1421void musb_host_rx(struct musb *musb, u8 epnum) 1422{ 1423 struct urb *urb; 1424 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1425 void __iomem *epio = hw_ep->regs; 1426 struct musb_qh *qh = hw_ep->in_qh; 1427 size_t xfer_len; 1428 void __iomem *mbase = musb->mregs; 1429 int pipe; 1430 u16 rx_csr, val; 1431 bool iso_err = false; 1432 bool done = false; 1433 u32 status; 1434 struct dma_channel *dma; 1435 1436 musb_ep_select(mbase, epnum); 1437 1438 urb = next_urb(qh); 1439 dma = is_dma_capable() ? hw_ep->rx_channel : NULL; 1440 status = 0; 1441 xfer_len = 0; 1442 1443 rx_csr = musb_readw(epio, MUSB_RXCSR); 1444 val = rx_csr; 1445 1446 if (unlikely(!urb)) { 1447 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least 1448 * usbtest #11 (unlinks) triggers it regularly, sometimes 1449 * with fifo full. (Only with DMA??) 1450 */ 1451 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, 1452 musb_readw(epio, MUSB_RXCOUNT)); 1453 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1454 return; 1455 } 1456 1457 pipe = urb->pipe; 1458 1459 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", 1460 epnum, rx_csr, urb->actual_length, 1461 dma ? dma->actual_len : 0); 1462 1463 /* check for errors, concurrent stall & unlink is not really 1464 * handled yet! */ 1465 if (rx_csr & MUSB_RXCSR_H_RXSTALL) { 1466 dev_dbg(musb->controller, "RX end %d STALL\n", epnum); 1467 1468 /* stall; record URB status */ 1469 status = -EPIPE; 1470 1471 } else if (rx_csr & MUSB_RXCSR_H_ERROR) { 1472 dev_dbg(musb->controller, "end %d RX proto error\n", epnum); 1473 1474 status = -EPROTO; 1475 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1476 1477 } else if (rx_csr & MUSB_RXCSR_DATAERROR) { 1478 1479 if (USB_ENDPOINT_XFER_ISOC != qh->type) { 1480 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum); 1481 1482 /* NOTE: NAKing is *NOT* an error, so we want to 1483 * continue. Except ... if there's a request for 1484 * another QH, use that instead of starving it. 1485 * 1486 * Devices like Ethernet and serial adapters keep 1487 * reads posted at all times, which will starve 1488 * other devices without this logic. 1489 */ 1490 if (usb_pipebulk(urb->pipe) 1491 && qh->mux == 1 1492 && !list_is_singular(&musb->in_bulk)) { 1493 musb_bulk_rx_nak_timeout(musb, hw_ep); 1494 return; 1495 } 1496 musb_ep_select(mbase, epnum); 1497 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 1498 rx_csr &= ~MUSB_RXCSR_DATAERROR; 1499 musb_writew(epio, MUSB_RXCSR, rx_csr); 1500 1501 goto finish; 1502 } else { 1503 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum); 1504 /* packet error reported later */ 1505 iso_err = true; 1506 } 1507 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) { 1508 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n", 1509 epnum); 1510 status = -EPROTO; 1511 } 1512 1513 /* faults abort the transfer */ 1514 if (status) { 1515 /* clean up dma and collect transfer count */ 1516 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1517 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1518 (void) musb->dma_controller->channel_abort(dma); 1519 xfer_len = dma->actual_len; 1520 } 1521 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1522 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1523 done = true; 1524 goto finish; 1525 } 1526 1527 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { 1528 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ 1529 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); 1530 goto finish; 1531 } 1532 1533 /* thorough shutdown for now ... given more precise fault handling 1534 * and better queueing support, we might keep a DMA pipeline going 1535 * while processing this irq for earlier completions. 1536 */ 1537 1538 /* FIXME this is _way_ too much in-line logic for Mentor DMA */ 1539 1540#ifndef CONFIG_USB_INVENTRA_DMA 1541 if (rx_csr & MUSB_RXCSR_H_REQPKT) { 1542 /* REVISIT this happened for a while on some short reads... 1543 * the cleanup still needs investigation... looks bad... 1544 * and also duplicates dma cleanup code above ... plus, 1545 * shouldn't this be the "half full" double buffer case? 1546 */ 1547 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1548 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1549 (void) musb->dma_controller->channel_abort(dma); 1550 xfer_len = dma->actual_len; 1551 done = true; 1552 } 1553 1554 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, 1555 xfer_len, dma ? ", dma" : ""); 1556 rx_csr &= ~MUSB_RXCSR_H_REQPKT; 1557 1558 musb_ep_select(mbase, epnum); 1559 musb_writew(epio, MUSB_RXCSR, 1560 MUSB_RXCSR_H_WZC_BITS | rx_csr); 1561 } 1562#endif 1563 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { 1564 xfer_len = dma->actual_len; 1565 1566 val &= ~(MUSB_RXCSR_DMAENAB 1567 | MUSB_RXCSR_H_AUTOREQ 1568 | MUSB_RXCSR_AUTOCLEAR 1569 | MUSB_RXCSR_RXPKTRDY); 1570 musb_writew(hw_ep->regs, MUSB_RXCSR, val); 1571 1572#ifdef CONFIG_USB_INVENTRA_DMA 1573 if (usb_pipeisoc(pipe)) { 1574 struct usb_iso_packet_descriptor *d; 1575 1576 d = urb->iso_frame_desc + qh->iso_idx; 1577 d->actual_length = xfer_len; 1578 1579 /* even if there was an error, we did the dma 1580 * for iso_frame_desc->length 1581 */ 1582 if (d->status != -EILSEQ && d->status != -EOVERFLOW) 1583 d->status = 0; 1584 1585 if (++qh->iso_idx >= urb->number_of_packets) 1586 done = true; 1587 else 1588 done = false; 1589 1590 } else { 1591 /* done if urb buffer is full or short packet is recd */ 1592 done = (urb->actual_length + xfer_len >= 1593 urb->transfer_buffer_length 1594 || dma->actual_len < qh->maxpacket); 1595 } 1596 1597 /* send IN token for next packet, without AUTOREQ */ 1598 if (!done) { 1599 val |= MUSB_RXCSR_H_REQPKT; 1600 musb_writew(epio, MUSB_RXCSR, 1601 MUSB_RXCSR_H_WZC_BITS | val); 1602 } 1603 1604 dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, 1605 done ? "off" : "reset", 1606 musb_readw(epio, MUSB_RXCSR), 1607 musb_readw(epio, MUSB_RXCOUNT)); 1608#else 1609 done = true; 1610#endif 1611 } else if (urb->status == -EINPROGRESS) { 1612 /* if no errors, be sure a packet is ready for unloading */ 1613 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { 1614 status = -EPROTO; 1615 ERR("Rx interrupt with no errors or packet!\n"); 1616 1617 /* FIXME this is another "SHOULD NEVER HAPPEN" */ 1618 1619/* SCRUB (RX) */ 1620 /* do the proper sequence to abort the transfer */ 1621 musb_ep_select(mbase, epnum); 1622 val &= ~MUSB_RXCSR_H_REQPKT; 1623 musb_writew(epio, MUSB_RXCSR, val); 1624 goto finish; 1625 } 1626 1627 /* we are expecting IN packets */ 1628#ifdef CONFIG_USB_INVENTRA_DMA 1629 if (dma) { 1630 struct dma_controller *c; 1631 u16 rx_count; 1632 int ret, length; 1633 dma_addr_t buf; 1634 1635 rx_count = musb_readw(epio, MUSB_RXCOUNT); 1636 1637 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n", 1638 epnum, rx_count, 1639 urb->transfer_dma 1640 + urb->actual_length, 1641 qh->offset, 1642 urb->transfer_buffer_length); 1643 1644 c = musb->dma_controller; 1645 1646 if (usb_pipeisoc(pipe)) { 1647 int d_status = 0; 1648 struct usb_iso_packet_descriptor *d; 1649 1650 d = urb->iso_frame_desc + qh->iso_idx; 1651 1652 if (iso_err) { 1653 d_status = -EILSEQ; 1654 urb->error_count++; 1655 } 1656 if (rx_count > d->length) { 1657 if (d_status == 0) { 1658 d_status = -EOVERFLOW; 1659 urb->error_count++; 1660 } 1661 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\ 1662 rx_count, d->length); 1663 1664 length = d->length; 1665 } else 1666 length = rx_count; 1667 d->status = d_status; 1668 buf = urb->transfer_dma + d->offset; 1669 } else { 1670 length = rx_count; 1671 buf = urb->transfer_dma + 1672 urb->actual_length; 1673 } 1674 1675 dma->desired_mode = 0; 1676#ifdef USE_MODE1 1677 /* because of the issue below, mode 1 will 1678 * only rarely behave with correct semantics. 1679 */ 1680 if ((urb->transfer_flags & 1681 URB_SHORT_NOT_OK) 1682 && (urb->transfer_buffer_length - 1683 urb->actual_length) 1684 > qh->maxpacket) 1685 dma->desired_mode = 1; 1686 if (rx_count < hw_ep->max_packet_sz_rx) { 1687 length = rx_count; 1688 dma->desired_mode = 0; 1689 } else { 1690 length = urb->transfer_buffer_length; 1691 } 1692#endif 1693 1694/* Disadvantage of using mode 1: 1695 * It's basically usable only for mass storage class; essentially all 1696 * other protocols also terminate transfers on short packets. 1697 * 1698 * Details: 1699 * An extra IN token is sent at the end of the transfer (due to AUTOREQ) 1700 * If you try to use mode 1 for (transfer_buffer_length - 512), and try 1701 * to use the extra IN token to grab the last packet using mode 0, then 1702 * the problem is that you cannot be sure when the device will send the 1703 * last packet and RxPktRdy set. Sometimes the packet is recd too soon 1704 * such that it gets lost when RxCSR is re-set at the end of the mode 1 1705 * transfer, while sometimes it is recd just a little late so that if you 1706 * try to configure for mode 0 soon after the mode 1 transfer is 1707 * completed, you will find rxcount 0. Okay, so you might think why not 1708 * wait for an interrupt when the pkt is recd. Well, you won't get any! 1709 */ 1710 1711 val = musb_readw(epio, MUSB_RXCSR); 1712 val &= ~MUSB_RXCSR_H_REQPKT; 1713 1714 if (dma->desired_mode == 0) 1715 val &= ~MUSB_RXCSR_H_AUTOREQ; 1716 else 1717 val |= MUSB_RXCSR_H_AUTOREQ; 1718 val |= MUSB_RXCSR_DMAENAB; 1719 1720 /* autoclear shouldn't be set in high bandwidth */ 1721 if (qh->hb_mult == 1) 1722 val |= MUSB_RXCSR_AUTOCLEAR; 1723 1724 musb_writew(epio, MUSB_RXCSR, 1725 MUSB_RXCSR_H_WZC_BITS | val); 1726 1727 /* REVISIT if when actual_length != 0, 1728 * transfer_buffer_length needs to be 1729 * adjusted first... 1730 */ 1731 ret = c->channel_program( 1732 dma, qh->maxpacket, 1733 dma->desired_mode, buf, length); 1734 1735 if (!ret) { 1736 c->channel_release(dma); 1737 hw_ep->rx_channel = NULL; 1738 dma = NULL; 1739 /* REVISIT reset CSR */ 1740 } 1741 } 1742#endif /* Mentor DMA */ 1743 1744 if (!dma) { 1745 /* Unmap the buffer so that CPU can use it */ 1746 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb); 1747 done = musb_host_packet_rx(musb, urb, 1748 epnum, iso_err); 1749 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : ""); 1750 } 1751 } 1752 1753finish: 1754 urb->actual_length += xfer_len; 1755 qh->offset += xfer_len; 1756 if (done) { 1757 if (urb->status == -EINPROGRESS) 1758 urb->status = status; 1759 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); 1760 } 1761} 1762 1763/* schedule nodes correspond to peripheral endpoints, like an OHCI QH. 1764 * the software schedule associates multiple such nodes with a given 1765 * host side hardware endpoint + direction; scheduling may activate 1766 * that hardware endpoint. 1767 */ 1768static int musb_schedule( 1769 struct musb *musb, 1770 struct musb_qh *qh, 1771 int is_in) 1772{ 1773 int idle; 1774 int best_diff; 1775 int best_end, epnum; 1776 struct musb_hw_ep *hw_ep = NULL; 1777 struct list_head *head = NULL; 1778 u8 toggle; 1779 u8 txtype; 1780 struct urb *urb = next_urb(qh); 1781 1782 /* use fixed hardware for control and bulk */ 1783 if (qh->type == USB_ENDPOINT_XFER_CONTROL) { 1784 head = &musb->control; 1785 hw_ep = musb->control_ep; 1786 goto success; 1787 } 1788 1789 /* else, periodic transfers get muxed to other endpoints */ 1790 1791 /* 1792 * We know this qh hasn't been scheduled, so all we need to do 1793 * is choose which hardware endpoint to put it on ... 1794 * 1795 * REVISIT what we really want here is a regular schedule tree 1796 * like e.g. OHCI uses. 1797 */ 1798 best_diff = 4096; 1799 best_end = -1; 1800 1801 for (epnum = 1, hw_ep = musb->endpoints + 1; 1802 epnum < musb->nr_endpoints; 1803 epnum++, hw_ep++) { 1804 int diff; 1805 1806 if (musb_ep_get_qh(hw_ep, is_in) != NULL) 1807 continue; 1808 1809 if (hw_ep == musb->bulk_ep) 1810 continue; 1811 1812 if (is_in) 1813 diff = hw_ep->max_packet_sz_rx; 1814 else 1815 diff = hw_ep->max_packet_sz_tx; 1816 diff -= (qh->maxpacket * qh->hb_mult); 1817 1818 if (diff >= 0 && best_diff > diff) { 1819 1820 /* 1821 * Mentor controller has a bug in that if we schedule 1822 * a BULK Tx transfer on an endpoint that had earlier 1823 * handled ISOC then the BULK transfer has to start on 1824 * a zero toggle. If the BULK transfer starts on a 1 1825 * toggle then this transfer will fail as the mentor 1826 * controller starts the Bulk transfer on a 0 toggle 1827 * irrespective of the programming of the toggle bits 1828 * in the TXCSR register. Check for this condition 1829 * while allocating the EP for a Tx Bulk transfer. If 1830 * so skip this EP. 1831 */ 1832 hw_ep = musb->endpoints + epnum; 1833 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in); 1834 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) 1835 >> 4) & 0x3; 1836 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) && 1837 toggle && (txtype == USB_ENDPOINT_XFER_ISOC)) 1838 continue; 1839 1840 best_diff = diff; 1841 best_end = epnum; 1842 } 1843 } 1844 /* use bulk reserved ep1 if no other ep is free */ 1845 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { 1846 hw_ep = musb->bulk_ep; 1847 if (is_in) 1848 head = &musb->in_bulk; 1849 else 1850 head = &musb->out_bulk; 1851 1852 /* Enable bulk RX NAK timeout scheme when bulk requests are 1853 * multiplexed. This scheme doen't work in high speed to full 1854 * speed scenario as NAK interrupts are not coming from a 1855 * full speed device connected to a high speed device. 1856 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and 1857 * 4 (8 frame or 8ms) for FS device. 1858 */ 1859 if (is_in && qh->dev) 1860 qh->intv_reg = 1861 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; 1862 goto success; 1863 } else if (best_end < 0) { 1864 return -ENOSPC; 1865 } 1866 1867 idle = 1; 1868 qh->mux = 0; 1869 hw_ep = musb->endpoints + best_end; 1870 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end); 1871success: 1872 if (head) { 1873 idle = list_empty(head); 1874 list_add_tail(&qh->ring, head); 1875 qh->mux = 1; 1876 } 1877 qh->hw_ep = hw_ep; 1878 qh->hep->hcpriv = qh; 1879 if (idle) 1880 musb_start_urb(musb, is_in, qh); 1881 return 0; 1882} 1883 1884static int musb_urb_enqueue( 1885 struct usb_hcd *hcd, 1886 struct urb *urb, 1887 gfp_t mem_flags) 1888{ 1889 unsigned long flags; 1890 struct musb *musb = hcd_to_musb(hcd); 1891 struct usb_host_endpoint *hep = urb->ep; 1892 struct musb_qh *qh; 1893 struct usb_endpoint_descriptor *epd = &hep->desc; 1894 int ret; 1895 unsigned type_reg; 1896 unsigned interval; 1897 1898 /* host role must be active */ 1899 if (!is_host_active(musb) || !musb->is_active) 1900 return -ENODEV; 1901 1902 spin_lock_irqsave(&musb->lock, flags); 1903 ret = usb_hcd_link_urb_to_ep(hcd, urb); 1904 qh = ret ? NULL : hep->hcpriv; 1905 if (qh) 1906 urb->hcpriv = qh; 1907 spin_unlock_irqrestore(&musb->lock, flags); 1908 1909 /* DMA mapping was already done, if needed, and this urb is on 1910 * hep->urb_list now ... so we're done, unless hep wasn't yet 1911 * scheduled onto a live qh. 1912 * 1913 * REVISIT best to keep hep->hcpriv valid until the endpoint gets 1914 * disabled, testing for empty qh->ring and avoiding qh setup costs 1915 * except for the first urb queued after a config change. 1916 */ 1917 if (qh || ret) 1918 return ret; 1919 1920 /* Allocate and initialize qh, minimizing the work done each time 1921 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. 1922 * 1923 * REVISIT consider a dedicated qh kmem_cache, so it's harder 1924 * for bugs in other kernel code to break this driver... 1925 */ 1926 qh = kzalloc(sizeof *qh, mem_flags); 1927 if (!qh) { 1928 spin_lock_irqsave(&musb->lock, flags); 1929 usb_hcd_unlink_urb_from_ep(hcd, urb); 1930 spin_unlock_irqrestore(&musb->lock, flags); 1931 return -ENOMEM; 1932 } 1933 1934 qh->hep = hep; 1935 qh->dev = urb->dev; 1936 INIT_LIST_HEAD(&qh->ring); 1937 qh->is_ready = 1; 1938 1939 qh->maxpacket = usb_endpoint_maxp(epd); 1940 qh->type = usb_endpoint_type(epd); 1941 1942 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier. 1943 * Some musb cores don't support high bandwidth ISO transfers; and 1944 * we don't (yet!) support high bandwidth interrupt transfers. 1945 */ 1946 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03); 1947 if (qh->hb_mult > 1) { 1948 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC); 1949 1950 if (ok) 1951 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx) 1952 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx); 1953 if (!ok) { 1954 ret = -EMSGSIZE; 1955 goto done; 1956 } 1957 qh->maxpacket &= 0x7ff; 1958 } 1959 1960 qh->epnum = usb_endpoint_num(epd); 1961 1962 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ 1963 qh->addr_reg = (u8) usb_pipedevice(urb->pipe); 1964 1965 /* precompute rxtype/txtype/type0 register */ 1966 type_reg = (qh->type << 4) | qh->epnum; 1967 switch (urb->dev->speed) { 1968 case USB_SPEED_LOW: 1969 type_reg |= 0xc0; 1970 break; 1971 case USB_SPEED_FULL: 1972 type_reg |= 0x80; 1973 break; 1974 default: 1975 type_reg |= 0x40; 1976 } 1977 qh->type_reg = type_reg; 1978 1979 /* Precompute RXINTERVAL/TXINTERVAL register */ 1980 switch (qh->type) { 1981 case USB_ENDPOINT_XFER_INT: 1982 /* 1983 * Full/low speeds use the linear encoding, 1984 * high speed uses the logarithmic encoding. 1985 */ 1986 if (urb->dev->speed <= USB_SPEED_FULL) { 1987 interval = max_t(u8, epd->bInterval, 1); 1988 break; 1989 } 1990 /* FALLTHROUGH */ 1991 case USB_ENDPOINT_XFER_ISOC: 1992 /* ISO always uses logarithmic encoding */ 1993 interval = min_t(u8, epd->bInterval, 16); 1994 break; 1995 default: 1996 /* REVISIT we actually want to use NAK limits, hinting to the 1997 * transfer scheduling logic to try some other qh, e.g. try 1998 * for 2 msec first: 1999 * 2000 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; 2001 * 2002 * The downside of disabling this is that transfer scheduling 2003 * gets VERY unfair for nonperiodic transfers; a misbehaving 2004 * peripheral could make that hurt. That's perfectly normal 2005 * for reads from network or serial adapters ... so we have 2006 * partial NAKlimit support for bulk RX. 2007 * 2008 * The upside of disabling it is simpler transfer scheduling. 2009 */ 2010 interval = 0; 2011 } 2012 qh->intv_reg = interval; 2013 2014 /* precompute addressing for external hub/tt ports */ 2015 if (musb->is_multipoint) { 2016 struct usb_device *parent = urb->dev->parent; 2017 2018 if (parent != hcd->self.root_hub) { 2019 qh->h_addr_reg = (u8) parent->devnum; 2020 2021 /* set up tt info if needed */ 2022 if (urb->dev->tt) { 2023 qh->h_port_reg = (u8) urb->dev->ttport; 2024 if (urb->dev->tt->hub) 2025 qh->h_addr_reg = 2026 (u8) urb->dev->tt->hub->devnum; 2027 if (urb->dev->tt->multi) 2028 qh->h_addr_reg |= 0x80; 2029 } 2030 } 2031 } 2032 2033 /* invariant: hep->hcpriv is null OR the qh that's already scheduled. 2034 * until we get real dma queues (with an entry for each urb/buffer), 2035 * we only have work to do in the former case. 2036 */ 2037 spin_lock_irqsave(&musb->lock, flags); 2038 if (hep->hcpriv) { 2039 /* some concurrent activity submitted another urb to hep... 2040 * odd, rare, error prone, but legal. 2041 */ 2042 kfree(qh); 2043 qh = NULL; 2044 ret = 0; 2045 } else 2046 ret = musb_schedule(musb, qh, 2047 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); 2048 2049 if (ret == 0) { 2050 urb->hcpriv = qh; 2051 /* FIXME set urb->start_frame for iso/intr, it's tested in 2052 * musb_start_urb(), but otherwise only konicawc cares ... 2053 */ 2054 } 2055 spin_unlock_irqrestore(&musb->lock, flags); 2056 2057done: 2058 if (ret != 0) { 2059 spin_lock_irqsave(&musb->lock, flags); 2060 usb_hcd_unlink_urb_from_ep(hcd, urb); 2061 spin_unlock_irqrestore(&musb->lock, flags); 2062 kfree(qh); 2063 } 2064 return ret; 2065} 2066 2067 2068/* 2069 * abort a transfer that's at the head of a hardware queue. 2070 * called with controller locked, irqs blocked 2071 * that hardware queue advances to the next transfer, unless prevented 2072 */ 2073static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) 2074{ 2075 struct musb_hw_ep *ep = qh->hw_ep; 2076 struct musb *musb = ep->musb; 2077 void __iomem *epio = ep->regs; 2078 unsigned hw_end = ep->epnum; 2079 void __iomem *regs = ep->musb->mregs; 2080 int is_in = usb_pipein(urb->pipe); 2081 int status = 0; 2082 u16 csr; 2083 2084 musb_ep_select(regs, hw_end); 2085 2086 if (is_dma_capable()) { 2087 struct dma_channel *dma; 2088 2089 dma = is_in ? ep->rx_channel : ep->tx_channel; 2090 if (dma) { 2091 status = ep->musb->dma_controller->channel_abort(dma); 2092 dev_dbg(musb->controller, 2093 "abort %cX%d DMA for urb %p --> %d\n", 2094 is_in ? 'R' : 'T', ep->epnum, 2095 urb, status); 2096 urb->actual_length += dma->actual_len; 2097 } 2098 } 2099 2100 /* turn off DMA requests, discard state, stop polling ... */ 2101 if (ep->epnum && is_in) { 2102 /* giveback saves bulk toggle */ 2103 csr = musb_h_flush_rxfifo(ep, 0); 2104 2105 /* REVISIT we still get an irq; should likely clear the 2106 * endpoint's irq status here to avoid bogus irqs. 2107 * clearing that status is platform-specific... 2108 */ 2109 } else if (ep->epnum) { 2110 musb_h_tx_flush_fifo(ep); 2111 csr = musb_readw(epio, MUSB_TXCSR); 2112 csr &= ~(MUSB_TXCSR_AUTOSET 2113 | MUSB_TXCSR_DMAENAB 2114 | MUSB_TXCSR_H_RXSTALL 2115 | MUSB_TXCSR_H_NAKTIMEOUT 2116 | MUSB_TXCSR_H_ERROR 2117 | MUSB_TXCSR_TXPKTRDY); 2118 musb_writew(epio, MUSB_TXCSR, csr); 2119 /* REVISIT may need to clear FLUSHFIFO ... */ 2120 musb_writew(epio, MUSB_TXCSR, csr); 2121 /* flush cpu writebuffer */ 2122 csr = musb_readw(epio, MUSB_TXCSR); 2123 } else { 2124 musb_h_ep0_flush_fifo(ep); 2125 } 2126 if (status == 0) 2127 musb_advance_schedule(ep->musb, urb, ep, is_in); 2128 return status; 2129} 2130 2131static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 2132{ 2133 struct musb *musb = hcd_to_musb(hcd); 2134 struct musb_qh *qh; 2135 unsigned long flags; 2136 int is_in = usb_pipein(urb->pipe); 2137 int ret; 2138 2139 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb, 2140 usb_pipedevice(urb->pipe), 2141 usb_pipeendpoint(urb->pipe), 2142 is_in ? "in" : "out"); 2143 2144 spin_lock_irqsave(&musb->lock, flags); 2145 ret = usb_hcd_check_unlink_urb(hcd, urb, status); 2146 if (ret) 2147 goto done; 2148 2149 qh = urb->hcpriv; 2150 if (!qh) 2151 goto done; 2152 2153 /* 2154 * Any URB not actively programmed into endpoint hardware can be 2155 * immediately given back; that's any URB not at the head of an 2156 * endpoint queue, unless someday we get real DMA queues. And even 2157 * if it's at the head, it might not be known to the hardware... 2158 * 2159 * Otherwise abort current transfer, pending DMA, etc.; urb->status 2160 * has already been updated. This is a synchronous abort; it'd be 2161 * OK to hold off until after some IRQ, though. 2162 * 2163 * NOTE: qh is invalid unless !list_empty(&hep->urb_list) 2164 */ 2165 if (!qh->is_ready 2166 || urb->urb_list.prev != &qh->hep->urb_list 2167 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) { 2168 int ready = qh->is_ready; 2169 2170 qh->is_ready = 0; 2171 musb_giveback(musb, urb, 0); 2172 qh->is_ready = ready; 2173 2174 /* If nothing else (usually musb_giveback) is using it 2175 * and its URB list has emptied, recycle this qh. 2176 */ 2177 if (ready && list_empty(&qh->hep->urb_list)) { 2178 qh->hep->hcpriv = NULL; 2179 list_del(&qh->ring); 2180 kfree(qh); 2181 } 2182 } else 2183 ret = musb_cleanup_urb(urb, qh); 2184done: 2185 spin_unlock_irqrestore(&musb->lock, flags); 2186 return ret; 2187} 2188 2189/* disable an endpoint */ 2190static void 2191musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) 2192{ 2193 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN; 2194 unsigned long flags; 2195 struct musb *musb = hcd_to_musb(hcd); 2196 struct musb_qh *qh; 2197 struct urb *urb; 2198 2199 spin_lock_irqsave(&musb->lock, flags); 2200 2201 qh = hep->hcpriv; 2202 if (qh == NULL) 2203 goto exit; 2204 2205 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ 2206 2207 /* Kick the first URB off the hardware, if needed */ 2208 qh->is_ready = 0; 2209 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) { 2210 urb = next_urb(qh); 2211 2212 /* make software (then hardware) stop ASAP */ 2213 if (!urb->unlinked) 2214 urb->status = -ESHUTDOWN; 2215 2216 /* cleanup */ 2217 musb_cleanup_urb(urb, qh); 2218 2219 /* Then nuke all the others ... and advance the 2220 * queue on hw_ep (e.g. bulk ring) when we're done. 2221 */ 2222 while (!list_empty(&hep->urb_list)) { 2223 urb = next_urb(qh); 2224 urb->status = -ESHUTDOWN; 2225 musb_advance_schedule(musb, urb, qh->hw_ep, is_in); 2226 } 2227 } else { 2228 /* Just empty the queue; the hardware is busy with 2229 * other transfers, and since !qh->is_ready nothing 2230 * will activate any of these as it advances. 2231 */ 2232 while (!list_empty(&hep->urb_list)) 2233 musb_giveback(musb, next_urb(qh), -ESHUTDOWN); 2234 2235 hep->hcpriv = NULL; 2236 list_del(&qh->ring); 2237 kfree(qh); 2238 } 2239exit: 2240 spin_unlock_irqrestore(&musb->lock, flags); 2241} 2242 2243static int musb_h_get_frame_number(struct usb_hcd *hcd) 2244{ 2245 struct musb *musb = hcd_to_musb(hcd); 2246 2247 return musb_readw(musb->mregs, MUSB_FRAME); 2248} 2249 2250static int musb_h_start(struct usb_hcd *hcd) 2251{ 2252 struct musb *musb = hcd_to_musb(hcd); 2253 2254 /* NOTE: musb_start() is called when the hub driver turns 2255 * on port power, or when (OTG) peripheral starts. 2256 */ 2257 hcd->state = HC_STATE_RUNNING; 2258 musb->port1_status = 0; 2259 return 0; 2260} 2261 2262static void musb_h_stop(struct usb_hcd *hcd) 2263{ 2264 musb_stop(hcd_to_musb(hcd)); 2265 hcd->state = HC_STATE_HALT; 2266} 2267 2268static int musb_bus_suspend(struct usb_hcd *hcd) 2269{ 2270 struct musb *musb = hcd_to_musb(hcd); 2271 u8 devctl; 2272 2273 if (!is_host_active(musb)) 2274 return 0; 2275 2276 switch (musb->xceiv->state) { 2277 case OTG_STATE_A_SUSPEND: 2278 return 0; 2279 case OTG_STATE_A_WAIT_VRISE: 2280 /* ID could be grounded even if there's no device 2281 * on the other end of the cable. NOTE that the 2282 * A_WAIT_VRISE timers are messy with MUSB... 2283 */ 2284 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2285 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 2286 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 2287 break; 2288 default: 2289 break; 2290 } 2291 2292 if (musb->is_active) { 2293 WARNING("trying to suspend as %s while active\n", 2294 otg_state_string(musb->xceiv->state)); 2295 return -EBUSY; 2296 } else 2297 return 0; 2298} 2299 2300static int musb_bus_resume(struct usb_hcd *hcd) 2301{ 2302 /* resuming child port does the work */ 2303 return 0; 2304} 2305 2306const struct hc_driver musb_hc_driver = { 2307 .description = "musb-hcd", 2308 .product_desc = "MUSB HDRC host driver", 2309 .hcd_priv_size = sizeof(struct musb), 2310 .flags = HCD_USB2 | HCD_MEMORY, 2311 2312 /* not using irq handler or reset hooks from usbcore, since 2313 * those must be shared with peripheral code for OTG configs 2314 */ 2315 2316 .start = musb_h_start, 2317 .stop = musb_h_stop, 2318 2319 .get_frame_number = musb_h_get_frame_number, 2320 2321 .urb_enqueue = musb_urb_enqueue, 2322 .urb_dequeue = musb_urb_dequeue, 2323 .endpoint_disable = musb_h_disable, 2324 2325 .hub_status_data = musb_hub_status_data, 2326 .hub_control = musb_hub_control, 2327 .bus_suspend = musb_bus_suspend, 2328 .bus_resume = musb_bus_resume, 2329 /* .start_port_reset = NULL, */ 2330 /* .hub_irq_enable = NULL, */ 2331}; 2332