1/* 2 * MUSB OTG driver - support for Mentor's DMA controller 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2007 by Texas Instruments 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 19 * 02110-1301 USA 20 * 21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33#include <linux/device.h> 34#include <linux/interrupt.h> 35#include <linux/platform_device.h> 36#include <linux/slab.h> 37#include "musb_core.h" 38#include "musbhsdma.h" 39 40static int dma_controller_start(struct dma_controller *c) 41{ 42 /* nothing to do */ 43 return 0; 44} 45 46static void dma_channel_release(struct dma_channel *channel); 47 48static int dma_controller_stop(struct dma_controller *c) 49{ 50 struct musb_dma_controller *controller = container_of(c, 51 struct musb_dma_controller, controller); 52 struct musb *musb = controller->private_data; 53 struct dma_channel *channel; 54 u8 bit; 55 56 if (controller->used_channels != 0) { 57 dev_err(musb->controller, 58 "Stopping DMA controller while channel active\n"); 59 60 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { 61 if (controller->used_channels & (1 << bit)) { 62 channel = &controller->channel[bit].channel; 63 dma_channel_release(channel); 64 65 if (!controller->used_channels) 66 break; 67 } 68 } 69 } 70 71 return 0; 72} 73 74static struct dma_channel *dma_channel_allocate(struct dma_controller *c, 75 struct musb_hw_ep *hw_ep, u8 transmit) 76{ 77 struct musb_dma_controller *controller = container_of(c, 78 struct musb_dma_controller, controller); 79 struct musb_dma_channel *musb_channel = NULL; 80 struct dma_channel *channel = NULL; 81 u8 bit; 82 83 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { 84 if (!(controller->used_channels & (1 << bit))) { 85 controller->used_channels |= (1 << bit); 86 musb_channel = &(controller->channel[bit]); 87 musb_channel->controller = controller; 88 musb_channel->idx = bit; 89 musb_channel->epnum = hw_ep->epnum; 90 musb_channel->transmit = transmit; 91 channel = &(musb_channel->channel); 92 channel->private_data = musb_channel; 93 channel->status = MUSB_DMA_STATUS_FREE; 94 channel->max_len = 0x100000; 95 /* Tx => mode 1; Rx => mode 0 */ 96 channel->desired_mode = transmit; 97 channel->actual_len = 0; 98 break; 99 } 100 } 101 102 return channel; 103} 104 105static void dma_channel_release(struct dma_channel *channel) 106{ 107 struct musb_dma_channel *musb_channel = channel->private_data; 108 109 channel->actual_len = 0; 110 musb_channel->start_addr = 0; 111 musb_channel->len = 0; 112 113 musb_channel->controller->used_channels &= 114 ~(1 << musb_channel->idx); 115 116 channel->status = MUSB_DMA_STATUS_UNKNOWN; 117} 118 119static void configure_channel(struct dma_channel *channel, 120 u16 packet_sz, u8 mode, 121 dma_addr_t dma_addr, u32 len) 122{ 123 struct musb_dma_channel *musb_channel = channel->private_data; 124 struct musb_dma_controller *controller = musb_channel->controller; 125 struct musb *musb = controller->private_data; 126 void __iomem *mbase = controller->base; 127 u8 bchannel = musb_channel->idx; 128 u16 csr = 0; 129 130 dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", 131 channel, packet_sz, dma_addr, len, mode); 132 133 if (mode) { 134 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; 135 BUG_ON(len < packet_sz); 136 } 137 csr |= MUSB_HSDMA_BURSTMODE_INCR16 138 << MUSB_HSDMA_BURSTMODE_SHIFT; 139 140 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) 141 | (1 << MUSB_HSDMA_ENABLE_SHIFT) 142 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) 143 | (musb_channel->transmit 144 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) 145 : 0); 146 147 /* address/count */ 148 musb_write_hsdma_addr(mbase, bchannel, dma_addr); 149 musb_write_hsdma_count(mbase, bchannel, len); 150 151 /* control (this should start things) */ 152 musb_writew(mbase, 153 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), 154 csr); 155} 156 157static int dma_channel_program(struct dma_channel *channel, 158 u16 packet_sz, u8 mode, 159 dma_addr_t dma_addr, u32 len) 160{ 161 struct musb_dma_channel *musb_channel = channel->private_data; 162 struct musb_dma_controller *controller = musb_channel->controller; 163 struct musb *musb = controller->private_data; 164 165 dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", 166 musb_channel->epnum, 167 musb_channel->transmit ? "Tx" : "Rx", 168 packet_sz, dma_addr, len, mode); 169 170 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || 171 channel->status == MUSB_DMA_STATUS_BUSY); 172 173 /* Let targets check/tweak the arguments */ 174 if (musb->ops->adjust_channel_params) { 175 int ret = musb->ops->adjust_channel_params(channel, 176 packet_sz, &mode, &dma_addr, &len); 177 if (ret) 178 return ret; 179 } 180 181 /* 182 * The DMA engine in RTL1.8 and above cannot handle 183 * DMA addresses that are not aligned to a 4 byte boundary. 184 * It ends up masking the last two bits of the address 185 * programmed in DMA_ADDR. 186 * 187 * Fail such DMA transfers, so that the backup PIO mode 188 * can carry out the transfer 189 */ 190 if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4)) 191 return false; 192 193 channel->actual_len = 0; 194 musb_channel->start_addr = dma_addr; 195 musb_channel->len = len; 196 musb_channel->max_packet_sz = packet_sz; 197 channel->status = MUSB_DMA_STATUS_BUSY; 198 199 configure_channel(channel, packet_sz, mode, dma_addr, len); 200 201 return true; 202} 203 204static int dma_channel_abort(struct dma_channel *channel) 205{ 206 struct musb_dma_channel *musb_channel = channel->private_data; 207 void __iomem *mbase = musb_channel->controller->base; 208 209 u8 bchannel = musb_channel->idx; 210 int offset; 211 u16 csr; 212 213 if (channel->status == MUSB_DMA_STATUS_BUSY) { 214 if (musb_channel->transmit) { 215 offset = MUSB_EP_OFFSET(musb_channel->epnum, 216 MUSB_TXCSR); 217 218 /* 219 * The programming guide says that we must clear 220 * the DMAENAB bit before the DMAMODE bit... 221 */ 222 csr = musb_readw(mbase, offset); 223 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 224 musb_writew(mbase, offset, csr); 225 csr &= ~MUSB_TXCSR_DMAMODE; 226 musb_writew(mbase, offset, csr); 227 } else { 228 offset = MUSB_EP_OFFSET(musb_channel->epnum, 229 MUSB_RXCSR); 230 231 csr = musb_readw(mbase, offset); 232 csr &= ~(MUSB_RXCSR_AUTOCLEAR | 233 MUSB_RXCSR_DMAENAB | 234 MUSB_RXCSR_DMAMODE); 235 musb_writew(mbase, offset, csr); 236 } 237 238 musb_writew(mbase, 239 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), 240 0); 241 musb_write_hsdma_addr(mbase, bchannel, 0); 242 musb_write_hsdma_count(mbase, bchannel, 0); 243 channel->status = MUSB_DMA_STATUS_FREE; 244 } 245 246 return 0; 247} 248 249static irqreturn_t dma_controller_irq(int irq, void *private_data) 250{ 251 struct musb_dma_controller *controller = private_data; 252 struct musb *musb = controller->private_data; 253 struct musb_dma_channel *musb_channel; 254 struct dma_channel *channel; 255 256 void __iomem *mbase = controller->base; 257 258 irqreturn_t retval = IRQ_NONE; 259 260 unsigned long flags; 261 262 u8 bchannel; 263 u8 int_hsdma; 264 265 u32 addr, count; 266 u16 csr; 267 268 spin_lock_irqsave(&musb->lock, flags); 269 270 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); 271 272#ifdef CONFIG_BLACKFIN 273 /* Clear DMA interrupt flags */ 274 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma); 275#endif 276 277 if (!int_hsdma) { 278 dev_dbg(musb->controller, "spurious DMA irq\n"); 279 280 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 281 musb_channel = (struct musb_dma_channel *) 282 &(controller->channel[bchannel]); 283 channel = &musb_channel->channel; 284 if (channel->status == MUSB_DMA_STATUS_BUSY) { 285 count = musb_read_hsdma_count(mbase, bchannel); 286 287 if (count == 0) 288 int_hsdma |= (1 << bchannel); 289 } 290 } 291 292 dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma); 293 294 if (!int_hsdma) 295 goto done; 296 } 297 298 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 299 if (int_hsdma & (1 << bchannel)) { 300 musb_channel = (struct musb_dma_channel *) 301 &(controller->channel[bchannel]); 302 channel = &musb_channel->channel; 303 304 csr = musb_readw(mbase, 305 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, 306 MUSB_HSDMA_CONTROL)); 307 308 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) { 309 musb_channel->channel.status = 310 MUSB_DMA_STATUS_BUS_ABORT; 311 } else { 312 u8 devctl; 313 314 addr = musb_read_hsdma_addr(mbase, 315 bchannel); 316 channel->actual_len = addr 317 - musb_channel->start_addr; 318 319 dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n", 320 channel, musb_channel->start_addr, 321 addr, channel->actual_len, 322 musb_channel->len, 323 (channel->actual_len 324 < musb_channel->len) ? 325 "=> reconfig 0" : "=> complete"); 326 327 devctl = musb_readb(mbase, MUSB_DEVCTL); 328 329 channel->status = MUSB_DMA_STATUS_FREE; 330 331 /* completed */ 332 if ((devctl & MUSB_DEVCTL_HM) 333 && (musb_channel->transmit) 334 && ((channel->desired_mode == 0) 335 || (channel->actual_len & 336 (musb_channel->max_packet_sz - 1))) 337 ) { 338 u8 epnum = musb_channel->epnum; 339 int offset = MUSB_EP_OFFSET(epnum, 340 MUSB_TXCSR); 341 u16 txcsr; 342 343 /* 344 * The programming guide says that we 345 * must clear DMAENAB before DMAMODE. 346 */ 347 musb_ep_select(mbase, epnum); 348 txcsr = musb_readw(mbase, offset); 349 txcsr &= ~(MUSB_TXCSR_DMAENAB 350 | MUSB_TXCSR_AUTOSET); 351 musb_writew(mbase, offset, txcsr); 352 /* Send out the packet */ 353 txcsr &= ~MUSB_TXCSR_DMAMODE; 354 txcsr |= MUSB_TXCSR_TXPKTRDY; 355 musb_writew(mbase, offset, txcsr); 356 } 357 musb_dma_completion(musb, musb_channel->epnum, 358 musb_channel->transmit); 359 } 360 } 361 } 362 363 retval = IRQ_HANDLED; 364done: 365 spin_unlock_irqrestore(&musb->lock, flags); 366 return retval; 367} 368 369void dma_controller_destroy(struct dma_controller *c) 370{ 371 struct musb_dma_controller *controller = container_of(c, 372 struct musb_dma_controller, controller); 373 374 if (!controller) 375 return; 376 377 if (controller->irq) 378 free_irq(controller->irq, c); 379 380 kfree(controller); 381} 382 383struct dma_controller *__init 384dma_controller_create(struct musb *musb, void __iomem *base) 385{ 386 struct musb_dma_controller *controller; 387 struct device *dev = musb->controller; 388 struct platform_device *pdev = to_platform_device(dev); 389 int irq = platform_get_irq_byname(pdev, "dma"); 390 391 if (irq == 0) { 392 dev_err(dev, "No DMA interrupt line!\n"); 393 return NULL; 394 } 395 396 controller = kzalloc(sizeof(*controller), GFP_KERNEL); 397 if (!controller) 398 return NULL; 399 400 controller->channel_count = MUSB_HSDMA_CHANNELS; 401 controller->private_data = musb; 402 controller->base = base; 403 404 controller->controller.start = dma_controller_start; 405 controller->controller.stop = dma_controller_stop; 406 controller->controller.channel_alloc = dma_channel_allocate; 407 controller->controller.channel_release = dma_channel_release; 408 controller->controller.channel_program = dma_channel_program; 409 controller->controller.channel_abort = dma_channel_abort; 410 411 if (request_irq(irq, dma_controller_irq, 0, 412 dev_name(musb->controller), &controller->controller)) { 413 dev_err(dev, "request_irq %d failed!\n", irq); 414 dma_controller_destroy(&controller->controller); 415 416 return NULL; 417 } 418 419 controller->irq = irq; 420 421 return &controller->controller; 422} 423