musbhsdma.c revision 5a0e3ad6af8660be21ca98a971cd00f331318c05
1/* 2 * MUSB OTG driver - support for Mentor's DMA controller 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2007 by Texas Instruments 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 19 * 02110-1301 USA 20 * 21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33#include <linux/device.h> 34#include <linux/interrupt.h> 35#include <linux/platform_device.h> 36#include <linux/slab.h> 37#include "musb_core.h" 38#include "musbhsdma.h" 39 40static int dma_controller_start(struct dma_controller *c) 41{ 42 /* nothing to do */ 43 return 0; 44} 45 46static void dma_channel_release(struct dma_channel *channel); 47 48static int dma_controller_stop(struct dma_controller *c) 49{ 50 struct musb_dma_controller *controller = container_of(c, 51 struct musb_dma_controller, controller); 52 struct musb *musb = controller->private_data; 53 struct dma_channel *channel; 54 u8 bit; 55 56 if (controller->used_channels != 0) { 57 dev_err(musb->controller, 58 "Stopping DMA controller while channel active\n"); 59 60 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { 61 if (controller->used_channels & (1 << bit)) { 62 channel = &controller->channel[bit].channel; 63 dma_channel_release(channel); 64 65 if (!controller->used_channels) 66 break; 67 } 68 } 69 } 70 71 return 0; 72} 73 74static struct dma_channel *dma_channel_allocate(struct dma_controller *c, 75 struct musb_hw_ep *hw_ep, u8 transmit) 76{ 77 struct musb_dma_controller *controller = container_of(c, 78 struct musb_dma_controller, controller); 79 struct musb_dma_channel *musb_channel = NULL; 80 struct dma_channel *channel = NULL; 81 u8 bit; 82 83 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { 84 if (!(controller->used_channels & (1 << bit))) { 85 controller->used_channels |= (1 << bit); 86 musb_channel = &(controller->channel[bit]); 87 musb_channel->controller = controller; 88 musb_channel->idx = bit; 89 musb_channel->epnum = hw_ep->epnum; 90 musb_channel->transmit = transmit; 91 channel = &(musb_channel->channel); 92 channel->private_data = musb_channel; 93 channel->status = MUSB_DMA_STATUS_FREE; 94 channel->max_len = 0x10000; 95 /* Tx => mode 1; Rx => mode 0 */ 96 channel->desired_mode = transmit; 97 channel->actual_len = 0; 98 break; 99 } 100 } 101 102 return channel; 103} 104 105static void dma_channel_release(struct dma_channel *channel) 106{ 107 struct musb_dma_channel *musb_channel = channel->private_data; 108 109 channel->actual_len = 0; 110 musb_channel->start_addr = 0; 111 musb_channel->len = 0; 112 113 musb_channel->controller->used_channels &= 114 ~(1 << musb_channel->idx); 115 116 channel->status = MUSB_DMA_STATUS_UNKNOWN; 117} 118 119static void configure_channel(struct dma_channel *channel, 120 u16 packet_sz, u8 mode, 121 dma_addr_t dma_addr, u32 len) 122{ 123 struct musb_dma_channel *musb_channel = channel->private_data; 124 struct musb_dma_controller *controller = musb_channel->controller; 125 void __iomem *mbase = controller->base; 126 u8 bchannel = musb_channel->idx; 127 u16 csr = 0; 128 129 DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", 130 channel, packet_sz, dma_addr, len, mode); 131 132 if (mode) { 133 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; 134 BUG_ON(len < packet_sz); 135 136 if (packet_sz >= 64) { 137 csr |= MUSB_HSDMA_BURSTMODE_INCR16 138 << MUSB_HSDMA_BURSTMODE_SHIFT; 139 } else if (packet_sz >= 32) { 140 csr |= MUSB_HSDMA_BURSTMODE_INCR8 141 << MUSB_HSDMA_BURSTMODE_SHIFT; 142 } else if (packet_sz >= 16) { 143 csr |= MUSB_HSDMA_BURSTMODE_INCR4 144 << MUSB_HSDMA_BURSTMODE_SHIFT; 145 } 146 } 147 148 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) 149 | (1 << MUSB_HSDMA_ENABLE_SHIFT) 150 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) 151 | (musb_channel->transmit 152 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) 153 : 0); 154 155 /* address/count */ 156 musb_write_hsdma_addr(mbase, bchannel, dma_addr); 157 musb_write_hsdma_count(mbase, bchannel, len); 158 159 /* control (this should start things) */ 160 musb_writew(mbase, 161 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), 162 csr); 163} 164 165static int dma_channel_program(struct dma_channel *channel, 166 u16 packet_sz, u8 mode, 167 dma_addr_t dma_addr, u32 len) 168{ 169 struct musb_dma_channel *musb_channel = channel->private_data; 170 171 DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", 172 musb_channel->epnum, 173 musb_channel->transmit ? "Tx" : "Rx", 174 packet_sz, dma_addr, len, mode); 175 176 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || 177 channel->status == MUSB_DMA_STATUS_BUSY); 178 179 channel->actual_len = 0; 180 musb_channel->start_addr = dma_addr; 181 musb_channel->len = len; 182 musb_channel->max_packet_sz = packet_sz; 183 channel->status = MUSB_DMA_STATUS_BUSY; 184 185 if ((mode == 1) && (len >= packet_sz)) 186 configure_channel(channel, packet_sz, 1, dma_addr, len); 187 else 188 configure_channel(channel, packet_sz, 0, dma_addr, len); 189 190 return true; 191} 192 193static int dma_channel_abort(struct dma_channel *channel) 194{ 195 struct musb_dma_channel *musb_channel = channel->private_data; 196 void __iomem *mbase = musb_channel->controller->base; 197 198 u8 bchannel = musb_channel->idx; 199 int offset; 200 u16 csr; 201 202 if (channel->status == MUSB_DMA_STATUS_BUSY) { 203 if (musb_channel->transmit) { 204 offset = MUSB_EP_OFFSET(musb_channel->epnum, 205 MUSB_TXCSR); 206 207 /* 208 * The programming guide says that we must clear 209 * the DMAENAB bit before the DMAMODE bit... 210 */ 211 csr = musb_readw(mbase, offset); 212 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 213 musb_writew(mbase, offset, csr); 214 csr &= ~MUSB_TXCSR_DMAMODE; 215 musb_writew(mbase, offset, csr); 216 } else { 217 offset = MUSB_EP_OFFSET(musb_channel->epnum, 218 MUSB_RXCSR); 219 220 csr = musb_readw(mbase, offset); 221 csr &= ~(MUSB_RXCSR_AUTOCLEAR | 222 MUSB_RXCSR_DMAENAB | 223 MUSB_RXCSR_DMAMODE); 224 musb_writew(mbase, offset, csr); 225 } 226 227 musb_writew(mbase, 228 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), 229 0); 230 musb_write_hsdma_addr(mbase, bchannel, 0); 231 musb_write_hsdma_count(mbase, bchannel, 0); 232 channel->status = MUSB_DMA_STATUS_FREE; 233 } 234 235 return 0; 236} 237 238static irqreturn_t dma_controller_irq(int irq, void *private_data) 239{ 240 struct musb_dma_controller *controller = private_data; 241 struct musb *musb = controller->private_data; 242 struct musb_dma_channel *musb_channel; 243 struct dma_channel *channel; 244 245 void __iomem *mbase = controller->base; 246 247 irqreturn_t retval = IRQ_NONE; 248 249 unsigned long flags; 250 251 u8 bchannel; 252 u8 int_hsdma; 253 254 u32 addr, count; 255 u16 csr; 256 257 spin_lock_irqsave(&musb->lock, flags); 258 259 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); 260 261#ifdef CONFIG_BLACKFIN 262 /* Clear DMA interrupt flags */ 263 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma); 264#endif 265 266 if (!int_hsdma) { 267 DBG(2, "spurious DMA irq\n"); 268 269 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 270 musb_channel = (struct musb_dma_channel *) 271 &(controller->channel[bchannel]); 272 channel = &musb_channel->channel; 273 if (channel->status == MUSB_DMA_STATUS_BUSY) { 274 count = musb_read_hsdma_count(mbase, bchannel); 275 276 if (count == 0) 277 int_hsdma |= (1 << bchannel); 278 } 279 } 280 281 DBG(2, "int_hsdma = 0x%x\n", int_hsdma); 282 283 if (!int_hsdma) 284 goto done; 285 } 286 287 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 288 if (int_hsdma & (1 << bchannel)) { 289 musb_channel = (struct musb_dma_channel *) 290 &(controller->channel[bchannel]); 291 channel = &musb_channel->channel; 292 293 csr = musb_readw(mbase, 294 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, 295 MUSB_HSDMA_CONTROL)); 296 297 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) { 298 musb_channel->channel.status = 299 MUSB_DMA_STATUS_BUS_ABORT; 300 } else { 301 u8 devctl; 302 303 addr = musb_read_hsdma_addr(mbase, 304 bchannel); 305 channel->actual_len = addr 306 - musb_channel->start_addr; 307 308 DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n", 309 channel, musb_channel->start_addr, 310 addr, channel->actual_len, 311 musb_channel->len, 312 (channel->actual_len 313 < musb_channel->len) ? 314 "=> reconfig 0" : "=> complete"); 315 316 devctl = musb_readb(mbase, MUSB_DEVCTL); 317 318 channel->status = MUSB_DMA_STATUS_FREE; 319 320 /* completed */ 321 if ((devctl & MUSB_DEVCTL_HM) 322 && (musb_channel->transmit) 323 && ((channel->desired_mode == 0) 324 || (channel->actual_len & 325 (musb_channel->max_packet_sz - 1))) 326 ) { 327 u8 epnum = musb_channel->epnum; 328 int offset = MUSB_EP_OFFSET(epnum, 329 MUSB_TXCSR); 330 u16 txcsr; 331 332 /* 333 * The programming guide says that we 334 * must clear DMAENAB before DMAMODE. 335 */ 336 musb_ep_select(mbase, epnum); 337 txcsr = musb_readw(mbase, offset); 338 txcsr &= ~(MUSB_TXCSR_DMAENAB 339 | MUSB_TXCSR_AUTOSET); 340 musb_writew(mbase, offset, txcsr); 341 /* Send out the packet */ 342 txcsr &= ~MUSB_TXCSR_DMAMODE; 343 txcsr |= MUSB_TXCSR_TXPKTRDY; 344 musb_writew(mbase, offset, txcsr); 345 } 346 musb_dma_completion(musb, musb_channel->epnum, 347 musb_channel->transmit); 348 } 349 } 350 } 351 352 retval = IRQ_HANDLED; 353done: 354 spin_unlock_irqrestore(&musb->lock, flags); 355 return retval; 356} 357 358void dma_controller_destroy(struct dma_controller *c) 359{ 360 struct musb_dma_controller *controller = container_of(c, 361 struct musb_dma_controller, controller); 362 363 if (!controller) 364 return; 365 366 if (controller->irq) 367 free_irq(controller->irq, c); 368 369 kfree(controller); 370} 371 372struct dma_controller *__init 373dma_controller_create(struct musb *musb, void __iomem *base) 374{ 375 struct musb_dma_controller *controller; 376 struct device *dev = musb->controller; 377 struct platform_device *pdev = to_platform_device(dev); 378 int irq = platform_get_irq(pdev, 1); 379 380 if (irq == 0) { 381 dev_err(dev, "No DMA interrupt line!\n"); 382 return NULL; 383 } 384 385 controller = kzalloc(sizeof(*controller), GFP_KERNEL); 386 if (!controller) 387 return NULL; 388 389 controller->channel_count = MUSB_HSDMA_CHANNELS; 390 controller->private_data = musb; 391 controller->base = base; 392 393 controller->controller.start = dma_controller_start; 394 controller->controller.stop = dma_controller_stop; 395 controller->controller.channel_alloc = dma_channel_allocate; 396 controller->controller.channel_release = dma_channel_release; 397 controller->controller.channel_program = dma_channel_program; 398 controller->controller.channel_abort = dma_channel_abort; 399 400 if (request_irq(irq, dma_controller_irq, IRQF_DISABLED, 401 dev_name(musb->controller), &controller->controller)) { 402 dev_err(dev, "request_irq %d failed!\n", irq); 403 dma_controller_destroy(&controller->controller); 404 405 return NULL; 406 } 407 408 controller->irq = irq; 409 410 return &controller->controller; 411} 412